8086/8088 ARCHITECTURE

8086/8088 ARCHITECTURE

HISTORY OF THE INTEL MICROPROCESSORS

F The 4-bit Microprocessors

Intel released the world’s first p in 1971. The 4004 is a 4-bit p with maximum memory of only up to 4,096 4-bit memory locations (2,048 bytes). It only has 45 instructions and was used in very limited applications such as early video games and small p-based controllers.


1. In 1972, Intel released the 8008 which is an 8-bit p capable of addressing 16,384 bytes and has 48 instructions. It can execute an ADD instruction in 20 s.

2. In 1973, Intel released the 8080. The 8080 can address a total of 65,536 bytes and can execute an ADD instruction in 2 s only.

3. In 1977, the 8085 was released. It addresses the same amount of memory as the 8080 but it can execute an ADD instruction in 1.3 s. It also has a built-in clock generator and system controller.

8086/8088 Architecture 1


In 1978, Intel released the 8086 p and a year later the 8088. Both are 16-bit p’s and can execute instructions in as little as 400 ns. Both can address a total of 1,048,576 bytes or 524,288 16-bit words.

These 16-bit microprocessors have multiplication and division instructions. These functions were not available in most 8-bit p’s.

The main difference between the 8086 and the 8088 is the size of their external data bus. The external data bus of the 8088 is only 8-bits wide while that of the 8086 is 16-bits wide (take note the internal data bus of the 8088 is 16-bits wide). The reason for this is that many designers still wanted to use the cheaper 8-bit support and peripheral chips in their 16-bit systems.

The 8088 was the p used by IBM in their Personal Computer (PC), the PC XT, and the Portable Computer.


BASIC 8086/8088 ARCHITECTURE


F Execution Unit (EU). This is responsible for executing the instructions.

F Bus Interface Unit (BIU). This is responsible for fetching an instruction, the operand of an instruction or data from the MM.

F Instruction Pointer (IP). This is the program counter.

F Prefetch Queue. The 8086/8088 prefetches the succeeding instructions while executing the current one.


8086/8088 BUS STRUCTURE

F Basic 8086 and 8088 Systems

F The M/IO (or IO/M) signal is for selecting the memory or I/O of the system. If it is a logic 0, then memory is selected; if it is logic 1, I/O is selected.


MEMORY AND THE 8086/8088

F Logical memory is the name given to the memory viewed by the programmer.

The logical memory space is the same for both the 8086 and the 8088. It starts at memory location 00000H and extends to location FFFFFH. The logical memory is 8 bits wide.

A 16-bit word of memory begins at any byte address and extends for two consecutive bytes. For example, the word at location 00122H is stored at byte 00122H and 00123H with the least significant byte stored in location 00122H.


F The physical memory is the actual organization of the memory that the hardware designers see. The physical memory map of the 8088 is identical to its logical memory map.

The physical memory of the 8086 contains two banks of memory.

The advantage of this organization is that the 8086 can read or write a 16-bit word in one operation (provided the addresses of the data are even). The 8088 requires two reads or writes to transfer 16 bits of data.


DEDICATED AND GENERAL USE OF MEMORY

F Addresses 00000H to 00013H (20 memory locations) are dedicated while addresses 00014H to 0007FH (108 memory locations) are reserved.

These 128 bytes or memory locations are used for storage or pointers to interrupt service routines.

F Addresses FFFF0H to FFFFBH (12 memory locations) are dedicated for functions such as storage of the hardware reset jump instruction.

F Addresses FFFFCH to FFFFFH (4 memory locations) are reserved for use with future products.


THE PROGRAMMING MODEL

F All forms of programming depend upon a clear understanding of the internal register structure of the p.

F Register Structure of the 8086/8088


F General Purpose Registers. These are used in any manner that the programmer wishes. Each is addressable as a 16-bit register (AX, BX, CX, DX) or as two 8-bit registers (AH, AL, BH, BL, CH, CL, DH, and DL).

1. AX (Accumulator). This is often used to hold temporary result after an arithmetic and logic operation.

2. BX (Base). This is often used to hold the base address of data located in the memory.

3. CX (Count). This holds the count for certain instructions such as shift count (CL) for shifts and rotates, the number of bytes (CX) operated upon by the repeated string instructions, and a counter (CX) with the LOOP instruction.

4. DX (Data). This holds the most significant part of the product after a 16-bit multiplication and the most significant part of the dividend before a division.


F Pointer and Index Registers. Although the pointer and index registers are also general purpose in nature, they are more often used to index or point to the memory location holding the operand data for many instructions.

1. SP (Stack Pointer). This is used to address data in a LIFO (last-in first-out) stack memory. This occurs most often when the PUSH and POP instructions are executed.

2. BP (Base Pointer). This is often used to address an array of data in memory.

3. SI (Source Index). This is used to address source data indirectly for use with string instructions.

4. DI (Destination Index). This is normally used to address destination data indirectly for use with the string instructions.


F Status Register or Processor Status Word. This contains 16 bits, but 7 of them are not used. Each bit in the PSW is a flag. These flags are divided into the conditional flags (they reflect the result of the previous operation involving the ALU) and the control flags (they control the execution of special functions).

The conditional flags are:

1. Sign Flag (SF) - b7

This is equal to the MSB of the result of the previous operation. 0 if positive, 1 if negative.

2. Zero Flag (ZF) - b6

This is set to 1 if the result of the previous operation is zero and 0 if the result is nonzero.

3. Parity Flag (PF) - b2

This is set to 1 if the low-order 8 bits of the result of the previous operation contain an even number of 1s. Otherwise, it is reset to 0.


4. Carry Flag (CF) - b0

An addition causes this flag to be set to 1 if there is a carry out of the MSB, and a subtraction causes it to be set to 1 if a borrow is needed.

5. Overflow Flag (OF) - b11

This is set to 1 if an overflow occurs, i.e., a result is out of range. More specifically, for addition this flag is set to 1 when there is a carry into the MSB and no carry out of the MSB or vice-versa. For subtraction, it is set to 1, when the MSB needs a borrow and there is no borrow from the MSB, or vice-versa.

6. Auxiliary Carry Flag (AF) - b4

This flag is used exclusively for BCD arithmetic. It is set to 1 if there is a carry out of bit 3 (b3) during an addition or a borrow by bit 3 during a subtraction.


Examples:

0010 0011 0100 0101+ 0011 0010 0001 1001

0101 0101 0101 1110

SF = 0 ZF = 0 PF = 0 CF = 0 AF = 0 OF = 0

1101 0111 1011 1001+ 1101 0111 0111 1010

1010 1111 0011 0011SF = 1 ZF = 0 PF = 1 CF = 1 AF = 1 OF =1

1110 1011 1110 0110+ 1011 1111 0110 1100

1010 1011 0101 0010SF = 1 ZF = 0 PF = 0 CF = 1 AF = 1 OF =1

0101 0110 0111 1110- 0100 1110 1110 1010

0000 0111 1001 0100SF = 0 ZF = 0 PF = 0 CF = 0 AF = 0 OF = 0


The control flags are:

1. Direction Flag (DF) - b10

This flag is used by string manipulation instructions. If clear, the string is processed from its beginning with the first element having the lowest address. Otherwise, the string is processed from the high address towards the low address.

2. Interrupt Enable Flag (IF) - b9

If set, a certain type of interrupt (a maskable interrupt) can be recognized by the CPU; otherwise, these interrupts are ignored.

3. Trap Flag (TF) - b8

If set, the 8086/8088 will enter into a single-step mode. In this mode, the CPU executes one instruction at a time.


SEGMENT REGISTERS AND MEMORY SEGMENTATION

F Even though the 8086/8088 has a 1 MB memory address space, not all this memory can be active at any one time.

F The MM can be prartitioned into 64 K (65,536) byte segments where each segment represents an independently addressable unit of memory consisting of 64 K consecutive byte-wide storage locations.

F Each segment is assigned a base address that identifies its starting point, that is, its lowest-addressed byte storage location.


GENERATING A MEMORY ADDRESS

F A logical address in the 8086/8088 is identified by a segment (its base address) and an offset. The offset identifies the distance in bytes that the storage location of interest resides from this starting address.

F Both segment base address and offset are 16 bits long. Therefore, the lowest-addressed byte in a segment has an offset of 0000H and the highest-addressed byte has an offset of FFFFH.

F However, the physical addresses that are used to access memory are 20 bits long. The generation of the physical address involves combining a 16-bit offset value and a 16-bit segment base address value that is shifted-left by 4 bits with its LSB’s being filled with 0s.


Examples:

1. Segment Base Address = 1234HOffset Address = 0022H

Computing for the physical address:

Physical Segment Base Address = 12340H+ Offset Address = 0022H

Physical Address = 12362H

2. Segment Base Address = 123AHOffset Address = 341BH

Computing for the physical address:

Physical Segment Base Address = 123A0H+ Offset Address = 341BH

Physical Address = 157BBH

F Take note that the offset address is sometimes called the effective address.

F Logical addresses are often written following the segment base address:offset format.

Example: 1234H:0022H


F Only four of these segments can be active at any one time. They are the code segment, stack segment, data segment, and extra segment.

F The locations of the segments of memory that are active are identified by the value of the address held in the 8086/8088’s four internal segment registers; CS, SS, DS, and ES.


F The segments are:

1. Code Segment. This contains the program or code. The address of the next instruction executed by the 8086/8088 is generated by adding the contents of IP (offset address) to the contents of CS x 10H.

2. Data Segment. This contains data referenced by almost all instructions and many addressing modes. Data are almost always moved into or out of MM via the data segment. The physical address of the data is generated by adding the contents of one of the index or pointer registers (BX, DI, or SI) to the contents of DS x 10H.

3. Stack Segment. This is for the LIFO stack. The physical address is a combination of the contents stack pointer (SP) plus SS x 10H.

4. Extra Segment. This is normally for string instructions. When a string instruction is executed, the destination location is addressed by the destination index register (DI) plus ES x 10H.


THE STACK

F The stack is implemented in MM of the 8086/8088. It is 64 KB long and is organized from a software point of view as 32 K words.

F The lowest-addressed byte in the current stack is pointed to by the base address in the SS register.

F Any number of stacks may exist in the 8086/8088. A new stack can be brought in by simply changing the value in the SS register. However, only one may be active at any one time.

F The SP contains an offset from the value in SS. The address obtained in the SS and SP is the physical address of the top of the stack or TOS (the last storage location in the stack to which data were pushed).

F The value of SP is initialized to FFFFH upon start-up of the microcomputer. Combining the value with the current value in SS gives the highest-addressed location in the stack (bottom of the stack). The stack grows down in memory from offset FFFFH to 0000H.


F Whenever a word of data is pushed onto the stack, the high-order 8 bits are placed in the location addressed by SP - 1, and the low-order 8 bits are placed in the location addressed by SP - 2.

SP is then decremented by 2 so that the next word of data is stored in the next available memory location.

Example:

PUSH BX

Assume: BX = 1234HSS = 1800H SP = 3A74H

Bottom of the Stack = SS x 10H + FFFFH = 18000H + FFFFH = 27FFFH

Stack Segment = 18000H up to 27FFFH

Top of the Stack = SS x 10H + SP = 18000H + 3A74H = 1BA74H

PUSH BX; 1BA73H (BH) = 12H1BA72H (BL) = 34H

New Top of Stack = 1BA72H (SP = 3A72H)


F Whenever a word of data is popped from the stack, the low-order 8 bits are removed from the location addressed by SP, and the high-order 8 bits are removed from the location addressed by SP + 1.

SP is then incremented by 2.

Example:

POP CX

Assume: SS = 1234H SP = 281AH

Bottom of the Stack = SS x 10H + FFFFH = 12340H + FFFFH = 2233FH

Stack Segment = 12340H up to 2233FH

Top of the Stack = SS x 10H + SP = 12340H + 281AH = 14B5AH

POP CX; CL (14B5AH) CH (14B5BH)

New Top of Stack = 14B5CH (SP = 281CH)


ADDRESSING MODES

F Addressing modes refer to the way in which an operand is specified.

F Data Addressing Modes:

Case Study: MOV destination, source

1. Register Addressing. The operand to be accessed is specified as residing in an internal register of the 8086/8088.

Examples:MOV AX, CX; AX [CX]MOV BX, DX; BX [DX]

In both examples, AX and BX are the destination operands while CX and DX are the source operands.

2. Immediate Addressing. The source operand is part of the instruction instead of the contents of a register. Typically, immediate operands represent constant data.

Examples:MOV AL, 15H; AL 15HMOV AX, 1A3F; AX 1A3FH


3. Direct Addressing. The location following the instruction opcode holds an effective memory address (EA) instead of data. This EA is the 16-bit offset of the storage location specified by the current value of the DS register.

Examples:

MOV AX, BETA

AX [DS x 10H + BETA]

If BETA = 1234H and DS = 0200H, then:

PA = DS x 10H + BETA= 02000H + 1234H = 03234H

MOV AX, BETA; AX [03234H]

AL [03234H]AH [03235H]


MOV AX, LIST

AX [DS x 10H + LIST]

If LIST = 000AH and DS = BAAFH, then:

PA = DS x 10H + LIST= BAAF0H + 000AH = BAAFAH

MOV AX, LIST; AX [BAAFAH]

AL [BAAFAH]AH [BAAFBH]

MOV CL, [2000H]

CL [DS x 10H + 2000H]

If DS = 1000H, then:

PA = DS x 10H + 2000H= 10000H + 2000H = 12000H

MOV CL, [2000H]; CL [12000H]


4. Register Indirect Addressing. Similar to direct addressing but this time, the EA resides in either a base register (BX, BP) or index register (SI, DI) within the 8086/8088.

Examples:

MOV AX, [BX]; AX [DS x 10H + BX]

If BX = C15EH and DS = 1829H, then:PA = DS x 10H + BX

= 18290H + C15EH = 243EEH

MOV AX, [BX]; AX [243EEH]

AL [243EEH]AH [243EFH]

MOV AX, [SI]; AX [DS x 10H + SI]

If SI = 00BEH and DS = 58A2H, then:PA = DS x 10H + SI

= 58A20H + 00BEH = 58ADEH

MOV AX, [SI]; AX [58ADEH]

AL [58ADEH]AH [58ADFH]


If BP is used, then the stack segment is addressed instead of the data segment

Example:

MOV CX, [BP]; AX [SS x 10H + BP]

If BP = 1800H and SS = 8050H, then:

PA = SS x 10H + BP= 80500H + 1800H = 81D00H

MOV CX, [BP]; CX [81D00H]

CL [81D00H]CH [81D01H]


5. Register Relative Addressing or Base Addressing. The physical address of the operand is obtained by adding a direct or indirect displacement to the contents of either BX or BP and the current value in DS or SS, respectively.

Examples:

MOV AX, [BX + 1000H]

AX [DS x 10H + BX + 1000H]

If BX = 0100H and DS = 0200H, then:

PA = DS x 10H + BX + 1000H= 02000H + 0100H + 1000H= 03100H

MOV AX, [BX + 1000H]; AX [03100H]

AL [03100H]AH [03101H]


MOV AL, [BX] + BETA

AX [DS x 10H + BX + BETA]

If BX = 1000H, BETA = 1234H and DS = 0200H, then:

PA = DS x 10H + BX + BETA= 02000H + 1000H + 1234H= 04234H

MOV AL, [BX] + BETA;AL [04234H]

MOV DI, SET+[BX]

DI [DS x 10H + SET + BX]

If BX = FB04H, SET = 001AH, and DS = 0210H, then:

PA = DS x 10H + SET + BX= 02100H + 001AH + FB04H= 11C1EH

MOV DI, SET[BX]; DI [11C1EH]

DIlow [11C1EH]DIhigh [11C1FH]


6. Base-Plus-Index Addressing. This is used to transfer a byte or word between a register and the memory location indicated by the sum of a base register and an index register.

Examples:

MOV AX, [BX + SI]

AX [DS x 10H + BX + SI]

If SI = 2000H, BX = 1234H, and DS = 0200H, then:

PA = DS x 10H + BX + SI= 02000H + 1234H + 2000H= 05234H

MOV AX, [BX + SI]; AX [05234H]

AL [05234H]AH [05235H]


MOV [BX + DI], SP

[DS x 10H + BX + DI] SP

If DI = 175CH, BX = 1256H, and DS = 0205H, then:

PA = DS x 10H + BX + DI= 02050H + 1256H + 175CH= 04A02H

MOV [BX + SI], SP; 04A02H [SP]

04A02H [SPlow]04A03H [SPhigh]


7. Base-Relative-Plus-Index Addressing. This is used to transfer a byte or word between a register and the memory location addressed by a base register and an index register plus a displacement.

Examples:

MOV AX, [BX + SI + 0100H];

AX [DS x 10H + BX + SI + 1000H]

If DS = 1000H, BX = 0020H, and SI = 0010H, then:

PA = DS x 10H + BX + SI + 1000H= 10000H + 0020H + 0010H + 1000H= 11030H

MOV AX, [BX + SI + 1000H];

AX [11030H]

AL [11030H]AH [11031H]


MOV AX, FILE[BX + DI];

AX [DS x 10H + BX + DI + FILE]

If DS = 1F00H, BX = 3000H, DI = 0015H, AND FILE = 1234H, then:

PA = DS x 10H + BX + DI + FILE= 1F000H + 3000H + 0015H + 1234H= 23249H

MOV AX, FILE[BX + DI];

AX [23249H]

AL [23249H]AH [2324AH]


8086/8088 ARCHITECTURE

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