8086 pin configuration
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![Page 1: 8086 pin configuration](https://reader034.fdocuments.us/reader034/viewer/2022051301/5a66632f7f8b9a47688b5dc7/html5/thumbnails/1.jpg)
8086 PIN CONFIGURATION
Sridari Iyer
St. Francis Inst. of Tech
Borivali (W), Mumbai
![Page 2: 8086 pin configuration](https://reader034.fdocuments.us/reader034/viewer/2022051301/5a66632f7f8b9a47688b5dc7/html5/thumbnails/2.jpg)
8086
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40 pin-DIP
(Dual Inline Package)
![Page 3: 8086 pin configuration](https://reader034.fdocuments.us/reader034/viewer/2022051301/5a66632f7f8b9a47688b5dc7/html5/thumbnails/3.jpg)
8086
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VccGND
GND
1 Power pin
2 Ground pins
![Page 4: 8086 pin configuration](https://reader034.fdocuments.us/reader034/viewer/2022051301/5a66632f7f8b9a47688b5dc7/html5/thumbnails/4.jpg)
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8086
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VccGND
GND
CLK
RESET
CLKβ’ Sync events
with a 8284 (clock)
RESET = 1 (for 4 clk cycles)
β’ Terminate current activity.
β’ Clears all registers and empties the instruction queue
![Page 5: 8086 pin configuration](https://reader034.fdocuments.us/reader034/viewer/2022051301/5a66632f7f8b9a47688b5dc7/html5/thumbnails/5.jpg)
READY
8086
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VccGND
GND
CLK
RESET
READY = 1β’Data transfer
is complete.β’Processor is
ready for execution
READY = 0β’Processor is
waiting for some resource.
![Page 6: 8086 pin configuration](https://reader034.fdocuments.us/reader034/viewer/2022051301/5a66632f7f8b9a47688b5dc7/html5/thumbnails/6.jpg)
Time Multiplexing
When the same pin has different functions during different time cycles,
that pin is said to be time multiplexed.
Arenβt all humans time multiplexed?
![Page 7: 8086 pin configuration](https://reader034.fdocuments.us/reader034/viewer/2022051301/5a66632f7f8b9a47688b5dc7/html5/thumbnails/7.jpg)
7/17/2017
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
8086
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VccGND
GND
AD15
CLK
RESET
READY
D0 β D15
16-bit data line
A0 β A15
Lower 16 bits of address line
ALE = 1Line carries address
ALE = 0Line carries data
ALE
![Page 8: 8086 pin configuration](https://reader034.fdocuments.us/reader034/viewer/2022051301/5a66632f7f8b9a47688b5dc7/html5/thumbnails/8.jpg)
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8086
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VccGND
GND
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
A19 / S6
A18 / S5
A17 / S4
A16 / S3
AD15
CLK
RESET
READY
A16 β A19
Higher 4 bits of address line
S3 β S6
Status Signals
![Page 9: 8086 pin configuration](https://reader034.fdocuments.us/reader034/viewer/2022051301/5a66632f7f8b9a47688b5dc7/html5/thumbnails/9.jpg)
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8086
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VccGND
GND
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
A19 / S6
A18 / S5
A17 / S4
A16 / S3
AD15
CLK
RESET
READY
S3 S4 Segment
0 0 Extra
0 1 Stack
1 0 Code
1 1 Data
S5 indicates interrupt flag is set
S6 is 0 when 8086 is BM
![Page 10: 8086 pin configuration](https://reader034.fdocuments.us/reader034/viewer/2022051301/5a66632f7f8b9a47688b5dc7/html5/thumbnails/10.jpg)
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8086
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VccGND
GND
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
A19 / S6
A18 / S5
A17 / S4
A16 / S3
AD15
CLK
RESET
READY
INTRNMI
INTRInterrupt Request
NMINon-MaskableInterrupt
![Page 11: 8086 pin configuration](https://reader034.fdocuments.us/reader034/viewer/2022051301/5a66632f7f8b9a47688b5dc7/html5/thumbnails/11.jpg)
Active High / Active Low?
β’Describes how a pin is activated.
β’Active high pins are enabled when set to 1
β’Active low pins are enabled when set to 0
β’By default all pins are directly connected to the Vcc.
β’Active low pins are connected via NOT gate
β’If we do not want certain pins to be active by default, we will reverse their role.
![Page 12: 8086 pin configuration](https://reader034.fdocuments.us/reader034/viewer/2022051301/5a66632f7f8b9a47688b5dc7/html5/thumbnails/12.jpg)
Why active low pins?
Consider a water tank.
When tank is filled more than half,
assume L = 1
When tank falls to less than half
assume L = 0
i.e., L indicates the water level.
When should the water pump motor start?
When L = 0
Or L = 1 ??
![Page 13: 8086 pin configuration](https://reader034.fdocuments.us/reader034/viewer/2022051301/5a66632f7f8b9a47688b5dc7/html5/thumbnails/13.jpg)
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8086
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VccGND
GND
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
π΅π»πΈ / S7
AD15
CLK
RESET
A19 / S6
A18 / S5
A17 / S4
A16 / S3
READY
INTRNMI
BHE = 0Enable data on D8 βD15
BHE = 1Enable data on D0 βD7
S7 reserved for future
BHE A0 Access
0 0 16-bit word (D15 β D0)
0 1 Upper byte (D15 β D8)
1 0 Lower byte (D7 β D0)
1 1 Invalid
![Page 14: 8086 pin configuration](https://reader034.fdocuments.us/reader034/viewer/2022051301/5a66632f7f8b9a47688b5dc7/html5/thumbnails/14.jpg)
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VccGND
GND
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
π΅π»πΈ/ S7
AD15
CLK
RESET
A19 / S6
A18 / S5
A17 / S4
A16 / S3
READY
ππΈππINTRNMI
TEST = 0Wait instruction
TEST = 1Resume execution
![Page 15: 8086 pin configuration](https://reader034.fdocuments.us/reader034/viewer/2022051301/5a66632f7f8b9a47688b5dc7/html5/thumbnails/15.jpg)
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VccGND
GND
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
π΅π»πΈ/ S7
AD15
CLK
RESET
A19 / S6
A18 / S5
A17 / S4
A16 / S3
READY
ππΈππ
π π·
INTRNMI
RD = 0Read
RD = 1No read
![Page 16: 8086 pin configuration](https://reader034.fdocuments.us/reader034/viewer/2022051301/5a66632f7f8b9a47688b5dc7/html5/thumbnails/16.jpg)
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8086
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VccGND
GND
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
π΅π»πΈ/ S7
AD15
CLK
RESET
A19 / S6
A18 / S5
A17 / S4
A16 / S3
READY
ππΈππ
π π·MN / ππ
INTRNMI
0Max Mode
1Min Mode
![Page 17: 8086 pin configuration](https://reader034.fdocuments.us/reader034/viewer/2022051301/5a66632f7f8b9a47688b5dc7/html5/thumbnails/17.jpg)
Modes of Operation
Processor needs control over the address, data and control buses to access memory and I/O devices.
β’ Minimum mode β single processor modeβ’ Processor issues control signals
β’ Maximum mode β multi processor modeβ’ The bus controller issues control signals
These modes of operations are available only in 8086/88.
![Page 18: 8086 pin configuration](https://reader034.fdocuments.us/reader034/viewer/2022051301/5a66632f7f8b9a47688b5dc7/html5/thumbnails/18.jpg)
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VccGND
GND
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
π΅π»πΈ/ S7
AD15
CLK
RESET
A19 / S6
A18 / S5
A17 / S4
A16 / S3
READY
ππΈππ
π π·ππ
INTRNMI
HOLD
HLDAππ M / πΌπDT / π
π·πΈπALE
πΌπππ΄
π π / GT0
π π / GT1
LOCK
ππ
π2QS0
π1
QS1
MN /
![Page 19: 8086 pin configuration](https://reader034.fdocuments.us/reader034/viewer/2022051301/5a66632f7f8b9a47688b5dc7/html5/thumbnails/19.jpg)
Minimum Mode
![Page 20: 8086 pin configuration](https://reader034.fdocuments.us/reader034/viewer/2022051301/5a66632f7f8b9a47688b5dc7/html5/thumbnails/20.jpg)
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8086
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VccGND
GND
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
π΅π»πΈ/ S7
AD15
CLK
RESET
A19 / S6
A18 / S5
A17 / S4
A16 / S3
READY
ππΈππ
π π·MN / ππ
INTRNMI
HOLD
HLDA
When the DMA controller wants to take control of the data bus, it seeks the permission of the processor by setting HOLD.Processor gives permission by setting HLDA.
![Page 21: 8086 pin configuration](https://reader034.fdocuments.us/reader034/viewer/2022051301/5a66632f7f8b9a47688b5dc7/html5/thumbnails/21.jpg)
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8086
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VccGND
GND
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
π΅π»πΈ/ S7
AD15
CLK
RESET
A19 / S6
A18 / S5
A17 / S4
A16 / S3
READY
ππΈππ
π π·MN / ππ
INTRNMI
HOLD
HLDAππ
![Page 22: 8086 pin configuration](https://reader034.fdocuments.us/reader034/viewer/2022051301/5a66632f7f8b9a47688b5dc7/html5/thumbnails/22.jpg)
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8086
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VccGND
GND
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
π΅π»πΈ/ S7
AD15
CLK
RESET
A19 / S6
A18 / S5
A17 / S4
A16 / S3
READY
ππΈππ
π π·MN / ππ
INTRNMI
HOLD
HLDAππ M / πΌπ
![Page 23: 8086 pin configuration](https://reader034.fdocuments.us/reader034/viewer/2022051301/5a66632f7f8b9a47688b5dc7/html5/thumbnails/23.jpg)
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8086
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VccGND
GND
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
π΅π»πΈ/ S7
AD15
CLK
RESET
A19 / S6
A18 / S5
A17 / S4
A16 / S3
READY
ππΈππ
π π·MN / ππ
INTRNMI
HOLD
HLDAππ M / πΌπDT / π
0Receive
1Transmit
![Page 24: 8086 pin configuration](https://reader034.fdocuments.us/reader034/viewer/2022051301/5a66632f7f8b9a47688b5dc7/html5/thumbnails/24.jpg)
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8086
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VccGND
GND
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
π΅π»πΈ/ S7
AD15
CLK
RESET
A19 / S6
A18 / S5
A17 / S4
A16 / S3
READY
ππΈππ
π π·MN / ππ
INTRNMI
HOLD
HLDAππ M / πΌπDT / π
π·πΈπ
Enables the data on the external buffers
![Page 25: 8086 pin configuration](https://reader034.fdocuments.us/reader034/viewer/2022051301/5a66632f7f8b9a47688b5dc7/html5/thumbnails/25.jpg)
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8086
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VccGND
GND
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
π΅π»πΈ/ S7
AD15
CLK
RESET
A19 / S6
A18 / S5
A17 / S4
A16 / S3
READY
ππΈππ
π π·MN / ππ
INTRNMI
HOLD
HLDAππ M / πΌπDT / π
π·πΈπALE
ALE=0Carry Data
ALE =1Carry Address
![Page 26: 8086 pin configuration](https://reader034.fdocuments.us/reader034/viewer/2022051301/5a66632f7f8b9a47688b5dc7/html5/thumbnails/26.jpg)
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8086
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30
29
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VccGND
GND
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
π΅π»πΈ/ S7
AD15
CLK
RESET
A19 / S6
A18 / S5
A17 / S4
A16 / S3
READY
ππΈππ
π π·MN / ππ
INTRNMI
HOLD
HLDAππ M / πΌπDT / π
π·πΈπALE
πΌπππ΄
![Page 27: 8086 pin configuration](https://reader034.fdocuments.us/reader034/viewer/2022051301/5a66632f7f8b9a47688b5dc7/html5/thumbnails/27.jpg)
Maximum Mode
![Page 28: 8086 pin configuration](https://reader034.fdocuments.us/reader034/viewer/2022051301/5a66632f7f8b9a47688b5dc7/html5/thumbnails/28.jpg)
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8086
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38
37
36
35
34
33
32
31
30
29
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21
VccGND
GND
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
π΅π»πΈ/ S7
AD15
CLK
RESET
A19 / S6
A18 / S5
A17 / S4
A16 / S3
READY
ππΈππ
π π·MN / ππ
INTRNMI
ππ
π2
π1
S0 S1 S2 Status
0 0 0 Interrupt Ack
0 0 1 I/O Read
0 1 0 I / O Write
0 1 1 HALT
1 0 0 Instruction Fetch
1 0 1 Memory Read
1 1 0 Memory Write
1 1 1 Inactive
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1
2
3
4
5
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7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VccGND
GND
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
π΅π»πΈ/ S7
AD15
CLK
RESET
A19 / S6
A18 / S5
A17 / S4
A16 / S3
READY
ππΈππ
π π·MN / ππ
INTRNMI
ππ
π2
π1
QS0
QS1
Instruction Queue Status pins
QS0 QS1 Status
0 0 No Operation
0 1 First byte of opcode from Queue
1 0 Empty Queue
1 1 Subsequent bytes of opcode
![Page 30: 8086 pin configuration](https://reader034.fdocuments.us/reader034/viewer/2022051301/5a66632f7f8b9a47688b5dc7/html5/thumbnails/30.jpg)
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8086
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7
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11
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13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VccGND
GND
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
π΅π»πΈ/ S7
AD15
CLK
RESET
A19 / S6
A18 / S5
A17 / S4
A16 / S3
READY
ππΈππ
π π·MN / ππ
INTRNMI
π π / GT0
π π / GT1
ππ
π2
π1
QS0
QS1
Signals for resource sharing between processors.RQ β Request
GT - Grant
![Page 31: 8086 pin configuration](https://reader034.fdocuments.us/reader034/viewer/2022051301/5a66632f7f8b9a47688b5dc7/html5/thumbnails/31.jpg)
7/17/20177/17/20177/17/20177/17/20177/17/2017
8086
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VccGND
GND
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
π΅π»πΈ/ S7
AD15
CLK
RESET
A19 / S6
A18 / S5
A17 / S4
A16 / S3
READY
ππΈππ
π π·MN / ππ
INTRNMI
π π / GT0
π π / GT1
LOCK
ππ
π2
π1
QS0
QS1
Lock the peripherals
![Page 32: 8086 pin configuration](https://reader034.fdocuments.us/reader034/viewer/2022051301/5a66632f7f8b9a47688b5dc7/html5/thumbnails/32.jpg)