8085micro Processor Notes 111225091948 Phpapp02

8/13/2019 8085micro Processor Notes 111225091948 Phpapp02

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?ith developments in integration technology Intel was able to integrate the additional chips li&e 177+

cloc& generator and the 1771 system controller along with 11 microprocessor with in a single

chip and released the 1 bit microprocessor 11< in the year /=0. 'he 11< microprocessor

consisted of 0


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'he =.< million transistors based chip, Intel entium II processor was released in //=. It wor&s at

a cloc& speed of ;M.89. entium II uses the 2ynamic 4)ecution 'echnology which consists of

three different facilities namely, Multiple branch prediction, 2ata flow analysis, and Speculative

e)ecution unit. Another important feature is a thermal sensor located on the mother board can

monitor the die temperature of the processor. (or thermal management applications.

Intel Celeron rocessors were introduced in the year ///. entium*III processor with /.< million

transistors was introduced in ///. It also uses dynamic e)ecution micro*architecture, a uni@ue

combination of multiple branch prediction, dataflow analysis and speculative e)ecution. 'he

entium III has improved MMD and processor serial number feature. 'he improved MMD enables

advanced imaging, ;2 streaming audio and video, and speech recognition for enhanced Internet

facility.

entium*IE with +7 million transistors and .< 89 cloc& speed was released by Intel in -ovember 7.

'he entium + processor has a system bus with ;.7 *bytes per second of bandwidth. 'his high

bandwidth is a &ey reason for applications that stream data from memory. 'his bandwidth is

achieved with 0+ Fbit wide bus capable of transferring data at a rate of + M89. 'he entium +

processor enables real*time M47 video encoding and near real*time M4+ encoding, allowing

efficient video editing and video conferencing.

Intel with partner 8ewlett*ac&ard developed the ne)t generation 0+*bit processor architecture called IA*

0+ .'his first implementation was named Itanium. Itanium processor which is the first in a family

of 0+ bit products was introduced in the year 7.'he Itanium processor was specially designed

to provide a very high level of parallel processing ,to enable high performance without re@uiring

very high cloc& fre@uencies .:ey strengths of the Itanium architecture include ,up to 0

instructions$cycle. 'he Itanium processor can handle up to 0 simultaneous 0+ Fbit instructions per

cloc& cycle.

'he Itanium II is an IA*0+ microprocessor developed Gointly by 8ewlett*ac&ard "8# and Intel

and released on 5uly 1,77..It is theoretically capable of performing nearly 1 times more wor& percloc& cycle than other CISC and 3ISC architectures due to its parallel computing micro*

architecture. 'he recent Itanium processor features a split >7 cache, adding a dedicated M6 >7

cache for instructions and thereby effectively growing the original 77 cache, which becomes

a dedicated data cache. 'he first Itanium 7 processor "code named Mc:inley# was more powerful

than the original Itanium processor, with appro)imately two times performance.

entium +44 was released by Intel in the year 7; and entium +4 was released in the year 7+.

'he entium 2ual*Core brand was used for mainstream D10*architecture microprocessors from

Intelfrom 70 to 7/ 'he 0+ bit Intel Core7 was released on 5uly 7=,70. In terms of features,

price and performance at a given cloc& fre@uency, entium 2ual*Core processors were positioned

above Celeronbut below Coreand Core 7microprocessors in IntelHs product range. 'he entium

2ual*Core was also a very popular choice for over cloc&ing, as it can deliver optimal performance"when over cloc&ed# at a low price.

'he entium 2ual Core, which consists of 0= million transistors was released on 5anuary 7, 7=. Intel

Core 2uo consists of two cores on one die, a 7 M6>7 cache shared by both cores, and an arbiter

bus that controls both >7 cache and (S6 access.

Core 7 uad processors are multi*chip modulesconsisting of two dies similar to those used in Core 7 2uo,

forming a @uad*core processor. ?hile this allows twice the performance to a dual*core processors

at the same cloc& fre@uency in ideal conditions, this is highly wor&load specific and re@uires

applications to ta&e advantage of the e)tra cores.

;
http://en.wikipedia.org/wiki/X86http://en.wikipedia.org/wiki/Microprocessorhttp://en.wikipedia.org/wiki/Intelhttp://en.wikipedia.org/wiki/Intel_Celeronhttp://en.wikipedia.org/wiki/Intel_Corehttp://en.wikipedia.org/wiki/Intel_Core_2http://en.wikipedia.org/wiki/Megabytehttp://en.wikipedia.org/wiki/Multi-chip_modulehttp://en.wikipedia.org/wiki/X86http://en.wikipedia.org/wiki/Microprocessorhttp://en.wikipedia.org/wiki/Intelhttp://en.wikipedia.org/wiki/Intel_Celeronhttp://en.wikipedia.org/wiki/Intel_Corehttp://en.wikipedia.org/wiki/Intel_Core_2http://en.wikipedia.org/wiki/Megabytehttp://en.wikipedia.org/wiki/Multi-chip_module


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In September.7/, new Core i= models based on the >ynnfield des&top @uad*core processor and the

Clar&sfield@uad*core mobile were added, and models based on the Arrandale dual*core mobile

processor have been announced. 'he first si)*core processor in the Core lineup is the ulftown,

which was launched on March 0, 7. 6oth the regular Core i= and the 4)treme 4dition are

advertised as five stars in the Intel rocessor 3ating.

T%" Int"l &'&( Micro!roc"$$orJ

Intel 11!#

"ii#.3egisters"iii#.'iming and Control unit.

Arit%m"tic and logic unit )A,U*

'he A>! performs all the arithmetic and logical operations li&e addition, subtraction,

complementing, logical A-2, logical %3, logical 4)clusive %3, incrementing and decrementing, rotate,

shift and clear. An A>! is made of many logic gates and adders etc.

'he arithmetic and logic unit consists of the following units

"a#.Accumulator "A#.

"b#.'emporary register.

"c#.(lag register.

)a* Accumulator )A*-

It is an 1*bit register which is treated as a special function register. Most of the arithmetic and logic

operations are performed using this accumulator. All the I$% data transfers between 11< and I$% devices

are performed via accumulator. %ne of the operands for arithmetic operations in A>! is from the

accumulator. After performing the arithmetic operations the result is stored bac& in accumulator. It is from

the accumulator only, the data is sent out to an output device. Similarly, the data from an input device is

read only through the accumulator. 'he data in the accumulator alone can be rotated or shifted. -o other

register can be used for these operations. Certain instructions li&e 2AA are performed using only

accumulator. So, many times the Accumulator register is treated as a default register.

+
http://en.wikipedia.org/wiki/Lynnfield_(microprocessor)http://en.wikipedia.org/wiki/Clarksfield_(microprocessor)http://en.wikipedia.org/wiki/Arrandale_(microprocessor)http://en.wikipedia.org/wiki/Gulftown_(microprocessor)http://en.wikipedia.org/w/index.php?title=Intel_Processor_Rating&action=edit&redlink=1http://en.wikipedia.org/wiki/Lynnfield_(microprocessor)http://en.wikipedia.org/wiki/Clarksfield_(microprocessor)http://en.wikipedia.org/wiki/Arrandale_(microprocessor)http://en.wikipedia.org/wiki/Gulftown_(microprocessor)http://en.wikipedia.org/w/index.php?title=Intel_Processor_Rating&action=edit&redlink=1


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'his is an 1*bit register which is not accessible to the user. 'his register is used by the

microprocessor to load the second operand during arithmetic$logical operations in A>!. 'he final result is

stored in the Accumulator and the flags are set or reset according to the result of the operation. (or

e)ample when MEI M, =8 instruction is fetched, I3 register will receive the opcode for MEI M and the

'emporary register will receive =8.

In arithmetic and logical operations, that involves two operands ,the accumulator provides one operand.

'he other is provided by the temporary register. (or e)ample in A22 C instruction C register

contents are moved to the 'emp. 3egister and the addition of A and 'emp. 3egister contents is

performed by the A>!.

"c#.(lag registerJ 'he flag register is an 1* bit register which generally reflect data conditions in the

accumulator with certain e)ceptions. 8ence this flag register is also &nown as Status register.

'hough this flag register is an eight bit register, it contains only < flag bits and the remaining three

bits are undefined as shown in (ig.;.; In the (lag register each flag bit is a (lip*(lop. i.e., the bit

may be either in the flip state or flop state

Figur" 0. Flag R"gi$t"r

S Sign Flag

After e)ecution of an arithmetic and logic operation, if bit 2=of the result "-ormally in the Accumulator#is , the sign flag is set. 'his (lag is used with signed numbers.(or e)ample in a given byte, if 2 = is

, the number is treated as a negative number. 4lse "if it is 9ero#, it is viewed as a positive. In

arithmetic operations with signed numbers bit 2=is reserved for indicating the sign and the

remaining seven bits are used to denote the magnitude of the number.

2 2"ro Flag

'his (lag is set "made # if the result after any arithmetic operation is 9ero, and the flag is reset "made # if

the result is not 9ero. So, this flag is set or reset based on the results in the accumulator as well as in

the other registers.

AC 3 Au4iliar/ carr/ Flag

In this arithmetic operation, when a carry is generated by and passed on to bit + , the AC flag is set. 'his

flag is used internally for 6C2 arithmetic and is not available for the programmer to change these@uence of a program with a Gump instruction. 6ut the B and CL flags can be used for this

purpose.

PParit/ Flag

If the result after an arithmetic and logical operation has an even number of s, this parity flag is set to

otherwise "if number of s is odd# the flag is reset "made#.

(or e)ample the data byte has even parity and the data byte has odd parity. So

bit.

C5Carr/ lag

After an arithmetic operation, li&e addition, subtraction if there e)ists a carry or barrow, this flag CL is set

to else it is reset "made#

E4am!l" J >et us consider the addition of two binary numbers and and chec& the (lag

register.

0


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2= 2

In the result, the sum is not 9ero, So B*(lag is reset "B#.

'here is a carry from the third bit to fourth bit. So AC (lag is set "AC#.

'he 2=bit, so, the sign (lag is set "S#.

In the result, the no. of s is even. So, parity is even "#.

After addition, there is a carry. So carry (lag is set "CL#.

'he (lag register contents after addition are shown belowJ

2= 2

R"gi$t"r Organi6ation

'he 11< microprocessor has different types of registers. It includes si) , 1 F bit registers "6, C, 2.

4, 8 and >#, one 1*bit Accumulator and two 0*bit registers "S and C#. Also there are two 1*bit

temporary registers ? and B. Among these registers ? and B are not accessible to the user, 'hey are used

by the processor for internal, intermediate operations. 'he remaining registers are accessible to the user.'he organi9ation of 11< registers is shown in Fig. 0.7

'he various registers of 11< are classified into three types. 'hey are

"i#.'emporary registers.

"ii#.eneral purpose registers

"iii#.Special purpose registers.

)i* T"m!orar/ r"gi$t"r$ -

'he 'emporary registers are temporary data registers, ? register and B register. All are 1*bit

registers. 'he temporary data register is associated with the A>! operations. %ne of the operand is stored

in this register. 'his is not accessible to user.

Similarly ? and B are also temporary registers used to hold 1*bit data during e)ecution of certaininstructions.As these registers are internally used by the C!, they are not accessible to the user.

'he ? and B registers are used by the processor during CA>> instruction. ?hen a CA>> instruction is

encountered in any program, the current rogram counter "C# contents are pushed on to the stac&

and the given address is loaded on to C. 'he given address is temporarily stored in ? and B

registers and placed on the bus for the fetch cycle. 'hus the program control is transferred to the

address given in the instruction.

Another e)ample is, during the e)ecution of DC8 instruction, the contents of 8*> pair are e)changed

with 2*4 pair. At the time of e)change ? and B registers are used for temporary storage of data.

)ii* 8"n"ral !ur!o$" r"gi$t"r$J

6, C, 2, 4, 8 and > are si), 1*bit general purpose registers to store data. 'hese registers can be

used as separate 1*bit registers and also can be paired as 0*bit registers to store the address of a memory

location. 6ut they must be paired as 6*CN 2*4 and 8*> register pairs only as shown below.

=


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Figur" 7. R"gi$t"r organi6ation

?hen used as pair, for e)ample 6*C, the higher order byte moves to the first register "6# and the low order

byte moves to the second register "C#. 'he 8*> pair also functions as a data pointer or memory

pointer

(or 4)J >DI 8, 1


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Au4iliar/ carr/ Flag-'his flag is set if there is a carry from ; rdbit to +thbit during 6C2 operations "carry

from lower nibble to higher nibble#. 'his flag is not accessible to the user.

Parit/ Flag-arity is defined by the number of s present in a binary number stored in A register. After

any arithmetic or logical operation, if the result has an even number of s it is called even parity

and the arity (lag is set to . %therwise. i.e. If there is odd number of s in the result, it is called

%dd arity and the arity flag is set .

Program Count"r )PC*-

It is a 0*bit special purpose register, which stores the address of the ne)t instruction to be fetched

or e)ecuted. 'he e)ecution of a program is initiated by loading the C by the address of the first

instruction of the program. %nce the first instruction is e)ecuted, the C is automatically incremented to

point to the ne)t instruction unless a Gump to some specific address occurs. 'his process is repeated till the

last instruction of the program.

In case of 5!M or CA>> instructions, current address is stored in the rogram Counter. 'he

processor then fetches the ne)t instruction from the new address specified by the 5!M or CA>>

instruction. In conditional 5!M and conditional CA>> instructions, if the condition is not

satisfied, the processor increments the rogram Counter by three so that it points the instruction

followed by the conditional 5!M or CA>> instruction. %therwise the processor fetches the ne)tinstruction from the new address specified by 5!M or CA>> instruction.

Stack Point"r )SP*-

It is a 0*bit special purpose register which always stores the address of top of the Stac&. i.e. it

always points to top of the Stac&. Stac& is a part of the memory location used to store the data temporarily.

A stac& wor&s on >ast in (irst out ">I(%# basis. As the Stac& pointer always points to the top of the Stac&,

only top of the Stac& of the memory can be accessed. ?hen a ?rite operation "!S8# ta&es place, the

contents of the stac& pointer is decremented by two so that the S points to the new location. Similarly

when the 3ead operation "%# occurs, the Stac& pointer is incremented by two to point to the ne)t data on

top of the Stac&.

'he Stac& ointer is initiali9ed by load register pair immediate instruction.

4)J >DI S, 1


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Addr"$$9Data Bu"r-'his is an 1*bit bi*directional buffer. It is used to drive multiple)ed address$data

bus. It means low order address bus "A=*A# and data bus "2=*2#. It is also used to tri*state the

multiple)ed address$data bus under certain conditions li&e reset, hold, and halt and also when A$2

bus lines are not in use.

'he address and data bus buffers are used to drive e)ternal address and data buses respectively.

2ue to these buffers the address and data buffers can be tri*stated when they are not in use. In

actual practice, in a microprocessor the driving capacity of the address pins after the internal

buffering may not be ade@uate. So, there will be e)ternal buffer chips also available.

S"rial I9O control-

'his control provides two lines S%2 "Serial %ut 2ata# and SI2 "serial In 2ata# for serial communication.

'hese lines are used during serial data transmission over long distance where data is transmitted

and received bit by bit. 'he Serial %utput 2ata "S%2# pin is used to send data out serially and

serial Input 2ata "SI2# pin is used to receive data serially by the 11< microprocessor.

Int"rru!t control-

'his is an important bloc& related to interrupts. 'his bloc& is lin&ed to the C! through the 1*bit

internal data bus. 'his interrupt control has five interrupt signals. 'hey are '3A, 3S' =.


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INTR- It is only non*vectored interrupt in 11< microprocessor. 'his interrupt has the lowest priority

among all the interrupts. 'his is also a mas&able interrupt and can be disabled using the instruction

2I "2isable Interrupt#. 'he mas& on I-'3 can be removed by e)ecuting 4I "4nable Interrupt#

instruction. ?hen 4I instruction is e)ecuted, the flip flop associated with this is set and the mas& is

removed. 'his is a non*vectored interrupt because when the remaining interrupts are initiali9ed,

they are automatically transferred "vectored# to specific locations on memory page 8 without

any e)ternal hardware. 'hey do not re@uire the signal. 'he necessary hardware is already

implemented inside the 11"$t !riorit/

Timing and control Unit'his unit of the microprocessor issues necessary timing and control signals for the e)ecution of

instructions. It generates three types of signals namely status, control and timing signals re@uired for the

operation of memory and I$% devices. 'his unit with the help of these signals controls the entire operation

of the microprocessor and the peripherals. 'he signals associated with this unit are two control signals.

and three status signals I%$ , Sand S to identify the nature of the operation and one special signal

A>4 which indicates the starting of the operation. 'hese signals are e)plained below in detail.

*3ead "active low#J 'his is a 3ead control signal. 'his signal indicates that the selected I$% or memory

device is to be read and data are available on the data bus.

S.- o Interrupts Call locations

7

;

+

.

Po>"r $u!!l/ and clock !in$-


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A&A'- 'hese are the upper half of the 0 bit address lines. 'hese lines are e)clusively used for the

most significant 1 bits of the 0 bits of the0 bit address bus.

Control and Statu$ Signal$-

A,E )Addr"$$ ,atc% Enal"*-'his is a positive going pulse generated every time the 11< begins

an operation. 'he A>48igh indicates that the bits on A2 =*A2are address bits. 'his signal is

mainly used to latch the low order address from the multiple)ed bus and generate a separate set of

eight address lines "A=*A#

"3ead#J 'his is an active low read control pin. 'his signal indicates that the selected I$% or

memory device is to be read and data are available on data bus.

"?rite#J 'his is an active low write control pin. It indicates that the data on the data on the

data bus are to be are to be written into a selected memory or I$% location

IO9 -'his is a status signal used to differentiate between I% and memory operations. ?hen it is

high, it indicates an I$% operation and when it is low, it indicates a memory operation. 'his signal

is combined with and signals to generate I$% and memory control signals.

S1 and S'-'hese are status signals and they indicate the type of machine cycle in progress during

e)ecution of an instruction.

READ5 )In!ut*-'hrough this pin, the microprocessor will &now whether peripheral device is

ready or not for data transfer. If the device is not ready the processor waits. So, this pin helps to

synchroni9e slow devices to the microprocessor.

Int"rru!t $ignal$-

'3A, 3S' =.


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-It is an active low signal. ?hen the signal on this pin goes low, the system is in reset

i.e. the program counter is set to 9ero, the address Q data buses are tristated.

RESETOUT-'his signal is used to 3eset other devices in microprocessor system.

S"rial in!ut9 Out!ut $ignal$-

SID-Serial input 2ata is a pin through which serial data are brought into the micro processor

accumulator after the 3IM instruction is e)ecuted.

SOD-Serial output 2ata pin is used by the microprocessor to output data serially to the e)ternal

devices. Serial data is sent out of the microprocessor by e)ecuting SIM instruction. 'he most

significant bit of accumulator should have the serial bit and 20bit of the accumulator must be made

high to enable the serial data transfer.

Timing Diagram -

'he graphical representation of the time ta&en for the e)ecution of each instruction by a

microprocessor is &nown as timing diagram. 'he e)ecution time is denoted by '*states. %ne '*state is

e@ual to the time period of the internal cloc& signal of the microprocessor

(or 4)J If the internal cloc& fre@uency of 11< microprocessor is ; M8B, %ne '*state is e@ual to

.;;;)*0sec;;;)*/sec. ";;; nano seconds nearly#

As far as e)ecution of instructions is concerned, in 11< microprocessor, each instruction is divided into

two partsJ 'he operation code "opcode# and the operand. 'he opcode tells us what

the operation is and the operand is the necessary information re@uired for the instruction. 'he operand may

be either data or an address or other information re@uired for the instruction.

4ach instruction is divided into machine cycles and each machine cycle is divided into cloc& cycles or '*states

'he first machine cycle is every instruction is the op*code fetch. 2uring this time the opcode is

fetched from memory and returned on the data bus to the microprocessor. 'he 11< machine cycles

are divided into following si) types. 'hey are

. %pcode fetch

7. Memory read

;. Memory write

+. I$% read


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Memory read machine cycle is a machine cycle during which memory is read. (or e)ample, the

instruction >2A 1/8 which is a ;*byte instruction has three memory read cycles immediately after the

opcode fetch cycle. 'he first two cycles are to get the memory address, in two 1*bit groups "the low*order

part of the address and then the high*order address#. 'he third read cycle is needed to read the data located

at the address previously retrieved. 'his data is then loaded into accumulator.

'he timing diagram for memory read cycle R(or 4)J >2A 778 is shown in Fig :. As shown in the

memory read timing diagram, after the opcode fetch cycle, the first two read cycles have the

address going out over the address bus first for the low*order of the address "78# and then for

the high*order of the address"778#. In the third read cycle, the address of the instruction Gust read

from memory "778# is sent bac& over the address bus in ' and then data from that memory

location is returned over the data bus in '7*';. I%$ goes low at the beginning of the opcode fetch

cycle and remains low during the ne)t three cycles. , on the other hand goes low each time data

on the data bus is to be read into the microprocessor.

Figur" :. Timing diagram or M"mor/ R"ad mac%in" c/cl"

M"mor/ rit" c/cl"-

'his memory write cycle is used when the microprocessor needs to send data out from accumulator

or specific register and then write into the memory. As an e)ample let us consider the instruction M%E M,

A "


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Figur" & .Timing diagram or M"mor/ rit" mac%in" c/cl"

'he timing diagram of the instruction M%E A, M is shown in (ig .1. 'he opcode fetch cycle shows theaddress R78 going out over the address bus and the opcode for the M%E M,A "


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Figur" . Timing diagram or I9O R"ad mac%in" c/cl"

I9O >rit" c/cl"-

2uring this I$% write cycle 2A'A is written into I$% device specified by the port address from the

accumulator. 'he out port instruction has three machine cycles. 'he first one is opcode fetch cycle, second

one is memory read to get the port address and the third cycle is an I$% write cycle. 'he %!' command

writes the data stored in the accumulator over the data bus to the device whose port address was sent out

over the address bus. 'he three machine cycle that forms the outport command has a total of ten '*states.

'he (ig Shows the timing diagram for %!' +8 instruction. +8 is the address of the output device

'he opcode fetch cycle sends the address of the instruction "78# over the address bus while the opcode

"2;8# for the %!' instruction is returns on the data bus. 'he second machine cycle shows the

address of the second byte of the instruction "78# going out over the address bus with the portaddress "1+8# returning over the data bus.

(rom the timing diagram it is clear that, In the third machine cycle the port address "1+8# is sent out over

both the upper and lower parts of the address bus, similar to I$% read cycle whenever the

microprocessor addresses an I$% device, the port address of the device being read is sent out over

both the lower and higher order parts of the address bus.

It is also to be noted that the data in the accumulator is being written to the output device and goes out over

the data bus during '7 *'; states after the port address has been sent over the two parts of the

address bus during 'of the I$% write cycle

7


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'his is shown diagrammatically in the Fig.0.11

Figur" 11 In$truction c/cl"

Mac%in" c/cl"J

Machine cycle is defined as the time re@uired for completing the operation of accessing either

memory or I$% device. In the 11


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According to the word or byte si9e the 11< instructions are classified into three types. 'hey are

"a# %ne byte "single# instructions.

"b#'wo byte instructions.

"c# 'hree byte instructions.

On"3/t" in$truction$- An instruction with only opcode and do not re@uire any dat or address is called a

one byte instruction.

E4- . M%E C, A 8e) code +(8 "one byte#

7. A22 6 8e) code 18 "one byte#

;. CMA 8e) code 7(8 "one byte#

T>o3/t" in$truction$-At wo byte instruction is one which contains an 1*bit op*code and 1*bit operand

"2ata#.

E4- . MEI A, / 8e) code ;4, / "two bytes#

7. A22 6, = 8e) code 1, = "two bytes#

;. S!6 A, < 8e) code /=, < "two bytes#

T%r""3/t" in$truction$-A three byte instruction contains an opcode plus a 0 F bit address.

E4- .>DI 8, 1


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Data tran$"r )co!/* in$truction$

'he data transfer instructions are used to transfer data from one register to another register,

from memory to register or register to memory but not from one memory location to another

memory location. Actually this data transfer instruction copies the data from source to destination

and the contents of the source are not altered. So, the data transfer instruction performs basically

copy operation.

4)amples of data transfer instructions are M%E, MEI "Move Immediate#, >DI ">oad Immediate 8*>

air#, >2A ">oad Accumulator#, S'A "Store Accumulator#, >8>2 ">oad 8*> pair direct#, S8>2

"Store 8*> pair direct#, DC8 "4)change the contents of 8*> pair with 2*4 pair# etcO

E4- MEI A, pair by address 1


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All the logic operations are performed in relation to the contents of the accumulator. 'he CMA instruction

does not affect any flags. 'he e)ecutions of the logical instruction do not affect the contents of the

operand register.

Branc% In$truction$

'hese instructions are very important because they allow the microprocessor to change the

se@uence of a program either conditionally or unconditionally. 'he conditional branch instructions transfer

the program to the specified label when certain condition is satisfied. 'he unconditional branch

instructions transfer the program to the specified location unconditionally.

?e &now that the microprocessor is a se@uential machine. So, it e)ecutes machine codes from one memory

location to the ne)t. 6ranch instructions instruct the microprocessor to go to a different memory

location and the processor continues e)ecuting machine codes from the new location. 'he address

of the new locations either specified e)plicitly or provided by the microprocessor or some times by

additional hardware. 'he 6ranch instructions are classified into three categories. 'hey are

"a#. 5ump instructions

"b#. Call and return instructions"c#. 3estart instructions.

5ump instructions specify memory locations e)plicitly and they are ;*byte instructions. 'hese 5ump

instructions are of two types. 'hey are , !nconditional 5ump and Conditional 5ump.

Unconditional um!-

'his is similar to !nconditional o to statement in 6ASIC. ?hen this instruction is e)ecuted the

0*bit address available immediately in the instruction is loaded into the program counter , so that the ne)t

se@uence of instruction e)ecution starts from this location. 'his !nconditional 5ump instruction enables

the programmer to create continuous loops.

5M "0 bit address#. So, this is a ;*byte instruction where the first byte is op*code and thesecond, third bytes specify memory address.

(or e)ample, the instruction 5M 1


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S. No In$truction D"$cri!tion

5C "0 bit Addr# 5ump on carry "if CL#

7 5-C "0 bit Addr# 5ump on no carry "if CL#

; 5B "0 bit Addr# 5ump on Bero "if B#

+ 5-B "0 bit Addr# 5ump on no Bero "if B#

< 5 "0 bit Addr# 5ump on plus "if 2=N S#

0 5M "0 bit Addr# 5ump on minus "if 2=N S#

= 54 "0 bit Addr# 5ump on 4ven arity "if #

1 5% "0 bit Addr# 5ump on %dd arity "if #

7=


28/87

Tal" 0 #ariou$ conditional um! in$truction$

'o understand the instructions, let us consider the instruction 5C "0 bit address#. 'he meaning of this

instruction is, the microprocessor is instructed to Gump the specified 0 bit memory location if there

e)ists a carry after the arithmetic operation else it will e)ecute the ne)t instruction in the se@uence.

CA,, and RETURN In$truction$

'he microprocessor uses the two instructions CA>> and 34'!3- to implement subroutines. 8ere

CA>> instruction calls a subroutine program which is not a part of the main program and the 34'

instruction at the end of the subroutine program to return the control to the main program.

E4-CA>> "0 bit memory address#

34'

RESET )RST* In$truction

'he 11< processor provides eight 3S' instructions to transfer the program control to a specific location

on page 8. 'hese instructions are *byte instructions. 'he various 3S' instructions and their call

locations are given in the following 'able ;.+

Tal" 7


29/87

Mac%in" control and I9O In$truction$

'here are si) basic machine control instructions. 'hey are

4I "4nable Interrupt#

2I "2isable Interrupt#

-% "-o %peration#

SIM "Set Interrupt Mas 3IM "3ead Interrupt Mas

8>' "8alt#

EI )Enal" Int"rru!t*-'his is a one byte instruction used to enable the interrupt. 'his instruction is used

to enable the interrupts when the microprocessor is reset or the interrupt enable flag is reset after

interrupt ac&nowledge. 'his instruction ta&es one machine cycle with four states. 'he op*code is

(68.

DI )Di$al" Int"rru!t*-'his is a one byte instruction which resets the interrupt enable flag to disable all

the interrupts e)cept '3A. It ta&es one machine cycle with four states. 'he op*code is (;8.

NOP )No O!"ration*- when this instruction is e)ecuted, the microprocessor performs nothing.

Microprocessor spends four states doing nothing. It is a one byte instruction whose op*code is

8.'his instruction is normally used to generate very small time delays of the order of few micro

seconds. 'his -% instruction is also very useful when we are re@uired to insert a few instructions

in the main program additionally .

SIM )S"t Int"rru!t Ma$k*- 'his instruction mas&s the interrupt as desired. 'his is a dual purpose

instruction. 'he first purpose is to set or reset the mas& of the mas&able interrupt. 'he second

purpose is to send the data out through the S%2 pin at pin number + of the microprocessor.

RIM )R"ad Int"rru!t Ma$k*-'his instruction copies the status of the interrupts into the accumulator. It is

also used to read the serial data through the SI2 pin

,T )alt*-After e)ecution of this instruction the microprocessor goes into the halt state. 'he processor

can be restarted by a valid interrupt or by applying a 34S4' signal. 'he microprocessor ta&es


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31/87

;


32/87

ARITMATIC INSTRUCTIONS

;7


33/87

;;


34/87

;+


35/87

;


36/87

;0


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38/87

;1


39/87

;/


40/87

+


41/87

+


42/87

SODF Serial output 2ata .6it 2=of accumulator is latched in to the S%2 output line made available to

serial peripheral if bit 20 .

SOEF Serial output enable.If this bit ,it enables the serial output.

???F 2ont care condition

R:.(F 3eset 3S'=.


43/87

)i#*. R"gi$t"r indir"ct addr"$$ing mod"$-'he 0*bit address location of the operand stored in a register

pair "8*># is given in the instruction. 'he address of the operand is given in an indirect way with

the help of a register pair. 8ence it is called 3egister indirect addressing mode

E4-"#. >DI8 /oad immediate the 8*> pair with the address of the location / pair to

accumulator

)#*. Im!licit Addr"$$ing mod"- 'he mode of instruction which do not specify the operand in the

instruction but it is implicated, is &nown as implicit addressing mode. i.e., the operand is

automatically considered to be in the Accumulator.

E4-"#.CMAN complement the contents of Accumulator

"7#.CMCN Complement carry

";#. 3>CN 3otate Accumulator left by one bit

"+#. 33CN 3otate Accumulator right by one bit

" pair with memory address DD "sayJ /#.

Step7. J Clear accumulator.

Step;. J Add contents of memory location M to accumulator.Step+. J Increment memory pointer "i.e. DD#.

Step


44/87


45/87

Fig 0.1&

E4am!l" +- Addition of two 1*bit numbers whose sum is 0 bits.

E4!lanation-'he first 1*bit number is stored in one memory location "say 1


46/87

Les

-o

Fig 0.1

PRO8RAM-

+0

Stop

'tore the sum in the location0%

Is

!arry

eists )'tore carry in the

XX0* location

'tore +ero in theXX0* location


47/87


48/87

1< =0 8>' Stop the e)ecution

+1


49/87

E4- In!ut- E4 - 1


50/87

Les

-o

Fig .+'PRO8RAM

Addr"$$ o

t%"

m"m

or/

locati

on

"4 ,a"l Mn"monic$ Comm"nt$

O!cod" O!"rand

1 7, >DI 8, 1


51/87

E4- In!ut- E4 - 1


52/87

Les

-o

Fig +1

PRO8RAM-

ADDRES

S

E? 3

C

O

D

E

,ABE, MNEMONIC COMMENTS

OPCO

D

E

OPERAND

1 7A,,1< >8>2 1 pair

1

17 18>2 1%CA'I%-16 4

1C 1

12 %C I-3 C Increment carry

14 77 (?2 S8>2 1S6 of the Sum in 1


53/87

E4- INPUT- 1S6 of the Ist-umber RESU,T-1


54/87

Figur" ++

PRO8RAM-

ADDRESS E?

C

O

D

E


OPCOD

E

OPERAN

D

1 7 >DI 8, 1 pair and get the (irst

number in to 1


55/87

INPUT- E4 - 1 pair with the address of second number "DD#.

Step7. J (ind its tens complement

Step;. J 2ecrement the 8*> pair for the first number "DD#

Step+. J Add the first number to the s complement of second number.

Step C%art

Figur" +0


56/87

PRO8RAM-

ADDRESS E?

C

O

D

E

,AB MNEMONIC COMMENTS

OPCODE OPERAND

1 7 >DI 8,1 pair and get theSecond

number in to 1


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Flo> C%art


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Les

-o

-o


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60/87

A,8ORITM-

Step J Initialise 8*> pair with the address of multiplicand."say 1 pair by 2*4 pair. so that multiplicand is in 2*4 pair.

Step ; J >oad the multiplier in Accumulator.

Step + J Shift the multiplier left by one bit.

Step < J If there is carry add multiplicand to product.

Step 0 J 2ecrement the count.

Step = J If count N o to step +

Step 1 J Store the product i.e. result in memory location.

Step / J Stop the e)ecution

Flo> C%art

0

Start

>oad the multiplier in to Accumulator Q

multiplicand in 2*4 pair

Initial alue of product:00$Count1


61/87

-o

Les

-o

Les

Figur" +(

PRO8RAM-

0

Shift product left by one bit QShiftmultiplier left by one bit

roduct roduct Multiplicand

!ount : count -1

Is carryeists

frommultiplier

)

'tore result

Stop

Iscount :

0 )


62/87

ADDRESS E ,AB MNEMONIC COMMENTS

%C%2

4

%43A-2

1 7A, >8>2 8, 1oad the multiplicand in to 8*> pair

1; 46 DC8 4)change the multiplicand in to 2*4 pair

1+ ;A >2A 1DI 8. Initial value in 8*> pair is

11

1/

1A 4 MEI C,1 Count 1

16 1

1C 7/ >%% 2A2 8 Shift the partial product left by one bit.

12 = 3A> 3otate multiplier left by one bit

14 27 5-C (?2 Is Multiplier bit U -o go to label (?2

1( 71 1

1 / 2A2 2 roduct roduct Multiplicand

17 2 (?2 2C3 C C%!-'C%!-'*

1; C7 5-B >%%

1+ C

1< 1

10 77 S8>2 1


63/87

Di#i$ion Program$

E4am!l" :- Di#i$ion o a 1; it num"r / a &it num"r.

E4!lanation- 'he division of a 0$1*bit number by a 1*bit number follows the successive subtraction

method. 'he divisor is subtracted from the MS6s of the dividend .If a borrow occurs, the bit of the

@uotient is set to else .(or correct subtraction process the dividend is shifted left by one bit

before each subtraction. 'he dividend and @uotient are in a pair of register 8*>.'he vacancy arised

due to shifting is occupied by the @uotient .In the present e)ample the dividend is a 0*bit number

and the divisor is a 1*bit number. 'he dividend is in locations 1 pair with address of dividend.

S'47. J et the divisor from 1


64/87

Flo>c%art

-o

Les

-o Les

Fig.+;

0+

S'A3'

Initialise H-L pair with address of

diidend

!opy the diisor in to "e$ A

# 'hift diidend left 2y one 2it# 'hift ;uotient left 2y one

/ M'3s of diidend :/ M'3s of diidend -diisor

Is!ount :0)

;uotient : ;uotient


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E4- In!ut G R"$ult Address 2ata

1S6 of 2ividend

1


67/87

,arg"$t G Small"$t num"r$ in an Arra/

E4am!l" &- 'o find the largest number in a data array

E4!lanation-'o find the largest number in a data array of - numbers "say#first the count is placed in

memory location "1


68/87


69/87

PRO8RAM

A22 84D F

C

%

2

4

>A64> M-4M%-IC C%MM4-'S

%C%2

4

%43A-2

1 7,,1< >DI 8, 1


70/87

E4 - In!utJ 1


71/87

Flo> C%art

Les

-o

=

S'A3'

Initialise H-L pair

>et the count in "eister !

>et first num2er in toAccumulator

>et smaller num2er inAccumulator

Is

?um2er inAccumulator

?etnum2er )


72/87

-o

Les

Fig.+&

=7

,ecrement !ount

store the result at 1


73/87

PRO8RAM

ADD E? 3

C

O

D

E


OPCOD

E

OPERAN

D

1 7 >DI 8, 1 pair.

1

17 1 pair

1< +4 M%E A,M Move first number in to

Accumulator

10 2 2C3 C 2ecrement the count

1= / >%% I-D 8 et the ne)t number

11 64 CM M Compare the ne)t number with

previous number1/ 27 5C >%%7 Is ne)t number Wprevious

smallest UIf yes go to the

loop7

1A 2

16 1

1C =4 M%E A,M -o,move the smaller number in

to Accumulator

12 2 >%%7 2C3 C 2ecrement the count

14 C7 5-B >%% If count not e@ual to 9ero,repeat

1( =

1 1

17 =1

1; ;7 S'A 1


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75/87

Figur".+ T%" PUS o!"ration o t%" Stack

>et us consider two registers "register pair# 6 Q C whose contents are 7< Q 07.

3eg. 6 3eg. C

After !S8 operation the status of the Stac& is as shown in Fig 0.0'

7< 07

=


76/87

Figur" .0' At"r PUS o!"ration t%" $tatu$ o t%" $tack

=0


77/87

>et us now consider % operationJ 'he Fig$ 0.01 G 0.0+e)plains before and after the % operation in

detail

.

Figur" 0.01 T%" POP o!"ration o t%" Stack

Figur" 0+ At"r POP o!"ration t%" $tatu$ o t%" $tack

6efore the operation the data < and C are in the locations +


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79/87

Suroutin"-It is a set of instructions written separately from the main program to e)ecute a function that

occurs repeatedly in the main program.

(or e)ample, let us assume that a delay is needed three times in a program. ?riting delay programs for

three times in a main program is nothing but repetition. So, we can write a subroutine program

called delay and can be called any number of times we need

Similarly, in 11< microprocessor we do not find the instructions for multiplication and division. (or

this purpose we write separate programs. So, in any main program if these operations are needed

more than once, the entire program will become lengthy and comple). So, we write subroutine

programs M!> Q 2IE separately from main program and use the instruction CA>> M!> "or#

CA>> 2IE in the main program. 'his can be done any number of times. At the end of every

subroutine program there must be an instruction called 34'. 'his will ta&e the control bac& to

main program.

'he 11< microprocessor has two instructions to implement the subroutines. 'hey are CA>> and 34'.

'he CA>> instruction is used in the main program to call a subroutine and 34' instruction is used

at the end of the subroutine to return to the main program. ?hen a subroutine is called, the contents

of the program counter, which is the address of the instruction following the CA>> instruction is

stored on the stac& and the program e)ecution is transferred to the subroutine address. ?hen the

34' instruction is e)ecuted at the end of the subroutine, the memory address stored on the stac& isretrieved and the se@uence of e)ecution is resumed in the main program.

Diagrammatic r"!r"$"ntation

>et us assume that the e)ecution of the main program started at 1 8. It continues until a CA>>

subroutine instruction at 17 8 is encountered. 'hen the program e)ecution transfers to 1= 8.

At the end of the subroutine 1=6 8. 'he 34' instruction is present. After e)ecuting this 34', it

comes bac& to main program at 17 8 as shown in the following Fig. 0.07

Fig.00 Diagrammatic r"!r"$"ntation o $uroutin" !rogram "4"cution

'he same is e)plained using the assembly language program e)ample.

=/


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81/87

M"mor/

Addr"$$

Mn"monic$ O!"rand Comm"nt$

1=

X

X

X

X

1=6

1=C

1=(

Instructions

34'

-e)t Subroutine

34'

6eginning of the Subroutine.

4nd of the program

Instructions of ne)t subroutine if any

4nd of the subroutine.

D"la/ !rogram$-

In many situations it may be desired to provide some delay between the e)ecution of twoinstructions by a microprocessor. 'he delay can be produced by either hardware chip li&e 17


82/87

Calculation o D"la/ tim" or t%" ao#" !rogram-

In the above program register A is loaded by ((8 6"7


83/87

Total T Stat"$H0(&7

'he time re@uired for one '*state in I-'4> 11< microprocessor is nearly ;;n.sec

2elay time is ;o r"gi$t"r$

Program-

Addr"$$ ,a"l Mac%in"

Cod"

Mn"monic O!"rand Comm"nt$

1+ MEI 6, 8 et desired number in register 6

1+7 >%% MEI C, %%7 2C3 C 2ecrement C.

1+< 5-B >%%7 Is RC 9eroU -o, go to >%%7. Les,

proceed further1+1 2C3 6 2ecrement register 6

1+/ 5-B >%% Is R6 9eroU -o, go to >%%. Les,

proceed further

1+C 34' 3eturn to main program.

1;


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(rom the above discussion it is clear that with increase of '*states re@uired for a delay subroutine ,the

delay time also increases.

4

Addr"$$ ,a"l Mac%in"

Cod"

Mn"monic O!"rand Comm"nt$

1+ MEI A, /18 et control word

1+7 %!' ; Initiali9e port foe >42 2isplay

1++ MEI 6, %%;

1+4 2C3 C

1+( 5-B >%%7

1+7 2C3 6

1+; 5-B >%%

1+0 MEI A,

1+1 %!' %utput for >42

1+/ 8>' Stop.

1


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10


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8085micro Processor Notes 111225091948 Phpapp02

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Transcript of 8085micro Processor Notes 111225091948 Phpapp02