8051 Inturrpt

03/30/15 T. L. Jong, Dept. of E.E., NTHU 1

Introduction 8051 Interrupt organization Processing Interrupts Program Design Using Interrupts Timer Interrupts Serial Port Interrupts External Interrupts Interrupt Timings


An interrupt is the occurrence of a condition--an event -- that cause a temporary suspension of a program while the event is serviced by another program (Interrupt Service Routine ISR or Interrupt Handler).

Interrupt-Driven System-- gives the illusion of doing many things simultaneously, quick response to events, suitable for real-time control application.

Base level--interrupted program, foreground. Interrupt level--ISR, background.



Main program (base level, foreground)

Main Main Main Main

ISRISRISR

Time

Interruptlevel execution

Base-levelexecution

Interrupt (occurs asynchronously)

Return from interrupt instruction

Program execution without interrupts

5 interrupt sources: 2 external, 2 timer, a serial port

2 programmable interrupt priority levels fixed interrupt polling sequence can be enabled or disabled IE (A8H), IP (B8H) for controlling interrupts


Two bits must be set to enable any interrupt: the individual enable bit and global enable bit

SETB ET1SETB EA

MOV IE,#10001000B


Bit Symbol Bit Address Description (1=enable, 0=disable)IE.7 EA AFH Global enable/disableIE.6 - AEH Undefined IE.5 ET2 ADH Enable timer 2 interrupt (8052)IE.4 ES ACH Enable serial port interruptIE.3 ET1 ABH Enable timer 1 interruptIE.2 EX1 AAH Enable external 1 interruptIE.1 ET0 A9H Enable timer 0 interrupt IE.0 EX0 A8H Enable external 0 interrupt

0= lower priority, 1= higher priority, reset IP=00H Lower priority ISR can be interrupted by a high

priority interrupt. A high priority ISR can not be interrupted.


Bit Symbol Bit Address Description (1=high, 0=low priority)IP.7 - - UndefinedIP.6 - - Undefined IP.5 PT2 BDH Priority for timer 2 interrupt (8052)IP.4 PS BCH Priority for serial port interruptIP.3 PT1 BBH Priority for timer 1 interruptIP.2 PX1 BAH Priority for external 1 interruptIP.1 PT0 B9H Priority for timer 0 interrupt IP.0 PX0 B8H Priority for external 0 interrupt

The state of all interrupt sources is available through the respective flag bits in the SFRs.

If any interrupt is disabled, an interrupt does not occur, but software can still test the interrupt flag.


Interrupt Flag SFR Register & Bit Position------------------------------------------------------------------------------External 0 IE0 TCON.1External 1 IE1 TCON.3Timer 1 TF1 TCON.7Timer 0 TF0 TCON.5Serial port TI SCON.1Serial Port RI SCON.0Timer 2 TF2 T2CON.7 (8052)Timer 2 EXF2 T2CON.6 (8052)

If two interrupts of the same priority occur simultaneously, a fixed polling sequence determines which is serviced first.

The polling sequence is External 0 > Timer 0 > External 1 > Timer 1 > Serial Port > Timer 2



IE1IT11

0

IE0IT01

0INT0

INT1

TF0

TF1

RI

TI

EXF2

TF2

Interruptenables

Global EnableAccent interrupt

High priorityinterrupt

Lowpriorityinterrupt

Interruptpollingsequence

IP registerIE register

When an interrupt occurs and is accepted by the CPU, the main program is interrupted. The following actions occur: The current instruction completes execution. The PC is saved on the stack. The current interrupt status is saved internally. Interrupts are blocked at the level of the interrupt. The PC is loaded with the vector address of the ISR The ISR executes.

The ISR finishes with an RETI instruction, which retrieves the old value of PC from the stack and restores the old interrupt status. Execution of the main program continues where it left off.


Interrupt vector = the address of the start of the ISR.

When vectoring to an interrupt, the flag causing the interrupt is automatically cleared by hardware. The exception is RI/TI and TF2/EXF2 which should be determined and cleared by software.


Interrupt Flag Vector AddressSystem Reset RST 0000H (LJMP 0030H)External 0 IE0 0003HTimer 0 TF0 000BHExternal 1 IE1 0013HTimer 1 TF1 001BHSerial Port RI or TI 0023HTimer 2 TF2 or EXF2 002BH

I/O event handling: Polling: main program keeps checking the flag,

waiting for the occurrence of the event. Inefficient in some cases.

Interrupt-driven: CPU can handle other things without wasting time waiting for the event. Efficient, prompt if ISR is not so complex. Suitable for control application.

I/O processor: dedicated processor to handle most of the I/O job without CPU intervention. Best but most expensive.



ORG 0000H ;reset entry pointLJMP Main ;takes up 3 bytesORG 0003H ;/INT0 ISR entry point. ;8 bytes for IE0 ISR or. ; jump out to larger IE0 ISRORG 000BH ;Timer 0 ISR entry point..ORG 0030H ;main program entry point

Main: ...

8 bytes for each interrupt vector. Small ISR utilizes the space.

For example: (assume only T0ISR is needed in the case) ORG 0000H LJMP MAIN ORG 000BHT0ISR: . . RETIMAIN: . ;only T0ISR


8 bytes not enough. Use LJMP to large ISR ORG 0000H LJMP MAIN ORG 000BH ; T0 ISR entry point

LJMP T0ISRORG 0030H ;above int vectors

MAIN: ..

T0ISR: . ; Timer 0 ISR.RETI ;return to main



ORG 0 ;reset entry pointLJMP MainORG 000BH ;T0 interrupt vector

T0ISR: CPL P1.0 ;toggle port bitRETIORG 0030H

Main: MOV TMOD,#02H ;T0 MODE 2MOV TH0,#-50 ;50 µS DELAYSETB TR0 ;START TIMER 0MOV IE,#82H ;ENABLE T0 INTSJMP $ ;DO NOTHING


ORG 0 ;reset entry pointLJMP MainORG 000BH ;T0 interrupt vectorLJMP T0ISRORG 001BH ;T1 vectorLJMP T1ISRORG 0030H ;main starts here

Main: MOV TMOD,#12H ;T0 mode 2, T1 mode 1MOV TH0,#-71 ;7-kHz using T0SETB TR0 ;START TIMER 0SETB TF1 ;force T1 intMOV IE,#8AH ;ENABLE T0,T1 INTSJMP $ ;DO NOTHING


T0ISR: CPL P1.7 ;7-kHz on P1.7RETI

T1ISR: CLR TR1 ;stop T1MOV TH1,#HIGH(-1000)MOV TL1,#LOW(-1000)

;1 ms for T1SETB TR1 ;START TIMER 1CPL P1.6 ;500-Hz on P1.6RETI

SPISR must check RI or TI and clears it. TI occurs at the end of the 8th bit time in

mode 0 or at the beginning of stop bit in the other modes. Must be cleared by software.

RI occurs at the end of the 8th bit time in mode 0 or half way through the stop bit in other modes when SM2 =0. If SM2 = 1, RI = RB8 in mode 2,3 and RI = 1 only if valid stop bit is received in mode 1.



;dump ASCII codes to serial portORG 0LJMP MainORG 0023H ;serial port vectorLJMP SPISRORG 0030H ;main entry point

Main: MOV TMOD,#20H ;Timer 1 mode 2MOV TH1,#-26 ;use 1200 baudSETB TR1 ;start T1MOV SCON,#42H ;mode1, set TI to force first

;interrupt; send 1st char.MOV A,#20H ;send ASCII space firstMOV IE,#90H ;enable SP interruptSJMP $ ;do nothing


SPISR: CJNE A,#7FH,Skip ;if ASCII code = 7FHMOV A,#20H ;wrap back to 20H

Skip: MOV SBUF,A ;start to transmitINC ACLR TI ;clear TI flagRETI

The CPU speed is much higher than 1200 baud serial transmission.Therefore, SJMP executes a very large percentage of the time.Time for one char = (1/1200 baud)(8+1+1) = 8333.3 µS compared to1 µS machine cycle!We could replace SJMP instruction with other useful instructionsdoing other things.


#include “io51.h”char *ptr;void InitialUART(int BaudRate) /*Max baudrate = 9600*/{

SCON = 0x52;TMOD = 0x21;TH1 = 256-(28800/BaudRate); /*11.059M/384=28800*/TR1 = 1;

}static const char msg1[]=“UART interrupt message!!”;void main(void){

InitialUART(9600);EA = 1;ptr = msg1;ES = 1;while(1); /*wait for SP interrupt*/

}


interrupt [0x23] void SCON_int(void) /*Serial port ISR*/{

if(RI==1)RI=0; /* we did nothing in this program for RxD */if(TI==1){

TI=0;if(*ptr!=‘\0’) /*string ends with ‘\0’ character*/

{SBUF=*ptr;++ptr;}

else{ES=0; /*complete a string tx, clear ES and let*/TI=1; /*main program decide next move */}

}}

/INT0 (P3.2 or pin12) and /INT1 (P3.3 or pin 13) produce external interrupt in flag IE0 and IE1 (in TCON) in S5P2.

/INT0 and /INT1 are sampled once each machine cycle (S5P2) and polled in the next machine cycle. An input should be held for at least 12 clock cycles to ensure proper sampling.

Low-level trigger (IT0 or IT1 =0): interrupt when /INT0 or /INT1 = 0

Negative edge trigger (IT0 or IT1 = 1): interrupt if sense high on /INT0 or /INT1 in one machine cycle and low in next machine cycle.

IE0 and IE1 are automatically cleared when CPU is vectored to the ISR.


If the external interrupt is low-level triggered (IT0 or IT1 =0), the external source must hold the request active until the requested interrupt is actually generated.

Then it must deactivate the request before the ISR is completed, or another interrupt will be generated.

Usually, an action taken in the ISR causes the requesting source to return the interrupting signal to the inactive state.



INT0

INT1

P1.7

8051

1 = solenoid engaged (furnace on) if T < 19°C0 = solenoid disengaged (furnace off) if T > 21°C

HOT = 0 if T > 21°C

COLD = 0 if T < 19°C

T = 21°C

T = 19°C

T = 20°C

HOT

COLD

P1.7


ORG 0LJMP Main

EX0ISR: CLR P1.7 ;turn furnace offRETIORG 13H

EX1ISR: SETB P1.7 ;turn furnace onRETIORG 0030H

Main: MOV IE,#85H ;enable ext intSETB IT0 ;negative edge triggerSETB IT1SETB P1.7 ;turn furnace on firstJB P3.2,Skip ;if T>21?CLR P1.7 ;yes, turn furnace off

Skip: SJMP $ ;do nothing


INT0 P1.7

805174LS04

Door opens

P1.7

P1.7

2.5 ms

1.25 ms400Hz

1 sec


ORG 0LJMP MainLJMP EX0ISRORG 0BHLJMP T0ISR ;use T0 and R7=20 time 1 sORG 1BHLJMP T1ISR ;use T1 to sound alarm

Main: SETB IT0 ;negative edge triggerMOV TMOD,#11H ;16-bit timerMOV IE,#81H ;enable EX0 only

Skip: SJMP $ ;relax & wait for intrusion


EX0ISR: MOV R7,#20 ;20x50000 µs = 1 sSETB TF0 ;force T0 ISRSETB TF1 ;force T1 ISRSETB ET0 ;enable T0 intSETB ET1 ;enable T1 intRETI

T0ISR: CLR TR0 ;stop T0DJNZ R7,SKIP ;if not 20th time, exitCLR ET0 ;if 20th, disable itselfCLR ET1 ;and toneLJMP EXIT

SKIP: MOV TH0,#HIGH(-50000) ;reload 0.05 s MOV TL0,#LOW(-50000) ;delaySETB TR0 ;turn on T0 again

EXIT: RETI


;T1ISR: CLR TR1 ;stop T1

MOV TH1,#HIGH(-1250) ;count for 400 HzMOV TL1,#LOW(-1250) ;toneCPL P1.7 ;music maestroSETB TR1 ;RETI

Since the external interrupt pins are sampled once each machine cycle, an input high or low should hold for at least 12 oscillator periods to ensure sampling.

If the external interrupt is transition-activated, the external source has to hold the request pin high for at least one cycle, and then hold it low for at least one cycle. This is done to ensure that the transition is seen so that interrupt request flag IEx will be set.

IEx will be automatically cleared by the CPU when the service routine is called.


If the external interrupt is level-activated, the external source has to hold the request active until the requested interrupt is actually generated. Then it has to deactivate the request before the interrupt service routine is completed, or else another interrupt will be generated.


Response Time The /INT0 and /INT1 levels are inverted and

latched into IE0 and IE1 at S5P2 of every machine cycle. The values are not actually polled by the circuitry until the next machine cycle.

If a request is active and conditions are right for it to be acknowledged, a hardware subroutine call to the requested service routine will be the next instruction to be executed. The call itself takes two cycles. Thus, a minimum of three complete machine cycles elapse between activation of an external interrupt request and the beginning of execution of the first instruction of the service routine.


A longer response time would result if the request is blocked by one of the 3 previously listed conditions.1. An interrupt of equal or higher priority level is

already in progress.2. The current (polling) cycle is not the final cycle

in the execution of the instruction in progress. (ensure completion)

3. The instruction in progress is RETI or any write to the IE or IP registers. (one more instruction will be executed)

If an interrupt of equal or higher priority level is already in progress, the additional wait time obviously depends on the nature of the other interrupt’s service routine.


If the instruction in progress is not in its final cycle, the additional wait time cannot be more than 3 cycles, since the longest instructions (MUL and DIV) are only 4 cycles long, and if the instruction in progress is RETI or an access to IE or IP, the additional wait time cannot be more than 5 cycles (a maximum of one more cycle to complete the instruction in progress, plus 4 cycles to complete the next instruction if the instruction is MUL or DIV).

Thus, in a single-interrupt system, the response time is always more than 3 cycles and less than 9 cycles.



RETI MUL AB Save PC ISR

Level 0 ISR Main program Level 0 ISR

9 cycles

Level 1 interrupt occurshere (missed last chancebefore RETI instruction)

Single-Step Operation The 80C51 interrupt structure allows single-step

execution with very little software overhead. As previously noted, an interrupt request will not be responded to while an interrupt of equal priority level is still in progress, nor will it be responded to after RETI until at least one other instruction has been executed. Thus, once an interrupt routine has been entered, it cannot be re-entered until at least one instruction of the interrupted program is executed.

One way to use this feature for single-step operation is to program one of the external interrupts (e.g., /INT0) to be level-activated.


The service routine for the interrupt will terminate with the following code:

JNB P3.2,$ ;Wait Till /INT0 Goes High JB P3.2,$ ;Wait Till /INT0 Goes Low RETI ;Go Back and Execute One Instruction Now if the /INT0 pin, which is also the P3.2 pin, is

held normally low, the CPU will go right into the External Interrupt 0 routine and stay there until /INT0 is pulsed (from low to high to low). Then it will execute RETI, go back to the task program, execute one instruction, and immediately re-enter the External Interrupt 0 routine to await the next pulsing of P3.2. One step of the task program is executed each time P3.2 is pulsed.


Reset The reset input is the RST pin, which is the input

to a Schmitt Trigger. A reset is accomplished by holding the RST pin

high for at least two machine cycles (24 oscillator periods), while the oscillator is running. The CPU responds by generating an internal reset.

The external reset signal is asynchronous to the internal clock. The RST pin is sampled during State 5 Phase 2 of every machine cycle. The port pins will maintain their current activities for 19 oscillator periods after a logic 1 has been sampled at the RST pin; that is, for 19 to 31 oscillator periods after the external reset signal has been applied to the RST pin.



Reset Timing

The internal reset algorithm writes 0s to all the SFRs except the port latches, the Stack Pointer, and SBUF.

The port latches are initialized to FFH (input mode), the Stack Pointer to 07H, and SBUF is indeterminate.

The internal RAM is not affected by reset. On power up the RAM content is indeterminate.


8051 Inturrpt

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