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Table 1 - General Specifications

ITEM SPECIFICATION

FREQUENCY TUNING

MechanicalElectrical

Channel Spacing

FREQUENCY STABILITY

LO POWER OUTPUT

LO NOMINAL IMPEDANCE

PHASE NOISE@25 kHz Offset

HUM AND NOISECompanion Receiver

HARMONICS @ LO PORT

SWITCHING SPEED

CURRENT DRAIN

+13.8V

+12V

REFERENCE OSCILLATORFrequency Output

Power OutputImpedance

EXT. REFERENCE OSCILLATOR

Frequency

PowerImpedance

735.8 MHz-754.8 MHz500 kHz

12.5 kHz

±1.0 ppm

2.0 dBm ±2 dBm

50 ohms

> -136 dBc/Hz

-55 dB

<-30 dBc

< 50 ms

<350 mA

<20 mA

12.8 MHz ±1.0 ppm

1 dBm ± 2 dBm50 ohms

5.00 MHz to 17.925 MHz (must be integerdivisible by the channel spacing)

+10 dBm ±3 dBm into 50 ohms50 ohms

Copyright© December 1993, Ericsson GE Mobile Communications Inc.

Figure 1- Receiver Synthesizer Block Diagram

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OUTLINE DI AGRAM 

RECEIVER SYNTHESIZER BOARD

19D902664G5(19D902664, Sh. 3, Rev. 0)

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IC DATA

U15, U1719A702293P2Dual Operational Amplifier

U6

19B800902P5Synethesizer

U2, U4, U7, U8, U1119A705927P1Silicon Bipolar IC

U12 & U1319A704383P302

Logic Gate/Inverter

U1019A703471P120Decoder/Demux

U519A149944P201Modulus Prescaler

U919A702705P4Quad Analog Switch

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IC DATA

U319A704971P85V Regulator

U1419A705537P2

U1 RYT102217÷2 Prescaler

Y119B801351P12Crystal Oscillator

U16

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ASSEMBLY DIAGRAM 

RECEIVER SYNTHESIZER MODULE19D902781G5(19D902781, Sh. 3, Rev. 1)

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SCHEMATIC DIAGRAM 

RECEIVER SYNTHESIZER MODUL

19D902664G(19D904745, Sh. 1, Rev

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SCHEMATIC DIAGRAM 

RECEIVER SYNTHESIZER MODULE

19D902664G5(19D904745, Sh. 2, Rev. 0)

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SCHEMATIC DIAGRAM 

RECEIVER SYNTHESIZER MODUL

19D902664G(19D904745, Sh. 3, Rev

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SCHEMATIC DIAGRAM 

RECEIVER SYNTHESIZER MODULE

19D902664G5(19D904745, Sh. 4, Rev. 0)

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LBI-3902