UCC1837UCC2837UCC3837

SLUS228A - AUGUST 1999

FEATURES• On Board Charge Pump to Drive

External N-MOSFET

• Input Voltage as Low as 3V

• Duty Ratio Mode Over CurrentProtection

• Extremely Low Dropout Voltage

• Low External Parts Count

• Output Voltages as Low as 1.5V

8-Pin N-FET Linear Regulator Controller

1

5

28

6

3

47

CHARGEPUMP

CAP

LEVELSHIFT

1.5V REF

UVLO

TIMER

CURRENT SENSECOMPARATOR

COMPCT

CSVDD

CURRENT SENSEAMPLIFIER

++

VOUT

FB

GND100mV

140mVERROR AMPLIFIER

BLOCK DIAGRAM

UDG-99145

DESCRIPTIONThe UCC3837 Linear Regulator Controller includes all the features re-quired for an extremely low dropout linear regulator that uses an externalN-channel MOSFET as the pass transistor. The device can operate frominput voltages as low as 3V and can provide high current levels, thus pro-viding an efficient linear solution for custom processor voltages, bus ter-mination voltages, and other logic level voltages below 3V. The on boardcharge pump creates a gate drive voltage capable of driving an externalN-MOSFET which is optimal for low dropout voltage and high efficiency.The wide versatility of this IC allows the user to optimize the setting ofboth current limit and output voltage for applications beyond or betweenstandard 3-terminal linear regulator ranges.

This 8-pin controller IC features a duty ratio current limiting technique thatprovides peak transient loading capability while limiting the averagepower dissipation of the pass transistor during fault conditions. See theApplication Section for detailed information.

2

UCC1837UCC2837UCC3837

CONNECTION DIAGRAM

ELECTRICAL CHARACTERISTICS: Unless otherwise specified, TA = –55°C to 125°C for the UCC1837, –25°C to 85°Cfor the UCC2837 and 0°C to 70°C for UCC3837; VDD = 5V, CT = 10nF, CCAP = 100nF.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

Input Supply

Supply Current VDD = 5V 1 1.5 mA

VDD = 10V 1.2 2 mA

Under Voltage Lockout

Minimum Voltage to Start 2.00 2.65 3.00 V

Minimum Voltage After Start 1.6 2.2 2.6 V

Hysteresis 0.25 0.45 0.65 V

Reference ( Note 1 )

VREF 25°C 1.485 1.5 1.515 V

0°C to 70°C 1.470 1.5 1.530 V

–55°C to 125°C 1.455 1.5 1.545 V

Current Sense

Comparator Offset 0°C to 70°C 90 100 110 mV

Comparator Offset –55°C to 125°C 85 100 115 mV

Amplifier Offset 120 140 160 mV

Input Bias Current VCS = 5V 0.5 5 µA

Current Fault Timer

CT Charge Current VCT = 1V 16 36 56 µA

CT Discharge Current VCT = 1V 0.4 1.2 1.9 µA

CT Fault Low Threshold 0.4 0.5 0.6 V

CT Fault Hi Threshold 1.3 1.5 1.7 V

Fault Duty Cycle 2 3.3 5 %

Error Amplifier

Input Bias Current 0.5 2 µA

Open Loop Gain 60 90 dB

Transconductance –10µA to 10µA 2 5 8 mMho

Charge Current VCOMP = 6V 20 40 60 µA

Discharge Current VCOMP = 6V 10 25 40 µA

DIL-8, SOIC-8 (Top View)J or N Package, D Package

ABSOLUTE MAXIMUM RATINGSAll pins referenced to GND . . . . . . . . . . . . . . . . . –0.3V to +15VCS, CT, FB . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to VDD + 0.3VStorage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°CJunction Temperature. . . . . . . . . . . . . . . . . . . –55°C to +150°CLead Temperature (Soldering, 10sec.) . . . . . . . . . . . . . +300°C

Currents are positive into, negative out of the specified terminal.Consult Packaging Section of Databook for thermal limitationsand considerations of packages.

3

UCC1837UCC2837UCC3837

ELECTRICAL CHARACTERISTICS: Unless otherwise specified, TA = –55°C to 125°C for the UCC1837, –25°C to 85°Cfor the UCC2837 and 0°C to 70°C for UCC3837; VDD = 5V, CT = 10nF, CCAP = 100nF.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

FET Driver

Peak Output Current VCAP = 10V, VOUT = 1V 0.5 1.5 2.5 mA

Average Output Current VOUT = 1V 25 100 175 µA

Max Output Voltage VDD = 4.5V, IOUT = 0µA 8.4 9.7 V

VDD = 4.5V, IOUT = 10µA, 0°C to 70°C 8 9 V

VDD = 4.5V, IOUT = 10µA, –55°C to 125°C 7.5 9 V

Charge Pump

CAP Voltage VDD = 4.5V, C/S = 0V 11 12.5 V

VDD = 12V, C/S = 0V 15 16.5 V

Note 1: This is defined as the voltage on FB which results in a DC voltage of 8V on VOUT.

PIN DESCRIPTIONSCAP: The output of the charge pump circuit. A capacitoris connected between this pin and GND to provide afloating bias voltage for an N-Channel MOSFET gatedrive. A minimum of a 0.01µF ceramic capacitor is rec-ommended. CAP can be directly connected to an exter-nal regulated source such as +12V, in which case theexternal voltage will be the source for driving theN-Channel MOSFET.

COMP: The output of the transconductance error ampli-fier and current sense amplifier. Used for compensatingthe small signal characteristics of the voltage loop (andcurrent loop when Current Sense Amplifier is active inover curret mode).

CS: The negative current sense input signal. This pinshould be connected through a low noise path to the lowside of the current sense resistor.

CT: The input to the duty cycle timer circuit. A capacitoris connected from this pin to GND, setting the maximumON time of the over current protection circuits. See theApplication Section for programming instructions.

FB: The inverting terminal of the voltage error amplifier,used to feedback the output voltage for comparison withthe internal reference voltage. The nominal DC operatingvoltage at this pin is 1.5V

GND: Ground reference for the device. For accurate out-put voltage regulation, GND should be referenced to theoutput load ground.

VDD: The system input voltage is connected to thispoint. VDD must be above 3V. VDD also acts as oneside of the Current Sense Amplifier and Comparator.

VOUT: This pin directly drives the gate of the externalN-MOSFET pass element. The typical output impedanceof this pin is 6.5kΩ.

Topology and General Operation

Unitrode Application Note U-152 is a detailed design of alow dropout linear regulator using an N-channelMOSFET as a pass element, and should be used as aguide for understanding the operation of the circuitshown in Fig. 1.

Charge Pump Operation

The internal charge pump of the UCC3837 is designed tocreate a voltage equal to 3 times the input VDD voltageat the CAP pin. There is an internal 5V clamp at the inputof the charge pump however that insures the voltage atCAP does not exceed the ratings of the IC. This CAPvoltage is used to provide gate drive current to the exter-nal pass element as well as bias current to internal sec-

tions of the UCC3837 itself. The charge pump output hasa typical impedance of 80kΩ and therefore the loading ofthe IC and the external gate drive reduces the voltagefrom its ideal level. The UCC3837 can operate in severalstates including having the error amplifier disabled (shutdown), in normal linear regulation mode, and in overdrivemode where the linear regulator is responding to a tran-sient load or line condition. The maximum output voltageavailable at VOUT is shown in Fig. 2 for these variousmodes of operation.

The charge pump output is designed to supply 10µA ofaverage current to the load which is typically theMOSFET gate capacitance present at the VOUT pin.Thecapacitor value used at CAP is chosen to provide holdup

APPLICATION INFORMATION

4

UCC1837UCC2837UCC3837

of the CAP voltage should the external load exceed theaverage current, which occurs during load and line tran-sient conditions. The value of CAP also determines thestartup time of the linear regulator. The voltage at CAPcharges up with a time constant determined by thecharge pump output impedance (typically 80kΩ) and thevalue of the capacitor on CAP.

An external voltage such as +12V may be tied to theCAP pin directly to insure a higher value of VOUT, whichmay be useful when a standard level MOSFET is used orwhen VDD is very low and the resulting VOUT voltagemay need to be higher. With an external source appliedto CAP, the maximum voltage at VOUT will be approxi-mately 1V below the external source.The external +12Vsource should be decoupled to GND using a minimum ofa 0.01µF capacitor.

Choosing a Pass Element

The UCC3837 is designed for use with an N-channelMOSFET pass element only. The designer may choosea logic level or standard gate level MOSFET dependingon the input voltage, the required gate drive, and theavailable voltage at VOUT as discussed previously.MOSFET selection should be based on required dropoutvoltage and gate drive characteristics. A lower RDS(on)MOSFET is used when low dropout is required, but thistype of MOSFET will have higher gate capacitance whichmay result in a slower transient response.

A MOSFET used in linear regulation is typically operatedat a gate voltage between the threshold voltage and thegate plateau voltage in order to maintain high gain. This

mode of operation is linear, and therefore the channel re-sistance is higher than the manufacturer’s publishedRDS(on) value. The MOSFET should only be operated inthe non-linear (switch) mode under transient conditions,when minimum dropout voltage is required.

Disabling the UCC3837

Grounding the CAP pin will remove the drive voltage andeffectively disable the output voltage. The device used toshort the output of CAP should have a very low leakagecurrent when in the OPEN state, since even a fewmicroamps will lower the charge pump voltage.

A second method of disabling the UCC3837 is to place ashort circuit across CCOMP. This will have an advantageof a quicker restart time as the voltage at CAP will not becompletely discharged. The charge pump will be loadeddown by the typical 40µA charging current of the erroramplifier with this configuration, resulting in a lower volt-age at CAP.

Compensating the Error Amplifier

Using a MOSFET as an external pass element intro-duces a pole in the control loop that is a function of theUCC3837 output impedance, ROUT, typically 6.5kΩ, andthe MOSFET input gate capacitance. Fig. 3 indicatesthat in the normal operation of a linear regulator using aMOSFET, the gate capacitance can be predicted directlyfrom the MOSFET characteristic charge curve, using therelationship:

CQgthVgthIN =

∆∆

This pole can be canceled by programming a zero fre-quency on the output of the UCC3837 error amplifierequal to the pole frequency. Therefore:

8

1 VDD

CS

5VOUT

2 CAP

7 CT

4 COMP

6FB

3GND

Q1IRL2203NOR EQUIVALENT

R21.8k

R31.5k

C31000µF

3.3V

R10.020

RCOMP10k

CCOMP820pF

0.1µF

0.1µFQ1

C1330µF

5V

ON/OFF

UCC3837

Figure 1. Typical application 5V to 3.3V, 5A

APPLICATION INFORMATION

5

6

7

8

9

10

11

12

13

14

15

3 4 5 6 7 8 9 10 11 12VDD

VO

UT

E/A DISABLED

LINEAR REGULATOR

OVERDRIVE

Figure 2. Typical V OUT(max) vs. VDD.

UDG-99137

5

UCC1837UCC2837UCC3837

FC RPOLE

IN OUT=

• • •1

2 π

F FR CZERO POLE

COMP COMP= =

• • •1

2 π

R CFCOMP COMP

POLE=

• •1

2 πwhere CIN is the MOSFET input capacitance and ROUT isthe output impedance of VOUT.

The value of CCOMP should be large enough thatparasitics connected to COMP do not effect the zero fre-quency. A minimum of 220pF is recommended.

Transient Response

The transient performance of a linear regulator built us-ing the UCC3837 can be predicted by understanding thedynamics of the transient event. Consider a load tran-sient on the application circuit of Fig. 1, where the outputcurrent steps from a low value to a high value. Initially,the output voltage will drop as a function of the outputcapacitors ESR times the load current change. In re-sponse to the decrease in feedback voltage at FB, theUCC3837 error amplifier will increase its charge currentto a typical value of 40µA. The output of the amplifier willtherefore respond by first stepping the voltage propor-tional to 40µA times RCOMP, and then ramping up pro-portional to 40µA and the value of CCOMP. Dynamicresponse can therefore be improved by increasingRCOMP and decreasing CCOMP .

The value of VOUT will increase the same amount as theincrease in the error amplifier output. The UCC3837 out-put gate drive current, however, is internally limited to1.5mA. The response of the voltage at the gate of the ex-ternal pass element is therefore a function of the 1.5mAdrive current and the external gate charge, as obtainedfrom the MOSFET data sheet gate charge curve.

For the application circuit shown in Fig. 1, the voltage atthe error amplifier output will increase quickly by 400mVdue to the 40µA current through RCOMP. The error am-plifier will then slew at approximately 50mV per micro-second as the 40µA charges CCOMP.

From the IRL2203N data sheet, the typical required gatevoltage at room temperature, to deliver 5A is 2.6V. Thethreshold for the device is approximately 1.5V. From thegate charge curve for the IRL2203N, approximately 7nCcharge is required to change the gate voltage from 1.5Vto 2.6V. With 1.5mA gate drive current, the required timeto charge the gate is therefore 4.7µs.

Overcurrent Protection and Thermal Management:

Overcurrent protection is provided via the UCC3837’s in-ternal current amplifier and overcurrent comparator. If atany time the voltage across the current sense resistorcrosses the comparator threshold, the UCC3837 beginsto modulate the output driver at a 3% duty cycle. Duringthe 3% on time, if the current forces 140mV across thesense amplifier, the UCC3837 will enter a constant out-put current mode. Fig. 4 illustrates the cyclical retry ofthe UCC3837 under fault conditions. Note that the initialfault time is longer than subsequent cycles due to thefact that the timing capacitor is completely dischargedand must initially charge to the reset threshold of 0.5V.

Figure 3. MOSFET turn-on characteristics.

APPLICATION INFORMATION (cont.)

UDG-97046

Figure 4. Load current, timing capacitor voltage andoutput voltage under fault conditions.

UDG-97046

6

UCC1837UCC2837UCC3837

Fault time duration is controlled by the value of the timingcapacitor, CT, according to the following equation:

t CVI

C CFAULT T T T= • = •−

•= • •

−∆ 1 5 0 5

36 1027 8 10

63. .

. (1)

Fig. 5 provides a plot of fault time vs. timing capacitance.The fault time duration is set based upon the load capac-itance, load current, and the maximum output current.The “on” or fault time must be of sufficient duration tocharge the load capacitance during a normal startup se-quence or when recovering from a fault. If not, thecharge accumulated on the output capacitance will bedepleted by the load during the “off” time. The cycle willthen repeat, preventing the output from turning on.

To determine the minimum fault time, assume a maxi-mum load current just less than the trip limit. This leavesthe difference between the IMAX and ITRIP values as thecurrent available to charge the output capacitance. Theminimum required fault time can then be calculated asfollows:

( )tC V

I IFAULTOUT OUT

MAX TRIPmin =

•−

(2)

The minimum timing capacitor can be calculated by sub-stituting equation (1) for tFAULT in equation (2) and solv-ing for CT.

( ) ( )C

C V

I IT

OUT OUT

MAX TRIPmin

.=

•

• • −27 8 103(3)

Switchmode protection offers significant heat sinking ad-vantages when compared to conventional, constant cur-rent solutions. Since the average power during a faultcondition is reduced as a function of the duty cycle, the

heat sink need only have adequate thermal mass to ab-sorb the maximum steady state power dissipation andnot the full short circuit power. With a 5.25V input and amaximum output current of 5A, the power dissipated inthe MOSFET is given by:

( )P V V V IIN SENSE OUT OUT= − − • (4)

( )( )P W= − • − • =5 25 5 0 02 3 3 5 9 25. . . .

Given that the thermal resistivity of the MOSFET is spec-ified as 1°C/W for the TO-220 package style and assum-ing an ambient temperature of 50°C and a case to heatsink resistivity of θCS = 0.3°C/W, the heat sink requiredto maintain a 125°C junction temperature can be calcu-lated as follows:

( )T T PJ A JC CS SA= + + +θ θ θ (5)

( )125 50 9 25 1 0 3= + • + +. . θSA

θSAC

W≤ °6 8.

Based on this analysis, any heatsink with a thermal re-sistivity of 6.8 °C/W or less should suffice. The current inthe circuit of Fig. 1, under short circuit conditions, will belimited to 7A at a 3% duty cycle, resulting in a MOSFETpower dissipation of only:

( ) ( )( )[ ]P V I R I DutyIN OUT SENSE OUT= − • • •max(6)

( )( )[ ]P W= − • • • =5 25 7 0 02 7 0 03 1 07. . . .

Without switchmode protection, the short circuit powerdissipation would be 35.8W, almost four times the nomi-nal dissipation.

Using Printed Circuit Board Etch as a Sense Resistor

Unitrode Design Note DN-71 discusses the use ofprinted circuit board copper etch as a low ohm sense re-sistor. This technique can easily be applied when usingthe UCC3837. The application circuit shown in Fig. 1 canbe used as an example. This linear regulator is designedwith a 5A average load current, demanding a 20mΩsense resistor to result in a 100mV current sense com-parator signal for the UCC3837. The maximum ambienttemperature of the linear regulator is 70°C.

Using DN-71, a 1 ounce outer layer etch of 0.05 incheswide and 1.57 inches long results in a resistance of20mΩ at an ambient temperature of 70°C and an operat-ing current of 5A. Because the resistivity of copper is afunction of temperature, the current limit at lower temper-atures will be higher, as shown in Fig. 6.

0

5

10

15

20

25

30

0 0.2 0.4 0.6 0.8 1CT (uF)

FAU

LTTI

ME

(ms)

Figure 5. Fault time vs. timing capacitance.

7

UCC1837UCC2837UCC3837

Practical Considerations

In order to achieve the expected performance, careful at-tention must be paid to circuit layout. The printed circuitboard should be designed using a single point ground,referenced to the return of the output capacitor. Alltraces carrying high current should be made as short andwide as possible in order to minimize parasitic resistanceand inductance effects.

To illustrate the importance of these concepts, considerthe effects of a 1.5" PCB trace located between the out-put capacitor and the UCC3837 feedback reference. A0.07" wide trace of 1oz. copper results in an equivalentresistance of 10.4mΩ. At a load current of 3A, 31.2mV isdropped across the trace, contributing almost 1% error tothe DC regulation. Likewise, the inductance of the traceis approximately 3.24nH, resulting in a 91mV spike dur-ing the 100ns it takes the load current to slew from200mA to 3A.

The dropout voltage of a linear regulator is often a keydesign parameter. Calculations of the dropout voltage ofa linear regulator based on the UCC3837 Controllershould consider all of the following:

• Sense resistor drop, including temperature andtolerance effects,

• Path resistance drops on both the input and outputvoltages,

• MOSFET resistance as a function of temperature andgate drive, including transient performance,

• Ground path drops.

APPLICATION INFORMATION

15

16

17

18

19

20

21

0 20 40 60 80

AMBIENT TEMPERATURE [°C]

4

5

6

7

8

9

RESISTANCE SHORT CIRCUIT LIMIT

CO

PP

ER

RE

SIS

TAN

CE

[mW

]

SH

OR

TC

IRC

UIT

CU

RR

EN

TFigure 6. Copper resistance and short circuit limitfor example resistor.

UNITRODE CORPORATION7 CONTINENTAL BLVD. • MERRIMACK, NH 03054TEL. (603) 424-2410 FAX (603) 424-3460

PACKAGE OPTION ADDENDUM

www.ti.com 30-Jan-2016

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead/Ball Finish(6)

MSL Peak Temp(3)

Op Temp (°C) Device Marking(4/5)

Samples

UCC2837D ACTIVE SOIC D 8 75 Green (RoHS& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR -40 to 85 UCC2837

UCC2837DG4 ACTIVE SOIC D 8 75 Green (RoHS& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR -40 to 85 UCC2837

UCC2837DTR ACTIVE SOIC D 8 2500 Green (RoHS& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR -40 to 85 UCC2837

UCC3837D ACTIVE SOIC D 8 75 Green (RoHS& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR 0 to 70 UCC3837

UCC3837DG4 ACTIVE SOIC D 8 75 Green (RoHS& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR 0 to 70 UCC3837

(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availabilityinformation and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement thatlead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used betweenthe die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weightin homogeneous material)

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.

PACKAGE OPTION ADDENDUM

www.ti.com 30-Jan-2016

Addendum-Page 2

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finishvalue exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device PackageType

PackageDrawing

Pins SPQ ReelDiameter

(mm)

ReelWidth

W1 (mm)

A0(mm)

B0(mm)

K0(mm)

P1(mm)

W(mm)

Pin1Quadrant

UCC2837DTR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 2-Sep-2015

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

UCC2837DTR SOIC D 8 2500 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 2-Sep-2015

Pack Materials-Page 2

IMPORTANT NOTICE

Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to itssemiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyersshould obtain the latest relevant information before placing orders and should verify that such information is current and complete.TI’s published terms of sale for semiconductor products (http://www.ti.com/sc/docs/stdterms.htm) apply to the sale of packaged integratedcircuit products that TI has qualified and released to market. Additional terms may apply to the use or sale of other types of TI products andservices.Reproduction of significant portions of TI information in TI data sheets is permissible only if reproduction is without alteration and isaccompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such reproduceddocumentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statementsdifferent from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for theassociated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.Buyers and others who are developing systems that incorporate TI products (collectively, “Designers”) understand and agree that Designersremain responsible for using their independent analysis, evaluation and judgment in designing their applications and that Designers havefull and exclusive responsibility to assure the safety of Designers' applications and compliance of their applications (and of all TI productsused in or for Designers’ applications) with all applicable regulations, laws and other applicable requirements. Designer represents that, withrespect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerousconsequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm andtake appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer willthoroughly test such applications and the functionality of such TI products as used in such applications.TI’s provision of technical, application or other design advice, quality characterization, reliability data or other services or information,including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended toassist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in anyway, Designer (individually or, if Designer is acting on behalf of a company, Designer’s company) agrees to use any particular TI Resourcesolely for this purpose and subject to the terms of this Notice.TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TIproducts, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections,enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specificallydescribed in the published documentation for a particular TI Resource.Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications thatinclude the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISETO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTYRIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, orother intellectual property right relating to any combination, machine, or process in which TI products or services are used. Informationregarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty orendorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of thethird party, or a license from TI under the patents or other intellectual property of TI.TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES ORREPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TOACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OFMERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUALPROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM,INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OFPRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL,DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES INCONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEENADVISED OF THE POSSIBILITY OF SUCH DAMAGES.Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements.Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, suchproducts are intended to help enable customers to design and create their own applications that meet applicable functional safety standardsand requirements. Using products in an application does not by itself establish any safety features in the application. Designers mustensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products inlife-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., lifesupport, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, allmedical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applicationsand that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatoryrequirements in connection with such selection.Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s non-compliance with the terms and provisions of this Notice.

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2017, Texas Instruments Incorporated