8-Bit Shift Register With 3-State Output Registers ... absolute maximum ratings(1) recommended...
15
1FEATURES PW PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 Q B Q C Q D Q E Q F Q G Q H GND V CC Q A SER OE RCLK SRCLK SRCLR Q H′ DESCRIPTION/ORDERING INFORMATION SN74AHC595-Q1 8-BIT SHIFT REGISTER WITH 3-STATE OUTPUT REGISTERS SCLS537B–AUGUST 2003–REVISED JANUARY 2008 www.ti.com • Qualified for Automotive Applications • Operating Range 2-V to 5.5-V V CC • 8-Bit Serial-In, Parallel-Out Shift • Shift Register Has Direct Clear The SN74AHC595 contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage registers. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and a serial output for cascading. When the output-enable (OE) input is high, all outputs, except Q H' , are in the high-impedance state. Both the shift-register clock (SRCLK) and storage-register clock (RCLK) are positive-edge triggered. If both clocks are connected together, the shift register always is one clock pulse ahead of the storage register. ORDERING INFORMATION (1) T A PACKAGE (2) ORDERABLE PART NUMBER TOP-SIDE MARKING –40°C to 125°C TSSOP – PW Reel of 2000 SN74AHC595QPWRQ1 HA595Q (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. (2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. FUNCTION TABLE INPUTS FUNCTION SER SRCLK SRCLR RCLK OE X X X X H Outputs Q A –Q H are disabled. X X X X L Outputs Q A –Q H are enabled. X X L X X Shift register is cleared. First stage of the shift register goes low. L ↑ H X X Other stages store the data of previous stage, respectively. First stage of the shift register goes high. H ↑ H X X Other stages store the data of previous stage, respectively. X X X ↑ X Shift-register data is stored into the storage register. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright © 2003–2008, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Transcript of 8-Bit Shift Register With 3-State Output Registers ... absolute maximum ratings(1) recommended...
1FEATURESPW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
QB
QC
QD
QE
QF
QG
QH
GND
VCC
QA
SEROERCLKSRCLKSRCLRQH′
DESCRIPTION/ORDERING INFORMATION
SN74AHC595-Q18-BIT SHIFT REGISTER
WITH 3-STATE OUTPUT REGISTERSSCLS537B–AUGUST 2003–REVISED JANUARY 2008
www.ti.com
• Qualified for Automotive Applications• Operating Range 2-V to 5.5-V VCC
• 8-Bit Serial-In, Parallel-Out Shift• Shift Register Has Direct Clear
The SN74AHC595 contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register.The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storageregisters. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and a serial output forcascading. When the output-enable (OE) input is high, all outputs, except QH', are in the high-impedance state.
Both the shift-register clock (SRCLK) and storage-register clock (RCLK) are positive-edge triggered. If bothclocks are connected together, the shift register always is one clock pulse ahead of the storage register.
ORDERING INFORMATION (1)
TA PACKAGE (2) ORDERABLE PART NUMBER TOP-SIDE MARKING–40°C to 125°C TSSOP – PW Reel of 2000 SN74AHC595QPWRQ1 HA595Q
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIweb site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
FUNCTION TABLEINPUTS
FUNCTIONSER SRCLK SRCLR RCLK OE
X X X X H Outputs QA–QH are disabled.X X X X L Outputs QA–QH are enabled.X X L X X Shift register is cleared.
First stage of the shift register goes low.L ↑ H X X Other stages store the data of previous stage, respectively.First stage of the shift register goes high.H ↑ H X X Other stages store the data of previous stage, respectively.
X X X ↑ X Shift-register data is stored into the storage register.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 2003–2008, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
www.ti.com
3DC3
1DC1
R
3DC3
2DC2
R
3DC3
2DC2
R
3DC3
2DC2
R
3DC3
2DC2
R
3DC3
2DC2
R
3DC3
2DC2
R
3DC3
2DC2
R
13
12
10
11
1415
1
2
3
4
5
6
7
9
QA
QB
QC
QD
QE
QF
QG
QH
QH′
OE
SRCLR
RCLK
SRCLK
SER Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
SN74AHC595-Q18-BIT SHIFT REGISTERWITH 3-STATE OUTPUT REGISTERSSCLS537B–AUGUST 2003–REVISED JANUARY 2008
LOGIC DIAGRAM (POSITIVE LOGIC)
2 Submit Documentation Feedback Copyright © 2003–2008, Texas Instruments Incorporated
Product Folder Link(s): SN74AHC595-Q1
www.ti.com
SRCLK
SER
RCLK
SRCLR
OE ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎQA ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎQB ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎQC ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎQD ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎQE ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎQF ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎQG ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎQH
QH′
SN74AHC595-Q18-BIT SHIFT REGISTER
WITH 3-STATE OUTPUT REGISTERSSCLS537B–AUGUST 2003–REVISED JANUARY 2008
TIMING DIAGRAM
Copyright © 2003–2008, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): SN74AHC595-Q1
www.ti.com
ABSOLUTE MAXIMUM RATINGS (1)
RECOMMENDED OPERATING CONDITIONS (1)
SN74AHC595-Q18-BIT SHIFT REGISTERWITH 3-STATE OUTPUT REGISTERSSCLS537B–AUGUST 2003–REVISED JANUARY 2008
over operating free-air temperature range (unless otherwise noted)
VCC Supply voltage range –0.5 V to 7 VVI Input voltage range (2) –0.5 V to 7 VVO Output voltage range (2) –0.5 V to VCC + 0.5 VIIK Input clamp current VI < 0 –20 mAIOK Output clamp current VO < 0 or VO > VCC ±20 mAIO Continuous output current VO = 0 to VCC ±25 mA
Continuous current through VCC or GND ±75 mAθJA Package thermal impedance, junction to free air (3) 108°C/WTstg Storage temperature range –65°C to 150°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.(3) The package thermal impedance is calculated in accordance with JESD 51-7.
MIN MAX UNITVCC Supply voltage 2 5.5 V
VCC = 2 V 1.5VIH High-level input voltage VCC = 3 V 2.1 V
VCC = 5.5 V 3.85VCC = 2 V 0.5
VIL Low-level input voltage VCC = 3 V 0.9 VVCC = 5.5 V 1.65
VI Input voltage 0 5.5 VVO Output voltage 0 VCC V
VCC = 2 V –50 µAIOH High-level output current VCC = 3.3 V ± 0.3 V –4
mAVCC = 5 V ± 0.5 V –8VCC = 2 V 50 µA
IOL Low-level output current VCC = 3.3 V ± 0.3 V 4mA
VCC = 5 V ± 0.5 V 8VCC = 3.3 V ± 0.3 V 100
Δt/Δv Input transition rise or fall rate ns/VVCC = 5 V ± 0.5 V 20I-suffix devices –40 85
TA Operating free-air temperature °CQ-suffix devices –40 125
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4 Submit Documentation Feedback Copyright © 2003–2008, Texas Instruments Incorporated
Product Folder Link(s): SN74AHC595-Q1
www.ti.com
ELECTRICAL CHARACTERISTICS
TIMING REQUIREMENTS
TIMING REQUIREMENTS
SN74AHC595-Q18-BIT SHIFT REGISTER
WITH 3-STATE OUTPUT REGISTERSSCLS537B–AUGUST 2003–REVISED JANUARY 2008
over recommended operating free-air temperature range (unless otherwise noted)
TA = 25°CPARAMETER TEST CONDITIONS VCC MIN MAX UNIT
MIN TYP MAX2 V 1.9 2 1.9
IOH = –50 µA 3 V 2.9 3 2.9VOH 4.5 V 4.4 4.5 4.4 V
IOH = –4 mA 3 V 2.58 2.48IOH = –8 mA 4.5 V 3.94 3.8
2 V 0.1 0.1IOL = 50 µA 3 V 0.1 0.1
VOL 4.5 V 0.1 0.1 VIOL = 4 mA 3 V 0.36 0.44IOL = 8 mA 4.5 V 0.36 0.44
II VI = 5.5 V or GND 0 V to 5.5 V ±0.1 ±1 µAQA–QH, VI = VCC or GND,IOZ 5.5 V ±0.25 ±10 µAVO = VCC or GND, OE = VIH or VIL
ICC VI = VCC or GND, IO = 0 5.5 V 4 40 µACi VI = VCC or GND 5 V 3 10 10 pFCo VO = VCC or GND 5 V 5.5 pF
VCC = 3.3 V ± 0.3 V, over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
TA = 25°CMIN MAX UNIT
MIN MAXSRCLK high or low 5.5 6.5
tw Pulse duration RCLK high or low 5.5 6.5 nsSRCLR low 5 6SER before SRCLK↑ 3.5 4.5SRCLK↑ before RCLK↑ (1) 8 9.5
tsu Setup time nsSRCLR low before RCLK↑ 8 10SRCLR high (inactive) before SRCLK↑ 3 4
th Hold time SER after SRCLK↑ 1.5 2.5 ns
(1) This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which casethe shift register is one clock pulse ahead of the storage register.
VCC = 5 V ± 0.5 V, over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
TA = 25°CMIN MAX UNIT
MIN MAXSRCLK high or low 5 6
tw Pulse duration RCLK high or low 5 6 nsSRCLR low 5.2 6.2SER before SRCLK↑ 3 4SRCLK↑ before RCLK↑ (1) 5 6
tsu Setup time nsSRCLR low before RCLK↑ 5 6SRCLR high (inactive) before SRCLK↑ 2.5 3.5
th Hold time SER after SRCLK↑ 2 3 ns
(1) This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which casethe shift register is one clock pulse ahead of the storage register.
Copyright © 2003–2008, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): SN74AHC595-Q1
www.ti.com
SWITCHING CHARACTERISTICS
SWITCHING CHARACTERISTICS
OPERATING CHARACTERISTICS
SN74AHC595-Q18-BIT SHIFT REGISTERWITH 3-STATE OUTPUT REGISTERSSCLS537B–AUGUST 2003–REVISED JANUARY 2008
VCC = 3.3 V ± 0.3 V, over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
TA = 25°CFROM TO LOADPARAMETER MIN MAX UNIT(INPUT) (OUTPUT) CAPACITANCE MIN TYP MAXfmax CL = 50 pF 55 105 40 MHztPLH 7.9 15.4 1 20
RCLK QA–QH CL = 50 pF nstPHL 7.9 15.4 1 20tPLH 9.2 16.5 1 21.5
SRCLK QH' CL = 50 pF nstPHL 9.2 16.5 1 21.5tPHL SRCLR QH' CL = 50 pF 9 16.3 1 20.2 nstPZH 7.8 15 1 20
OE QA–QH CL = 50 pF nstPZL 9.6 15 1 20tPHZ 8.1 15.7 1 19.2
OE QA–QH CL = 50 pF nstPLZ 9.3 15.7 1 19.2
VCC = 5 V ± 0.5 V, over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
TA = 25°CFROM TO LOADPARAMETER MIN MAX UNIT(INPUT) (OUTPUT) CAPACITANCE MIN TYP MAXfmax CL = 50 pF 95 140 75 MHztPLH 5.6 9.4 1 13.5
RCLK QA–QH CL = 50 pF nstPHL 5.6 9.4 1 13.5tPLH 6.4 10.2 1 14.4
SRCLK QH' CL = 50 pF nstPHL 6.4 10.2 1 14.4tPHL SRCLR QH' CL = 50 pF 6.4 10 1 14.1 nstPZH 5.7 10.6 1 15
OE QA–QH CL = 50 pF nstPZL 6.8 10.6 1 15tPHZ 3.5 10.3 1 14
OE QA–QH CL = 50 pF nstPLZ 3.4 10.3 1 14
VCC = 5 V, TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS TYP UNITCpd Power dissipation capacitance No load, f = 10 MHz 114 pF
6 Submit Documentation Feedback Copyright © 2003–2008, Texas Instruments Incorporated
Product Folder Link(s): SN74AHC595-Q1
www.ti.com
PARAMETER MEASUREMENT INFORMATION
50% VCC
VCC
VCC
0 V
0 V
thtsu
VOLTAGE WAVEFORMSSETUP AND HOLD TIMES
Data Input
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
VCC
0 V
50% VCC50% VCC
Input
Out-of-PhaseOutput
In-PhaseOutput
Timing Input
50% VCC
VOLTAGE WAVEFORMSPROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
OutputControl
OutputWaveform 1
S1 at VCC(see Note B)
OutputWaveform 2
S1 at GND(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
≈VCC
0 V
50% VCC VOL + 0.3 V
50% VCC≈0 V
VCC
VOLTAGE WAVEFORMSENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
tPLH/tPHLtPLZ/tPZLtPHZ/tPZH
Open Drain
OpenVCCGNDVCC
TEST S1
VCC
0 V
50% VCC
tw
VOLTAGE WAVEFORMSPULSE DURATION
Input
NOTES: A. CL includes probe and jig capacitance.B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.D. The outputs are measured one at a time, with one input transition per measurement.
From OutputUnder Test
CL(see Note A)
LOAD CIRCUIT FOR3-STATE AND OPEN-DRAIN OUTPUTS
S1VCC
RL = 1 kΩGND
From OutputUnder Test
CL(see Note A)
TestPoint
LOAD CIRCUIT FORTOTEM-POLE OUTPUTS
Open
50% VCC
50% VCC 50% VCC
50% VCC
50% VCC 50% VCC
50% VCC 50% VCC
VOH − 0.3 V
SN74AHC595-Q18-BIT SHIFT REGISTER
WITH 3-STATE OUTPUT REGISTERSSCLS537B–AUGUST 2003–REVISED JANUARY 2008
Figure 1. Load Circuit and Voltage Waveforms
Copyright © 2003–2008, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): SN74AHC595-Q1
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status(1)
Package Type PackageDrawing
Pins PackageQty
Eco Plan(2)
Lead finish/Ball material
(6)
MSL Peak Temp(3)
Op Temp (°C) Device Marking(4/5)
Samples
SN74AHC595QPWRQ1 ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HA595Q
(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substancedo not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI mayreference these types of products as "Pb-Free".RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide basedflame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to twolines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74AHC595-Q1 :
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 2
• Catalog: SN74AHC595
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device PackageType
PackageDrawing
Pins SPQ ReelDiameter
(mm)
ReelWidth
W1 (mm)
A0(mm)
B0(mm)
K0(mm)
P1(mm)
W(mm)
Pin1Quadrant
SN74AHC595QPWRQ1 TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Oct-2020
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74AHC595QPWRQ1 TSSOP PW 16 2000 853.0 449.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Oct-2020
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
14X 0.65
2X4.55
16X 0.300.19
TYP6.66.2
1.2 MAX
0.150.05
0.25GAGE PLANE
-80
BNOTE 4
4.54.3
A
NOTE 3
5.14.9
0.750.50
(0.15) TYP
TSSOP - 1.2 mm max heightPW0016ASMALL OUTLINE PACKAGE
4220204/A 02/2017
1
89
16
0.1 C A B
PIN 1 INDEX AREA
SEE DETAIL A
0.1 C
NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.5. Reference JEDEC registration MO-153.
SEATINGPLANE
A 20DETAIL ATYPICAL
SCALE 2.500
www.ti.com
EXAMPLE BOARD LAYOUT
0.05 MAXALL AROUND
0.05 MINALL AROUND
16X (1.5)
16X (0.45)
14X (0.65)
(5.8)
(R0.05) TYP
TSSOP - 1.2 mm max heightPW0016ASMALL OUTLINE PACKAGE
4220204/A 02/2017
NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
LAND PATTERN EXAMPLEEXPOSED METAL SHOWN
SCALE: 10X
SYMM
SYMM
1
8 9
16
15.000
METALSOLDER MASKOPENING
METAL UNDERSOLDER MASK
SOLDER MASKOPENING
EXPOSED METALEXPOSED METAL
SOLDER MASK DETAILS
NON-SOLDER MASKDEFINED
(PREFERRED)
SOLDER MASKDEFINED
www.ti.com
EXAMPLE STENCIL DESIGN
16X (1.5)
16X (0.45)
14X (0.65)
(5.8)
(R0.05) TYP
TSSOP - 1.2 mm max heightPW0016ASMALL OUTLINE PACKAGE
4220204/A 02/2017
NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLEBASED ON 0.125 mm THICK STENCIL
SCALE: 10X
SYMM
SYMM
1
8 9
16
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS.These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources.TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2020, Texas Instruments Incorporated
