8 BIT MICROPROCESSOR ARCHITECTURE -...

Unit 18 BIT MICROPROCESSOR ARCHITECTURE

8085 -Internal Architecture - Addressing modes - Instruction set -Timing diagrams -Interrupts-Assembly language Programming

PREPARED BY S.RAVINDRAKUMAR, Sr.AP//ECE, CHETTINAD COLLEGE OF ENGG AND TECH, KARUR

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1. Internal Architecture of 8085 Microprocessor

Control Unit

� Generates signals within uP to carry out the instruction, which has been decoded.

� In reality causes certain connections between blocks of the uP to be opened or closed, so that data goes where it is required, and so that ALU operations occur.

Arithmetic Logic Unit

� The ALU performs the actual numerical and logic operation such as ‘add’, ‘subtract’, ‘AND’, ‘OR’, etc.

� Uses data from memory and from Accumulator to perform arithmetic. Always stores result of

operation in Accumulator.


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Registers

� The 8085/8080A-programming model includes six registers, one accumulator, and one flag register, as shown in Figure. In addition, it has two 16-bit registers: the stack pointer and the program counter.

� They are described briefly as follows. � The 8085/8080A has six general-purpose registers to store 8-bit data; these are identified as

B,C,D,E,H, and L as shown in the figure.

� They can be combined as register pairs - BC, DE, and HL - to perform some 16-bit operations.

� The programmer can use these registers to store or copy data into the registers by using data copy instructions.

Accumulator

� The accumulator is an 8-bit register that is a part of arithmetic/logic unit (ALU).

� This register is used to store 8-bit data and to perform arithmetic and logical operations.

� The result of an operation is stored in the accumulator. The accumulator is also identified as register A.

Flags

� The ALU includes five flip-flops, which are set or reset after an operation according to data conditions of the result in the accumulator and other registers. They are called Zero(Z), Carry (CY), Sign (S), Parity (P), and Auxiliary Carry (AC) flags; they are listed in the Table and their bit positions in the flag register are shown in the Figure below.

� The most commonly used flags are Zero, Carry, and Sign. The microprocessor uses these

flags to test data conditions. For example, after an addition of two numbers, if the sum in the accumulator id larger than eight bits, the flip-flop uses to indicate a carry -- called the Carry flag (CY) – is set to one.

� When an arithmetic operation results in zero, the flip-flop called the Zero(Z) flag is set to

one. The first Figure shows an 8-bit register, called the flag register, adjacent to the accumulator.

� However, it is not used as a register; five bit positions out of eight are used to store the

outputs of the five flip-flops.


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� The flags are stored in the 8-bit register so that the programmer can examine these flags

(data conditions) by accessing the register through an instruction.

� These flags have critical importance in the decision-making process of the microprocessor. The conditions (set or reset) of the flags are tested through the software instructions.

� For example, the instruction JC (Jump on Carry) is implemented to change the sequence of a

program when CY flag is set.

� The thorough understanding of flag is essential in writing assembly language programs.

Program Counter (PC)

� This 16-bit register deals with sequencing the execution of instructions.

� This register is a memory pointer. Memory locations have 16-bit addresses, and that is why this is a 16-bit register.

� The microprocessor uses this register to sequence the execution of the instructions.

� The function of the program counter is to point to the memory address from which the next

byte is to be fetched. When a byte (machine code) is being fetched, the program counter is incremented by one to point to the next memory location

Stack Pointer (SP) � The stack pointer is also a 16-bit register used as a memory pointer. It points to a memory

location in R/W memory, called the stack.

� The beginning of the stack is defined by loading 16-bit address in the stack pointer. The stack concept is explained in the chapter "Stack and Subroutines."

Instruction Register/Decoder

� Temporary store for the current instruction of a program. Latest instruction sent here from memory prior to execution.

� Decoder then takes instruction and ‘decodes’ or interprets the instruction. Decoded

instruction then passed to next stage.

Memory Address Register


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� Holds address, received from PC, of next program instruction. Feeds the address bus with addresses of location of the program under execution.

Control Generator

� Generates signals within uP to carry out the instruction which has been decoded. In reality causes certain connections between blocks of the uP to be opened or closed, so that data goes where it is required, and so that ALU operations occur.

Register Selector

� This block controls the use of the register stack in the example. Just a logic circuit which switches between different registers in the set will receive instructions from Control Unit.

General Purpose Registers

� uP requires extra registers for versatility. Can be used to store additional data during a program. More complex processors may have a variety of differently named registers.

Microprogramming How does the µP knows what an instruction means, especially when it is only a binary number? The microprogram in a uP/uC is written by the chip designer and tells the uP/uC the meaning of each instruction uP/uC can then carry out operation.

2. 8085 System Bus

Typical system uses a number of busses, collection of wires, which transmit binary numbers, one bit per wire. A typical microprocessor communicates with memory and other devices (input and output) using three busses: Address Bus, Data Bus and Control Bus.

Address Bus

One wire for each bit, therefore 16 bits = 16 wires. Binary number carried alerts memory to ‘open’ the designated box. Data (binary) can then be put in or taken out.

The Address Bus consists of 16 wires, therefore 16 bits. Its "width" is 16 bits. A 16 bit binary number allows 216 different numbers, or 32000 different numbers, ie 0000000000000000 up to 1111111111111111.


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Because memory consists of boxes, each with a unique address, the size of the address bus determines the size of memory, which can be used.

To communicate with memory the microprocessor sends an address on the address bus, eg 0000000000000011 (3 in decimal), to the memory.

The memory the selects box number 3 for reading or writing data. Address bus is unidirectional, ie numbers only sent from microprocessor to memory, not other way.

Question?: If you have a memory chip of size 256 kilobytes (256 x 1024 x 8 bits), how many wires does the address bus need, in order to be able to specify an address in this memory? Note: the memory is organized in groups of 8 bits per location, therefore, how many locations must you be able to specify?

Data Bus

Data Bus: carries ‘data’, in binary form, between µP and other external units, such as memory.

Typical size is 8 or 16 bits. Size determined by size of boxes in memory and µP size helps determine performance of µP.

The Data Bus typically consists of 8 wires. Therefore, 28 combinations of binary digits. Data bus used to transmit "data", ie information, results of arithmetic, etc, between memory and the microprocessor.

Bus is bi-directional. Size of the data bus determines what arithmetic can be done. If only 8 bits wide then largest number is 11111111 (255 in decimal). Therefore, larger number have to be broken down into chunks of 255.

This slows microprocessor. Data Bus also carries instructions from memory to the microprocessor.

Size of the bus therefore limits the number of possible instructions to 256, each specified by a separate number.

Control Bus

Control Bus are various lines which have specific functions for coordinating and controlling uP operations.

Eg: Read/NotWrite line, single binary digit. Control whether memory is being ‘written to’ (data stored in mem) or ‘read from’ (data taken out of mem) 1 = Read, 0 = Write. May also include clock line(s) for timing/synchronising, ‘interrupts’, ‘reset’ etc.

Typically µP has 10 control lines. Cannot function correctly without these vital control signals.


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The Control Bus carries control signals partly unidirectional, partly bi-directional. Control signals are things like "read or write". This tells memory that we are either reading from a location, specified on the address bus, or writing to a location

specified.

Various other signals to control and coordinate the operation of the system. Modern day microprocessors, like 80386, 80486 have much larger busses.

Typically 16 or 32 bit busses, which allow larger number of instructions, more memory location, and faster arithmetic.

Microcontrollers organized along same lines, except: because microcontrollers have memory etc inside the chip, the busses may all be internal. In the microprocessor the three busses are external to the chip (except for the internal data bus).

In case of external busses, the chip connects to the busses via buffers, which are simply an electronic connection between external bus and the internal data bus.

3. 8085 Pin description. Properties

Single + 5V Supply 4 Vectored Interrupts (One is Non Maskable) Serial In/Serial Out Port Decimal, Binary, and Double Precision Arithmetic Direct Addressing Capability to 64K bytes of memory

The Intel 8085A is a new generation, complete 8 bit parallel central processing unit (CPU).


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The 8085A uses a multiplexed data bus. The address is split between the 8bit address bus and the 8bit data bus. Figures are at the end of the document.

Pin Description The following describes the function of each pin:

A6 - A1s (Output 3 State) Address Bus; The most significant 8 bits of the memory address or the 8 bits of the I/0 address,3 stated during Hold and Halt modes.

AD0 - 7 (Input/Output 3state) Multiplexed Address/Data Bus; Lower 8 bits of the memory address (or I/0 address) appear on the bus during the first clock cycle of a machine state. It then becomes the data bus during the second and third clock cycles. 3 stated during Hold and Halt modes.

ALE (Output) Address Latch Enable: It occurs during the first clock cycle of a machine state and enables the address to get latched into the on chip latch of peripherals. The falling edge of ALE is set to guarantee setup and hold times for the address information. ALE can also be used to strobe the status information. ALE is never 3stated.

SO, S1 (Output) Data Bus Status. Encoded status of the bus cycle: S1 S0 O O HALT 0 1 WRITE 1 0 READ 1 1 FETCH S1 can be used as an advanced R/W status.

RD (Output 3state) READ; indicates the selected memory or 1/0 device is to be read and that the DataBus is available for the data transfer.

WR (Output 3state) WRITE; indicates the data on the Data Bus is to be written into the selected memory or 1/0 location. Data is set up at the trailing edge of WR. 3stated during Hold and Halt modes.

READY (Input) If Ready is high during a read or write cycle, it indicates that the memory or peripheral is ready to send or receive data. If Ready is low, the CPU will wait for Ready to go high before completing the read or write cycle.


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HOLD (Input) HOLD; indicates that another Master is requesting the use of the Address and Data Buses.

The CPU, upon receiving the Hold request. will relinquish the use of buses as soon as the completion of the current machine cycle. Internal processing can continue.

The processor can regain the buses only after the Hold is removed. When the Hold is acknowledged, the Address, Data, RD, WR, and IO/M lines are 3stated.

HLDA (Output)

HOLD ACKNOWLEDGE; indicates that the CPU has received the

Hold request and that it will relinquish the buses in the next clock cycle. HLDA goes low after the Hold request is removed.

The CPU takes the buses one half clock cycle after HLDA goes low.

INTR (Input)

INTERRUPT REQUEST; is used as a general purpose interrupt. It is sampled only during the next to the last clock cycle of the instruction.

If it is active, the Program Counter (PC) will be inhibited from incrementing and an INTA will be issued.

During this cycle a RESTART or CALL instruction can be inserted to jump to the interrupt service routine.

The INTR is enabled and disabled by software. It is disabled by Reset and immediately after an interrupt is accepted.

INTA (Output) INTERRUPT ACKNOWLEDGE; is used instead of (and has the same timing as) RD during the Instruction cycle after an INTR is accepted.

It can be used to activate the 8259 Interrupt chip or some other interrupt port.

RST 5.5 RST 6.5 - (Inputs) RST 7.5 RESTART INTERRUPTS; These three inputs have the same timing as I NTR except


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they cause an internal RESTART to be automatically inserted. RST 7.5 ~~ Highest Priority RST 6.5 RST 5.5 o Lowest Priority The priority of these interrupts is ordered as shown above. These interrupts have a higher priority than the INTR.

TRAP (Input) Trap interrupt is a nonmaskable restart interrupt. It is recognized at the same time as INTR. It is unaffected by any mask or Interrupt Enable. It has the highest priority of any interrupt.

RESET IN (Input) Reset sets the Program Counter to zero and resets the Interrupt Enable and HLDA flipflops. None of the other flags or registers (except the instruction register) are affected The CPU is held in the reset condition as long as Reset is applied.

RESET OUT (Output) Indicates CPlJ is being reset. Can be used as a system RESET. The signal is synchronized to the processor clock.

X1, X2 (Input) Crystal or R/C network connections to set the internal clock generator X1 can also be an external clock input instead of a crystal. The input frequency is divided by 2 to give the internal operating frequency.

CLK (Output) Clock Output for use as a system clock when a crystal or R/ C network is used as an input to the CPU. The period of CLK is twice the X1, X2 input period.

IO/M (Output) IO/M indicates whether the Read/Write is to memory or l/O Tristated during Hold and Halt modes.

SID (Input) Serial input data line The data on this line is loaded into accumulator bit 7 whenever a RIM instruction is executed.

SOD (output) Serial output data line. The output SOD is set or reset as specified by the SIM instruction.

Vcc +5 volt supply.


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Vss Ground Reference. 4. 8085 Functional Description • The 8085A is a complete 8 bit parallel central processor. It requires a single +5 volt supply.

• Its basic clock speed is 3 MHz thus improving on the present 8080's performance with higher

system speed. Also it is designed to fit into a minimum system of three IC's: The CPU, a RAM/ IO, and a ROM or PROM/IO chip.

• The 8085A uses a multiplexed Data Bus. The address is split between the higher 8bit Address

Bus and the lower 8bit Address/Data Bus. During the first cycle the address is sent out.

• The lower 8bits are latched into the peripherals by the Address Latch Enable (ALE).

• During the rest of the machine cycle the Data Bus is used for memory or l/O data.

• The 8085A provides RD, WR, and lO/Memory signals for bus control.

• An Interrupt Acknowledge signal (INTA) is also provided. Hold, Ready, and all Interrupts are synchronized.

• The 8085A also provides serial input data (SID) and serial output data (SOD) lines for simple

serial interface.

• In addition to these features, the 8085A has three maskable, restart interrupts and one non-maskable trap interrupt.

• The 8085A provides RD, WR and IO/M signals for Bus control.

Status Information Status information is directly available from the 8085A.

• ALE serves as a status strobe

• The status is partially encoded, and provides the user with advanced timing of the type of bus transfer being done.

• IO/M cycle status signal is provided directly also. Decoded So, S1 Carries the following status

information:


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HALT, WRITE, READ, FETCH

• S1 can be interpreted as R/W in all bus transfers. In the 8085A the 8 LSB of addressare multiplexed with the data instead of status.

• The ALE line is used as a strobe to enter the lower half of the address into the memory or

peripheral address latch.

• This also frees extra pins for expanded interrupt capability.

Interrupt and Serial l/O

• The8085A has5 interrupt inputs: INTR, RST5.5, RST6.5, RST 7.5, and TRAP. INTR is identical in function to the 8080 INT.

• Each of the three RESTART inputs, 5.5, 6.5. 7.5, has a programmable mask. TRAP is also a

RESTART interrupt except it is nonmaskable.

• The three RESTART interrupts cause the internal execution of RST (saving the program counter in the stack and branching to the RESTART address) if the interrupts are enabled and if the interrupt mask is not set.

• The non-maskable TRAP causes the internal execution of a RST independent of the state of

the interrupt enable or masks.

• The interrupts are arranged in a fixed priority that determines which interrupt is to be recognized if more than one is pending as follows: TRAP highest priority, RST 7.5,RST 6.5, RST 5.5, INTR lowest priority

• This priority scheme does not take into account the priority of a routine that was started by a

higher priority interrupt. RST 5.5 can interrupt a RST 7.5 routine if the interrupts were re-enabled before the end of the RST 7.5 routine.

• The TRAP interrupt is useful for catastrophic errors such as power failure or bus error. • The TRAP input is recognized just as any other interrupt but has the highest priority. It is not

affected by any flag or mask. The TRAP input is both edge and level sensitive.

Basic System Timing

• The 8085A has a multiplexed Data Bus. ALE is used as a strobe to sample the lower 8bits of address on the Data Bus.


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• Figure 2 shows an instruction fetch, memory read and l/ O write cycle (OUT). Note that during the l/O write and read cycle that the l/O port address is copied on both the upper and lower half of the address.

• As in the 8080, the READY line is used to extend the read and write pulse lengths so that the

8085A can be used with slow memory.

• Hold causes the CPU to relingkuish the bus when it is through with it by floating the Address and Data Buses.

System Interface

• 8085A family includes memory components, which are directly compatible to the 8085A CPU.

• For example, a system consisting of the three chips, 8085A, 8156, and 8355 will have the

following features: · 2K Bytes ROM · 256 Bytes RAM · 1 Timer/Counter · 4 8bit l/O Ports · 1 6bit l/O Port · 4 Interrupt Levels · Serial In/Serial Out Ports

• In addition to standard l/O, the memory mapped I/O offers an efficient l/O addressing technique.

• With this technique, an area of memory address space is assigned for l/O address, thereby, using the memory address for I/O manipulation.

• The 8085A CPU can also interface with the standard memory that does not have the

multiplexed address/data bus.


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5. The 8085 Programming Model • In the previous tutorial we described the 8085 microprocessor registers in reference to the

internal data operations.

• The same information is repeated here briefly to provide the continuity and the context to the instruction set and to enable the readers who prefer to focus initially on the programming aspect of the microprocessor.

• The 8085 programming model includes six registers, one accumulator, and one flag register,

as shown in Figure.

• In addition, it has two 16-bit registers: the stack pointer and the program counter.

• They are described briefly as follows. Registers The 8085 has six general-purpose registers to store 8-bit data; these are identified as B,C,D,E,H, and L as shown in the figure.

• They can be combined as register pairs -BC, DE, and HL - to perform some 16-bit operations.

• The programmer can use these registers to store or copy data into the registers by using data

copy instructions.

• Accumulator • The accumulator is an 8-bit register that is a part of arithmetic/logic unit (ALU). This register

is used to store 8-bit data and to perform arithmetic and logical operations. The result of an operation is stored in the accumulator. The accumulator is also identified as register A.

ACCUMULATOR A (8) FLAG REGISTER B (8) D (8) H (8)

Stack Pointer (SP) (16) Program Counter (PC) (16) C (8) E (8) L (8) Data Bus Address Bus 8 Lines Bidirectional 16 Lines unidirectional

Flags • The ALU includes five flip-flops, which are set or reset after an operation according to data

conditions of the result in the accumulator and other registers. They are called Zero(Z), Carry (CY), Sign (S),


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Parity (P), and Auxiliary Carry (AC) flags; their bit positions in the flag register are shown in the Figure below.

• The most commonly used flags are Zero, Carry, and Sign. The microprocessor uses these flags to test data conditions.

• For example, after an addition of two numbers, if the sum in the accumulator id larger than

eight bits, the flip-flop uses to indicate a carry -- called the Carry flag (CY) – is set to one.

• When an arithmetic operation results in zero, the flip-flop called the Zero(Z) flag is set to one. The first Figure shows an 8-bit register, called the flag register, adjacent to the accumulator.

• However, it is not used as a register; five bit positions out of eight are used to store the

outputs of the five flip-flops.

• The flags are stored in the 8-bit register so that the programmer can examine these flags (data conditions) by accessing the register through an instruction.

• These flags have critical importance in the decision-making process of the microprocessor.

• The conditions (set or reset) of the flags are tested through the software instructions.

• For example, the instruction JC (Jump on Carry) is implemented to change the sequence of a

program when CY flag is set. The thorough understanding of flag is essential in writing assembly language programs.

Program Counter (PC)

• This 16-bit register deals with sequencing the execution of instructions. This register is a memory pointer.

• Memory locations have 16-bit addresses, and that is why this is a 16-bit register.

• The microprocessor uses this register to sequence the execution of the instructions. • The function of the program counter is to point to the memory address from which the next

byte is to be fetched.

• When a byte (machine code) is being fetched, the program counter is incremented by one to point to the next memory location

Stack Pointer (SP)


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• The stack pointer is also a 16-bit register used as a memory pointer. It points to a memory

location in R/W memory, called the stack.

• The beginning of the stack is defined by loading 16-bit address in the stack pointer.

• This programming model will be used in subsequent tutorials to examine how these registers are affected after the execution of an instruction.

6.8085 Instructions - Datatransfer

DATA TRANSFER INSTRUCTIONS

Opcode Operand Explanation of Instruction

Description

MOV

Rd, Rs

M, Rs

Rd, M

Copy from source(Rs) to destination(Rd)

This instruction copies the contents of the source register into the destination register; the contents of the source register are not altered. If one of the operands is a memory location, its location is specified by the contents of the HL registers.

Example: MOV B, C or MOV B, M

MVI Rd, data

M, data

Move immediate 8-

bit

The 8-bit data is stored in the destination register or memory. If the operand is a memory location, its location is specified by the contents of the HL registers.

Example: MVI B, 57H or MVI M, 57H

LDA 16-bit address

Load accumulator

The contents of a memory location, specified by a 16-bit address in the operand, are copied to the accumulator. The contents of the source are not altered.

Example: LDA 2034H

LDAX B/D

Reg. pair

Load accumulator indirect

The contents of the designated register pair point to a memory location. This instruction copies the contents of that memory location into the accumulator. The contents of either the register pair or the memory location are not altered.


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Example: LDAX B

LXI Reg. pair, 16-bit data

Load register pair immediate

The instruction loads 16-bit data in the register pair designated in the operand.

Example: LXI H, 2034H or LXI H, XYZ

LHLD 16-bit address

Load H and L registers direct

The instruction copies the contents of the memory location pointed out by the 16-bit address into register L and copies the contents of the next memory location into register H. The contents of source memory locations are not altered.

Example: LHLD 2040H

STA 16-bit address

16-bit address

The contents of the accumulator are copied into the memory location specified by the operand. This is a 3-byte instruction, the second byte specifies the low-order address and the third byte specifies the high-order address.

Example: STA 4350H

STAX Reg. pair

Store accumulator indirect

The contents of the accumulator are copied into the memory location specified by the contents of the operand (register pair). The contents of the accumulator are not altered.

Example: STAX B

SHLD 16-bit address

Store H and L registers direct

The contents of register L are stored into the memory location specified by the 16-bit address in the operand and the contents of H register are stored into the next memory location by incrementing the operand. The contents of registers HL are not altered. This is a 3-byte instruction, the second byte specifies the low-order address and the third byte specifies the high-order address.

Example: SHLD 2470H

XCHG none Exchange H and L with D

and E

The contents of register H are exchanged with the contents of register D, and the contents of register L are exchanged with the contents of register E.

Example: XCHG


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SPHL none Copy H and L registers to the stack pointer

The instruction loads the contents of the H and L registers into the stack pointer register, the contents of the H register provide the high-order address and the contents of the L register provide the low-order address. The contents of the H and L registers are not altered.

Example: SPHL

XTHL none Exchange H and L with top

of stack

The contents of the L register are exchanged with the stack location pointed out by the contents of the stack pointer register. The contents of the H register are exchanged with the next stack location (SP+1); however, the contents of the stack pointer register are not altered.

Example: XTHL

PUSH Reg. pair

Push register pair onto stack

The contents of the register pair designated in the operand are copied onto the stack in the following sequence. The stack pointer register is decremented and the contents of the highorder register (B, D, H, A) are copied into that location. The stack pointer register is decremented again and the contents of the low-order register (C, E, L, flags) are copied to that location.

Example: PUSH B or PUSH A

POP Reg. pair

Pop off stack to register pair

The contents of the memory location pointed out by the stack pointer register are copied to the low-order register (C, E, L, status flags) of the operand. The stack pointer is incremented by 1 and the contents of that memory location are copied to the high-order register (B, D, H, A) of the operand. The stack pointer register is again incremented by 1.

Example: POP H or POP A

OUT 8-bit port

address

Output data from

accumulator to a port with 8-bit address

The contents of the accumulator are copied into the I/O port specified by the operand.

Example: OUT F8H


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IN 8-bit port

address

Input data to accumulator from a port with 8-bit address

The contents of the input port designated in the operand are read and loaded into the accumulator.

Example: IN 8CH

ARITHMETIC INSTRUCTIONS

Opcode Operand Explanation

of Instruction

Description

ADD R

M

Add register or memory,

to accumulator

The contents of the operand (register or memory) are added to the contents of the accumulator and the result is stored in the accumulator. If the operand is a memory location, its location is specified by the contents of the HL registers. All flags are modified to reflect the result of the addition.

Example: ADD B or ADD M

ADC R

M

Add register to

accumulator with carry

The contents of the operand (register or memory) and M the Carry flag are added to the contents of the accumulator and the result is stored in the accumulator. If the operand is a memory location, its location is specified by the contents of the HL registers. All flags are modified to reflect the result of the addition.

Example: ADC B or ADC M

ADI 8-bit data

Add immediate

to accumulator

The 8-bit data (operand) is added to the contents of the accumulator and the result is stored in the accumulator. All flags are modified to reflect the result of the addition.

Example: ADI 45H

ACI 8-bit data

Add immediate

to accumulator with carry

The 8-bit data (operand) and the Carry flag are added to the contents of the accumulator and the result is stored in the accumulator. All flags are modified to reflect the result of the addition.

Example: ACI 45H

LXI Reg. pair, 16-

Load register pair

The instruction loads 16-bit data in the register


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bit data immediate pair designated in the operand.

Example: LXI H, 2034H or LXI H, XYZ

DAD Reg. pair

Add register pair to H and L

registers

The 16-bit contents of the specified register pair are added to the contents of the HL register and the sum is stored in the HL register. The contents of the source register pair are not altered. If the result is larger than 16 bits, the CY flag is set. No other flags are affected.

Example: DAD H

SUB R

M

Subtract register or memory from

accumulator

The contents of the operand (register or memory ) are subtracted from the contents of the accumulator, and the result is stored in the accumulator. If the operand is a memory location, its location is specified by the contents of the HL registers. All flags are modified to reflect the result of the subtraction.

Example: SUB B or SUB M

SBB R

M

Subtract source and borrow from

accumulator

The contents of the operand (register or memory ) and M the Borrow flag are subtracted from the contents of the accumulator and the result is placed in the accumulator. If the operand is a memory location, its location is specified by the contents of the HL registers. All flags are modified to reflect the result of the subtraction.

Example: SBB B or SBB M

SUI 8-bit data

Subtract immediate

from accumulator

The 8-bit data (operand) is subtracted from the contents of the accumulator and the result is stored in the accumulator. All flags are modified to reflect the result of the subtraction.

Example: SUI 45H

SBI 8-bit data

Subtract immediate

from accumulator

with borrow

The contents of register H are exchanged with the contents of register D, and the contents of register L are exchanged with the contents of register E.

Example: XCHG

INR R

M

Increment register or memory by

The contents of the designated register or memory) are incremented by 1 and the result is stored in the same place. If the operand is a


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1 memory location, its location is specified by the contents of the HL registers.

Example: INR B or INR M

INX R Increment register pair

by 1

The contents of the designated register pair are incremented by 1 and the result is stored in the same place.

Example: INX H

DCR R

M

Decrement register or memory by

1

The contents of the designated register or memory are M decremented by 1 and the result is stored in the same place. If the operand is a memory location, its location is specified by the contents of the HL registers.

Example: DCR B or DCR M

DCX R Decrement register pair

by 1

The contents of the designated register pair are decremented by 1 and the result is stored in the same place.

Example: DCX H

DAA none Decimal adjust

accumulator

The contents of the accumulator are changed from a binary value to two 4-bit binary coded decimal (BCD) digits. This is the only instruction that uses the auxiliary flag to perform the binary to BCD conversion, and the conversion procedure is described below. S, Z, AC, P, CY flags are altered to reflect the results of the operation.

If the value of the low-order 4-bits in the accumulator is greater than 9 or if AC flag is set, the instruction adds 6 to the low-order four bits.

If the value of the high-order 4-bits in the accumulator is greater than 9 or if the Carry flag is set, the instruction adds 6 to the high-order four bits.

Example: DAA

BRANCHING INSTRUCTIONS

Opcode Operand Explanation of Description


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Instruction

JMP 16-bit address

Jump unconditionally

The program sequence is transferred to the memory location specified by the 16-bit address given in the operand.

Example: JMP 2034H or JMP XYZ

Opcode Description Flag Status

JC Jump on Carry

CY = 1

JNC Jump on no Carry

CY = 0

JP Jump on positive

S = 0

JM Jump on minus

S = 1

JZ Jump on zero

Z = 1

JNZ Jump on no zero

Z = 0

JPE Jump on parity even

P = 1

JPO Jump on parity odd

P = 0

16-bit address

Jump conditionally

The program sequence is transferred to the memory location specified by the 16-bit address given in the operand based on the specified flag of the PSW as described below.

Example: JZ 2034H or JZ XYZ


CC Call on Carry

CY = 1

CNC Call on no Carry

CY = 0

CP Call on positive

S = 0

CM Call on minus

S = 1

CZ Call on zero

Z = 1

16-bit address

Unconditional subroutine call

The program sequence is transferred to the memory location specified by the 16-bit address given in the operand. Before the transfer, the address of the next instruction after CALL (the contents of the program counter) is pushed onto the stack.

Example: CALL 2034H or CALL XYZ


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CNZ Call on no zero

Z = 0

CPE Call on parity even

P = 1

CPO Call on parity odd

P = 0

RET none Return from subroutine

unconditionally

The program sequence is transferred from the subroutine to the calling program. The two bytes from the top of the stack are copied into the program counter,and program execution begins at the new address.

Example: RET


RC Return on Carry

CY = 1

RNC Return on no Carry

CY = 0

RP Return on positive

S = 0

RM Return on minus

S = 1

RZ Return on zero

Z = 1

RNZ Return on no zero

Z = 0

RPE Return on parity even

P = 1

RPO Return on parity odd

P = 0

none Return from subroutine conditionally

The program sequence is transferred from the subroutine to the calling program based on the specified flag of the PSW as described below. The two bytes from the top of the stack are copied into the program counter, and program execution begins at the new address.

Example: RZ

PCHL none Load program counter with HL contents

The contents of registers H and L are copied into the program counter. The contents of H are placed as the high-order byte and the contents of L as the


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low-order byte.

Example: PCHL

RST

0-7 Restart

The RST instruction is equivalent to a 1-byte call instruction to one of eight memory locations depending upon the number. The instructions are generally used in conjunction with interrupts and inserted using external hardware. However these can be used as software instructions in a program to transfer program execution to one of the eight locations. The addresses are:

Instruction Restart Address

RST 0 0000H

RST1 0008H

RST 2 0010H

RST 3 0018H

RST 4 0020H

RST 5 0028H

RST 6 0030H

RST 7 0038H

The 8085 has four additional interrupts and these interrupts generate RST instructions internally and thus do not require any external hardware. These instructions and their Restart addresses are:

Interrupt Restart Address

TRAP 0024H

RST 5.5 002CH


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RST 6.5 0034H

RST 7.5 003CH

LOGICAL INSTRUCTIONS

Opcode Operand Explanation

of Instruction

Description

CMP R

M

Compare register or memory with

accumulator

The contents of the operand (register or memory) are M compared with the contents of the accumulator. Both contents are preserved . The result of the comparison is shown by setting the flags of the PSW as follows:

if (A) < (reg/mem): carry flag is set if (A) = (reg/mem): zero flag is set if (A) > (reg/mem): carry and zero flags are reset

Example: CMP B or CMP M

CPI 8-bit data

Compare immediate

with accumulator

The second byte (8-bit data) is compared with the contents of the accumulator. The values being compared remain unchanged. The result of the comparison is shown by setting the flags of the PSW as follows:

if (A) < data: carry flag is set if (A) = data: zero flag is set if (A) > data: carry and zero flags are reset

Example: CPI 89H

ANA R

M

Logical AND register or memory with

accumulator

The contents of the accumulator are logically ANDed with M the contents of the operand (register or memory), and the result is placed in the accumulator. If the operand is a memory location, its address is specified by the contents of HL registers. S, Z, P are modified to reflect the result of the operation. CY is


26

reset. AC is set.

Example: ANA B or ANA M

ANI 8-bit data

Logical AND immediate

with accumulator

The contents of the accumulator are logically ANDed with the 8-bit data (operand) and the result is placed in the accumulator. S, Z, P are modified to reflect the result of the operation. CY is reset. AC is set.

Example: ANI 86H

XRA R

M

Exclusive OR register or memory

with accumulator

The contents of the accumulator are Exclusive ORed with M the contents of the operand (register or memory), and the result is placed in the accumulator. If the operand is a memory location, its address is specified by the contents of HL registers. S, Z, P are modified to reflect the result of the operation. CY and AC are reset.

Example: XRA B or XRA M

XRI 8-bit data

Exclusive OR

immediate with

accumulator

The contents of the accumulator are Exclusive ORed with the 8-bit data (operand) and the result is placed in the accumulator. S, Z, P are modified to reflect the result of the operation. CY and AC are reset.

Example: XRI 86H

ORA R

M

Logical OR register or memory with

accumulator

The contents of the accumulator are logically ORed with M the contents of the operand (register or memory), and the result is placed in the accumulator. If the operand is a memory location, its address is specified by the contents of HL registers. S, Z, P are modified to reflect the result of the operation. CY and AC are reset.

Example: ORA B or ORA M

ORI 8-bit data

Logical OR immediate

with accumulator

The contents of the accumulator are logically ORed with the 8-bit data (operand) and the result is placed in the accumulator. S, Z, P are modified to reflect the result of the operation. CY and AC are reset.

Example: ORI 86H

RLC none Rotate

accumulator left

Each binary bit of the accumulator is rotated left by one position. Bit D7 is placed in the position of D0 as well as in the Carry flag. CY is modified according to bit D7.


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S, Z, P, AC are not affected.

Example: RLC

RRC none Rotate

accumulator right

Each binary bit of the accumulator is rotated right by one position. Bit D0 is placed in the position of D7 as well as in the Carry flag. CY is modified according to bit D0. S, Z, P, AC are not affected.

Example: RRC

RAL none

Rotate accumulator left through

carry

Each binary bit of the accumulator is rotated left by one position through the Carry flag. Bit D7 is placed in the Carry flag, and the Carry flag is placed in the least significant position D0. CY is modified according to bit D7. S, Z, P, AC are not affected.

Example: RAL

RAR none

Rotate accumulator

right through carry

Each binary bit of the accumulator is rotated right by one position through the Carry flag. Bit D0 is placed in the Carry flag, and the Carry flag is placed in the most significant position D7. CY is modified according to bit D0. S, Z, P, AC are not affected.

Example: RAR

CMA none Complement accumulator

The contents of the accumulator are complemented. No flags are affected.

Example: CMA

CMC none Complement

carry

The Carry flag is complemented. No other flags are affected.

Example: CMC

STC none Set Carry Set Carry

Example: STC

CONTROL INSTRUCTIONS

Opcode

Operand

Explanation of

Instruction Description

NOP none No

operation No operation is performed. The instruction is fetched and decoded. However no operation is executed.


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Example: NOP

HLT none Halt and enter wait

state

The CPU finishes executing the current instruction and halts any further execution. An interrupt or reset is necessary to exit from the halt state.

Example: HLT

DI none Disable

interrupts

The interrupt enable flip-flop is reset and all the interrupts except the TRAP are disabled. No flags are affected.

Example: DI

EI none Enable

interrupts

The interrupt enable flip-flop is set and all interrupts are enabled. No flags are affected. After a system reset or the acknowledgement of an interrupt, the interrupt enable flipflop is reset, thus disabling the interrupts. This instruction is necessary to reenable the interrupts (except TRAP).

Example: EI

RIM none Read

interrupt mas

This is a multipurpose instruction used to read the status of interrupts 7.5, 6.5, 5.5 and read serial data input bit. The instruction loads eight bits in the accumulator with the following interpretations.

Example: RIM

SIM none Set

interrupt mask

This is a multipurpose instruction and used to implement the 8085 interrupts 7.5, 6.5, 5.5, and serial data output. The instruction interprets the accumulator contents as follows.

Example: SIM


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7. The 8085 Addressing Modes

• The instructions MOV B, A or MVI A, 82H are to copy data from a source into a destination. In these instructions the source can be a register, an input port, or an 8-bit number (00H to FFH).

• Similarly, a destination can be a register or an output port. The sources and destination are

operands.

• The various formats for specifying operands are called the ADDRESSING MODES. For 8085, they are: 1. Immediate addressing. 2. Register addressing. 3. Direct addressing. 4. Indirect addressing.

Immediate addressing Data is present in the instruction. Load the immediate data to the destination provided. Example: MVI R,data


30

Register addressing Data is provided through the registers. Example: MOV Rd, Rs

Direct addressing Used to accept data from outside devices to store in the accumulator or send the data stored in the accumulator to the outside device. Accept the data from the port 00H and store them into the accumulator or Send the data from the accumulator to the port 01H. Example: IN 00H or OUT 01H

Indirect Addressing

• This means that the Effective Address is calculated by the processor. And the contents of the address (and the one following) is used to form a second address.

• The second address is where the data is stored. Note that this requires several memory

accesses; two accesses to retrieve the 16-bit address and a further access (or accesses) to retrieve the data which is to be loaded into the register.

Self check 1: “how will you design your own REGISTER using the digital techniques which you have studied in digital electronics” 1)Compare XRA A and MVI A,00 2)LDA 5000 ! which flag will be affected?


31

8.TIMING DIAGRAM OF 8085 INSTRUCTIONS

MEMORY WRITE MACHINE CYCLE OF 8085:

• The memory write machine cycle is executed by the processor to write a data byte in a memory location.

• The processor takes 3T states to execute this machine cycle.

Fig - Timing Diagram for Memory Write Machine Cycle I/O Read Cycle of 8085:

• The I/O Read cycle is executed by the processor to read a data byte from I/O port or from the peripheral, which is I/O, mapped in the system.

• The processor takes 3T states to execute this machine cycle. • The IN instruction uses this machine cycle during the execution.

Fig - Timing Diagram for I/O Read Machine Cycle

I/O Write Cycle of 8085:


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• The I/O write machine cycle is executed by the processor to write a data byte in the I/O port or to a peripheral, which is I/O, mapped in the system.

• The processor takes, 3T states to execute this machine cycle.

Fig - Timing Diagram for I/O Write Machine Cycle

Timing diagram for MVI B, 43H.

• Fetching the Opcode 06H from the memory 2000H. (OF machine cycle) • Read (move) the data 43H from memory 2001H. (memory read)

Timing diagram for INR M


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• Fetching the Opcode 34H from the memory 4105H. (OF cycle) • Let the memory address (M) be 4250H. (MR cycle -To read Memory address and data) • Let the content of that memory is 12H. • Increment the memory content from 12H to 13H. (MW machine cycle)

• The 8085 instructions consist of one to five machine cycles. • Actually the execution of an instruction is the execution of the machine cycles of that

instruction in the predefined order. • The timing diagram of an instruction ate obtained by drawing the timing diagrams of the

machine cycles of that instruction, one by one in the order of execution.

Timing diagram for IN C0H.

• Fetching the Opcode DBH from the memory 4125H. • Read the port address C0H from 4126H. • Read the content of port C0H and send it to the accumulator. • Let the content of port is 5EH.

Fig - Timing Diagram for Opcode Fetch Machine Cycle

Timing diagram for STA 526AH.

• STA means Store Accumulator -The contents of the accumulator is stored in the specified address(526A).

• The opcode of the STA instruction is said to be 32H. It is fetched from the memory 41FFH(see fig). - OF machine cycle

• Then the lower order memory address is read(6A). - Memory Read Machine Cycle • Read the higher order memory address (52).- Memory Read Machine Cycle • The combination of both the addresses are considered and the content from accumulator is

written in 526A. - Memory Write Machine Cycle • Assume the memory address for the instruction and let the content of accumulator is C7H. So,

C7H from accumulator is now stored in 526A.


34


35

Self check 2:

1.What are the pins used for nterrupts in 8085, 2.Will the clock frequency change the machine cycle? 3.mention the machine cycles of sta 2506 and shld 2000 9. Sample Programs Write an assembly program to add two numbers

Program MVI D, 8BH MVI C, 6FH MOV A, C 1100 0011 1000 0101 0010 0000

ADD D OUT PORT1 HLT

Write an assembly program to multiply a number by 8


36

Program MVI A, 30H RRC RRC RRC OUT PORT1 HLT

Write an assembly program to find greatest between two numbers Program

MVI B, 30H MVI C, 40H MOV A, B CMP C JZ EQU JC GRT OUT PORT1 HLT EQU: MVI A, 01H OUT PORT1 HLT GRT: MOV A, C OUT PORT1 HLT

SELF CHECK 3

“FOR THE ABOVE PROGRAMS ,FIND THE TIME REQUIRED TO EXECUTE THE PROGRAM!!”

1.RST 7.5 refers to _________________________________ 3.what is the clock frequency of 8085? 4.What is the maximum number of I/O devices can be connected with 8085.

Key Terms A Accumulator2 Addressing Modes29 Architecture2 Arithmetic instruction 19 ALE 8 B Branch instruction 21 C Control bus6 CLK 10 Control instruction 27 D DATA bus 6 Data transfer instruction 16 F FLAGS 3 KEY TERM QUIZ

I Instructions16 Interrupts 9 INTA – Interrupt Acknowledge5 L Logical instruction 25 P Pin description 7 Program Counter4 R REGISTERS3 RESTART INTERRUPTS9 RESET 10 S Stack Pointer 4 System Bus 5 System Timing12 T Timing Diagram 31 X X1,X2 10

1.What is the purpose of pin X1 and X2? 2.stack pointer is a ___________ bit register. 3. sign flag will be affected by data transfer instructions?Yes/no 4. ldax b what type of addressing mode 5. HL register is a __________ bit register? 6. The number of flags in 8085 is________ 7. ALE pin remails low during multiplexing of higher order address say yes/no 8. The SOD and SID are used for _________ 9. The clock frequency of 8085 is______ 10. MVI B,20 no of bytes of the instruction is ______


38

OBJECTIVE TYPE QUESTIONS

1. In Synchronous data Transfer type both Transmitter and Receiver will operate in a) Same Clock pulse b) Different Clock pulse c) None of the above

2. The term PSW Program Status word refers a) Accumulator & Flag register b) H and L register c) Accumulator & Instruction register d) B and C register

3. In 8085 the MAR, or ?.. register, latches the address from the program counter. A bit later the MAR applies this address to the ??, where a read operations performed a) Memory address, ROM b) Memory address, RAM c) Memory address, PROM d) Memory address EPROM

4. In micro ? processors like 8080 and the 8085, the ?..cycle may have from one to live machine cycle a) micro ? instruction b) source program c) instruction d) fetch cycle

5. Repeated addition is one way to do multiplication, programmed multiplication is used in most microprocessors because a) that ALU?s can only add and subtract b) this saves on memory c) a separate set of instructions is needed for the two d) None of the above.

6. A —— is used to isolate a bit, it does this because that ANI sets all other bits to Zero a) subroutine b) flag c) label d) mask

7. Interaction between a CPU and a peripheral device that takes place during and imput output operation is known as a) handshaking b) flagging


39

c) relocating d) sub?routine

8. Addressing in which the instructions contains the address of the data to the operated on is known as a) immediate addressing b) implied addressing c) register addressing d) direct addressing

9. Resart is a special type of CALL in which a) the address is programmed but not built into the hardware b) the address is programmed built into the hardware c) the address is not programmed but built into the hardware d) None of the above

10. 8085 has ?? software restarts and ?.. hardware restarts a) 10, 5 b) 8,4 c) 7,5 d) 6,6

11. Serial input data of 8085 can be loaded into bit 7 of the accumulator by a) executing a RIM instruction b) executing RST1 c) using TRAP c) None of the above

12. The address to which a software or hardware restart branches is known as a) vector location b) SID c) SOD d) TRAP

13. TRAP is ?..whereas RST 7.5, RST 6.5, RST 5.5 are?. a) maskable, non maskable b) maskable, maskable c) non - maskable, non ? maskable d) non - maskable, maskable

14. micro processor with a 16 ? bit address bus is used in a linear memory selection configuration address bus lines are directly used as chip selects of memory chips with four memory chips. The maximum addressable memory space is a) 64K b) 16 K c) 8K


40

d) 4K 15. How many outputs are there in the output of a 10-bit D/A converter? a) 1000 b) 1023 c) 1024 d) 1224

16. The stack is a specialized temporary ?? access memory during ?.. and ?? instructions a) random, store, load b) random, push, load c) sequential, store, pop d) sequential, push, pop

17. The memory address of the last location of a 1K byte memory chip is given as OFBFFH what will be the address of the first location ? a) OF817H b) OF818H c) OF8OOH d) OF801H

18. What is the direction of address bus ? a) Uni ? directional into microprocessors b) Uni ? directional out of microprocessors c) Bi ? directional d) mixed direction is when lines into micro processor and some other out of micro processes.

19. The No. of control lines are ——-

20. The length of A ? register is ——- bits

21. The length of program counter is ——– bits

22. The length of stack pointer is ——– bits

23. The length of status word is ——- bits

24. The length of temporary register ——- bits

25. The length of Data buffer register ——- bits

26. The No. of flags are ——-

27. The No. of interrupts are ——-

28. The memory word addressing capability is —— K


41

29. The No. of input output ports can be accessed by direct method ——-

30. The No. of input output ports can be accessed by memory mapped method —— K

31. If instruction RST is written in a program the program will jump ——- location.

32. When TRAP interrupt is triggered program control is transferred to ——- location.

33. The RST 5.5 interrupt service routine start from ——– location.

34. What is the purpose of using ALE signal high ? a) To latch low order address from bus to separate A0 ? A7 b) To latch data Do ? D 7 from bus go separate data bus c) To disable data bus latch

35. What is the purpose of READY signal? a) It is used to indicate to user that microprocessor is working and ready to use b) It is used to provide for proper WAIT states when microprocessor is communicating with slow peripheral device. c) It is used to provide for proper showing down of fast peripheral devices so as to communicate at micro processors speed.

36. What is the addressing mode used in instruction MOV M, C? a) Direct b) Indirect c) Indexed d) Immediate

37. In 8085 the direction of address business is a)bidirectional b)unidirectional out of MP c)unidirectional int MP d)none of the above

38. In 8085 the hardware interrupts are a)TRAP,RST 6.5,RST 7.5, RST 5.5 and INTR b)RST o, RST 1?..RST 7 c)both a b d)none of the above

39. In the TRAP, RST 7.5, RST 6.5, RST 5.5, which is having top priority a)TRAP b)RST 7.5 c)RST 6.5 d)RST 5.5 40.In 8085 the no . of software interrupts are a) 8


42

b)7 c)5 d)4

41. In the following interrupts which is the non-vectored interrupt a)TRAP b)INTR c)RST 7.5 d)RST 6.5

42. Vector address for the TRAP interrupt is a)0024 H b)003C H c)0034 H d)002C H

43. In the following interrupt which is non-maskable interrupt (a) Rst7.5 b) Rst 6.5 c) TRAP d) INTR

44. Vector location Address for RST O Instruction is inflex (a) ooooH b) ooo8H c) oo1oH d)oo18H

45. In 8085 the Interput Acknowledge is represended by _______ (a) INTA b)INTA c) INTR d) none of the above

46. The maximum number of I\o devices can be interfaced with 8085 in the I\o mapped I\o technique are a) 128 b) 256 c) 64 d) 1024

47. The maximum number of I\o devices which can be interfaced in the memory mapped I\o technique are a) 256 b) 128


43

c) 65536 d) 32768

48. Shadow Address will exist in a) absolute decoding b) linear decoding c) partical decoding d) none of the above

49. The Instructions used for data transfer in I\o mapped I\O are a) IN, OUT b) IN, LDA add c) STA add d) None of the above

50. Number of Address lines required to interface 1KB of memory are a) 10 b)11 c) 12 d) 13

REVIEW QUESTIONS

2 MARKS

1. Differentiate between memory mapped I/O and I/O mapped I/O.

2. Classify the different groups of 8085 instruction set with example.

3. Differentiate between unidirectional buffer and bi-directional buffer.

4. What is the need for ALE signal in 8085 microprocessor?

5. Give the operation of the foll instructions:(a) DAA (b) DEC.

6. State the functions for ALE and TRAP pins in 8085.

7. If the frequency of the crystal connected to 8085 is 6MHz, calculate the time to fetch and executed NOP instruction.

8. What is a MPU?


44

9. What do you mean by multiplexing the bus?

10. List out the two parts of an instruction.

11. What is a program counter?

12. What is an instruction?

13. What is PSW?

14. Define - Interrupt.

15. What are the addressing modes for 8085 microprocessor?

16. Where the READY signal used?

17. Define stack.

18. Specify how a program counter is useful in program execution.

19. How the data and address lines are demultiplexed?

20. Show the bit positions of various flags in 8085 flag register?

21. List the various machine cycles of 8085.

22. What is the instruction format of 8085.

23. What are the similarity and difference between subtract and compare instructions?

24. List the type of signals that have to be applied to initiate hardware interrupts in 8085.


45

25. Write a subroutine to clear the flag register and accumulator?

26. Draw a simple circuit to decode three controls signals RD, WR, IO/M and to produce separate read/write control signal for memory and I/O device?

27. List out the similarities between CALL_RET and PUSH_POP instructions.

28. List four interrupts of 8085.

29. Define: (a) Instruction Cycle (b) M/c cycle (c) T-state.

30. Explain the execution of the instruction CMA M in 8085.

31. If the program counter is always one count ahead of the memory locations from which the machine code is being fetched, how does the microprocessor change the sequence of program execution with a "Jump" execution?

32. Differentiate between hardware interrupts and software interrupts of 8085.

33. What is DAD and what are the flags, affected by this instructions?

34. What is the function performed by SIM Instruction?

35. What is meant by processor cycle?

36. What are the different memory mapping schemes? Give any one advantage and disadvantage for each

BIG QUESTIONS

1. a. Draw the block diagram of 8085 mp and explain? (18 b. Write an assembly language program to add two 2-digits BCD Number? (4) 2. a. Explain the instruction set of 8085? (10) b. Write notes on status flag? (2


46

3. a. Explain the architecture of Intel 8085 with the help of a block diagram? (10 b. Explain the similarities diff b/w subtract and compare instructions in 8085? (2) 4. a. Describe the sequence of event that may occur during the different T state in the opcode Fetch machine cycle of 8085? (6) b. Write an assembly language program to convert on array of ASCII code to corresponding Binary (hex) value. The ASCII array is stored starting from 4200H.The first element of the number of elements in the array. (6) 5. a. With neat block diagram explain the architecture of 8085? (8) b. List out the maskable and non maskable interrupts available in 8085? (4) 6. a. How do the instructions of 8085 is classified based on their function and word length? Give an example? (8) b. Write an ALP to Add two 8bit numbers? (4) 7.(a)Specify the contents of the registers and the flag status as the following instructions are executed.(4) i. MVI A, 00H ii. MVI B, F8H iii. MOV C, A vi. HLT (b)Write instructions to load the hexadecimal number 65H in register C and 92H in accumulator A. Display the number 65H at PORT0 and 92H at PORT1.(8) 8. (a)Why the lower order address bus is multiplexed with data bus? How they will be de-multiplexed? (6) (b) Differentiate between maskable and non-maskable interrupts.(6) 9. a)Write an 8085 assembly language program using minimum number of instructions to add the 16 bit no. in BC, DE & HL. Store the 16 bit result in DE pair. (6) b) Explain the similarities diff b/w subtract and compare instructions in 8085? (6) 10. (a)Explain in detail the following instructions:- (i) ADC (ii) LHLD (iii) RLC (iv) DI

(b) Define & explain the term addressing modes.

11. (a)Draw the timing diagram for the following instructions:- (i) SHLD (ii) OUT 40

12. Explain with examples the arithmetic instruction .(12)


47

EXERCISE:ASSEMBLY LANGUAGE PROGRAME FOR 8085

1. Write an ALP for 8085 to find the sum of two decimal numbers (34)10 & (59)10. Store the result in memory location say XXXXH.

2. Write an ALP for 8085 to find the subtraction of two decimal numbers (74)10 &

(37)10. Store the result in memory location say XXXXH. 3. Write an ALP for 8085 to find the sum of Ist 100 natural numbers. Store the 16-bit

sum in two successive memory locations XXXXH & (XXXX+1)H respectively where the LSB of the sum should be in XXXXH.

4. Write an ALP for 8085 to find the no of negative, zero & positive elements from a

given set of data where the length of the data is in memory location (XXXX+3) H and the data itself starts from memory location (XXXX+4)H. Store the no of negative, zero & positive elements in memory location starting from XXXXH.

5. Write an ALP for 8085 to find the checksum of a series of numbers where the length

of the series is in memory location (XXXX+1)H and the numbers start from memory location (XXXX+2)H. Store the checksum in memory location say XXXXH.

6. Write an ALP for 8085 to find the number of 1’s in an 8 bit data in memory location

say (XXXX+1)H. Store the number of 1’s in memory location say XXXXH. 7. Write an ALP for 8085 to find the unsigned largest/smallest number from a given

series of numbers. The length of the series is in memory location say (XXXX+1)H and the numbers start from memory location (XXXX+2)H. Store the largest/smallest 8 bit unsigned number in memory location XXXXH.

8. Write an ALP for 8085 to convert the BINARY data in memory location XXXXH

into its equivalent GREY code and place this in memory location (XXXX+1)H. 9. Write an ALP for 8085 to convert the GREY code data in memory location

XXXXH into its equivalent BINARY code and place this in memory location (XXXX+1)H. FFH as error marker in memory location (XXXX+1)H.

the MPD = 1234H and MPR = 34H, are in memory location (XXXX+3)H to


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10. Write an ALP for 8085 to convert the hexadecimal no in memory location XXXXH into its equivalent decimal number and place it in memory location (XXXX+1)H. If Te memory location XXXXH contain a hexadecimal number which cannot be represented by a two digit decimal number then place FFH as error marker in memory location (XXXX+1)H. 11. Write an ALP for 8085 to convert the decimal no in memory location XXXXH into its equivalent hexadecimal number and place it in memory location (XXXX+1)H. If the memory location XXXXH contain a decimal number greater than 99 then place

12. Write an ALP for 8085 to find the sum of squares of several numbers using a square data table. The length of the number is in memory location say (XXXX+2)H and thenumbers whose sum of squares are to be found starts from memorylocation (XXXX+3)H. Store the sum of square in memory locationXXXXH & (XXXX+1)H. 13. Write an ALP for 8085 to find the sum of multiple byte decimal number wherethe length of the byte is in memory location XXXXH .The Augend and Addendbytes starts from memory location YYYYH and ZZZZH respectively. Store thedecimal sum in the same place where the Augend bytes reside. 14. Write an ALP for 8085 to find the subtraction of multiple byte decimalnumber where the length of the byte is in memory location XXXXH .TheMinuend and Subtrahend bytes starts from memory location YYYYH and ZZZZHrespectively. Store the decimal sum in the same place where the Minuend bytes reside. 15. Write an ALP for 8085 to find the sum of series of sixteen bit numbers wherethe length of the series is in memory location (XXXX+3)H and the numbers itselfstarts from memory location (XXXX+4)H. Store the sum which is say 24 bitlong in memory location XXXXH onwards. 16. Write an ALP for 8085 to search a given pattern say a carriage returnpattern (having hex code of 20H) from a given series of data where the length ofthe series is in memory location XXXXH and the data itself starts from memorylocation (XXXX+1)H. Store the no of matches found in memory location XXXXH. 17. Write an ALP for 8085 to sort the given series of unsigned eight bit numbersin Ascending/Descending order. The length of the numbers is in memorylocation XXXXH and the numbers starts from memory location YYYYH. Place thesorted numbers in the same place where they originally reside. 18. Write an ALP for 8085 to perform the multiplication of two unsigned number where (XXXX+5)H. Store the 24 bit product in memory location starting fromXXXXH onwards.


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19. Write an ALP for 8085 to perform the division of two unsigned number where the

dividend = 0567H and divisor = D8H, are in memory location (XXXX+2)H to (XXXX+4)H. Store the 8 bit quotient and reminder in memory location XXXXH and (XXXX+1)H respectively.

20. Write an ALP for 8085 to generate a square wave at the SOD pin of 8085

Microprocessor. 21. Connect the male connector pins of 8255PPI of Microprocessor kit with a female

connector. Short circuit the port pins of port A with port B by using single strand wire on the other side of the female connector. Now write an ALP for 8085 to configure the port A as output port and port B & port C as input port in mode zero. Then output data continuously to the output port A and read the same data back from input port B and store this data sequentially in memory starting from say XXXXH onwards. After executing the program verify that the data which is send to the output port A is again obtained via input port B in successive memory location starting from XXXXH onwards.

22. Write an ALP for 8085 to configure all ports of 8255 as output port in mode zero.

Then send any data to each of these three output port and verify after executing the program that the intended data is available at the respective output ports by checking the status of the respective port pins either by using a logic probe or by using a digital voltmeter. The pin connection of various port pins will be supplied.

23. Write an ALP for 8085 to configure all ports of 8255 as output port and hence write

a program to generate a square wave at all the port pins of port A.


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Appendix

A

INSTRUCTION CLASSIFICATION An instruction is a binary pattern designed inside a microprocessor to perform a specific function. The group of instructions called instruction set determines the various functions of the µP. the instructions may be classified to five functional categories:

1. Data transfer (Copy) operations. 2. Arithmetic operations 3. Logic operations 4. Branching operations 5. Machine control operations

Data transfer (Copy) operations This group of instructions copies data from a location called source to another location called destination without modifying the contents of the source. IT IS A COPYING FUNCTION. The different types are: Between registers: Copy the contents of register B to register C. Specific data byte to register/ memory location: load register B with data byte 32H. Between a memory location & a register: from the memory location 2000H to register B. Between an I/O device & the accumulator: From input keyboard to Accumulator.


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Between a register pair & the stack: From register pair BC to two memory locations defined as the stack. ARITHMETIC OPERATIONS

• These instructions perform addition, subtraction, increment & decrement.

• Addition: Any 8 bit number, or register contents or contents of memory locations can be added to the contents of Accumulator & the result i.e. SUM is stored in the Accumulator. No two other registers can be added directly ( Contents of register B cannot be added directly to contents of register D).

• Instruction DAD is the only exception; it adds 16-bit data directly in register pairs. Subtraction: Any 8 bit number, or register contents or contents of memory locations can be subtracted from the contents of Accumulator & the result i.e. DIFFERENCE is stored in the Accumulator. Subtraction is performed in the 2’s complement method & if it is negative is expressed in 2’s complement method. No two other registers can be subtracted directly. Increment/ decrement:

• The 8-bit contents of a register or a memory location can be incremented/ decremented by 1.

• Similarly, the 16 bit contents of a register pair may be also incremented/ decremented by 1.

• These operations differ from add/sub in an important way. They can be performed on any ONE of the REGISTERS or IN A MEMORY LOCATION.

LOGICAL OPERATIONS: These instructions perform various logical operations with the contents of the Accumulator.

1. AND, OR, Exclusive OR: Any 8 bit number, or register contents or contents of memory locations can be logically AND-ed. OR-ed, XOR-ed with the contents of Accumulator & the result stored in the Accumulator.

2. Rotate: Each bit in the Accumulator can be shifted either left or right to the next position.

3. Compare: Any 8-bit number or contents of register or memory location can be compared for

equality, greater than or less than with the contents of the accumulator.


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4. Complement: The contents of the accumulator can be complemented; all 0s are replaced by 1s & all 1s are replaced by 0s.

BRANCHING OPERATIONS

• This group of instructions alters the sequence of program execution either conditionally or unconditionally.

• Jump – Conditional jumps are an important aspect of decision making process in

programming. These instructions test for a certain condition (zero/ carry flag) & alter the program sequence when the condition is met. In addition, the instruction set includes an instruction called Unconditional Jump.

• Call, return, re-start – They change the sequence of a program either by calling a subroutine

or returning from a sub-routine. The conditional call & return instructions also can test condition flags.

MACHINE CONTROL OPERATIONS This group of instructions control machine functions such as Halt, Interrupt or do nothing (NOP). Review of 8085 operations. The microprocessor operations related to data manipulation can be summarized in four functions:

1. Copying data 2. Performing arithmetic & logical operations 3. Testing for a given condition & altering program sequence.

INSTRUCTION FORMAT

An instruction is a command to the microprocessor to perform a given task on specified data. Each instruction has two parts: One is the task to be performed called operation code (Opcode) & the second is the data to be operated on called operand. This operand (data) can be specified in several ways like:

1. 8-bit/ 16-bit data 2. An internal register 3. A memory location 4. 8-bit/ 16 but address 5. Implicit where operand is not mentioned like CMA (Complement the contents of

Accumulator).


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Instruction Word Size: It may be

1. One-word/ 1 byte instruction: Includes Opcode & operand in the same byte. Ex: Task Opcode Operand Binary code Hex code a) Copy the contents MOV C, A 0100 1111 4FH Of the accumulator in register C b) Add the contents ADD B 1000 0000 80H Of the accumulator to register B c) Invert (Complement CMA 0010 1111 2FH each bit in the Accumlator)

Instruction 1 has both operand registers are specified, in instruction 2 only register B is specified & accumulator is assumed, in the third the operand Accumulator is implicit.

2. Two-word/ 2 byte instruction: First byte specifies operation code, 2nd. Byte specifies the operand.

Task Opcode Operand Binary code Hex code Load an 8-bit data MVI A, data 0011 1110 3E 1st byte Byte in accumulator DATA Data 2nd byte Assume data byte is 32H. Assembly language instruction is written as: Mnemonics Hex code MVI A, 32H 3E 32H This instruction needs two memory locations to store in memory.

3. Three-word/ 3 byte instruction

1st byte specifies Opcode, 2nd & 3rd byte specify the 16-bit address. Second byte is the low order address & third byte is the high order address.

Task Opcode Operand Binary code Hex code Transfer the program JMP 2085H 1100 0011 C3 1ST. BYTE sequence to the memory 1000 0101 85 2ND. BYTE location 2085H 0010 0000 20 3RD. BYTE This instruction needs three memory locations to store in memory. (Word & byte are synonymous as 8085 is an 8-bit µP). OPCODE FORMAT To understand the operation codes, it is to be examined how an instruction is designed to the µP. In design of µP chip, all operations registers, status flags are identified with specific code. All internal registers are identified with:


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Code registers Code register pairs 00 B 00 BC 001 C 01 DE 010 D 10 HL 011 E 11 AF or SP 100 H 101 L 111 A 110 reserved for memory related operations Function Op-code Add the contents of register 10000 SSS to accumulator (5-bit Opcode, 3 bits reserved

for a register) Instruction is completed by adding the code of a register. For ADD B, Add : 10000 Register B : 000 To A : Implicit Binary Instruction : 10000 000 = 80H |____| |__| Add Reg. B In assembly language, it is expressed as Opcode operand Hex code ADD B 80H A small illustrative program. Problem Statement: Add two hexadecimal nos. 32H & 48H & store the result in register C. Problem analysis: The two nos. need to be stored separately in two internal registers (can be a combination of any two registers with one register being the accumulator) .

1. Load 32H in one register say accumulator 2. Load 48H in the other register 3. Add the contents of the two registers. 4. Save the sum in register C. 5. End the program.

Program in Assembly language Opcode Operand Comments

1. MVI A, 32H ; load the no. 32H in Acc 2. MVI B, 48H ; load the no. 48H in Reg. B 3. ADD B ; add the contents of B to that of A

& store result in A


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4. MOV C,A ; Copy the result from A to C 5. HLT : End of program

Mnemonics Machine code( Hex)

1. MVI A, 3E } 32H ; 32 } 2 byte instruction 2. MVI B, 06} 48H ; 48} 2 byte instruction

3. ADD B 80 }1 byte instruction

4. MOV C,A 1 byte instruction 5. HLT 1 byte instruction

Q: How is an instruction executed by the µP? What is the time taken to execute an instruction? A: The program or instructions are stored in the memory of the micro-computer. To execute it, the µP must locate the memory location; fetch the code via the data bus, decode it in the instruction register & perform the functions specified in the code. This sequence is called “Fetch-decode-execute”. The timing is provided by the cock of the system & the sequencing is done by the control unit of the µP. Show the timing diagram for the instruction MVI A, 32H. The instruction may be written as: Mem. Loc M/C code Mnemonics 2000 3E MVI A 32H 2001 32 This instruction has 2 MCs. The first is M1, the Opcode fetch that has 4 T states, the 2nd. Is memory read with 3 T states: total there are 7 T states.

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