8-bit MCU with nested interrupts, Flash, 10-bit ADC, brushless … · April 2009 Rev 13 1/309...

April 2009 Rev 13 1/309

ST7MC1xx/ST7MC2xx8-bit MCU with nested interrupts, Flash, 10-bit ADC,

brushless motor control, five timers, SPI, LINSCI™

Features■ Memories

– 8K to 60K dual voltage Flash Program memo-ry or ROM with read-out protection capability,In-application programming and In-circuit pro-gramming.

– 384 to 1.5K RAM– HDFlash endurance: 100 cycles, data reten-

tion: 40 years at 85°C■ Clock, reset and supply management

– Enhanced reset system– Enhanced low voltage supervisor (LVD) for

main supply and auxiliary voltage detector(AVD) with interrupt capability

– Clock sources: crystal/ceramic resonator os-cillators and by-pass for external clock, clocksecurity system.

– Four power saving modes: Halt, Active-halt,Wait and Slow

■ Interrupt management– Nested interrupt controller– 14 interrupt vectors plus TRAP and RESET– MCES top level interrupt pin– 16 external interrupt lines (on 3 vectors)

■ Up to 60 I/O ports– up to 60 multifunctional bidirectional I/O lines– up to 41 alternate function lines– up to 12 high sink outputs

■ 5 timers– Main clock controller with: Real-time base,

Beep and clock-out capabilities– Configurable window watchdog timer– Two 16-bit timers with: 2 input captures, 2 out-

put compares, external clock input, PWM andpulse generator modes

– 8-bit PWM Auto-reload timer with: 2 input cap-tures, 4 PWM outputs, output compare andtime base interrupt, external clock with

event detector■ 2 Communication interfaces

– SPI synchronous serial interface– LINSCI™ asynchronous serial interface

■ Brushless motor control peripheral– 6 high sink PWM output channels for sine-

wave or trapezoidal inverter control – Motor safety including asynchronous emer-

gency stop and write-once registers– 4 analog inputs for rotor position detection

(sensorless/hall/tacho/encoder)– Permanent magnet motor coprocessor includ-

ing multiplier, programmable filters, blankingwindows and event counters

– Operational amplifier and comparator for cur-rent/voltage mode regulation and limitation

■ Analog peripheral– 10-bit ADC with 16 input pins

■ In-circuit Debug■ Instruction set

– 8-bit data manipulation– 63 basic instructions with illegal opcode de-

tection– 17 main Addressing modes– 8 x 8 unsigned multiply instruction– True bit manipulation

■ Development tools– Full hardware/software development package

Table 1. Device summary

Note 1: For development only. No production

LQFP6414 x 14

LQFP8014 x 14

LQFP32 7x 7LQFP4410 x 10

Features ST7MC1K2 / ST7MC1K4 ST7MC2N6 1)/ ST7MC2S4 / ST7MC2S6 / ST7MC2S7 / ST7MC2S9

/ ST7MC2R6 / ST7MC2R7 / ST7MC2R9 / ST7MC2M9Program memory - bytes 8K 16K 16K 32K 48K 60KRAM (stack) - bytes 384 (256) 768 (256) 768 (256) 1024 (256) 1536 (256)

PeripheralsWatchdog, 16-bit Timer A, LINSCI™, 10-bit ADC, MTC, 8-bit PWM ART, ICD

- SPI, 16-bit Timer BOperating Supply vs. Frequency

4.5 to 5.5V with fCPU≤ 8MHz

Temperature Range -40°C to +85°C

/-40°C to +125°C -40°C to +85°C

-40°C to +85°C-40°C to +125°C

-40°C to +85 °C-40°C to +125°C

Package LQFP32 LQFP32 LQFP44 SDIP561)/LQFP64 LQFP64/44 LQFP80/64 LQFP44

1

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1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.3 STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.4 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.5 ICP (IN-CIRCUIT PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.6 IAP (IN-APPLICATION PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.7 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.8 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286.1 OSCILLATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.2 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6.3 SYSTEM INTEGRITY MANAGEMENT (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6.4 MAIN CLOCK CONTROLLER WITH REAL-TIME CLOCK AND BEEPER (MCC/RTC) . 37

7 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7.2 MASKING AND PROCESSING FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7.3 INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

7.4 CONCURRENT & NESTED MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

7.5 INTERRUPT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

7.6 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

7.7 EXTERNAL INTERRUPT CONTROL REGISTER (EICR) . . . . . . . . . . . . . . . . . . . . . . . 47

8 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

8.2 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

8.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

8.4 ACTIVE-HALT AND HALT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

9 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

9.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

9.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

9.4 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

9.5 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

10 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6010.1 WINDOW WATCHDOG (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

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10.2 PWM AUTO-RELOAD TIMER (ART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

10.3 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

10.4 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

10.5 LINSCI SERIAL COMMUNICATION INTERFACE (LIN MASTER/SLAVE) . . . . . . . . . 107

10.6 MOTOR CONTROLLER (MTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

10.7 OPERATIONAL AMPLIFIER (OA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233

10.8 10-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

11 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24111.1 CPU ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

11.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

12 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24712.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

12.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248

12.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250

12.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252

12.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256

12.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260

12.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

12.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

12.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267

12.10 TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270

12.11 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 271

12.12 MOTOR CONTROL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273

12.13 OPERATIONAL AMPLIFIER CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . 280

12.14 10-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281

13 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28513.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285

13.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288

13.3 SOLDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289

14 ST7MC DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . 29014.1 FLASH OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290

14.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . 292

14.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294

14.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296

15 IMPORTANT NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29915.1 FLASH/FASTROM DEVICES ONLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299

15.2 CLEARING ACTIVE INTERRUPTS OUTSIDE INTERRUPT ROUTINE . . . . . . . . . . . . 300

15.3 TIMD SET SIMULTANEOUSLY WITH OC INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . 300

15.4 LINSCI LIMITATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300

15.5 MISSING DETECTION OF BLDC “Z EVENT” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303

15.6 INJECTED CURRENT ON PD7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303

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15.7 RESET VALUE OF UNAVAILABLE PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303

15.8 MAXIMUM VALUES OF AVD THRESHOLDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304

15.9 EXTERNAL INTERRUPT MISSED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304

16 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307

To obtain the most recent version of this datasheet,please check at www.st.com>products>technical literature>datasheet

Please also pay special attention to the Section “IMPORTANT NOTES” on page 299.

1

http://www.st.com/stonline/books/toc/ds/379.htm

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1 INTRODUCTIONThe ST7MCx device is member of the ST7 micro-controller family designed for mid-range applica-tions with a Motor Control dedicated peripheral.

All devices are based on a common industry-standard 8-bit core, featuring an enhanced instruc-tion set and are available with FLASH, ROM orFASTROM program memory.

Under software control, all devices can be placedin Wait, Slow, Active-halt or Halt mode, reducingpower consumption when the application is in idleor stand-by state.

The enhanced instruction set and addressingmodes of the ST7 offer both power and flexibility tosoftware developers, enabling the design of highlyefficient and compact application code. In additionto standard 8-bit data management, all ST7 micro-controllers feature true bit manipulation, 8x8 un-signed multiplication and indirect addressingmodes.

The devices feature an on-chip Debug Module(DM) to support in-circuit debugging (ICD). For adescription of the DM registers, refer to the ST7ICC Protocol Reference Manual.

Figure 1. Device Block Diagram

8-BIT COREALU

AD

DR

ES

S A

ND

DA

TA

BU

S

OSC1

VPP CONTROL

PROGRAM

(8K - 60K Bytes)

VDD

RESET

PORT DPD7:0(8-bits)

TIMER A

10-BIT ADC

PORT A

RAM(384 - 1536Bytes)

PORT B

MCC/RTC/BEEP1

VAREFVSSA

PORT E1

TIMER B1

PE5:0(6-bits)

MTC VOLT INPUT

PA7:0 1)(8-bits)

PORT F1

PF5:0(6-bits)

SPI1

PB7:0(8-bits)

VSS

WATCHDOG

OSC

LVD

OSC2

MEMORY

SCI/LIN

AVD

PWM ART

PORT C

(8-bits)MOTOR CONTROL

PC7:0

PORT G 1)

PORT H 1)

PG7:0 1)(8-bits)

PH7:0 1)(8-bits)

MCES

On some devices only, see Table 1, “ST7MC Device Pin Description,” on page 12

DEBUG MODULE

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2 PIN DESCRIPTION

Figure 2. 80-Pin LQFP 14x14 Package Pinout

21

345678

109

12

14

16

18

20

11

15

13

17

19

25 26 2827 30 32 34 36 3829 3331 35 37 39

5758

565554535251

4950

47

45

43

41

48

44

46

42

6059

616263646668 65676970717274 73757677787980

PD3 / ICAP1_A / AIN13PD2 / ICAP2_A / AIN12PD1 (HS) / OCMP1_A

PF0 / MCDEM / AIN8

VDD_0VSS_0VSSA

PD0 / OCMP2_A / AIN11PH3

PH2PH1

PF4 (HS)

PF1 / MCZEM / AIN9

PG1PG2PG3

OSC1

AIN2 / PA7

VDD_1

PG0

OSC2

PWM3 / PA0PWM2 / (HS) PA1

PWM1 / PA2AIN0 / PWM0 / PA3ARTCLK / (HS) PA4

AIN1 / ARTIC1 / PA5ARTIC2 / PA6

(HS) MCO3(HS) MCO4(HS) MCO5

PG

4P

G5

(HS

) P

C0

AIN

5 / M

CC

FI 0

/ PC

1

MC

PW

MU

/ PC

5

MIS

O /

PB

4A

IN3

/ MO

SI /

PB

5S

CK

/ (H

S)

PB

6A

IN4

/SS

/(H

S)

PB

7

OA

P /

PC

2 O

AN

/ P

C3

AIN

6 / M

CC

FI 1

/ OA

Z

40M

CP

WM

V/ P

C6

21 22 2423

MC

VR

EF

/ P

B0

MC

IA /

PB

1M

CIB

/ P

B2

MC

IC /

PB

3V

PP

/ICC

SE

LP

E5

PE

4 / E

XT

CLK

_B

MC

O2

(HS

)M

CO

1 (H

S)

MC

O0

(HS

)

RESET

PF3 (HS) / BEEP

PF5 (HS)

PH0

PG

6P

G7

VAREF

PC7 / MCPWMW / AIN7

* M

CC

RE

F /

PC

4

PE

3 / I

CA

P1_

B

PH

7P

H6

PH

5

PE

2 / I

CA

P2_

BP

E1

/ OC

MP

1_B

P

E0

(HS

) / O

CM

P2_

B

PH

4

PD

7 (H

S)

/ TD

OP

D6

(HS

) / R

DI

PD

5 / A

IN15

/ IC

CD

AT

A

VD

D_2

VS

S_2

PD

4 /E

XT

CLK

_A /

AIN

14 /

ICC

CLK

PF2 / MCO / AIN10VSS_1

ei0

ei2ei2ei1

ei1

(HS) 20mA high sink capabilityeix associated external interrupt vector

MCES

* Once the MTC peripheral is ON, the pin PC4 is configured to an alternate function. PC4 is no longer usable as a digital I/O

1

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PIN DESCRIPTION (Cont’d)


MIS

O /

PB

4

AIN

3 / M

OS

I / P

B5

SC

K /

(HS

) P

B6

AIN

4 / S

S /(

HS

) P

B7

(HS

) P

C0

AIN

5 / M

CC

FI0

/ P

C1

OA

P /

PC

2

OA

N /

PC

3

AIN

6 / M

CC

FI1

/ O

AZ

* M

CC

RE

F /

PC

4

MC

PW

MU

/ P

C5

MC

PW

MV

/ PC

6

MC

VR

EF

/ P

B0

MC

IA /

PB

1

MC

IB /

PB

2

MC

IC /

PB

3

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 4948

47

46

45

44

43

42

41

40

39

38

37

36

35

34

3317 18 19 20 21 22 23 24 29 30 31 3225 26 27 28

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

ei2

ei0

ei1

VSS_1VDD_1

OSC1

OSC2

PWM3 / PA0

PWM2 / (HS) PA1

PWM1 / PA2

AIN0 / PWM0 / PA3

ARTCLK / (HS) PA4AIN1 / ARTIC1 / PA5

ARTIC2 / PA6

AIN2 / PA7

(HS) MCO3

(HS) MCO4

(HS) MCO5

MCESPF5 (HS)

PF4 (HS)

PF3 (HS) / BEEP

PF2 / MCO / AIN10

PF1 / MCZEM / AIN9

PF0 / MCDEM / AIN8

RESET

VDD_0

VAREF

VSSA

VSS_0

PC7 / MCPWMW / AIN7

PD3 / ICAP1_A / AIN13


PD1 (HS) / OCMP1_A

PD0 / OCMP2_A / AIN11

PE

5 /

PE

4 / E

XT

CLK

_B

PE

3 / I

CA

P1_

B

PE

2 / I

CA

P2_

B

PE

1 / O

CM

P1_

B

PE

0 (H

S)

/ OC

MP

2_B

VD

D_2

VS

S_2

PD

7 (H

S) /

TD

O

PD

6 (H

S)

/ RD

I

PD

5 / A

IN15

/ IC

CD

AT

A

PD

4 /E

XT

CLK

_A /

AIN

14 /

ICC

CLK

MC

O2

(HS

)

MC

O1

(HS

)

MC

O0

(HS

)

VP

P /I

CC

SE

L

(HS) 20mA high sink capabilityeix associated external interrupt vector

ei1


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Figure 4. 32-Pin SDIP Package Pinouts

ICCSEL / VPP

MCO0

MCO1

MCO2

MCO3

MCO4

MCO5

MCES

OSC1

OSC2

AIN0 / PWM0 / PA3

AIN1 / ARTIC1 / PA5

MCVREF / PB0

MCIA / PB1

MCIB / PB2

MCIC / PB3

PD7 (HS) / TDO

PD6 (HS) / RDI

PD5 / AIN15 / ICCDATA

PD4 / EXTCLK_A / AIN14 / ICCCLK


PD2 / ICAP2_A / MCZEM / AIN12

PD1 (HS) / OCMP1_A / MCPWMV / MCDEM

PD0 / OCMP2_A / MCPWMW / AIN11

RESET

VDD_0

VSS_0

VAREF

PC4 / MCCREF *

OAZ / MCCFI1 / AIN6

PC3 / OAN

PC2 / OAP

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

ei1

ei2

ei0

(HS) 20mA high sink capability

eix associated external interrupt vector


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Figure 5. 56-Pin SDIP Package Pinouts

52

51

50

49

48

47

46

45

44

43

42

4116

15

1

2

3

4

5

6

7

8

9

10

11

12

13

14

53

54

55

56

(HS) MCO1

(HS) MCO0

VPP/ICCSEL

ICAP1_B / PE3

ICAP2_B / PE2

OCMP1_B / PE1

21

20

17

18

19

MCES

(HS) MCO5

(HS) MCO4

(HS) MCO3

(HS) MCO2

40

39

38

37

36

23

22

28

27

24

25

26

35

34

33

32

31

30

29

OSC2

OSC1

Vdd_1Vss_1

PWM2 / (HS) PA1AIN0 / PWM0 / PA3

ARTCLK / (HS) PA4AIN1 / ARTIC1 / PA5

ARTIC2 / PA6

MISO / PB4

AIN3 / MOSI / PB5

SCK / (HS) PB6

AIN4 / SS /(HS) PB7

MCVREF / PB0

MCIA / PB1

MCIB / PB2

MCIC / PB3

PF3 (HS) / BEEP

PF1 / MCZEM / AIN9

PF0 / MCDEM / AIN8

RESET

VDD_0

VAREF

VSSA

VSS_0

PC7 / MCPWMW / AIN7



PD1 (HS) / OCMP1_A


PE0 (HS) / OCMP2_B

VDD_2

VSS_2

PD7 (HS) / TDOPD6 (HS) / RDI

PD5 / AIN15 / ICCDATA

PD4 /EXTCLK_A / AIN14 / ICCCLK

OAZ / MCCFI1 / AIN6

PC4 / MCCREF *

PC3 / OAN

PC2 / OAP

PC6 / MCPWMV

PC5 / MCPWMU

PC1 / MCCFI0/AIN5

PC0(HS)

ei0

ei2

ei1

ei1

ei2

(HS) 20mA high sink capabilityeix associated external interrupt vector* Once the MTC peripheral is ON, the pin PC4 is configured to an alternate function. PC4 is no longer usable as a digital I/O

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Figure 6. 44-Pin LQFP Package Pinouts

MIS

O /

PB

4

AIN

3 / M

OS

I / P

B5

SC

K /

(HS

) P

B6

AIN

4 / S

S /(

HS

) P

B7

OA

P /

PC

2

OA

N /

PC

3

AIN

6 / M

CC

FI1

/ O

AZ

* M

CC

RE

F /

PC

4

MC

IA /

PB

1

MC

IB /

PB

2

MC

IC /

PB

344 43 42 41 40 39 38 37 36 35 34

33

32

31

30

29

28

27

26

25

24

2312 13 14 15 16 17 18 19 20 21 22

1

2

3

4

5

6

7

8

9

10

11ei2

ei0

ei1

VSS_1

OSC1

OSC2

AIN0 / PWM0 / PA3

AIN1 / ARTIC1 / PA5

MCVREF / PB0

(HS) MCO3

(HS) MCO4

(HS) MCO5

MCES


RESET

VDD_0

VAREF

VSSA

VSS_0

PC7 / MCPWMW / AIN7

PD4 /EXTCLK_A / AIN14 / ICCCLK



PD1 (HS) / OCMP1_A / MCPWMV/MCDEMP

E3

/ IC

AP

1_B

PE

2 / I

CA

P2_

B

PE

1 / O

CM

P1_

B

PE

0 (H

S)

/ OC

MP

2_B

PD

7 (H

S) /

TD

O

PD

6 (H

S)

/ RD

I

PD

5 / A

IN15

/ IC

CD

AT

A

MC

O2

(HS

)

MC

O1

(HS

)M

CO

0 (H

S)

VP

P /I

CC

SE

L

eix associated external interrupt vector(HS) 20mA high sink capability

VDD_1


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MC

IC /

PB

3

OA

P /

PC

2

OA

N /

PC

3

AIN

6 / M

CC

FI1

/ O

AZ

* M

CC

RE

F /

PC

4

MC

VR

EF

/ P

B0

MC

IA /

PB

1

MC

IB /

PB

2

32 31 30 29 28 27 26 2524

23

22

21

20

19

18

179 10 11 12 13 14 15 16

1

2

3

4

5

6

7

8 ei1

ei0

OSC1

OSC2

AIN0 / PWM0 / PA3

AIN1 / ARTIC1 / PA5

(HS) MCO3

(HS) MCO4

(HS) MCO5

MCES

RESET

VDD_0

VAREF

VSS_0



PD1 (HS) / OCMP1_A / MCPWMV / MCDEM

PD0 / OCMP2_A / MCPWMW /AIN11

PD

7 (H

S) /

TD

O

PD

6 (H

S)

/ RD

I

PD

5 / A

IN15

/ IC

CD

AT

A

PD

4 /E

XT

CLK

_A /

AIN

14 /

ICC

CLK

MC

O2

(HS

)

MC

O1

(HS

)

MC

O0

(HS

)

VP

P /I

CC

SE

L

ei2

eix associated external interrupt vector(HS) 20mA high sink capability


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For external pin connection guidelines, See “ELECTRICAL CHARACTERISTICS” on page 247.

Legend / Abbreviations for Table 1:Type: I = input, O = output, S = supply

Input level: A = Dedicated analog input

In/Output level: CT= CMOS 0.3VDD/0.7VDD with Schmitt trigger

TT= Refer to the G&H ports Characteristics in section 12.8.1 on page 264

Output level: HS = 20mA high sink (on N-buffer only)

Port and control configuration:

– Input: float = floating, wpu = weak pull-up, wpd = weak pull-down, int = interrupt 1), ana = analog

– Output: OD = open drain, PP = push-pull

Refer to “I/O PORTS” on page 54 for more details on the software configuration of the I/O ports.

The RESET configuration of each pin is shown in bold which is valid as long as the device is in reset state.

Table 1. ST7MC Device Pin Description

Pin n°

Pin Name

Typ

e

Level Port Mainfunction

(afterreset)

Alternate function 2)

LQ

FP

80

LQ

FP

64

SD

IP56

LQ

FP

44

SD

IP32

LQ

FP

32

Inp

ut

Ou

tpu

t Input 1) Output

flo

at

wp

u

int

ana

OD

PP

1 1 8 1 5 1 MCO3 (HS) O HS X Motor Control Output 3



4 4 11 4 8 4 MCES3) I CT X MTC Emergency Stop

5 - - - - - PG0 I/O TT X X X X Port G0




9 5 12 5 9 5 OSC14) IExternal clock input or Resonator oscillator inverter input

10 6 13 6 10 6 OSC24) I/O Resonator oscillator inverter output

11 7 14 7 - - Vss_15) S Digital Ground Voltage

12 8 15 8 - - Vdd_15) S Digital Main Supply Voltage

13 9 - - - - PA0/PWM3 I/O CT X X X X Port A0 PWM Output 3

14 10 16 - - - PA1/PWM2 I/O CT HS X X X X Port A1 PWM Output 2

15 11 - - - - PA2PWM1 I/O CT X X X X Port A2 PWM Output 1

16 12 17 9 11 7PA3/PWM0/AIN0

I/O CT X ei1 X X X Port A3PWM Out-put 0

ADC Ana-log Input 0

17 13 18 - - -PA4 (HS)/ART-CLK

I/O CT HS X X X X Port A4 PWM-ART External Clock

18 14 19 10 12 8PA5 / ARTIC1/AIN1

I/O CT X ei1 X X X Port A5PWM-ART Input Cap-ture 1

ADC Analog Input 1

19 15 20 - - - PA6 / ARTIC2 I/O CT X ei1 X X Port A6PWM-ART Input Capture 2

20 16 - - - - PA7/AIN2 I/O CT X ei1 X X X Port A7 ADC Analog Input 2

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21 17 21 11 13 9 PB0/MCVREF I/O CT X X X X X Port B0 MTC Voltage Reference

22 18 22 12 14 10 PB1/MCIA I/O CT X X X X X Port B1 MTC Input A

23 19 23 13 15 11 PB2/MCIB I/O CT X X X X X Port B2 MTC Input B

24 20 24 14 16 12 PB3/MCIC I/O CT X X X X X Port B3 MTC Input C

25 21 25 15 - - PB4/MISO I/O CT X X X X Port B4SPI Master In / Slave Out Data

26 22 26 16 - -PB5/MOSI/AIN3

I/O CT X X X X Port B5SPI Master Out / Slave In Data

ADC Ana-log Input 3

27 23 27 17 - - PB6/SCK I/O CT HS X ei2 X X Port B6 SPI Serial Clock

28 24 28 18 - - PB7/SS/AIN4 I/O CT HS X ei2 X X Port B7SPI Slave Select (ac-tive low)

ADC Ana-log Input 4





33 25 29 - - - PC0 I/O CT HS X ei2 X X Port C0

34 26 30 - - -PC1/MCCFI06) /AIN5

I/O CT X ei2 X X X Port C1

MTC Cur-rent Feed-back Input 06)

ADC Ana-log Input 5

35 27 31 19 17 13 PC2/OAP I/O CT X ei2 X X X Port C2 OPAMP Positive Input

36 28 32 20 18 14 PC3/OAN I/O CT X X ei2 X X X Port C3 OPAMP Negative Input

37 29 33 21 19 15OAZ/MCCFI16)/AIN6

I/O XOpamp Output

MTC Cur-rent Feed-back Input 16)

ADC analog Input 6

38 30 34 22 20 16 PC4/MCCREF I/O CT X X X X X Port C4MTC Current Feedback Reference 9)

39 31 35 - - -PC5/MCPW-MU

I/O CT X X X X Port C5 MTC PWM Output U

40 32 36 - - -PC6/MCPWMV8)

I/O CT X X X X Port C6 MTC PWM Output V8)

41 33 37 23 - -PC7/MCPWMW8)/AIN7

I/O CT X X X X X Port C7MTC PWM Output W8)

ADC Ana-logInput 7

42 34 38 24 21 17 VAREF I Analog Reference Voltage for ADC

43 35 39 25 - - VSSA5) S Analog Ground Voltage

44 36 40 26 22 18 VSS_05) S Digital Ground Voltage

45 37 41 27 23 19 VDD_05) S Digital Main Supply Voltage

46 38 42 28 24 20 RESET I/O CT Top priority non maskable interrupt


Pin n°

Pin Name

Typ

e


(afterreset)


LQ

FP

80

LQ

FP

64

SD

IP56

LQ

FP

44

SD

IP32

LQ

FP

32

Inp

ut

Ou

tpu

t Input 1) Output

flo

at

wp

u

int

ana

OD

PP

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47 39 43 - - -PF0/MCDEM7)/AIN8

I/O CT X X X X X Port F0

MTC De-magnetiza-tion Output7)

ADC Ana-log Input 8

48 40 44 - - -PF1/MCZEM7)/AIN9

I/O CT X X X X X Port F1MTC BEMF Output7)

ADC Ana-log Input 9

49 41 - - - -PF2/MCO/AIN10

I/O CT X X X X X Port F2Main Clock Out (fosc/2)

ADC Ana-log Input 10

50 42 45 - - - PF3/BEEP I/O CT HS X X X X Port F3 Beep Signal Output

51 43 - - - - PF4 I/O CT HS X X X X Port F4

52 44 - - - - PF5 I/O CT HS X X X X Port F5

53 - - - - - PH0 I/O TT X X X X Port H0




57 45 46 29 25 21

PD0/OCMP2_A/MCPWMW8)/AIN11

I/O CT X X X X Port D0

Timer A Output Compare 2

MTC PWM Output W8)

ADC Analog Input 11

58 46 47 30 26 22

PD1 (HS)/OCMP1_A/MCPWMV8)/MCDEM7)

I/O CT HS X ei0 X X Port D1

Timer A Output Compare 1

MTC PWM Output V8)

MTC Demagnetization7)

59 47 48 31 27 23PD2/ICAP2_A/MCZEM7) / AIN12

I/O CT X ei0 X X X Port D2

Timer A Input Capture 2

MTC BEMF7)

ADC Analog Input 12

60 48 49 32 28 24PD3/ICAP1_A/AIN13

I/O CT X ei0 X X X Port D3Timer A Input Capture 1

ADC AnalogInput 13

61 49 50 33 29 25PD4/EXTCLK_A/IC-CCLK/AIN14

I/O CT X ei0 X X X Port D4

Timer A External Clock source

ICC Clock Output

ADC Analog Input 14

62 50 51 34 30 26PD5/ICCDA-TA/AIN15

I/O CT X ei0 X X X Port D5ICC Data Input

ADC Analog Input 15

63 51 52 35 31 27 PD6/RDI I/O CT HS X ei0 X X Port D6 SCI Receive Data In

64 52 53 36 32 28 PD7/TDO I/O CT HS X X X X Port D7 SCI Transmit Data Output

65 53 54 - - - VSS_2 S Digital Ground Voltage

66 54 55 - - - VDD_2 S Digital Main Supply Voltage




Pin n°

Pin Name

Typ

e


(afterreset)


LQ

FP

80

LQ

FP

64

SD

IP56

LQ

FP

44

SD

IP32

LQ

FP

32

Inp

ut

Ou

tpu

t Input 1) Output

flo

at

wp

u

int

ana

OD

PP

1

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Notes:1. In the interrupt input column, “eiX” defines the associated external interrupt vector. If the weak pull-upcolumn (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input,else the configuration is floating interrupt input2. If two alternate function outputs are enabled at the same time on a given pin (for instance, MCPWMVand MCDEM on PD1 on LQFP32), the two signals will be ORed on the output pin.3. MCES is a floating input. To disable this function, a pull-up resistor must be used.4. OSC1 and OSC2 pins connect a crystal/ceramic resonator or an external source to the on-chip oscilla-tor; see Section 1 INTRODUCTION and Section 12.5 CLOCK AND TIMING CHARACTERISTICS formore details.5. It is mandatory to connect all available VDD and VDDA pins to the supply voltage and all VSS and VSSApins to ground.6. MCCFI can be mapped on 2 different pins on 80 ,64 and 56-pin packages. This allows:- either to use PC1 as a standard I/O and map MCCFI on OAZ (MCCFI1) with or without using the oper-ational amplifier (selected case after reset),- or to map MCCFI on PC1 (MCCFI0) and use the amplifier for another function.The mapping can be selected in MREF register of motor control cell. See section MOTOR CONTROL formore details.7. MCZEM is mapped on PF1 on 80, 64 and 56-pin packages and on PD2 on 44 and 32-pins.MCDEM is mapped on PF0 on 80, 64 and 56-pin packages and on PD1 on 44 and 32-pin packages.8. MCPWMV is mapped on PC6 on 80 and 64-pin packages and on PD1 on 44,and 32-pins packages.MCPWMW is mapped on PC7 on 80, 64 and 44-pin packages and on PD0 on 32-pins package.9. Once the MTC peripheral is ON (bits CKE=1 or DAC=1 in the register MCRA), the pin PC4 is configured



71 55 56 37 - -PE0/OCMP2_B

I/O CT HS X X X X Port E0Timer B Output Compare 2

72 56 1 38 - -PE1/OCMP1_B

I/O CT X X X X X Port E1Timer B Output Compare 1

73 57 2 39 - - PE2/ICAP2_B I/O CT X X X X Port E2 Timer B Input Capture 2

74 58 3 40 - - PE3/ICAP1_B/ I/O CT X X X X X Port E3 Timer B Input Capture 1

75 59 - - - -PE4/EXTCLK_B

I/O CT X X X X Port E4Timer B External Clock source

76 60 - - - - PE5 I/O CT X X X X X Port E5

77 61 4 41 1 29 VPP/ICCSEL I

Must be tied low. In the program-ming mode when available, this pin acts as the programming voltage in-put VPP./ ICC mode pin. See section 12.9.2 on page 269

78 62 5 42 2 30 MCO0 (HS) O HS X MTC Output Channel 0




Pin n°

Pin Name

Typ

e


(afterreset)


LQ

FP

80

LQ

FP

64

SD

IP56

LQ

FP

44

SD

IP32

LQ

FP

32

Inp

ut

Ou

tpu

t Input 1) Output

flo

at

wp

u

int

ana

OD

PP

1

ST7MC1xx/ST7MC2xx

16/309

to an alternate function. PC4 is no longer usable as a digital I/O.l10. On the chip, each I/O port has 8 pads. Pads that are not bonded to external pins are in input pull-upconfiguration after reset. The configuration of these pads must be kept at reset state to avoid added cur-rent consumption. Refer to section 15.7 on page 303

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3 REGISTER & MEMORY MAPAs shown in Figure 8, the MCU is capable of ad-dressing 64K bytes of memories and I/O registers.

The available memory locations consist of 128bytes of register locations, up to 2Kbytes of RAMand up to 60Kbytes of user program memory. TheRAM space includes up to 256 bytes for the stackfrom 0100h to 01FFh.

The highest address bytes contain the user resetand interrupt vectors.

IMPORTANT: Memory locations marked as “Re-served” must never be accessed. Accessing a re-served area can have unpredictable effects on thedevice.

Figure 8. Memory Map

As shown in Figure 9, the MCU is capable of ad-dressing 64K bytes of memories and I/O registers.

The available memory locations consist of 128bytes of register locations, up to 1536 bytes ofRAM and up to 60 Kbytes of user program memo-

ry. The RAM space includes up to 256 bytes forthe stack from 0100h to 01FFh.

The highest address bytes contain the user resetand interrupt vectors.

0000h

RAM

Program Memory(60K, 48K, 32K, 16K, 8K)

Interrupt & Reset Vectors

HW Registers

0080h007Fh

0FFFh

(see Table 2)

1000h

FFDFhFFE0h

FFFFh(see Table 8)

0680hReserved

067Fh

Short AddressingRAM (zero page)

256 Bytes Stack

16-bit AddressingRAM

0100h

01FFh

01FFh

0080h

0200h

00FFh

1000h

32 KBytes

60 KBytes

FFFFh

8000h

(1536/1024

or 047Fh

8 KBytesE000h

768/384 Bytes)

or 037Fh

or 067Fh

16 KBytesC000h

48 KBytes4000h

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Table 2. Hardware Register Map

Address BlockRegister

LabelRegister Name

Reset Status

Remarks

0000h0001h0002h

Port APADRPADDRPAOR

Port A Data RegisterPort A Data Direction RegisterPort A Option Register

00h1)

00h00h

R/WR/WR/W2)

0003h0004h0005h

Port BPBDRPBDDRPBOR

Port B Data RegisterPort B Data Direction RegisterPort B Option Register

00h1)

00h00h

R/WR/WR/W

0006h0007h0008h

Port CPCDRPCDDRPCOR

Port C Data RegisterPort C Data Direction RegisterPort C Option Register

00h1)

00h00h

R/WR/WR/W

0009h000Ah000Bh

Port DPDDRPDDDRPDOR

Port D Data RegisterPort D Data Direction RegisterPort D Option Register

00h1)

00h00h

R/WR/WR/W

000Ch000Dh000Eh

Port EPEDRPEDDRPEOR

Port E Data RegisterPort E Data Direction RegisterPort E Option Register

00h1)

00h00h

R/WR/W2)

R/W2)

000Fh0010h0011h

Port FPFDRPFDDRPFOR

Port F Data RegisterPort F Data Direction RegisterPort F Option Register

00h1)

00h00h

R/WR/WR/W

0012h0013h0014h

Port GPGDRPGDDRPGOR

Port G Data RegisterPort G Data Direction RegisterPort G Option Register

00h1)

00h00h

R/WR/WR/W

0015h0016h0017h

Port HPHDRPHDDRPHOR

Port H Data RegisterPort H Data Direction RegisterPort H Option Register

00h1)

00h00h

R/WR/WR/W

0018h0019h001Ah001Bh001Ch001Dh001Eh001Fh

LINSCI™

SCISRSCIDRSCIBRRSCICR1SCICR2SCICR3SCIERPRSCIETPR

SCI Status RegisterSCI Data RegisterSCI Baud Rate RegisterSCI Control Register 1SCI Control Register 2SCI Control Register 3SCI Extended Receive Prescaler RegisterSCI Extended Transmit Prescaler Register

C0hxxh00hxxh00h00h00h00h

Read Only R/W R/W R/W R/W R/WR/W R/W

0020h Reserved Area (1 Byte)

0021h0022h0023h

SPISPIDRSPICRSPICSR

SPI Data I/O RegisterSPI Control RegisterSPI Control/Status Register

xxh0xh00h

R/W R/W R/W

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0024h0025h0026h0027h0028h

ITC

ITSPR0ITSPR1ITSPR2ITSPR3EICR

Interrupt Software Priority Register 0Interrupt Software Priority Register 1Interrupt Software Priority Register 2Interrupt Software Priority Register 3External Interrupt Control Register

FFhFFhFFhFFh00h

R/WR/WR/WR/WR/W

0029h FLASH FSCR Flash Control/Status Register 00h R/W

002Ah

002BhWATCHDOG

WDGCR Window Watchdog Control Register 7Fh R/W

WDGWR Window Watchdog Window Register 7Fh R/W

002Ch002Dh

MCCMCCSRMCCBCR

Main Clock Control / Status RegisterMain Clock Controller: Beep Control Register

00h00h

R/WR/W

002Eh002Fh0030h

ADCADCCSRADCDRMSBADCDRLSB

Control/Status RegisterData Register MSBData Register LSB

00h00h00h

R/WRead Only Read Only

0031h0032h0033h0034h0035h0036h0037h0038h0039h003Ah003Bh003Ch003Dh003Eh003Fh

TIMER A

TACR2TACR1TACSRTAIC1HRTAIC1LRTAOC1HRTAOC1LRTACHRTACLRTAACHRTAACLRTAIC2HRTAIC2LRTAOC2HRTAOC2LR

Timer A Control Register 2Timer A Control Register 1Timer A Control/Status RegisterTimer A Input Capture 1 High RegisterTimer A Input Capture 1 Low RegisterTimer A Output Compare 1 High RegisterTimer A Output Compare 1 Low RegisterTimer A Counter High RegisterTimer A Counter Low RegisterTimer A Alternate Counter High RegisterTimer A Alternate Counter Low RegisterTimer A Input Capture 2 High RegisterTimer A Input Capture 2 Low RegisterTimer A Output Compare 2 High RegisterTimer A Output Compare 2 Low Register

00h00hxxhxxhxxh80h00hFFhFChFFhFChxxhxxh80h00h

R/W R/W R/W Read Only Read Only R/W R/W Read Only Read Only Read Only Read Only Read Only Read Only R/W R/W

0040h SIM SICSR System Integrity Control/Status Register 000x000x b R/W

0041h0042h0043h0044h0045h0046h0047h0048h0049h004Ah004Bh004Ch004Dh004Eh004Fh

TIMER B

TBCR2TBCR1TBCSRTBIC1HRTBIC1LRTBOC1HRTBOC1LRTBCHRTBCLRTBACHRTBACLRTBIC2HRTBIC2LRTBOC2HRTBOC2LR

Timer B Control Register 2Timer B Control Register 1Timer B Control/Status RegisterTimer B Input Capture 1 High RegisterTimer B Input Capture 1 Low RegisterTimer B Output Compare 1 High RegisterTimer B Output Compare 1 Low RegisterTimer B Counter High RegisterTimer B Counter Low RegisterTimer B Alternate Counter High RegisterTimer B Alternate Counter Low RegisterTimer B Input Capture 2 High RegisterTimer B Input Capture 2 Low RegisterTimer B Output Compare 2 High RegisterTimer B Output Compare 2 Low Register

00h00hxxhxxhxxh80h00hFFhFChFFhFChxxhxxh80h00h

R/W R/W R/W Read Only Read Only R/W R/W Read Only Read Only Read Only Read Only Read Only Read Only R/W R/W



LabelRegister Name

Reset Status

Remarks

1

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0050h0051h0052h0053h0054h0055h0056h0057h0058h0059h005Ah005Bh005Ch005Dh005Eh005Fh0060h0061h0062h0063h0064h0065h0066h0067h0068h0069h006Ah

MTC(page 0)

MTIMMTIMLMZPRVMZREGMCOMPMDREGMWGHTMPRSRMIMRMISRMCRAMCRBMCRCMPHSTMDFRMCFRMREFMPCRMREPMCPWHMCPWLMCPVHMCPVLMCPUHMCPULMCP0HMCP0L

Timer Counter High RegisterTimer Counter Low RegisterCapture Zn-1 RegisterCapture Zn RegisterCompare Cn+1 RegisterDemagnetization RegisterAn Weight RegisterPrescaler & Sampling RegisterInterrupt Mask RegisterInterrupt Status RegisterControl Register AControl Register BControl Register CPhase State RegisterD event Filter RegisterCurrent feedback Filter RegisterReference RegisterPWM Control RegisterRepetition Counter RegisterCompare Phase W Preload Register HighCompare Phase W Preload Register LowCompare Phase V Preload Register HighCompare Phase V Preload Register LowCompare Phase U Preload Register HighCompare Phase U Preload Register LowCompare Phase 0 Preload Register HighCompare Phase 0 Preload Register Low

00h00h00h00h00h00h00h00h00h00h00h00h00h00h0Fh00h00h00h00h00h00h00h00h00h00h0FhFFh

R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/W

0050h0051h0052h0053h0054h0055h0056h

MTC (page 1)

MDTGMPOLMPWMEMCONFMPARMZRFMSCR

Dead Time Generator EnablePolarity RegisterPWM RegisterConfiguration RegisterParity RegisterZ event Filter RegisterSampling Clock Register

FFh3Fh00h02h00h0Fh00h

see MTC description

0057h to 006Ah

Reserved Area (4 Bytes)

006Bh006Ch006Dh006Eh006Fh0070h

DM

DMCRDMSRDMBK1HDMBK1LDMBK2HDMBK2L

Debug Control RegisterDebug Status RegisterDebug Breakpoint 1 MSB RegisterDebug Breakpoint 1 LSB RegisterDebug Breakpoint 2 MSB RegisterDebug Breakpoint 2 LSB Register

00h10hFFhFFhFFhFFh

R/WRead OnlyR/WR/WR/WR/W



LabelRegister Name

Reset Status

Remarks

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Legend: x=undefined, R/W=read/writeNotes:1. The contents of the I/O port DR registers are readable only in output configuration. In input configura-tion, the values of the I/O pins are returned instead of the DR register contents.2. The bits associated with unavailable pins must always keep their reset value.

0074h0075h0076h0077h0078h

0079h007Ah007Bh

007Ch007Dh007Eh

PWM ART

PWMDCR3PWMDCR2PWMDCR1PWMDCR0PWMCR

ARTCSRARTCARARTARR

ARTICCSRARTICR1ARTICR2

PWM AR Timer Duty Cycle Register 3PWM AR Timer Duty Cycle Register 2PWM AR Timer Duty Cycle Register 1PWM AR Timer Duty Cycle Register 0PWM AR Timer Control Register

Auto-Reload Timer Control/Status RegisterAuto-Reload Timer Counter Access RegisterAuto-Reload Timer Auto-Reload Register

AR Timer Input Capture Control/Status Reg.AR Timer Input Capture Register 1AR Timer Input Capture Register 2

00h00h00h00h00h

00h00h00h

00h00h00h

R/WR/WR/WR/WR/W

R/WR/WR/W

R/WRead OnlyRead Only

007Fh OPAMP OACSR OPAMP Control/Status Register 00h R/W



LabelRegister Name

Reset Status

Remarks

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4 FLASH PROGRAM MEMORY

4.1 INTRODUCTION

The ST7 dual voltage High Density Flash (HDFlash) is a non-volatile memory that can beelectrically erased as a single block or by individu-al sectors and programmed on a Byte-by-Byte ba-sis using an external VPP supply.

The HDFlash devices can be programmed anderased off-board (plugged in a programming tool)or on-board using ICP (In-Circuit Programming) orIAP (In-Application Programming).

The array matrix organisation allows each sectorto be erased and reprogrammed without affectingother sectors.

4.2 MAIN FEATURES

■ 3 Flash programming modes:– Insertion in a programming tool. In this mode,

all sectors including option bytes can be pro-grammed or erased.

– ICP (In-Circuit Programming). In this mode, allsectors including option bytes can be pro-grammed or erased without removing the de-vice from the application board.

– IAP (In-Application Programming) In thismode, all sectors except Sector 0, can be pro-grammed or erased without removing the de-vice from the application board and while theapplication is running.

■ ICT (In-Circuit Testing) for downloading andexecuting user application test patterns in RAM

■ Read-out protection■ Register Access Security System (RASS) to

prevent accidental programming or erasing

4.3 STRUCTURE

The Flash memory is organised in sectors and canbe used for both code and data storage.

Depending on the overall Flash memory size in themicrocontroller device, there are up to three usersectors (see Table 3). Each of these sectors canbe erased independently to avoid unnecessaryerasing of the whole Flash memory when only apartial erasing is required.

The first two sectors have a fixed size of 4 Kbytes(see Figure 9). They are mapped in the upper partof the ST7 addressing space so the reset and in-terrupt vectors are located in Sector 0 (F000h-FFFFh).

Table 3. Sectors available in Flash devices

4.3.1 Read-out ProtectionRead-out protection, when selected, provides aprotection against Program Memory content ex-traction and against write access to Flash memo-ry. Even if no protection can be considered as to-tally unbreakable, the feature provides a very highlevel of protection for a general purpose microcon-troller.

In Flash devices, this protection is removed by re-programming the option. In this case, the entireprogram memory is first automatically erased andthe device can be reprogrammed.

Read-out protection selection depends on the de-vice type:

– In Flash devices it is enabled and removed through the FMP_R bit in the option byte.

– In ROM devices it is enabled by mask option specified in the Option List.

Figure 9. Memory Map and Sector Address

Flash Size (bytes) Available Sectors

4K Sector 0

8K Sectors 0,1

> 8K Sectors 0,1, 2

4 Kbytes

4 Kbytes

2 Kbytes

SECTOR 1

SECTOR 0

16 Kbytes

SECTOR 2

8K 16K 32K 60K FLASH

FFFFh

EFFFh

DFFFh

3FFFh

7FFFh

1000h

24 Kbytes

MEMORY SIZE

8 Kbytes 40 Kbytes 52 Kbytes

9FFFh

BFFFh

D7FFh

4K 10K 24K 48K

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FLASH PROGRAM MEMORY (Cont’d)

4.4 ICC INTERFACE

ICC (In-Circuit Communication) needs a minimumof four and up to six pins to be connected to theprogramming tool (see Figure 10). These pins are:

– RESET: device reset– VSS: device power supply ground

– ICCCLK: ICC output serial clock pin– ICCDATA: ICC input/output serial data pin– ICCSEL/VPP: programming voltage– OSC1(or OSCIN): main clock input for exter-

nal source (optional)– VDD: application board power supply (see Fig-

ure 10, Note 3)

Figure 10. Typical ICC Interface

Notes:1. If the ICCCLK or ICCDATA pins are only usedas outputs in the application, no signal isolation isnecessary. As soon as the Programming Tool isplugged to the board, even if an ICC session is notin progress, the ICCCLK and ICCDATA pins arenot available for the application. If they are used asinputs by the application, isolation such as a serialresistor has to implemented in case another de-vice forces the signal. Refer to the ProgrammingTool documentation for recommended resistor val-ues.

2. During the ICC session, the programming toolmust control the RESET pin. This can lead to con-flicts between the programming tool and the appli-cation reset circuit if it drives more than 5mA athigh level (push pull output or pull-up resistor 1K or a reset man-

agement IC with open drain output and pull-upresistor > 1K, no additional components are need-ed. In all cases the user must ensure that no exter-nal reset is generated by the application during theICC session.

3. The use of Pin 7 of the ICC connector dependson the Programming Tool architecture. This pinmust be connected when using most ST Program-ming Tools (it is used to monitor the applicationpower supply). Please refer to the ProgrammingTool manual.

4. Pin 9 has to be connected to the OSC1 or OS-CIN pin of the ST7 when the clock is not availablein the application or if the selected clock option isnot programmed in the option byte. ST7 deviceswith multi-oscillator capability need to have OSC2grounded in this case.

ICC CONNECTOR

ICC

DA

TA

ICC

CLK

RE

SE

T

VD

D

HE10 CONNECTOR TYPE

APPLICATIONPOWER SUPPLY

1

246810

9 7 5 3

PROGRAMMING TOOL

ICC CONNECTOR

APPLICATION BOARD ICC Cable

(See Note 3)

10kΩ

VS

S

ICC

SE

L/V

PP

ST7

CL2 CL1

OS

C1

OS

C2

OPTIONAL

See Note 1

See Note 2

APPLICATIONRESET SOURCE

APPLICATIONI/O

(See Note 4)

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FLASH PROGRAM MEMORY (Cont’d)

4.5 ICP (IN-CIRCUIT PROGRAMMING)

To perform ICP the microcontroller must beswitched to ICC (In-Circuit Communication) modeby an external controller or programming tool.

Depending on the ICP code downloaded in RAM,Flash memory programming can be fully custom-ized (number of bytes to program, program loca-tions, or selection serial communication interfacefor downloading).

When using an STMicroelectronics or third-partyprogramming tool that supports ICP and the spe-cific microcontroller device, the user needs only toimplement the ICP hardware interface on the ap-plication board (see Figure 10). For more detailson the pin locations, refer to the device pinout de-scription.

4.6 IAP (IN-APPLICATION PROGRAMMING)

This mode uses a BootLoader program previouslystored in Sector 0 by the user (in ICP mode or byplugging the device in a programming tool).

This mode is fully controlled by user software. Thisallows it to be adapted to the user application, (us-er-defined strategy for entering programmingmode, choice of communications protocol used tofetch the data to be stored, etc.). For example, it ispossible to download code from the SPI, SCI orother type of serial interface and program it in theFlash. IAP mode can be used to program any ofthe Flash sectors except Sector 0, which is write/erase protected to allow recovery in case errorsoccur during the programming operation.

4.7 RELATED DOCUMENTATION

For details on Flash programming and ICC proto-col, refer to the ST7 Flash Programming Refer-ence Manual and to the ST7 ICC Protocol Refer-ence Manual.

4.8 REGISTER DESCRIPTION

FLASH CONTROL/STATUS REGISTER (FCSR)

Read/Write

Reset Value: 0000 0000 (00h)

This register is reserved for use by ProgrammingTool software. It controls the Flash programmingand erasing operations.

7 0

0 0 0 0 0 0 0 0

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5 CENTRAL PROCESSING UNIT

5.1 INTRODUCTION

This CPU has a full 8-bit architecture and containssix internal registers allowing efficient 8-bit datamanipulation.

5.2 MAIN FEATURES

■ Enable executing 63 basic instructions■ Fast 8-bit by 8-bit multiply■ 17 main addressing modes (with indirect

addressing mode)■ Two 8-bit index registers■ 16-bit stack pointer■ Low power Halt and Wait modes■ Priority maskable hardware interrupts■ Non-maskable software/hardware interrupts

5.3 CPU REGISTERS

The six CPU registers shown in Figure 11 are notpresent in the memory mapping and are accessedby specific instructions.

Accumulator (A)The Accumulator is an 8-bit general purpose reg-ister used to hold operands and the results of thearithmetic and logic calculations and to manipulatedata.

Index Registers (X and Y)These 8-bit registers are used to create effectiveaddresses or as temporary storage areas for datamanipulation. (The Cross-Assembler generates aprecede instruction (PRE) to indicate that the fol-lowing instruction refers to the Y register.)

The Y register is not affected by the interrupt auto-matic procedures.

Program Counter (PC) The program counter is a 16-bit register containingthe address of the next instruction to be executedby the CPU. It is made of two 8-bit registers PCL(Program Counter Low which is the LSB) and PCH(Program Counter High which is the MSB).

Figure 11. CPU Registers

ACCUMULATOR

X INDEX REGISTER

Y INDEX REGISTER

STACK POINTER

CONDITION CODE REGISTER

PROGRAM COUNTER

7 0

1 C1 I1 H I0 N Z

RESET VALUE = RESET VECTOR @ FFFEh-FFFFh

7 0

7 0

7 0

0715 8PCH PCL

15 8 7 0

RESET VALUE = STACK HIGHER ADDRESS

RESET VALUE = 1 X1 1 X 1 X X

RESET VALUE = XXh

RESET VALUE = XXh

RESET VALUE = XXh

X = Undefined Value

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CENTRAL PROCESSING UNIT (Cont’d)

Condition Code Register (CC) Read/Write

Reset Value: 111x1xxx

The 8-bit Condition Code register contains the in-terrupt masks and four flags representative of theresult of the instruction just executed. This registercan also be handled by the PUSH and POP in-structions.

These bits can be individually tested and/or con-trolled by specific instructions.

Arithmetic Management Bits

Bit 4 = H Half carry.This bit is set by hardware when a carry occurs be-tween bits 3 and 4 of the ALU during an ADD orADC instructions. It is reset by hardware duringthe same instructions.

0: No half carry has occurred.1: A half carry has occurred.

This bit is tested using the JRH or JRNH instruc-tion. The H bit is useful in BCD arithmetic subrou-tines.

Bit 2 = N Negative.This bit is set and cleared by hardware. It is repre-sentative of the result sign of the last arithmetic,logical or data manipulation. It’s a copy of the re-sult 7th bit.0: The result of the last operation is positive or null.1: The result of the last operation is negative

(that is, the most significant bit is a logic 1).

This bit is accessed by the JRMI and JRPL instruc-tions.

Bit 1 = Z Zero.

This bit is set and cleared by hardware. This bit in-dicates that the result of the last arithmetic, logicalor data manipulation is zero.0: The result of the last operation is different from

zero.1: The result of the last operation is zero.

This bit is accessed by the JREQ and JRNE testinstructions.

Bit 0 = C Carry/borrow.This bit is set and cleared by hardware and soft-ware. It indicates an overflow or an underflow hasoccurred during the last arithmetic operation.0: No overflow or underflow has occurred.1: An overflow or underflow has occurred.

This bit is driven by the SCF and RCF instructionsand tested by the JRC and JRNC instructions. It isalso affected by the “bit test and branch”, shift androtate instructions.

Interrupt Management Bits

Bit 5,3 = I1, I0 Interrupt

The combination of the I1 and I0 bits gives the cur-rent interrupt software priority.

These two bits are set/cleared by hardware whenentering in interrupt. The loaded value is given bythe corresponding bits in the interrupt software pri-ority registers (IxSPR). They can be also set/cleared by software with the RIM, SIM, IRET,HALT, WFI and PUSH/POP instructions.

See the interrupt management chapter for moredetails.

7 0

1 1 I1 H I0 N Z C

Interrupt Software Priority I1 I0Level 0 (main) 1 0Level 1 0 1Level 2 0 0Level 3 (= interrupt disable) 1 1

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CENTRAL PROCESSING UNIT (Cont’d)

Stack Pointer (SP)Read/Write

Reset Value: 01 FFh

The Stack Pointer is a 16-bit register which is al-ways pointing to the next free location in the stack.It is then decremented after data has been pushedonto the stack and incremented before data ispopped from the stack (see Figure 12).

Since the stack is 256 bytes deep, the 8 most sig-nificant bits are forced by hardware. Following anMCU Reset, or after a Reset Stack Pointer instruc-tion (RSP), the Stack Pointer contains its reset val-ue (the SP7 to SP0 bits are set) which is the stackhigher address.

The least significant byte of the Stack Pointer(called S) can be directly accessed by a LD in-struction.

Note: When the lower limit is exceeded, the StackPointer wraps around to the stack upper limit, with-out indicating the stack overflow. The previouslystored information is then overwritten and there-fore lost. The stack also wraps in case of an under-flow.

The stack is used to save the return address dur-ing a subroutine call and the CPU context duringan interrupt. The user may also directly manipulatethe stack by means of the PUSH and POP instruc-tions. In the case of an interrupt, the PCL is storedat the first location pointed to by the SP. Then theother registers are stored in the next locations asshown in Figure 12.

– When an interrupt is received, the SP is decre-mented and the context is pushed on the stack.

– On return from interrupt, the SP is incremented and the context is popped from the stack.

A subroutine call occupies two locations and an in-terrupt five locations in the stack area.

Figure 12. Stack Manipulation Example

15 8

0 0 0 0 0 0 0 1

7 0

SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0

PCH

PCL

SP

PCH

PCL

SP

PCL

PCH

X

ACC

PCH

PCL

SP

PCL

PCH

X

ACC

PCH

PCL

SP

PCL

PCH

X

ACC

PCH

PCL

SP

SP

Y

CALLSubroutine

Interrupt Event

PUSH Y POP Y IRET RETor RSP

@ 01FFh

@ 0100h

Stack Higher Address = 01FFhStack Lower Address = 0100h

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6 SUPPLY, RESET AND CLOCK MANAGEMENTThe device includes a range of utility features forsecuring the application in critical situations (forexample in case of a power brown-out), and re-ducing the number of external components. Anoverview is shown in Figure 13.

For more details, refer to dedicated parametricsection.

Main features■ Reset Sequence Manager (RSM)■ 1 Crystal/Ceramic resonator oscillator■ System Integrity Management (SI)

– Main supply Low voltage detection (LVD)– Auxiliary Voltage detector (AVD) with interrupt

capability for monitoring the main supply– Clock Security System (CSS) with the VCO of

the PLL, providing a backup safe oscillator– Clock Detector– PLL which can be used to multiply the fre-

quency by 2 if the clock frequency input is8MHz

Figure 13. Clock, Reset and Supply Block Diagram

LOW VOLTAGE

DETECTOR

(LVD)

AUXILIARY VOLTAGE

DETECTOR

(AVD)

OSCILLATOROSC1

RESET

VSS

VDD

RESET SEQUENCE

MANAGER

(RSM)

CLOCK SECURITY SYSTEM

OSC2

MAIN CLOCK

CSS Interrupt Request

AVD Interrupt Request

CONTROLLER

SYSTEM

WATCHDOG

SICSR, page 0 TIMER (WDG)

WITH REALTIME CLOCK (MCC/RTC)

AVD AVD LVDRF

CSSIEIE

CSSD

WDGRF

fOSC

0F

fCPU

PA

fMTC

1/2 Safeosc

8Mhz PLL

Clock Detector

VCO CK0EN

PA LOCK

PLLEN

SICSR, page 1

16Mhz

fOSC

CKSELDIV2 OPT

lock

GE0 0

GE

INTEGRITY MANAGEMENT

SEL

fCLK

* It is recommended to decouple the power supply by placing a 0.1µF capacitor as close as possible to VDD

*

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6.1 OSCILLATOR

The main clock of the ST7 can be generated by acrystal or ceramic resonator oscillator or an exter-nal source.

The associated hardware configurations areshown in Table 4. Refer to the electrical character-istics section for more details.

External Clock SourceIn this external clock mode, a clock signal (square,sinus or triangle) with ~50% duty cycle has to drivethe OSC1 pin while the OSC2 pin is not connect-ed.

Crystal/Ceramic OscillatorsThis family of oscillators has the advantage of pro-ducing a very accurate rate on the main clock ofthe ST7. In this mode, the resonator and the loadcapacitors have to be placed as close as possibleto the oscillator pins in order to minimize outputdistortion and start-up stabilization time.

This oscillator is not stopped during the RESETphase to avoid losing time in its start-up phase.

See Electrical Characteristics for more details.

Note: When crystal oscillator is used as a clocksource, a risk of failure may exist if no series resis-tors are implemented.

Table 4. ST7 Clock Sources

Hardware Configuration

Ext

erna

lClo

ckC

ryst

al/C

eram

icR

eson

ator

s

OSC1 OSC2

EXTERNAL

ST7

SOURCE

NC

OSC1 OSC2

LOADCAPACITORS

ST7

CL2CL1

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6.2 RESET SEQUENCE MANAGER (RSM)

6.2.1 IntroductionThe reset sequence manager includes three RE-SET sources as shown in Figure 15:■ External RESET source pulse■ Internal LVD RESET (Low Voltage Detection)■ Internal WATCHDOG RESET

Note: A reset can also be triggered following thedetection of an illegal opcode or prebyte code. Re-fer to section 11.2.1 on page 244 for further de-tails.

These sources act on the RESET pin and it is al-ways kept low during the delay phase.

The RESET service routine vector is fixed at ad-dresses FFFEh-FFFFh in the ST7 memory map.

The basic RESET sequence consists of 3 phasesas shown in Figure 14:■ Active Phase depending on the RESET source■ 256 or 4096 CPU clock cycle delay (selected by

option byte)■ RESET vector fetch

Caution: When the ST7 is unprogrammed or fullyerased, the Flash is blank and the RESET vectoris not programmed. For this reason, it is recom-mended to keep the RESET pin in low state untilprogramming mode is entered, in order to avoidunwanted behavior.

The 256 or 4096 CPU clock cycle delay allows theoscillator to stabilise and ensures that recoveryhas taken place from the Reset state. The shorteror longer clock cycle delay should be selected byoption byte to correspond to the stabilization timeof the external oscillator used in the application.

The RESET vector fetch phase duration is 2 clockcycles.

Figure 14. RESET Sequence Phases

6.2.2 Asynchronous External RESET pinThe RESET pin is both an input and an open-drainoutput with integrated RON weak pull-up resistor.This pull-up has no fixed value but varies in ac-cordance with the input voltage. It can be pulledlow by external circuitry to reset the device. SeeElectrical Characteristic section for more details.

A RESET signal originating from an externalsource must have a duration of at least th(RSTL)in inorder to be recognized (see Figure 16). This de-tection is asynchronous and therefore the MCUcan enter reset state even in Halt mode.

Figure 15. Reset Block Diagram

RESET

Active PhaseINTERNAL RESET

256 or 4096 CLOCK CYCLESFETCH

VECTOR

RESET

RON

VDD

WATCHDOG RESET

LVD RESET

INTERNALRESET

PULSEGENERATOR

Filter

ILLEGAL OPCODE RESET 1)

Note 1: See “Illegal Opcode Reset” on page 244. for more details on illegal opcode reset conditions.

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RESET SEQUENCE MANAGER (Cont’d)

The RESET pin is an asynchronous signal whichplays a major role in EMS performance. In a noisyenvironment, it is recommended to follow theguidelines mentioned in the electrical characteris-tics section.

6.2.3 External Power-On RESETIf the LVD is disabled by option byte, to start up themicrocontroller correctly, the user must ensure bymeans of an external reset circuit that the resetsignal is held low until VDD is over the minimumlevel specified for the selected fOSC frequency.

A proper reset signal for a slow rising VDD supplycan generally be provided by an external RC net-work connected to the RESET pin.

6.2.4 Internal Low Voltage Detector (LVD)RESETTwo different RESET sequences caused by the in-ternal LVD circuitry can be distinguished:■ Power-On RESET■ Voltage Drop RESET

The device RESET pin acts as an output that ispulled low when VDD

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6.3 SYSTEM INTEGRITY MANAGEMENT (SI)

The System Integrity Management block containsthe Low Voltage Detector (LVD), Auxiliary VoltageDetector (AVD) and Clock Security System (CSS)functions. It is managed by the SICSR register.

Note: A reset can also be triggered following thedetection of an illegal opcode or prebyte code. Re-fer to section 11.2.1 on page 244 for further de-tails.

6.3.1 Low Voltage Detector (LVD)The Low Voltage Detector function (LVD) gener-ates a static reset when the VDD supply voltage isbelow a VIT- reference value. This means that itsecures the power-up as well as the power-downkeeping the ST7 in reset.

The VIT- reference value for a voltage drop is lowerthan the VIT+ reference value for power-on in orderto avoid a parasitic reset when the MCU starts run-ning and sinks current on the supply (hysteresis).

The LVD Reset circuitry generates a reset whenVDD is below:

– VIT+ when VDD is rising – VIT- when VDD is falling

The LVD function is illustrated in Figure 17.

Provided the minimum VDD value (guaranteed forthe oscillator frequency) is above VIT-, the MCUcan only be in two modes:

– under full software control– in static safe reset

In these conditions, secure operation is always en-sured for the application without the need for ex-ternal reset hardware.

During a Low Voltage Detector Reset, the RESETpin is held low, thus permitting the MCU to resetother devices.

Notes:The LVD allows the device to be used without anyexternal RESET circuitry.

The LVD is an optional function which can be se-lected by option byte.

It is recommended to make sure that the VDD sup-ply voltage rises monotonously when the device isexiting from Reset, to ensure the application func-tions properly.

Figure 17. Low Voltage Detector vs Reset

VDD

VIT+

RESET

VIT-

Vhys

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SYSTEM INTEGRITY MANAGEMENT (Cont’d)

6.3.2 Auxiliary Voltage Detector (AVD)The Voltage Detector function (AVD) is based onan analog comparison between a VIT-(AVD) andVIT+(AVD) reference value and the VDD main sup-ply. The VIT- reference value for falling voltage islower than the VIT+ reference value for rising volt-age in order to avoid parasitic detection (hystere-sis).

The output of the AVD comparator is directly read-able by the application software through a real-time status bit (AVDF) in the SICSR register. Thisbit is read only.Caution: The AVD function is active only if theLVD is enabled through the option byte (see sec-tion 14.1 on page 290).6.3.2.1 Monitoring the VDD Main SupplyIf the AVD interrupt is enabled, an interrupt is gen-erated when the voltage crosses the VIT+(AVD) orVIT-(AVD) threshold (AVDF bit toggles).

In the case of a drop in voltage, the AVD interruptacts as an early warning, allowing software to shutdown safely before the LVD resets the microcon-troller. See Figure 18.

The interrupt on the rising edge is used to informthe application that the VDD warning state is over.

If the voltage rise time trv is less than 256 or 4096CPU cycles (depending on the reset delay select-ed by option byte), no AVD interrupt will be gener-ated when VIT+(AVD) is reached.

If trv is greater than 256 or 4096 cycles then:

– If the AVD interrupt is enabled before the VIT+(AVD) threshold is reached, then 2 AVD inter-rupts will be received: the first when the AVDIE bit is set, and the second when the threshold is reached.

– If the AVD interrupt is enabled after the VIT+(AVD) threshold is reached then only one AVD interrupt will occur.

Figure 18. Using the AVD to Monitor VDD

VDD

VIT+(AVD)

VIT-(AVD)

AVDF bit 0 01

IF AVDIE bit = 1

Vhyst

AVD INTERRUPTREQUEST

INTERRUPT PROCESS INTERRUPT PROCESS

VIT+(LVD)

VIT-(LVD)

LVD RESET

Early Warning Interrupt(Power has dropped, MCU not not yet in reset)

trv VOLTAGE RISE TIME

1

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6.3.3 Clock Security System (CSS)The Clock Security System (CSS) protects theST7 against main clock problems. To allow the in-tegration of the security features in the applica-tions, it is based on a PLL which can provide abackup clock. The PLL can be enabled or disabledby option byte or by software. It requires an 8-MHzinput clock and provides a 16-MHz output clock.

6.3.3.1 Safe Oscillator ControlThe safe oscillator of the CSS block is made of aPLL.

If the clock signal disappears (due to a broken ordisconnected resonator...) the PLL continues toprovide a lower frequency, which allows the ST7 toperform some rescue operations.

Note: The clock signal must be present at start-up.Otherwise, the ST7MC will not start and will bemaintained in RESET conditions.

6.3.3.2 Limitation detectionThe automatic safe oscillator selection is notifiedby hardware setting the CSSD bit of the SICSRregister. An interrupt can be generated if the CS-SIE bit has been previously set.These two bits are described in the SICSR registerdescription.

6.3.4 Low Power Modes

6.3.4.1 InterruptsThe CSS or AVD interrupt events generate an in-terrupt if the corresponding Enable Control Bit(CSSIE or AVDIE) is set and the interrupt mask inthe CC register is reset (RIM instruction).

Note 1: This interrupt allows to exit from Active-halt mode.

Mode Description

WaitNo effect on SI. CSS and AVD interrupts cause the device to exit from Wait mode.

Halt

The CRSR register is frozen.The CSS (including the safe oscillator) is disabled until Halt mode is exited. The pre-vious CSS configuration resumes when the MCU is woken up by an interrupt with “exit from Halt mode” capability or from the coun-ter reset value when the MCU is woken up by a RESET. The AVD remains active, and an AVD interrupt can be used to exit from Halt mode.

Interrupt EventEventFlag

Enable Control

Bit

Exit fromWait

Exit from Halt

CSS event detection (safe oscillator acti-vated as main clock)

CSSD CSSIE Yes No 1)

AVD event AVDF AVDIE Yes Yes

1

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6.3.5 Register DescriptionSYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR, page 0)Read/Write

Reset Value: 000x 000x (00h)

Bit 7 = PAGE SICSR Register Page SelectionThis bit selects the SICSR register page. It is setand cleared by software0: Access to SICSR register mapped in page 0.1: Access to SICSR register mapped in page 1.

Bit 6 = AVDIE Voltage Detector interrupt enableThis bit is set and cleared by software. It enablesan interrupt to be generated when the AVDF flagchanges (toggles). The pending interrupt informa-tion is automatically cleared when software entersthe AVD interrupt routine.0: AVD interrupt disabled1: AVD interrupt enabled

Bit 5 = AVDF Voltage Detector flagThis read-only bit is set and cleared by hardware.If the VDIE bit is set, an interrupt request is gener-ated when the AVDF bit changes value.0: VDD over VIT+ (AVD) threshold1: VDD under VIT-(AVD) threshold

Bit 4 = LVDRF LVD reset flagThis bit indicates that the last Reset was generat-ed by the LVD block. It is set by hardware (LVD re-set) and cleared by software (writing zero). SeeWDGRF flag description for more details. Whenthe LVD is disabled by OPTION BYTE, the LVDRFbit value is undefined.

Bit 3 = Reserved, must be kept cleared.

Bit 2 = CSSIE Clock security syst. interrupt enableThis bit enables the interrupt when a disturbance

is detected by the Clock Security System (CSSDbit set). It is set and cleared by software.0: Clock security system interrupt disabled1: Clock security system interrupt enabledWhen the PLL is disabled (PLLEN=0), the CSSIEbit has no effect.

Bit 1 = CSSD Clock security system detectionThis bit indicates a disturbance on the main clocksignal (fOSC): the clock stops (at least for a few cy-cles). It is set by hardware and cleared by readingthe SICSR register when the original oscillator re-covers.0: Safe oscillator is not active1: Safe oscillator has been activatedWhen the PLL is disabled (PLLEN=0), the CSSDbit value is forced to 0.

Bit 0 = WDGRF Watchdog reset flagThis bit indicates that the last Reset was generat-ed by the Watchdog peripheral. It is set by hard-ware (watchdog reset) and cleared by software(writing zero) or an LVD Reset (to ensure a stablecleared state of the WDGRF flag when CPUstarts).Combined with the LVDRF flag information, theflag description is given by the following table.

Application notesThe LVDRF flag is not cleared when another RE-SET type occurs (external or watchdog), theLVDRF flag remains set to keep trace of the origi-nal failure.In this case, a watchdog reset can be detected bysoftware while an external reset can not.

7 0

PAGE

AVD

IEAVD

FLVDRF

0CSS

IECSS

DWDG

RF

RESET Sources LVDRF WDGRF

External RESET pin 0 0Watchdog 0 1

LVD 1 X

1

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SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR, page 1)Reset Value: 00000000 (00h)

Bit 7 = PAGE SICSR Register Page SelectionThis bit selects the SICSR register page. It is setand cleared by software0: Access to SICSR register mapped in page 0.1: Access to SICSR register mapped in page 1.


Bit 5 = VCOEN VCO EnableThis bit is set and cleared by software.0: VCO (Voltage Controlled Oscillator) connected

to the output of the PLL charge pump (default mode), to obtain a 16-MHz output frequency (with an 8-MHz input frequency).

1: VCO tied to ground in order to obtain a 10-MHz frequency (fvco)

Notes: 1. During ICC session, this bit is set to 1 in order tohave an internal frequency which does not dependon the input clock. Then, it can be reset in order torun faster with an external oscillator.

Bit 4 = LOCK PLL LockedThis bit is read only. It is set by hardware. It is setautomatically when the PLL reaches its operatingfrequency.0: PLL not locked1: PLL locked

Bit 3 = PLLEN PLL EnableThis bit enables the PLL and the clock detector. Itis set and cleared by software.0: PLL and Clock Detector (CKD) disabled1: PLL and Clock Detector (CKD) enabled

Notes: 1. During ICC session, this bit is set to 1.2. PLL cannot be disabled if PLL clock source isselected (CKSEL= 1).


Bit 1 = CKSEL Clock Source SelectionThis bit selects the clock source: oscillator clock orclock from the PLL. It is set and cleared by soft-ware. It can also be set by option byte (PLL opt)0: Oscillator clock selected1: PLL clock selected

Notes:1. During ICC session, this bit is set to 1. Then,CKSEL can be reset in order to run with fOSC.2. Clock from the PLL cannot be selected if thePLL is disabled (PLLEN =0)3. If the clock source is selected by PLL option bit,CKSEL bit selection has no effect.


7 0

PAGE

0VCO

EN

LO

CK

PLL

EN0

CK-SEL

0

1

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6.4 MAIN CLOCK CONTROLLER WITH REAL-TIME CLOCK AND BEEPER (MCC/RTC)

The Main Clock Controller consists of three differ-ent functions:■ a programmable CPU clock prescaler■ a clock-out signal to supply external devices■ a real-time clock timer with interrupt capability

Each function can be used independently and si-multaneously.6.4.1 Programmable CPU Clock PrescalerThe programmable CPU clock prescaler suppliesthe clock for the ST7 CPU and its internal periph-erals. It manages Slow power saving mode (SeeSection 8.2 SLOW MODE for more details).

The prescaler selects the fCPU main clock frequen-cy and is controlled by three bits in the MCCSRregister: CP[1:0] and SMS.6.4.2 Clock-out CapabilityThe clock-out capability is an alternate function ofan I/O port pin that outputs a fOSC2 clock to drive

external devices. It is controlled by the MCO bit inthe MCCSR register.CAUTION: When selected, the clock out pin sus-pends the clock during Active-halt mode.6.4.3 Real-time Clock Timer (RTC)The counter of the real-time clock timer allows aninterrupt to be generated based on an accuratereal-time clock. Four different time bases depend-ing directly on fOSC2 are available. The wholefunctionality is controlled by four bits of the MCC-SR register: TB[1:0], OIE and OIF.

When the RTC interrupt is enabled (OIE bit set),the ST7 enters Active-halt mode when the HALTinstruction is executed. See Section 8.4 ACTIVE-HALT AND HALT MODES for more details.6.4.4 BeeperThe beep function is controlled by the MCCBCRregister. It can output three selectable frequencieson the BEEP pin (I/O port alternate function).

Figure 19. Main Clock Controller (MCC/RTC) Block Diagram

DIV 2, 4, 8, 16

MCC/RTC INTERRUPTSMS

DIV128

CP0 TB1 TB0 OIE OIF

CPU CLOCK

MCCSR

RTCCOUNTER

TO CPU ANDPERIPHERALS

fOSC2

fCPU

MCO

MCO

BC1 BC0

MCCBCR

BEEP

GENERATORBEEP SIGNAL

TO MOTORCONTROL

PERIPHERALfMTC

(AND TO MTCPERIPHERAL)

DIV 2, 4, 8, 16

DIV 2

fCLK

DIV 2 fADC

1

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MAIN CLOCK CONTROLLER WITH REAL-TIME CLOCK (Cont’d)

6.4.5 Low Power Modes

6.4.6 InterruptsThe MCC/RTC interrupt event generates an inter-rupt if the OIE bit of the MCCSR register is set andthe interrupt mask in the CC register is not active(RIM instruction).

Note:The MCC/RTC interrupt wakes up the MCU fromActive-halt mode, not from Halt mode.

6.4.7 Register DescriptionMCC CONTROL/STATUS REGISTER (MCCSR)Read/Write

Reset Value: 0000 0000 (00h)

Bit 7 = MCO Main clock out selectionThis bit enables the MCO alternate function on thePF0 I/O port. It is set and cleared by software.0: MCO alternate function disabled (I/O pin free for

general-purpose I/O)1: MCO alternate function enabled (fOSC2on I/O

port)

Note: To reduce power consumption, the MCOfunction is not active in Active-halt mode.

Bit 6:5 = CP[1:0] CPU clock prescalerThese bits select the CPU clock prescaler which isapplied in the different slow modes. Their action isconditioned by the setting of the SMS bit. Thesetwo bits are set and cleared by software

Bit 4 = SMS Slow mode selectThis bit is set and cleared by software.0: Normal mode. fCPU = fOSC21: Slow mode. fCPU is given by CP1, CP0See Section 8.2 SLOW MODE and Section 6.4MAIN CLOCK CONTROLLER WITH REAL-TIMECLOCK AND BEEPER (MCC/RTC) for more de-tails.

Bit 3:2 = TB[1:0] Time base controlThese bits select the programmable divider timebase. They are set and cleared by software.

A modification of the time base is taken into ac-count at the end of the current period (previouslyset) to avoid an unwanted time shift. This allows touse this time base as a real-time clock.

Bit 1 = OIE Oscillator interrupt enableThis bit set and cleared by software.0: Oscillator interrupt disabled1: Oscillator interrupt enabledThis interrupt can be used to exit from Active-haltmode.When this bit is set, calling the ST7 software HALTinstruction enters the Active-halt power savingmode.

Mode Description

WaitNo effect on MCC/RTC peripheral.MCC/RTC interrupt cause the device to exit from Wait mode.

Active-halt

No effect on MCC/RTC counter (OIE bit is set), the registers are frozen.MCC/RTC interrupt cause the device to exit from Active-halt mode.

Halt

MCC/RTC counter and registers are frozen.MCC/RTC operation resumes when the MCU is woken up by an interrupt with “exit from Halt” capability.

Interrupt EventEventFlag

Enable Control

Bit

Exit fromWait

Exit from Halt

Time base overflow event

OIF OIE Yes No 1)

7 0

MCO CP1 CP0 SMS TB1 TB0 OIE OIF

fCPU in Slow mode CP1 CP0

fOSC2 / 2 0 0

fOSC2 / 4 0 1

fOSC2 / 8 1 0

fOSC2 / 16 1 1

Counter Prescaler

Time BaseTB1 TB0

fOSC2 =4MHz fOSC2=8MHz

16000 4ms 2ms 0 0

32000 8ms 4ms 0 1

80000 20ms 10ms 1 0

200000 50ms 25ms 1 1

1

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MAIN CLOCK CONTROLLER WITH REAL-TIME CLOCK (Cont’d)

Bit 0 = OIF Oscillator interrupt flagThis bit is set by hardware and cleared by softwarereading the CSR register. It indicates when setthat the main oscillator has reached the selectedelapsed time (TB1:0). 0: Timeout not reached1: Timeout reached

CAUTION: The BRES and BSET instructionsmust not be used on the MCCSR register to avoidunintentionally clearing the OIF bit.

MCC BEEP CONTROL REGISTER (MCCBCR)Read/Write

Reset Value: 0000 0000 (00h)

Bit 7:4 = Reserved, must be kept cleared.

Bit 3 = ADSTS A/D Converter Sample TimeStretchThis bit is set and cleared by software to enable ordisable the A/D Converter sample time stretch fea-ture.0: AD sample time stretch disabled (for

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