7th sem syllabus

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7XT1 DATA COMMUNICATION NETWORK SECTION-A Unit 1: - Introduction to Communication Network Network Functions; Network Topology; Types of network: LAN, MAN, WAN, Basics of Circuit switching, packet switching, message switching and cell switching, Layered Architecture: Need for Protocol; Protocol & Protocol architecture model; OSI Reference model; Overview of TCP/IP architecture (6) Unit 2: - Peer to Peer Protocols and Data Link control, Point to Point Protocol and service models; End to End requirements and Adaptation Function; End to End versus Hop by Hop Flow Control: Need for flow control; Stop and Wait Flow Control; Sliding Window Flow Control; Stop and wait ARQ; Go-Back-N ARQ; Selective Repeat ARQ; Transmission efficiency of ARQ protocols; HDLC Protocol (8) Unit 3: - Local Area Networks and Access Control Protocols, LAN Architecture; Medium Access Control (MAC) and Logical Link Control (LLC) for LAN; Contention Techniques: CSMA, CSMA/CD (IEEE 802.3) Control Access Techniques: Token Bus (IEEE 802.4); Token Ring (IEEE 802.5); Polling; FDDI, Random Access Techniques: ALOHA; Slotted ALOHA; (10) SECTION-B

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hey here is the syllabus for 7th sem engineering SGBAU ....

Transcript of 7th sem syllabus

Page 1: 7th sem syllabus

7XT1 DATA COMMUNICATION NETWORK

SECTION-A

Unit 1: - Introduction to Communication Network

Network Functions; Network Topology; Types of network: LAN, MAN, WAN, Basics of Circuit switching, packet switching, message switching and cell switching, Layered Architecture: Need for Protocol; Protocol & Protocol architecture model; OSI Reference model; Overview of TCP/IP architecture

(6)

Unit 2: - Peer to Peer Protocols and Data Link control, Point to Point Protocol and service models; End to End requirements and Adaptation Function; End to End versus Hop by Hop

Flow Control: Need for flow control; Stop and Wait Flow Control; Sliding Window Flow Control; Stop and wait ARQ; Go-Back-N ARQ; Selective Repeat ARQ; Transmission efficiency of ARQ protocols; HDLC Protocol (8)

Unit 3: - Local Area Networks and Access Control Protocols, LAN Architecture; Medium Access Control (MAC) and Logical Link Control (LLC) for LAN; Contention Techniques: CSMA, CSMA/CD (IEEE 802.3)

Control Access Techniques: Token Bus (IEEE 802.4); Token Ring (IEEE 802.5); Polling; FDDI, Random Access Techniques: ALOHA; Slotted ALOHA;

(10)

SECTION-B

Unit 4: - Networking Devices, Routing Techniques and Traffic Control Protocols:

Hubs; Switches; Bridges; Routers; Gateways; Routing Switches

Routing Algorithms: Alternate routing in circuit switched network; Fixed Routing, Flooding, and Random Routing in Packet Switched networks

Least Cost Algorithms: Dijkstra’s Algorithm (Problems expected); Bellman Ford Algorithm (Problems expected) Traffic Control: Leaky Bucket algorithm; Token Bucket Algorithm

(8)

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Unit 5: - Asynchronous Transfer Mode (ATM), Frame Relay and ISDN

ATM: - ATM Protocol Architecture; Concept of Virtual channel and Virtual path; ATM Cell; ATM Services

Frame Relay: - Protocol architecture

ISDN: -Principles of ISDN; ISDN Architecture; ISDN Channels; Broadband ISDN Functional Architecture

(7)

Unit 6: - TCP/IP Protocol

Overview of TCP/IP; IP Services; Internet Protocol (IPv4); Classfull and Classless IP Addressing; Internet Control Message Protocol (ICMP); IP Address Resolution protocol; Reverse Address Resolution Protocol; IPv4 versus IPv6; IP Datagram; Datagram Forwarding; TCP (Frame Format); UDP (Frame Format) (7)

TEXT BOOKS :1. W. Stallings : “Data and Computer Communications”, (Maxwell Macmillan)2. Behrouz A Forouzan : “Data Communication and Networking” , (TMH)

REFERENCE BOOKS :1. D Bertsekas and R.G. Gallager: “Data Networks”, (2 e) , Pearson Ed., (PHI)2. A. S. Tanenbaum : “Computer Networks”, PHI3. Uyless Black : “Computer Networks”, (PHI)4. Douglas E. Comer : “Computer Networks and Internets”, ( Pearson Education)5. Gerd Kaiser, “ Local area network”, (TMH) 2nd Edition 6. Leon Garcia, “ Communication Network.

*************7XT2 MICROCONTROLLER & APPLICATIONS

SECTION-A

UNIT-I : An Introduction to uC 8051:Architecture of 8051, Signal description of 8051, Register set of 8051, Timer structure and their mode and I/O port structure. Bus standards : Serial RS 232, Parallel IEE-488

8 Lectures

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UNIT-II: Instruction set of 8051, Addressing modes of 8051, Memory and I/O addressing by 8051, Assembly Language Programming using 8051.

8 LecturesUNIT-III: Study of ADC 0809, DAC 0808 and its interfacing with 8051,

Interfacing of Sensors, Measurement of Temperature, Speed and Resistance.

8 LecturesSECTION-B

UNIT-IV: Interfacing LCD & Keyboard with 8051., Relays and Optoisolators, Stepper Motor interfacing, DC motor interfacing and PWM with 8051.

UNIT-V: Serial port programming in assembly: Basics of serial communication, 8051 connection to RS232C, 8051 Serial port programming in assembly. RTC interfacing and Programming : DS 12887 RTC interfacing, Programming, Alarm, SQW, and IRQ features of DS 12887 Chip.

(10 )UNIT-VI : 8051 programming in C : Data types and time delay in 8051 C, IO

programming in 8051 C, Logic operations in 8051 C, Data conversion programs in 8051 C, Accessing code ROM space in 8051 C, Data serialization using 8051 C.

 TEXT BOOKS :1. M. A. Mazidi, J. G. Mazidi and R. D. McKinley : “The 8051

Microcontroller and Embedded Systems using Assembly and C”, Pearson Education (2nd Ed.)

2. K. J. Ayala : “The 8051 Microcontroller”, Penram Int. Pubs., 1996 REFERENCE BOOKS :

1. Using the MCS-51 Microcontroller by Han- Way Huang, Oxford University Press

2. National Semiconductor : Data Acquisition Linear Devices Data Book.3. Embedded Microcontrollers and Processors:-Volume-I-Intel4. Intel Peripheral Devices Data Book.

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7XT3 DIGITAL SIGNAL PROCESSINGSECTION-A

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UNIT-I : Introduction to DSP, Frequency domain description of signals & systems, Discrete time sequences systems: Linearity, causal, Time invariant system, Stability criteria, Convolution unit sample response. (10)

UNIT-II: Z- transform: complex Z-plane, ROC determination of filter coefficients and its properties, Solution of difference equations using Z-transform, inverse Z-transform.

(12)

UNIT-III: Introduction to Fourier transform of discrete time signal and its properties. Inverse Fourier transforms DFT and its properties, Circular convolution, linear convolution from DFT, FFT: Decimation in time and frequency radix 2 algorithm.

(10)

SECTION-B

UNIT-IV: Filter Structures: Direct form I, Direct form II, Cascade and parallel structure for IIR and FIR Filter, Frequency sampling structures for F.I.R. filter. FIR filter design: Design by Pole Zero Placements and Windowing method: Rectangular, Triangular, Blackman window and Kaiser window. (8)

UNIT-V: Methods to convert analog filter into IIR digital: Mapping of differential equation, Impulse invariant, bilinear transformation, and Matched Z transformation. Design of Analog filter: Specification and formulae to decide to filter order cut of frequency and transfer function of Butterworth filter and Chebyshev filter.

(8)

UNIT-VI: Multi rate DSP, Introductory concept of multi rate signal processing, Design of Practical sampler, Rate converters, Decimators and Interpolator, Filter Bank application and examples. Overview and architecture of DSP processor TMS320C54XX. (8 )

TEXT BOOKS :1. Oppenheim & Schafer: Discrete time Processing (PHI)2. Proakis & Manolakis D.G. : Digital Signal Processing (PHI)

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3. Mitra S.K. : Digital Signal Processing (TMH)

REFERENCE BOOKS :1. Roman Kuc : Digital Signal Processing (MGH)2. Ifeacher E.C., Jervis B. W. : Digital Signal Processing (Addison Wesley)3. P. P. Vaidyanathan : DSP and Multirate Systems (PHI)4. Rabiner and Chrocherie : Multirate DSP (PHI)5. Avtar Singh, S Shrinivasan : DSP implementation using DSP microprocessor with example From TMS320C54XX. Brooks cole publisher 2003.

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Professional Elective -I

7XT4 (1) VLSI DESIGN

SECTION-A

Unit I : Digital Design Fundamentals: Review of techniques of using a truth table, canonical forms to develop the AND/OR or OR/AND combinational circuit models, minimization techniques, Hazards and Hazard free circuits. Difference between combinational and sequential circuits. General modelof sequential machine, timing and triggering considerations.

Unit II : Basic HDL Constructs: VLSI Design flow, Overview of different modeling styles in VHDL, Data types and data objects in VHDL, Dataflow Modeling, Behavioral Modeling, using VHDL for combinational Circuits and sequentialCircuits.

Unit III : Hardware Description Language: Structural Modeling, Subprograms, Packages and Libraries, Generics, Configurations, attributes. Comparison of various Hardware Description Languages.

SECTION-BUnit IV : Programmable Logic Devices: Introduction to CPLDs: Function block architecture, input/output block, switch matrix, Study of architecture of CPLDs of Altera /Xilinx. Introduction to FPGAs: Configurable logic block,

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input/output block and interconnect, Study of architecture of FPGAs of Xilinx /Altera.

Unit V: CMOS Circuits: Different logic families, MOS Transistor, CMOS as an inverter, propagation delay, power consumption/ dissipation issues, simple circuits using CMOS.

Unit VI: CMOS Processing & Digital Circuit Verification: CMOS Fabrication: Different steps of fabrication, CMOS p-well, n-Well and twin tub processes, CMOS Layout and Design rules. Simple Test Bench, Simulation and Synthesis issues, case study of ALU/ Sequence Detector.

Text Books:1) Neil H.Weste and Kamran Eshraghian, “Principles of CMOS VLSI

design”. Pearson2) J Bhasker,” VHDL Primer”. Addison Wesley3) Douglas Perry,” VHDL” Tata McGraw HILL4) William I. Fletcher “An Engineering approach to Digital Design”,

Prentice Hall India.Reference Books:1) Stephen Brown and Zvonko Vranesic, “Fundamentals of Digital Logic

with VHDL Design”. Tata McGRAW HILL2) Wayne Wolf: “VLSI Technology”3) VLSI Test Principles and Architectures by Laung Terng Wang, Elsevier

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