Slaviša Aleksić VOL. 1, NO. 3 /AUGUST 2009/J. OPT. COMMUN. NETW. 245

Analysis of Power Consumption inFuture High-Capacity Network Nodes

Slaviša Aleksic

sw

cc

Riwteohnskv

ptctssSydatuhct

leaHtcc

Abstract—Power consumption and the footprint offuture network elements are expected to become themain limiting factors for scaling the current architec-tures and approaches to capacities of hundreds of ter-abits or even petabits per second. Since the underly-ing demand for network capacity can be satisfiedonly by contemporaneously increasing transmissionbit rate, processing speed, and switching capacity, itunavoidably will lead to increased power consump-tion of network nodes. On the one hand, using opticalswitching fabrics could relax the limitations to someextent, but large optical buffers occupy larger areasand dissipate more power than electronic ones. Onthe other hand, electronic technology has made fastprogress during the past decade regarding reducedfeature size and decreased power consumption. It isexpected that this trend will continue in the future.This paper addresses power consumption issues infuture high-capacity switching and routing elementsand examines different architectures based on bothpure packet-switched and pure circuit-switched de-signs by assuming either all-electronic or all-opticalimplementation, which can be seen as upper andlower bounds regarding power consumption. The to-tal power consumption of a realistic and appropriatetechnology for future high-performance core networknodes would probably lie somewhere between thosetwo extreme cases. Our results show that implemen-tation in optics is generally more power efficient; es-pecially circuit-switched architectures have a lowpower consumption. When taking into account pos-sible future developments of Si CMOS technology,even very large electronic packet routers having ca-pacities of more than hundreds of terabits per secondseem to be feasible. Because circuit switching is morepower efficient and easier to implement in opticsthan pure packet switching, the scalability limitationdue to increased power consumption could be consid-erably relaxed when a kind of dynamic optical circuit

Manuscript received November 3, 2008; revised March 24, 2009;accepted June 12, 2009; published July 31, 2009 �Doc. ID 103537�.

S. Aleksic (e-mail: slavisa.aleksic@tuwien.ac.at) is with theInstitute of Broadband Communications, Vienna University ofTechnology, Favoritenstrasse 9-11/388, 1040 Vienna, Austria.

Digital Object Identifier 10.1364/JOCN.1.000245

1943-0620/09/030245-14/$15.00 ©

witching is used within the core network togetherith an efficient flow aggregation at edge nodes.

Index Terms—Fiber optics and opticalommunications; Network node architecture; Poweronsumption; Routers and switches.

I. INTRODUCTION

ecent development of new transmission andswitching technologies has led to a continuously

ncreasing available capacity provided by optical net-ork infrastructure. Since demand on high-

ransmission capacity is expected to increase consid-rably in the near future because of the introductionf new high-speed access systems and bandwidth-ungry services and applications, the requirements onetwork elements will increase, too. Next-generationwitching and routing elements have to be able toeep pace with these developments and should pro-ide a high throughput in a more dynamic manner.

Optical packet and burst switching have gainedarticular attention in recent years because theseechniques promise high transmission efficiency whenonsidering IP traffic, which is the dominant trafficype in today’s communication networks. However,uch systems require deployment of fast opticalwitches, wavelength converters, and optical buffers.ince optical random access memories are not feasibleet, optical buffering is mostly realized by using fiberelay lines (FDLs). Very large buffers, which are usu-lly required in high-performance packet-switched In-ernet routers, are impractical when implemented bysing FDLs because of their large physical size. Theigh attenuation of the long fibers in FDLs needs to beompensated by optical amplifiers that, in turn, con-ribute to increased total power consumption.

Already today there is a difficulty of packagingarge-scale routers in a single rack or a single room ofquipment. Most of the high-performance routers thatre currently in development are multirack systems.owever, they still suffer from poor scalability, since

he internal interconnection network becomes moreritical when the number of switching chips, lineards, and racks is increased. Moreover, the perfor-

2009 Optical Society of America

bticstsakaAascnpTarsfpc

cnhpatWaTmpI

FsmoMg

246 J. OPT. COMMUN. NETW./VOL. 1, NO. 3 /AUGUST 2009 Slaviša Aleksić

mance of such complex and highly interconnected sys-tems is usually unpredictable. Currently, networkequipment manufactures and operators can supplyand dissipate more than 10 kW per rack of equipment[1]. Power consumption of current network processorsoperating at 10 Gbits/s is around 30 W [2]. State-of-the-art electronic routers have already reached ca-pacities over 1 Tbit/s [3,4]. Under these circum-stances, scaling of electronic routers to support ofhundreds of terabits per second or even 1 Pbit/s be-comes very difficult. Using a hybrid approach, inwhich data processing in line cards including switchcontrol and scheduling are performed electronicallywhile interconnects and switching fabrics are imple-mented in optics, large capacities of hundreds of ter-abits per second are currently possible [1,5]. Switchesor routers based on all-optical technology may be scal-able even to petabits per second capacities, but powerconsumption and supply as well as footprint will stillremain an issue.

II. ARCHITECTURE OF FUTURE SWITCHES AND ROUTERS

It is difficult to predict what technology and archi-tecture will dominate in future high-performance net-work elements. High-speed electronic and opticalpacket switching as well as optical burst switchinggained particular attention in recent years becausethey promise high bandwidth utilization when consid-ering IP traffic. However, such systems require eitherdeployment of huge and very fast buffered electronicpacket switches or fast optical switching together withsome optical buffering. Optical buffer sizes compa-rable with those used in today’s packet-switched IProuters are impractical because of their physical size.

When looking at the current Internet traffic, onecan observe that many applications require establish-ing a connection. Thus, despite the connectionless na-ture of IP, the use of the core network is very connec-tion oriented. Recently, it has been shown that above90% of traffic within backbone networks is using thetransmission control protocol (TCP) [6]. Especiallynew applications such as IP television (IPTV), voiceover IP (VoIP), video conferencing, and interactivegaming set very high requirements on the quality ofservice that cannot be easily met with pure packetswitching. And, indeed, if we look more closely, we willfind that there is plenty of circuit switching in the corenetworks provided through transport technologiessuch as SONET/SDH and WDM. However, the circuitsin the Internet are considered by IP as static point-to-point paths provided by layer 2, which are completelydecoupled from the IP layer. Different signalingmechanisms for a more dynamic circuit provisioningin the core area have already been specified in differ-ent proposals including generalized multiprotocol la-

el switching (GMPLS) [7,8], automatic switchedransport network (ASTN) [9], Optical Internetwork-ng Forum (OIF) [10], optical channel (OCh) and opti-al data unit (ODU) switching [11,12], and TCPwitching [13]. A network architecture that allows in-egration of circuit switching in the core of the packet-witched Internet in an efficient way may be the mostppropriate solution. Such an approach could be aind of hybrid switching that combines circuit, burst,nd packet switching within a single network [14–19].

performance analysis as well as both qualitativend quantitative comparisons between differentwitching paradigms is a very complex task that isertainly outside of the scope of this paper. It wouldeed clarification of representative architectures, to-ologies, traffic scenarios and realization options.herefore, the study described here concentrates onrchitectures that are seen as lower and upper boundsegarding power consumption. The total power con-umption of a realistic and appropriate technology foruture high-performance core network nodes wouldrobably lie somewhere between those two extremeases.

Regardless of the switching technology used, onean define a generic architecture of a high-capacityetwork node as shown in Fig. 1. It is composed of aigh port-count switching fabric, a large number of in-ut and output interfaces, a switch control module,nd transmission subsystems. High-capacity links be-ween two core nodes will probably be based on optical

DM multistrand fiber transmission systems, as is tolarge extent already the case in current networks.

ransmission efficiency and bandwidth utilizationay be even further improved by using hybrid multi-

lexing techniques and advanced modulation formats.nput and output interfaces, i.e., line cards, could be

ig. 1. (Color online) Generic architecture of a high-capacitywitching node. OA, optical amplifier; WDM, wavelength-divisionultiplexing; OTDM, optical time-division multiplexing; OCDM,

ptical code-division multiplexing; SCM, subcarrier multiplexing;EMS, micro-electro-mechanical system; AWG, arrayed waveguide

rating; SOA, semiconductor optical amplifier.

cn

tpdlpweebltrnld(s(mttts

ena6ncutnrt

FtP

Slaviša Aleksić VOL. 1, NO. 3 /AUGUST 2009/J. OPT. COMMUN. NETW. 247

implemented by using different technologies evenwithin one switch to optimally scale costs. A possibleimplementation option is to strictly follow the optical-electrical-optical approach, i.e., to realize line cardsand switching fabrics completely in electronics. Somefunctions could also be implemented in optics, leadingto hybrid implementations. An all-optical implemen-tation would require all functions to be implementedin optics. A very important question is whether elec-tronic or optical buffers will be used and what size andtype of buffer will dominate.

Because the predominant type of traffic in today’scommunication networks is packet-based IP traffic,one could conclude that packet switching is and willremain the key technology in the Internet and thathigh-capacity IP routers will play the key role intransmitting the traffic through the network. How-ever, their high complexity, the need for large buffers,and large power dissipation severely limit the scal-ability of conventional electronic routers. Using opti-cal switching fabrics could relax the limitations tosome extent, but optical buffers occupy larger areaand dissipate more power than electronic ones. An ex-cellent comparison between different implementa-tions of future packet-based routers using optical endelectronic technologies is given in [20]. One of the con-clusions of this comparison, based on an estimation oftotal power dissipation together with a prediction forthe year 2020, is that a large additional concerted re-search effort is needed to overcome technology limita-tions, while the crucial consideration when examiningany new technologies for packet switching needs to bepower and energy. This paper also focuses on power-related issues, but in a different way. First, I concen-trate on power consumption rather than on power dis-sipation. The developed model considers currentrealizations and approaches and uses data of realcomponents and devices currently available on themarket. Then the model is extended by introducingnovel approaches and technologies that are still in theresearch phase, scaling it to very high capacities, andconsidering future developments in technology by tak-ing into account the predictions given by the Interna-tional Roadmap for Semiconductors (ITRS) [21]. Sec-ond, the switching paradigms considered includeoptical and electronic circuit switching in addition topacket switching. Optical technologies are certainlybetter suited for implementing circuit-switched archi-tectures. Therefore, they also need to be taken intoconsideration, even if pure circuit-switched designsmostly provide poor bandwidth utilization. To betterutilize the available bandwidth, the circuits can beprovided in a more dynamic manner, resulting in so-called dynamic circuit switching, or we can combinecircuit switching with other switching paradigms in ahybrid switching system, paradigms that are already

onsidered to be serious candidates for future coreetworks.

There are a number of different approaches andechnologies that can be used for implementing high-erformance switching fabrics. For example, one canecide to use a single high-capacity fabric with a veryarge number of ports. However, a more likely ap-roach is to use multistage switch architectures, inhich small switching elements are connected withach other in an optimal way to form a large and pow-rful switch structure. The switching elements coulde either electronic ones or optical ones. There is aarge variety of different feasible architectures andechnologies, and therefore it is delicate to define rep-esentative architectures of future high-capacity coreodes. However, four particular architectures are se-

ected in this study that are considered potential can-idates. Within all the four considered architecturessee Figs. 2–5), the incoming dense WDM (DWDM)ignal is first amplified by using optical amplifiersOAs) and then split into single channels by WDM de-ultiplexers. At the output, WDM channels belonging

o the same output fiber are combined in WDM mul-iplexers and amplified by optical booster amplifiershereafter. The gain of optical amplifiers is chosenuch that overall losses in the nodes are compensated.

The first architecture shown in Fig. 2 represents anlectronic implementation of a packet-switched coreode. It consists of a large electronic switching fabricnd many line cards whose structure is shown in Fig.. Various functions of the physical, data link, andetwork layers are implemented on the line cards, in-luding complex packet processing and routing, as issually the case in current high-performance elec-ronic switches and routers. The switching fabriceeds to be fast enough to allow a dynamic reconfigu-ation of paths through the switch within the shortime gap between two consecutive packets.

The architecture depicted in Fig. 3 represents an

ig. 2. (Color online) Packet-switched electronic core node. TP/FE,raffic processor/forwarding engine; E/O electro-optical conversion;HY, physical layer chip; MAC, media access control chip.

Tftrntbtdsot

ffiagaaupcnTwnpc

Fc

248 J. OPT. COMMUN. NETW./VOL. 1, NO. 3 /AUGUST 2009 Slaviša Aleksić

optical packet- or burst-switching node using a largeoptical packet switch based on semiconductor opticalamplifiers (SOAs). At the input of the node, incomingpackets are first synchronized respectively to becomealigned with each other. Eventual contentions can beresolved by using wavelength conversion (WC) mod-ules located at input ports and optical buffering atoutputs. Other different structures are also imagin-able, e.g., combined output and input buffering, vir-tual output buffers, and placement of WCs within theswitch. However, the total power consumption is notaffected by the placement of the components as longas the overall number of WC modules and the size ofoptical buffers per port remain unchanged.

A simple architecture of a circuit-switched WDMcore node is shown in Fig. 4. It comprises wavelengthconverters (WCs) at input ports and an optical crossconnect that is realized by using microelectromechani-cal system (MEMS) switches.

Finally, a generic diagram of a circuit-switched elec-tronic core node is shown in Fig. 5. It uses a large elec-tronic cross-point switch and comprises line cardswith a simplified structure compared with the linecards of the first architecture presented in Fig. 2.

Fig. 4. (Color online) Circuit-switched optical core node.

Fig. 3. (Color online) Packet/burst-switched optical core node. WC,wavelength converter; SOA, semiconductor optical amplifier.

hus, no complex packet processing, classifying, andorwarding functions are needed here, and the pathhrough the switch is configured for a longer time pe-iod that corresponds to the duration of a circuit andot on a packet-by-packet basis. Therefore, only func-ions of the physical and the data link layers need toe implemented. Such functions are signal reception/ransmission, serialization/deserialization, clock andata recovery, encoding/decoding, scrambling/de-crambling, and mapping and framing, as well asther functions of the media access control (MAC) pro-ocol.

III. ESTIMATION OF POWER CONSUMPTION

In this study, the total power consumption of theour considered node architectures is calculated byrst taking into account data of real componentsvailable on the market. For this purpose, we defineeneric structures for line cards and switching fabricsnd scale the capacity of network nodes up to 1 Pbit/s,ssuming that future core nodes are implemented bysing current state-of-the-art technologies and ap-roaches. Then we take into account the projectionsoncerning the future development in Si CMOS tech-ology for the year 2018 as issued by the ITRS [21].he estimations for future optical and all-optical net-ork elements are based on state-of-the-art compo-ents as well as data from spec sheets and researchapers. It should be mentioned that any predictiononcerning future development of optical technologies

Fig. 5. (Color online) Circuit-switched electronic core node.

ig. 6. (Color online) Generic structure of a packet router’s lineard with 40 Gbit/s ports. TIA, transimpedance amplifier.

4etlitattpv

sptmetswestofnt(mtfcwhm

ttb

sbskmSAlEiJnpefs

Slaviša Aleksić VOL. 1, NO. 3 /AUGUST 2009/J. OPT. COMMUN. NETW. 249

is difficult, especially if emerging technologies such asnovel fiber types, advanced amplifier structures, de-vices for quantum communications, and photonic crys-tals should be considered. The intention of this studyis not to compare and benchmark different architec-tures, approaches, and implementation technologies;it will point out some trends and issues regardingpower consumption only. It concentrates on maximumtotal power consumption of fully loaded high-perfor-mance network nodes, assuming utilization largerthan 90%. It should be mentioned at this point that amore complete and fair comparison should addition-ally take into consideration physical size (footprint),bandwidth utilization, and technical and economic as-pects. For example, as the result of a high integrationdensity of electronic integrated circuits, more complexfunctions can be implemented within a smaller areain electronics than when using optical processing ele-ments. Because packet switching benefits from statis-tical multiplexing, higher bandwidth utilization canbe achieved in packet-switched networks than in net-works based on circuit switching. Consequently,circuit-switched nodes usually need to have higher ca-pacity than packet-switched ones to achieve the sameperformance. However, most of the links in currentpacket-switched core networks are utilized below 50%[6,13]. That is, packet-switched networks also useoverprovisioning and overdimensioning to handletraffic variability and to protect the network againstmultiple failures. On the one hand, an optimized ag-gregation of user flows at edge nodes and their map-ping either to lightweight, fine-grain circuits or tocoarse-grain circuits (wavelength channels) might in-crease the resource utilization in the circuit-switchedcore at the cost of an increased complexity of edgenodes [13]. On the other hand, edge nodes of a packet-switched core are also complex owing to the need forclassification at the packet level and traffic shapingmechanisms. Thus, an extensive study is needed toanalyze different aspects of packet, circuit, and burstswitching as well as to compare them to a number ofhybrid switching proposals by taking into account allrelevant parameters such as technology issues, futuretraffic characteristics, achievable throughput, end-to-end delay, and packet loss rate.

The general assumptions made in the study are asfollows: aggregate switching capacities are assumed tobe from 320 Gbits/s to 1 Pbit/s. There are W=1–40wavelength channels per fiber port, N=8–625 fiberports, and the line data rate is 40 Gbits/s. Switchsizes assumed are from 8�8 ports for 320 Gbits/s(N=8 and W=1) up to 25,000�25,000 ports for1 Pbit/s aggregated switching capacity (N=625 andW=40). For electronic packet-switched routers, 1 Gbitof buffering per port is assumed, while for opticalpacket-switched routers feasible FDL buffer sizes of

00 kbits and 40 Mbits per output port are consid-red. Power consumption of optical amplifiers is be-ween 3 and 12 W, depending on the overall insertionoss and the length of fiber delay lines. Additionally, its assumed for all four architectures that the elec-ronic control unit consumes about 150 W. All thebove assumptions reflect the current state of elec-ronic and optical transmission technologies, whilehe large number of switching ports for 1 Pbit/s ca-acity is due to the fact that the line data rate of con-entional systems is currently limited to 40 Gbits/s.

The generic structure of line cards for packet-witched electronic routers used for the estimation ofower consumption is shown in Fig. 6. It comprisesransceivers, PHY (physical layer) devices, framers/appers, MAC chips, a traffic processor/forwarding

ngine, memory devices, and a fabric interface. Sincehere are different realization options for each of theubblocks, the most likely ones are first determined,hich serve as exemplary options. In some cases, sev-ral different realizations are considered for the sameubblock. The power consumption of the subblock ishen estimated by averaging the values of differentptions. Such an example is the traffic processor/orwarding engine, which can be realized by usingetwork processors either with or without integratedraffic managers or by using specialized ASICsapplication-specific integrated circuits) and externalemories. Also, specialized coprocessors can be used

o offload data-intensive searches and classificationunctions. Table lookup is mostly realized in a ternaryontent addressable memory (TCAM). Recently, net-ork search engines and route acceleration devicesave been used instead of ternary content addressableemories.

The same structure of line cards is used for the elec-ronic circuit-switched architecture, however, withouthe traffic processor/forwarding engine and memorylocks.

In order to determine realistic values for power con-umption of devices, subsystems, and functionallocks, we first created a large database containingpecs of components currently available on the mar-et. The database includes components from differentanufacturers such as Vitesse Semiconductor, Intel,amsung, IDT, Xelerated, Cypress, SilberCore,MCC, NetLogic Microsystems, PMC Sierra, LSI

ogic, IBM Corporation, Opnext, Bay Microsystems,ZChip Technologies, Micram, Broadcom, Altera, Xil-

nx, Sumitomo Electric Industries, Dune Networks,DSU, Fujitsu, and many others. Most of the compo-ents are based on either the 130 or the 90 nm CMOSrocess technology that is widely used in current rout-rs and switches. A brief description of subblocks andunctions as well as values of power consumption con-idered in calculations can be found in Table I. The

papp[mbistr

F1ic

250 J. OPT. COMMUN. NETW./VOL. 1, NO. 3 /AUGUST 2009 Slaviša Aleksić

values considered are realistic power consumptionsobtained from data sheets of a large number of com-ponents and devices.

Also, the efficiency of power supply units has to betaken into account. The power conversion efficiency isconsidered by introducing an efficiency factor. Due tothe fact that about 15% of the supplied power is lostowing to the inefficiency of the power supply units[22], the values listed in Table I are 15% lower thanthe total power consumed.

Recently, there have been significant research andstandardization efforts to specify and implement100 Gbit Ethernet (100GbE) systems. The proposalsfor the physical transport layer range from paralleltransmission using a number of optical fibers or anumber of wavelength channels within a single fiber[23] to serial transmission over a single wavelengthchannel by exploiting advanced modulation formatsand high-speed data processing [24–29].

The considered applications of 100GbE include localarea networking, short range interconnections withinswitches, routers, and supercomputers, and as long-haul carrier-grade Ethernet connections. Since thispaper focuses on switching and routing nodes withinthe core network, serial transport may be the mostpractical and cost-effective choice for 100 Gbit/stransmission. Various modulation schemes have been

TABCONSIDERED VALUES OF POWER CONSUMPTION AND CALCUL

SWITCH

Subblock Functions Imp

Line card 40 Gbits/sTransceiver Laser (modulator) driver, T

equalization, clock and datdemux

PHY Encoding/decoding, scrambFEC

Framer/MAC Mapping, framing, OH proprocessing, MAC

TP/FE Packet processing, classifypacket forwarding

Fabric interface Switch fabric protocol, portinterface

Memory Packet memory, lookup tabparameters

Subtotal line card �40 Gbits/s�Line cards �8�40 Gbits/s=320 Gbits/s�Switching fabric �320 Gbits/s�

Packet Switch Packet switching capacityduplex)

InterconnectsBackplane Board-to-board interconnec

transceivers �2.5 mW/GbitTotal power consumption �320 Gbits/s�

TIA, transimpendance amplifier; FEC, forward error correction; OH, ofunctions/devices; TP/FE, traffic processor/forwarding engine.

roposed for use in 100 Gbit/s serial transport, suchs polarization-multiplexed differential quadraturehase shift keying (DQPSK) [24,25], single-olarization DQPSK [26,27], and binary on/off keying28,29]. However, the single-polarization DQPSK for-at is considered in this study because it has already

een demonstrated in a field trial [30]. A possiblemplementation of a 100 Gbit/s DQPSK line card ishown in Fig. 7. The power consumption of all func-ional blocks is taken either from data sheets or fromesearch papers [23–35].

ID TOTAL POWER CONSUMPTION OF A 320 GBITS/S PACKET-NODE

ented Power Consumption (W)

postamp.,covery, mux/

5.9

/descrambling, 3.4

ing, payload 30.6

table lookup, 183.6

euing, TP/FE 61.2

configuration 13.6

298.32,386.4

20 Gbits/s (full 224.4

s, high-speed 0.8

2,611.6

ead; PHY, physical layer functions/devices; MAC, media access control

ig. 7. (Color online) Generic structure of a line card with00 Gbit/s ports. DQPSK, differential quadrature phase shift key-ng; DI, delay interferometer; DCR, data and clock recovery; CW,ontinuous wave; BP, balanced photodetector.

LEATE

ED

lem

IA,a re

ling

cess

ing,

qu

le,

of 3

tions/s�

verh

ptc

ta

lp[bcos

c(u3ts1apcptotlt

Fb

Slaviša Aleksić VOL. 1, NO. 3 /AUGUST 2009/J. OPT. COMMUN. NETW. 251

The large optical and electronic packet and cross-point switches are composed of smaller units arrangedin the three-stage Clos structure (see Fig. 8). Theminimal nonblocking Clos arrangement is achievedwhen [36,37]

p = 2n − 1, n =�Ns

2, k =

Ns

n, Ns =

B

b, �1�

where the number of switching units in the first andthe third stage is k and that in the middle stage is p(see also Fig. 8). B denotes the aggregate switching ca-pacity, while b is the line data rate. Ns=NW is thenumber of global fiber ports, and n is the number ofthe ports belonging to a single switching unit, i.e.,n=Ns /k. The total power consumption of the largeelectronic packet switch can then be calculated as

PSW = 2PSWD

NSWDnp +

PSWD

NSWDk2, �2�

where PSWD is the power consumption and NSWD is theport count of a single switching device. By combiningEq. (2) with Eqs. (1) we can obtain the following ex-pression for the total power consumption of the largeClos-based switch:

PSW = 4PSWD

NSWD

B

b�1 −� b

8B� . �3�

The SOA-based switching units, which are used torealize the large optical packet switch in the Clos ar-rangement, comprise internally the Spanke architec-ture as shown in Fig. 9. For power demand calculationonly the SOAs within an active path through theswitch are taken into account, and their averagepower consumption inclusive electronic drivers is sup-posed to be 230 mW [38]. The wastage of power in theinactive SOAs is neglected. The number of hops in aSpanke switch element is 2 log2 n, where n is thenumber of ports. If we assume that the switching ele-ments always have the same number of input and out-

Fig. 8. (Color online) Structure of a three-stage Clos network.

ut ports and that p is always larger than n, then theotal number of SOAs within the active paths can bealculated as

Nactive_SOA = Ns�4 log2 p + 2 log2 k�. �4�

Thus, when combining Eqs. (1) and (4), one can ob-ain the following expression for the total number ofctive SOAs in a large Clos-based switch:

Nactive_SOA =2B

b �1

2log2�2B

b � + 2 log2��2B

b− 1�� .

�5�

Several methods and structures for all-optical wave-ength conversion and 3R regeneration have been pro-osed and experimentally demonstrated recently39–45]. The structures based on an integrated SOA-ased Mach–Zehnder interferometer (MZI) are benefi-ial because of their potential to be integrated withther components of the switch. Therefore, two suchtructures are considered for use in optical nodes.

The wavelength conversion module shown in Fig. 10omprises two SOAs and one distributed feedbackDFB) laser [39], where bias currents applied to thepper and lower SOAs are assumed to be 600 and00 mA, respectively, while the drive current appliedo the DFB laser is 200 mA. Thus, the total power con-umption of an all-optical WC is calculated to be.65 W. The all-optical 3R regenerator uses an all-ctive integrated SOA-MZI [40–42] and a self-ulsating, three-section DFB laser diode [43,44] forlock recovery. The bias currents applied to the com-onents are noted in Fig. 10. 3R regenerators are usedo regenerate the optical signal after a certain numberf SOA stages. The number of SOA stages that can beraversed by the signal without any regeneration isimited mainly by accumulation of the amplified spon-aneous emission (ASE) noise. A simple analytical

ig. 9. (Color online) Active SOAs in an optical packet switchased on the Spanke architecture.

ptnss

t1cpyrqwpaSlrt

ttsshp

Ft

252 J. OPT. COMMUN. NETW./VOL. 1, NO. 3 /AUGUST 2009 Slaviša Aleksić

model described in Appendix A is used to find themaximum number of cascaded SOA-based switchstages between two 3R stages. By assuming a maxi-mum allowed optical signal-to-noise ratio (OSNR)degradation of −20 dB [40], a maximum bit error rateat the receiver of 10−9, and operation of all SOAs out-side of the saturation regime, at maximum nine SOAscan be cascaded without 3R regeneration (see Appen-dix A). Consequently, 3R regenerators need to beplaced after each ninth SOA within the switch.

Optical buffers are simply FDLs demanding addi-tional amplification. Thus, the deployment of large op-tical buffers causes an increase in power consumptionof optical amplifiers (OAs). The synchronizers can beimplemented by using either a feed-forward [46,47] ora parallel structure [48] or a combination of all-opticalwavelength converters and highly dispersive fiber[49]. The use of the feed-forward structure with SOA-based gates as shown in Fig. 11 is assumed here be-cause of its high operation speed, large tuning range,and the potential for integration within the largeSOA-based switch [46].

The MEMS-based optical cross-connects are as-sumed to be of 3D type such as those described in [50].The power consumed by 3D MEMS is assumed to be107 mW per input/output port pair, i.e., per internalpath through the switch. Similarly, the power con-sumption of electronic cross-point switches is sup-posed to be 250 mW [51] per internal path, and that ofoptical interconnects 2.5 mW/Gbit/s [52].

IV. RESULTS

Now we can estimate the total power consumptionof the considered node architectures by using the ap-

Fig. 10. (Color online) Structure of an all-optical (a) wavelength coDFB, distributed feedback laser; SOA, semiconductor optical amplipulsating laser diode.

Fig. 11. (Color online) Schematic of a feed-forward synchronizerthat utilizes SOAs and optical delay lines (ODLs).

roach and assumptions described in the previous sec-ion. Figure 12 shows the results for electronic coreode architectures. It is evident that the power con-umption increases with increasing aggregatedwitching capacity.

For example, state-of-the-art packet-switched elec-ronic routers with capacities of approximatelyTbit/s consume about 8–11 kW. The total power

onsumption exceeds 900 kW when we scale electronicacket routers to capacities of 100 Tbits/s and be-ond. Moreover, the footprint of such high-capacityouters increases too, and thus a 100 Tbit/s router re-uires more than 80 racks to house the equipment. Ife scale packet routers to 1 Pbit/s, then the requiredort count increases to 25,000 at a 40 Gbit/s line rate,nd the total power consumption approaches 9 MW.uch a large power consumption and high number of

ine cards would raise requirements on power supply,oom cooling, and interconnection infrastructure thatoday and in the near future hardly can be met.

One could try to reduce the large complexity andhe huge buffer size of electronic packet routers byransmitting data through core nodes in a circuit-witched manner rather than using a purely packet-witched network. Indeed, several research groupsave proposed different architectures for high-erformance electronic circuit-switched systems

rter and (b) 3R regenerator considered for use in optical core nodes.; OBF, optical bandpass filter; ODL, optical delay line; SPLD, self-

ig. 12. (Color online) Estimated total power consumption of elec-ronic core switches and routers.

nvefier

cenw

aobthstst1c1ei

tmcclust

ptcbsismtba

caoiwwwsp6m1

d

Slaviša Aleksić VOL. 1, NO. 3 /AUGUST 2009/J. OPT. COMMUN. NETW. 253

[53–55]. Thus, smaller buffers would be required, andpaths through the cross-point switch could be set forlonger time periods so that data processing within linecards could also be extremely simplified. Thus, nohigh-performance traffic processors would be needed.Additionally, the structure of switching devices wouldbe simpler, too, and instead of complex and power-hungry packet processing, routing, and switching ele-ments, large cross-point devices can be used. Together,savings in total power consumption of up to 70% couldthereby be achieved. However, the reduction of pro-cessing complexity, and thus, the lower power con-sumption comes at a certain cost: the network edgenodes’ tasks become more complex, and the utilizationof available network resources likely more inefficientif not planned well in advance. The estimated powerconsumption of such a 100 Tbit/s circuit-switchedelectronic core node is approximately 300 kW, whichseems practically feasible, but a 1 Pbit/s circuit-switched node would still consume about 3 MW.

Figure 13 shows the total estimated power con-sumption of electronic packet-switched nodes for ca-pacities up to 100 Tbits/s. There are a number ofhigh-performance routers with capacities within thisrange currently available on the market. For example,the value of the maximum power consumption givenby Cisco for the 1.2 Tbit/s CRS-1 router [3] is veryclose to the estimated power consumption for packet-switched electronic routers with the same capacity.The largest multishelf configuration of the CRS-1router having a total capacity of 92 Tbits/s and re-quiring 80 racks to carry the networking equipmentwould consume about 1 MW of power as shown in Fig.9. The results of our study also fit very well to thepower-consumption-related specs of other commer-

Fig. 13. (Color online) Estimated total power consumption of elec-tronic core node architectures together with examples of currenthigh-performance routers.

ially available routers. Figure 13 shows additionalxamples of current high-performance routers,amely Black Diamond 20808 from Extreme Net-orks and Juniper’s M320 and T-series [4,56].

Because capacities of several hundreds of terabitsre envisaged for the next 10 years, the future devel-pment of technology within this period also needs toe taken into account. According to the ITRS predic-ions, both the size and power consumption of futureigh-capacity electronic routers should significantlyhrink. Applying that, we can expect that an elec-ronic packet-switched 100 Tbit/s node would con-ume no more than 45 kW, a circuit-switched node ofhe same capacity about 26 kW, a packet-switchedPbit/s router about 440 kW, and a corresponding

ircuit-switched one approximately 250 kW (see Fig.2). That is, if the predictions become reality, thenven 1 Pbit/s packet routers could be realized by us-ng electronics and current approaches.

However, it should be mentioned here that, in addi-ion to the power supplied to the networking equip-ent, noticeable power is also consumed by the room

ooling equipment, which leads to a significant in-rease of the total power required. Moreover, a veryarge number of batteries have to be used as backup inninterruptible power supply (UPS) units, which con-equently leads to a significantly larger footprint ofhe whole system.

It would be of interest to see what portion of theower is consumed by different subsystems of elec-ronic packet-switched nodes. For this purpose, the ar-hitecture of a 100 Tbit/s router is divided into sub-locks for data transmission, processing and routing,torage, switching, and internal interconnection. Thent was possible to calculate the power allocated to eachubsystem. A description of the functions imple-ented in different subblocks of a 320 Gbit/s router

ogether with values of their power consumptions cane found in Table I. Those values scaled to 100 Tbits/sre presented in the diagram in Fig. 14.

As can be seen from Fig. 14, the most power-onsuming part is the subsystem for data processingnd packet forwarding that consumes more than halff the total power supplied. At the second place is thenterconnecting network including fabric interfaceith 19%, followed by the transmission subsystemith 12%, switching fabric with 9%, and memoriesith 4%. Let us mention that those results are very

imilar to the results reported by Cisco [22], where theower consumed by routing engine is estimated to be1% (in our calculations 56% for TP/FE plus 4% foremory) and that consumed by switching fabrics is

1% (9% in our calculations).

Using line cards equipped with 100 Gbit/s ports asepicted in Fig. 7 would certainly lead to a lower over-

ap7t1r4oTrp

cstisiaiprmeaiswttsmoptaofrv

Fc

254 J. OPT. COMMUN. NETW./VOL. 1, NO. 3 /AUGUST 2009 Slaviša Aleksić

all power consumption. Figure 15 shows a comparisonof the calculated power consumption for 40 and100 Gbit/s line cards for different aggregated capaci-ties. However, the power savings are not large becausethe transmission subsystem contributes only 12% tothe total power consumption. Thus, in the case of acircuit-switched node, savings of up to 30% can beachieved, while the power consumption of packet-switched line cards can be reduced by only 9% whenusing the 100 Gbit/s DQPSK format instead of40 Gbit/s non-return-to-zero data transmission.

The estimated power consumption of the two opticalcore node variants is shown in Fig. 16. One can ob-serve only slight differences in power consumption be-tween the two realizations using 400 kbit and 40 MbitFDL buffers; however, the footprint of the 40 Mbitbuffers option would be much larger.

Please note that both all-optical wavelength con-verters and optical 3R regenerators are assumed to beused in the large optical packet switches. Under theseassumptions, the estimated power consumption of a100 Tbit/s optical router using current optoelectronic

Fig. 14. (Color online) Calculated power consumption allocation bysubsystems. The power conversion efficiency is not included.

Fig. 15. (Color online) Power consumption of 40 and 100 Gbit/sline cards when assuming non-return-to-zero DQPSK transmissionfor 100 Gbits/s (fabric interface and switching modules are nottaken into account).

nd optical technologies and 400 kbit buffering perort is slightly less than 68 kW, and for 1 Pbit/s about84 kW. When using 40 Mbit buffers, the consump-ion increases slightly to 69 and 794 kW for00 Tbits/s and 1 Pbits/s, respectively. Because theequired length of a 40 Mbit optical buffer at0 Gbits/s is about 200 km, the required total lengthf FDLs in a 100 Tbit/s optical router is 500,000 km.he main limiting factor for packet-switched opticalouters is thus not their power consumption but thehysical size of optical buffers.

At this point, it should be mentioned that the mainonclusions of this work as well as the main trends ob-erved are generally in agreement with the results ofhe study presented in [20]. The results of both stud-es indicate that power consumption needs to be con-idered as a very important parameter when design-ng new high-capacity network elements. Both opticalnd electronic technologies will play significant rolesn future high-capacity routers, although the largehysical size of optical buffers and the lack of opticalandom access memories make an all-optical imple-entation of packet-switched nodes difficult. How-

ver, there are relatively large differences between thebsolute values of estimated total power consumptionn the two studies. This is mainly due to different as-umptions and methodologies used. For example, theork presented in [20] concentrates on power dissipa-

ion and assumes slightly different architectures andechnologies than those assumed in this paper. Thetudy presented here, however, concentrates on esti-ation of maximum power consumption rather than

n power dissipation. Therefore, the absolute valuesresented in this paper are significantly higher thanhose shown in [20]. Because various practical aspectsre considered, such as concrete components availablen the market, implementation of various functionsor packet processing, classification, forwarding, andouting, as well as power conversion efficiency, thealues of power consumption for electronic packet-

ig. 16. (Color online) Estimated total power consumption of opti-al core nodes.

ptcCcfiwptspbslcpons

mssgtcbTost(p

o3givp

Sap

Fs

Slaviša Aleksić VOL. 1, NO. 3 /AUGUST 2009/J. OPT. COMMUN. NETW. 255

switched nodes presented in this paper fit very well tothose given by the manufactures of current high-performance switching and routing systems.

When taking a look at the results regarding thehigh-capacity optical circuit-switched core nodes, itcan be concluded that they would consume the lowestpower and would also occupy the lowest area in thepremises of network providers. A 100 Tbit/s nodewithout WC would consume slightly more than 2 kW,and that with 1 Pbit/s aggregated capacity no morethan 21 kW. Thus, this architecture is the most scal-able architecture with respect to power consumption;however, as with electronic circuit switching, the re-duction in power consumption comes at the cost ofmore complex edge node tasks and potentially less ef-ficient bandwidth utilization. When employing all-optical wavelength conversion for contention reso-lution, the power consumption increases noticeably.The consumption of a 1 Pbit/s circuit-switched nodeincreases from 21 to 62 kW, but it still remains thelowest-power-consuming architecture.

V. CONCLUSION

In conclusion, this paper discussed issues andtrends concerning power consumption of future high-capacity network nodes. Four different core node ar-chitectures and technologies were considered andevaluated with respect to power consumption andscalability. When using current state-of-the-art tech-nologies and approaches, optical nodes consume gen-erally less power than electronic ones. Especially, op-tical circuit-switched architectures based on MEMSswitching devices seem to be the most scalable solu-tion among the four considered architectures with re-spect to power consumption. However, because theswitching time of MEMS-based cross connects is of theorder of milliseconds, the achievable bandwidth utili-zation is normally relatively low. In order to achieve ahigh throughput, the required port count of MEMS-based switches must be higher than that of fastpacket switches. Therefore, a more complete and faircomparison should additionally take into consider-ation physical size (footprint), throughput, andtechnical–economic aspects. If we take into accountthe reduction in size and in energy consumption of fu-ture Si CMOS devices as predicted by the ITRS, thenthe power consumption of electronic packet routersshrinks to numbers considerably lower than that ofcurrent optical designs. That is, our results show thata 1 Pbit/s optical packet router would consume al-most the same power as current 100 Tbit/s electronicpacket routers, or it would consume twice as muchpower as an electronic packet router in the year 2018when considering the ITRS predictions. Opticalcircuit-switched nodes consume less than 10% of the

ower consumed by optical packet-switched architec-ures. Similarly, electronic circuit-switched designsonsume 43% less power than packet-switched ones.onsequently, we can conclude that using dynamicircuit switching or a kind of hybrid switching that ef-ciently combines packet, circuit, and burst switchingithin the core network would lead to a lower com-lexity of core nodes and to a significant reduction inotal power consumption. The power consumption ofuch a system is expected to be higher than that of theure circuit-switched design considered in this paper,ut still below the consumption of a pure packet-witched architecture. Thus, it is an important chal-enge to find a well-suited and feasible network con-ept that will be able to provide both higherformance and low power consumption, in order tovercome the scalability limitations of core networkodes due to the high complexity and large power con-umption of current approaches.

APPENDIX: PLACEMENT OF 3R REGENERATORS

The semiconductor optical amplifiers used to imple-ent large optical packet switches are the main

ources of the ASE noise and may cause various unde-irable effects when operated in the saturation re-ime. The accumulation of ASE noise causes degrada-ion of the OSNR, while saturation leads to gainompression, intersymbol interference, and crosstalketween signals on different wavelength channels.herefore, we have to find out the maximum numberf SOA gates that can be cascaded without need forignal regeneration. This can be done by consideringwo effects: degradation of the signal-to-noise ratioSNR) and saturation of SOAs, similar to the ap-roach presented in [57].Figure 17 shows the signal path through a cascade

f SOA-based switch stages. There is only a singledB coupler needed in each stage before the SOA

ates in order to either split the input optical powernto two ways or to combine output powers of two pre-ious stages into a single output. The loss in this cou-ler is denoted LC.The coupling losses at the input and the output of

OAs (fiber-to-chip coupling) are considered by LSOA,innd LSOA,out, respectively. Thus, the power at the out-ut of the ith stage, Pout,i, can be calculated as

ig. 17. (Color online) Signal path through an optical packetwitch based on the Spanke architecture.

Est3sB=tcap�

theOsiswbtlmr

Tttlt

F

256 J. OPT. COMMUN. NETW./VOL. 1, NO. 3 /AUGUST 2009 Slaviša Aleksić

Pout,i = LCLSOA,inLSOA,outGPin,i + LSOA,outPASE, �6�

where Pin,i is the power at the input of the ith stage, Gis the internal gain of the SOA, and PASE is the powerof the ASE noise generated within the ith stage thatcan be expressed as

PASE = pnsph��G − 1�BO. �7�

In Eq. (7), p represents the polarization-dependantfactor �1�p�2), nsp is the population inversion factor,BO is the amplifier optical bandwidth, h is the Plank’sconstant, and � is the optical carrier frequency. Theoverall signal gain of q cascaded stages is given by

Gsig,q = �LCLSOA,inLSOA,outG�q. �8�

Similarly, the overall spontaneous emission gain,Gsp,q, can be expressed as

Gsp,q = � Gsig,q1/q

LinLSOA,in− LSOA,out� 1 − Gsig,q

1 − Gsig,q1/q . �9�

Finally, the power at the output of the cascade of qswitch stages is given by

Pout,q = Gsig,qPin + Gsp,qPASE,eff, �10�

where PASE,eff is the amplified spontaneous noisegiven by PASE,eff=peffnsph�BO,eff. Here, BO,eff and peff�1�peff�2� are the effective overall gain bandwidthdue to the cascade of q SOAs and the effectivepolarization-dependant factor, respectively.

The accumulated noise after a cascade of q switchstages is due mainly to the ASE in SOAs. If we as-sume that the extinction ratio of SOAs is as high as45 dB [38], the noise caused by imperfect suppressionof optical signals in inactive SOAs can be neglected.Consequently, the OSNR can be calculated as

OSNRq =Psig,q

Pnoise,q=

Gsig,qPin

Gsp,qPASE,eff. �11�

The noise in a receiver placed after the qth stage isdominated by signal–spontaneous and spontaneous–spontaneous beat noise. To achieve a bit error rate of10−9, the value of the postdetection SNR, �, has to belarger than 144 [58]. The postdetection SNR can beapproximately calculated by

� =�Gsig,qPin�2

4Gsp,qnsph�Be�Gsig,qPin + Gsp,qnsph�BOF�, �12�

where Be is the bandwidth of the receiver and BOF isthe bandwidth of the optical filter placed before the re-ceiver.

The second constraint to be considered here is theSOA saturation power. Thus, the power at the outputof the SOA in the q-th stage, PSOA,q, must not behigher than the SOA saturation power, P ; i.e.,

sat

PSOA,q =Pout,q

LSOA,out� Psat. �13�

quation (13) ensures that all SOAs are operated out-ide of the saturation regime. Let us now determinehe maximum number of stages achievable withoutR regeneration for the considered optical packetwitch. We can assume LSOA,in=LSOA,out=LC=0.5,O,eff=1 THz, BOF=100 GHz, Be=40 GHz, and Pin0 dBm. The internal gain of SOAs is chosen such

hat the overall loss of a switch stage is effectivelyompensated. First we need to calculate Gsig,Q, Gsp,Q,nd PASE,eff. Then we can obtain the values for signalower at the output of the switch stages, OSNROSNRq� as well as postdetection SNR ���.

The maximum number of stages is limited by bothhe above-mentioned constraints; namely, � has to beigher than 144 and PSOA,q should be lower than orqual to Psat. Additionally, the maximum allowedSNR degradation is set to −20 dB because the con-

idered all-optical 3R regeneration units are able tomprove OSNR by exactly this value [40]. The SOAaturation power is assumed to be 13.6 dBm [59]. Nowe can plot the values of OSNR and � versus the num-er of cascaded stages. It can be seen from Fig. 18 thathe maximum number of SOA-based switch stages isimited mostly by the postdetection SNR. Hence, no

ore than nine stages can be cascaded without signalegeneration.

ACKNOWLEDGMENT

he work described in this paper was carried out withhe support of the BONE project (“Building the Fu-ure Optical Network in Europe”), a Network of Excel-ence funded by the European Commission throughhe 7th ICT Framework Programme.

REFERENCES

[1] I. Keslassy, S.-T. Chuang, K. Yu, D. Miller, M. Horowitz, O.Solgaard, and N. McKeown, “Scaling internet routers using op-

ig. 18. (Color online) Maximum number of cascaded SOA stages.

Slaviša Aleksić VOL. 1, NO. 3 /AUGUST 2009/J. OPT. COMMUN. NETW. 257

tics,” in Proc. 2003 Conf. on Applications, Technologies, Archi-tectures, and Protocols for Computer Communications,Karlsruhe, Germany, Aug. 25–29, 2003, pp. 189–200.

[2] Intel IXP2855 Network Processor, Intel Corporation, http://www.intel.com/networkprocessors.

[3] Cisco IP Router CR1, Cisco Systems, http://www.cisco.com.[4] Juniper Networks, T Series Routing Platforms, http://

www.juniper.net.[5] H. J. Chao, K.-L. Deng, and Z. Jing, “Petastar: a petabit pho-

tonic packet switch,” IEEE J. Sel. Areas Commun., vol. 21, pp.1096–1112, 2003.

[6] C. Fraleigh, S. Moon, B. Lyles, C. Cotton, M. Khan, D. Moll, R.Rockell, T. Seely, and C. Diot, “Packet-level traffic measure-ments from the sprint IP backbone,” IEEE Netw. Mag., vol. 17,no. 6, pp. 6–16, Nov.–Dec 2002.

[7] A. Banerjee, J. Drake, J. Lang, B. Turner, D. Awduche, L.Berger, K. Kompella, and Y. Rekhter, “Generalized multiproto-col label switching: an overview of signaling enhancementsand recovery techniques,” IEEE Commun. Mag., vol. 39, no. 7,pp. 144–151, July 2001.

[8] A. Banerjee, J. Drake, J. Lang, B. Turner, K. Kompella, and Y.Rekhter, “Generalized multiprotocol label switching: an over-view of routing and management enhancements,” IEEE Com-mun. Mag., vol. 39, no. 1, pp. 144–150, Jan. 2001.

[9] ITU Telecommunication Standardization Sector, “Architecturefor the automatic switched transport network (ASTN),” ITU-TRec. G.807/Y.1302 ed, Nov. 2001.

[10] G. Bernstein, B. Rajagopalan, and D. Spears, “OIF UNI 1.0—controlling optical networks,” White paper, Optical Internet-working Forum, 2001.

[11] ITU Telecommunication Standardization Sector, “Opticaltransport network (OTN),” ITU-T Rec. G.709/Y1331 ed., Mar.2003.

[12] ITU Telecommunication Standardization Sector, “Opticaltransport hierarchy,” ITU-T Rec. G.871/Y.1301 ed., 2000.

[13] P. Molinero-Fernández and N. McKeown, “TCP switching: ex-posing circuits to IP,” IEEE MICRO, vol. 22, no. 1, pp. 82–89,Jan.–Feb. 2002.

[14] E. W. M. Wong and M. Zukerman, “Analysis of an optical hy-brid switch,” IEEE Commun. Lett., vol. 10, pp. 108–110, 2006.

[15] N. Yamanaka and K. Shiomoto, “DTM: dynamic transfer modebased on dynamically assigned short-hold time-slot relay,” IE-ICE Trans. Commun., E-82b, pp. 439–446, 1999.

[16] J. Baert, M. De Leenheer, B. Volckaert, T. Wauters, P. Thyse-baert, F. De Turck, B. Dhoedt, and P. Demeester, “Hybrid opti-cal switching for data-intensive media grid applications,” inProc. of the Workshop on Design of Next Generation OpticalNetworks, Ghent, Belgium, Feb. 2006, pp. 9–14.

[17] S. Bjørnstad, L. E. Eriksen, and D. R. Hjelme, “The OpMiGuamultiservice optical hybrid packet/circuit switched networksupporting TV-broadcasting QoS requirements,” in 2006 Int.Conf. on Transparent Optical Networks, Nottingham, UK, June18–22, 2006, vol. 3, pp. 219–224.

[18] C. M. Gauger, P. J. Kuhn, E. Van Breusegem, M. Pickavet, andP. Demeester, “Hybrid optical network architectures: bringingpackets and circuits together,” IEEE Commun. Mag., vol. 44,no. 8, pp. 36–42, Aug. 2006.

[19] H. R. van As, “Time for a change in electronic and photonicswitching,” in 10th Anniversary Int. Conf. on Transparent Op-tical Networks, 2008. ICTON 2008, Athens, Greece, June 22–26, 2008, vol. 1, pp. 140–143.

[20] R. S. Tucker, The role of optics and electronics in high-capacityrouters, J. Lightwave Technol., vol. 24, pp. 4655–4673, 2006.

[21] The International Technology Roadmap for Semiconductors,2005 ed., http://www.itrs.net.

[22] G. Epps, D. Tsiang, and T. Boures, “System power challenges,”presented at Cisco Routing Research Seminar, Aug. 29–30,2006.

[23] “IEEE P802.3ba 40 Gb/s and 100 Gb/s ethernet task force,”http://www.ieee802.org/3/ba/.

[24] S. Chandrasekhar, X. Liu, E. C. Burrows, and L. L. Buhl, “Hy-brid 107-Gb/s polarization-multiplexed DQPSK and 42.7DQPSK transmission at 1.4-bits/s /Hz spectral efficiency over1280 km of SSMF and 4 bandwidth-managed ROADMs,” pre-sented at 33rd European Conf. and Exhibition on Optical Com-munications, Berlin, Germany, Sept. 16–20, 2007, paper PD1.92.

[25] C. R. S. Fludger, T. Duthel, D. van den Borne, C. Schulien,E.-D. Scmidt, T. Wuth, E. de Man, G. D. Khoe, and H. deWaardt, “10�111 Gbit/s, 50 GHz spaced, POLMUX-RZ-DQPSK transmission over 2375 km employing coherentequalisation,” in Optical Fiber Communication Conf. and Ex-position and The Nat. Fiber Optic Engineers Conf., Anaheim,CA, March 25, 2007, OSA Technical Digest Series (CD), Wash-ington, DC: Optical Society of America, 2007, paper PDP22.

[26] H. Masuda, A. Sano, T. Kobayashi, E. Yoshida, Y. Miyamoto, Y.Hibino, K. Hagimoto, T. Yamada, T. Furuta, and H. Fukuyama,“20.4-Tb/s �204�111 Gb/s� transmission over 240 km usinghybrid Raman/EDFAs,” in Optical Fiber Communication Conf.and Exposition and The Nat. Fiber Optic Engineers Conf., Ana-heim, CA, March 25, 2007, OSA Technical Digest Series (CD),Washington, DC: Optical Society of America, 2007, paperPDP20.

[27] P. J. Winzer, G. Raybon, C. R. Doerr, L. L. Buhl, T. Kawanishi,T. Sakamoto, M. Izutsu, and K. Higuma, “2000-km WDMtransmission of 10�107-Gb/s RZ-DQPSK,” presented at Euro-pean Conf. on Optical Communication, Cannes, France, Sept.24–28, 2006, paper Th 4.1.3.

[28] P. J. Winzer, G. Raybon, C. R. Doerr, M. Duelk, and C. Dorrer,“107-Gb/s optical signal generation using electronic time-division multiplexing,” J. Lightwave Technol., vol. 24, pp.3107–3113, 2006.

[29] R. H. Derksen, G. Lehmann, C.-J. Weiske, C. Schubert, R. Lud-wig, S. Ferber, C. Schmidt-Langenhorst, M. Moeller, and J.Lutz, “Integrated 100 Gbit/s ETDM receiver in a transmissionexperiment over 480 km DMF,” in Optical Fiber Communica-tion Conf. and Exposition and The Nat. Fiber Optic EngineersConf., Anaheim, CA, March 5, 2006, Technical Digest (CD),Washington, DC: Optical Society of America, 2006, paperPDP37.

[30] P. J. Winzer, G. Raybon, H. Song, A. Adamiecki, S. Corteselli,A. H. Gnauck, D. A. Fishman, C. R. Doerr, S. Chandrasekhar,L. L. Buhl, T. J. Xia, G. Wellbrock, W. Lee, B. Basch, T. Kawan-ishi, K. Higuma, and Y. Painchaud, “100-Gb/s DQPSK trans-mission: from laboratory experiments to field trials,” J. Light-wave Technol., vol. 26, no. 20, pp. 3388–3402, 2008.

[31] SHF Communication Technologies AG, http://www.shf.de.[32] R.-E. Makon, R. Driad, K. Schneider, M. Ludwig, R. Aidam, R.

Quay, M. Schlechtweg, and G. Weimann, “80 Gbit/s monolithi-cally integrated clock and data recovery circuit with 1:2 DE-MUX using InP-based DHBTs,” in IEEE Compound Semicon-ductor Integrated Circuit Symp., 2005, CSIC ’05, PalmSprings, CA, Oct. 30–Nov. 2005, pp. 268–271.

[33] EM4, Inc., http://www.em4inc.com/.[34] u2t Photonics AG, http://www.u2t.de/.[35] Broadcom, Corporation, http://www.broadcom.com/.[36] C. Clos, “A study of non-blocking switching networks,” Bell

Syst. Tech. J., vol. 32, pp. 406–424, 1953.[37] K.-H. Tsai and D.-W. Wang, “Lower bounds for wide-sense non-

blocking Clos network,” in Computing and Combinatorics: 4thAnnual Int. Conf., Taipei, Taiwan, August 1998, pp. 213–218,vol. 1449 of Lecture Notes in Computer Science, Berlin, Ger-many: Springer, 1998.

[38] N. Sahri, D. Prieto, S. Silvestre, D. Keller, F. Pommereau, M.Renaud, O. Rofidal, A. Dupas, F. Dorgueille, and D. Chiaroni,“A highly integrated 32-SOA gates optoelectronic module suit-

ecpmitampodnEtDEttc

258 J. OPT. COMMUN. NETW./VOL. 1, NO. 3 /AUGUST 2009 Slaviša Aleksić

able for IP milti-terabit optical packet routers,” in Optical Fi-ber Communication Conf. and Exhibit, 2001. OFC 2001, Ana-heim, CA, 2001, vol. 4, pp. PD32-1–PD32-3.

[39] T. Hatta, T. Miyahara, Y. Miyazaki, K. Takagi, K. Matsumoto,T. Aoyagi, K. Motoshima, K. Mishina, A. Maruta, and K. Ki-tayama, “Polarization-insensitive monolithic 40-Gbps SOA-MZI wavelength converter with narrow active waveguides,”IEEE J. Sel. Top. Quantum Electron., vol. 13, pp. 32–39, 2007.

[40] D. Wolfson, A. Kloch, T. Fjelde, C. Janz, B. Dagens, and M.Renaud, “40-Gb/s all-optical wavelength conversion, regenera-tion, and demultiplexing in an SOA-based all-active Mach–Zehnder interferometer,” IEEE Photon. Technol. Lett., vol. 12,pp. 3332–334, 2000.

[41] M. Y. Jeon, Y. A. Leem, D. C. Kim, E. Sim, S.-B. Kim, H. Ko, D.S. Yee, and K. H. Park, “40 Gbps all-optical 3R regenerationand format conversion with related InP-based semiconductordevices,” ETRI J., vol. 29, pp. 633–640, 2007.

[42] J. P. Wang, S. J. Savage, B. S. Robinson, S. A. Hamilton, E. P.Ippen, R. Mu, H. Wang, L. Spiekman, and B. B. Stefanov, “Re-generation using an SOA-MZI in a 100-pass 10,000-km recir-culating fiber loop,” in Conf. on Lasers and Electro-Optics/Quantum Electronics and Laser Science Conf. and PhotonicApplications Systems Technologies, Baltimore, MD, May 6,2007, OSA Technical Digest Series (CD), Washington, DC: Op-tical Society of America, 2007, paper CMZ1.

[43] W. Mao, X. Wang, M. Al-Mumin, and G. Li, “40 Gb/s all-opticalclock recovery using three section self-pulsation DFB lasers,”in Optical Fiber Communication Conf., Baltimore, MD, March7, 2000, OSA Technical Digest Series, Washington, DC: OpticalSociety of America, 2000, paper ThF2, pp. 79–80.

[44] C. Bornholdt, B. Sartorius, S. Schelhase, M. Möhrle, and S.Bauer, “Self-pulsating DFB laser for all-optical clock recoveryat 40 Gbit/s,” Electron. Lett., vol. 36, pp. 327–328, 2000.

[45] O. Leclerc, B. Lavigne, B. Balmefrezol, P. Brindel, L. Pierre, D.Rouvillain, and F. Seguineau, “All-optical signal regeneration:from first principles to a 40 Gbit/s system demonstration,” C.R. Phys., vol. 4, no. 1, pp. 163–173, Jan.–Feb. 2003.

[46] J. P. Mack, H. N. Poulsen, and D. J. Blumenthal, “40Gb/s au-tonomous optical packet synchronizer,” in Optical Fiber Com-munication Conf. and Exposition and The Nat. Fiber Optic En-gineers Conf., San Diego, CA, Feb. 24, 2008, OSA TechnicalDigest (CD), Washington, DC: Optical Society of America,2008, paper OTuD3.

[47] A. Stavdas, A. Salis, A. Dupas, and D. Chiaroni, “All-opticalpacket synchronizer for slotted core/metropolitan networks,” J.Opt. Netw., vol. 7, pp. 88–93, 2008.

[48] T. Sakamoto, A. Okada, M. Hirayama, Y. Sakai, O. Moriwaki,I. Ogawa, R. Sato, K. Noguchi, and M. Matsuoka, “Opticalpacket synchronizer using wavelength and space switching,”IEEE Photon. Technol. Lett., vol. 14, pp. 1360–1362, 2002.

[49] Z. Hu, J. Sun, L. Liu, and J. Wang, “All-optical tunable delayline based on wavelength conversion in semiconductor opticalamplifiers and dispersion in dispersion-compensating fiber,”Appl. Phys. B, vol. 91, nos. 3–4, pp. 421–424, June 2008.

[50] M. Yano, F. Yamagishi, and T. Tsuda, “Optical MEMS for pho-tonic switching-compact and stable optical crossconnectswitches for simple, fast, and flexible wavelength applicationsin recent photonic networks,” IEEE J. Sel. Top. Quantum Elec-tron., vol. 11, pp. 383–394, 2005.

[51] Crosspoint Switches VSC3040, VSC3004, and VSC3008, Vit-esse Semiconductor Corporation, http://www.vitesse.com/products

[52] C. Kromer, G. Sialm, C. Berger, T. Morf, M. L. Schmatz, F. El-linger, D. Erni, G.-L. Bona, and H. Jäckel, “A 100-mW410 Gb/s transceiver in 80-nm CMOS for high-density opticalinterconnects,” IEEE J. Solid-State Circuits, vol. 40, pp. 2667–2679, 2005.

[53] P. T. Wolkotte, G. J. M. Smit, G. K. Rauwerda, and L. T. Smit,“An energy-efficient reconfigurable circuit-switched network-on-chip,” in 19th IEEE Int. Parallel and Distributed ProcessingSymp., 2005. Proceedings, Denver, CO, Apr. 4–8, 2005, paperA155.

[54] P.-H. Pham, Y. Kumar, and C. Kim, “High performance andarea-efficient circuit-switched network on chip design,” in The6th IEEE Int. Conf. on Computer and Information Technology,2006. CIT ’06, Seoul, South Korea, Sept. 2006, p. 243.

[55] K.-C. Chang, J.-S. Shen, and T.-F. Chen, “Tailoring circuit-switched network-on-chip to application-specific system-on-chip by two optimization schemes,” in ACM Trans. Design Au-tom. Electron. Syst., vol. 13, no. 1, article 12, Jan. 2008.

[56] Extreme Networks, Inc., “Black diamond 20808 switch,” http://www.extremenetworks.com/.

[57] R. F. Kalman, L. G. Kazovsky, and J. W. Goodman, “Space di-vision switches based on semiconductor optical amplifiers,”IEEE Photon. Technol. Lett., vol. 4, pp. 1040–1051, 1992.

[58] N. A. Olsson, “Lightwave systems with optical amplifiers,” J.Lightwave Technol., vol. 7, pp. 1071–1082, 1989.

[59] S. Tanaka, S.-H. Jeong, S. Yamazaki, S. Tomabechi, A. Uetake,M. Ekawa, and K. Morito, “Polarization-insensitivemonolithically-integrated 8:1 SOA gate switch with large gainand high extinction ratio,” in Optical Fiber CommunicationConf. and Exposition and The Nat. Fiber Optic EngineersConf., San Diego, CA, Feb. 24, 2008, OSA Technical Digest(CD), Washington, DC: Optical Society of America, 2008, paperOWE2.

Slaviša Aleksić (M’00) received his Dipl.-Ing. and his Ph.D. degrees in electrical en-gineering from the Vienna University ofTechnology, Austria, in 1999 and 2004, re-spectively. Currently, he is employed as anAssistant Professor at the Institute ofBroadband Communications, Vienna Uni-versity of Technology, where he is respon-sible for teaching and research activities.His current research interests include com-munication networks, photonic networks,

nergy consumption, high-speed optical and electrical signal pro-essing systems, as well as high-speed media access control (MAC)rotocol design and implementation. He is author or coauthor ofore than 40 scientific publications including book chapters, papers

n peer-reviewed scientific journals, and contributions to interna-ionally recognized conferences. He has experience in both researchnd industrial fields through successfully managing and conductingany projects related to communication networks including two

rojects funded by the Austrian Science Fund (FWF) and a numberf projects in collaboration with several Austrian and European aca-emic institutions and companies. He was involved in COST actiono. 291 “Towards Digital Optical Internet” and the EU Network ofxcellence “e-Photon/One.” Currently, he is the leader of the Aus-

rian research group within the EU Network of Excellence “BONE.”r. Aleksić is a member of the Institute of Electrical and Electronicsngineers (IEEE—USA), of the Austrian Electrotechnical Associa-

ion (OVE—Austria), and of the Institute of Electronics, Informa-ion and Communication Engineers (IEICE—Japan). He has re-eived several international awards, grants, and recognitions.