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VLSI Design
Special Issue on
Networks-on-Chip
Call for Papers
While semiconductor device scaling continues providinggreater transistor counts, much of the traditional power ben-efit of scaling has ceased, leading to the current proliferationof parallel computing architectures. To cope with powerconsumption challenges without sacrificing performance inthese architectures, Networks-on-Chip (NoC) architectureshave replaced bus-based and point-to-point (P2P) intercon-nect designs. As we approach hundreds and even a thousandcores on the same chip, there are several open problemsacross all design layers (technology, circuit, microarchitec-ture, and application) that require revolutionary approachesfrom a wide range of disciplines. This special issue onNetworks-on-Chip, scheduled to appear in March 2013,seeks original and ambitious manuscripts advancing thestate of the art in both theory and practice of designingand analyzing NoCs for the many-core era. Potential topicsinclude, but are not limited to:
NoC architectures for CMP/MPSoCs (topology, rout-
ing, switching, flow control, etc.) NoC support for memory and cache access
Workload characterization and evaluation
Novel interconnect link/switch/router designs
Timing, synchronous/asynchronous communication
Signaling and circuit design for NoC links
Physical design of interconnect and NoC
Power, energy, and thermal issues
Quality of Service
NoCs for real-time multicore systems
Network interface issues
NoCs for FPGAs and structured ASICs
OS support for NoCs and programming models Mapping of applications onto NoCs
NoC design for 3D stacked logic and memory
Optical and RF for on-chip/in-package interconnects
NoC reliability issues
Impact of process variations on NoC power/- perfor-mance
Design methodologies and tools
Verification, debug, and test of NoCs
Modeling, simulation, and synthesis of NoCs
Metrics and benchmarks for NoCs
NoC performance analysis
NoC case studies, application-specific NoC design
Before submission authors should carefully read overthe journals Author Guidelines, which are located athttp://www.hindawi.com/journals/vlsi/guidelines/. Prospec-tive authors should submit an electronic copy of theircomplete manuscript through the journal Manuscript Track-ing System at http://mts.hindawi.com/ according to thefollowing timetable:
Manuscript Due Friday, 5 October 2012
First Round of Reviews Friday, 28 December 2012
Publication Date Friday, 22 February 2013
Lead Guest Editor
Paul Bogdan,Department of Electrical and ComputerEngineering, Carnegie Mellon University, Pittsburgh, PA,USA;[email protected]
GuestEditors
SiddharthGarg,Electrical and Computer Engineering,University of Waterloo, Waterloo, ON, Canada;[email protected]
Paul V. Gratz,Department of Electrical and ComputerEngineering, Texas A&M University, College Station, TX,USA;[email protected]
Zhonghai Lu,Department of Electronic Systems, KTHRoyal Institute of Technology, Stockholm, Sweden;[email protected]
Hindawi Publishing Corporation
http://www.hindawi.com/
http://www.hindawi.com/journals/vlsi/guidelines/http://mts.hindawi.com/mailto:[email protected]:[email protected]:[email protected]:[email protected]:[email protected]:[email protected]:[email protected]:[email protected]://mts.hindawi.com/http://www.hindawi.com/journals/vlsi/guidelines/
