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Timers in Coldfire Processor

Computer Science & Engineering DepartmentArizona State University

Tempe, AZ 85287

Dr. Yann-Hang Leeyhlee@asu.edu(480) 727-7507

set 6 -- 2

General Purpose Timer

The basic unit – counter (up or down) a clock source generate timing events (interrupts or timer output)

if overflow or reach 0 if match with a preset value

measure time – read counter values (captured) free running, reset or reload, compare

binary counter clock (external or internal)

control circuit

set 6 -- 3

Measurement

Input-capture : identify the moment that an event occurs latch the counter value when triggered CPU can read the value later

Output compare : control the timing of output bit CPU sets a value in output compare register compare with counter every clock cycle if equal, send an output signal

External event counting Measuring elapsed time, pulse width, frequency, and period

binary counter

input capture register

clockload

interrupt orready flag

event

edgedetection

set 6 -- 4

Hardware Timer

Typical approach – hardware unit generates an interrupt per unit of time (e.g.

millisecond) Avoid overflow with a software counter (in memory) –

incremented when interrupts assume the input clock of 2MHz (0.5x10-3 ms) set a compare counter to 1999 start counting with the input clock and, when equals to the

compare register interrupt restart the counter from 0

binary counter=

compare register (1999)

input clock (2MHz)

restart

interruptor toggle output

Delay Function using DMA Timer

Initialize a timer and input frequency Set up a compare value Check for flag or wait for interrupt

set 6 -- 5

DMA Timer

Control and status registers mode register:

#define MCF_DTIM3_DTMR *(vuint16*)(&__IPSBAR[0x0004C0])) extended mode register event register reference register: for comparison capture register: save counter value on capture event counter register: counting

set 6 -- 6

Fucntion cpu_pause

void cpu_pause_m(int usecs)

{

/* Enable the DMA Timer 3 */

MCF_DTIM3_DTRR = (usecs - 1);

MCF_DTIM3_DTER = MCF_DTIM_DTER_REF; // 0x02

MCF_DTIM3_DTMR = 0

| MCF_DTIM_DTMR_PS(sys_clk_khz / 1000)

| MCF_DTIM_DTMR_ORRI // 0x0010

| MCF_DTIM_DTMR_FRR // 0x0008

| MCF_DTIM_DTMR_CLK_DIV1 // 0x0002

| MCF_DTIM_DTMR_RST; // 0x0001

while ((MCF_DTIM3_DTER & MCF_DTIM_DTER_REF) == 0) {};

/* Disable the timer */

MCF_DTIM3_DTMR = 0;

}set 6 -- 7

set 6 -- 8

Pulse Width Measurement

Capture counter values on edges Read the difference to know the width

(count2-count1)/(timer frequency) If the pulse is much longer, counter may overflow

interrupts on overflows use software counter to count number of overflows.

capture count1 capture count2

set 6 -- 9

Waveform Generator

Duty cycle : (pulse duration)/(clock period) 50% -- square wave

Free-running or reset on compare event Use DMA timer to generate a square wave of 1KHz based on

an input clock is 40MHz— Pin assignment of DMA timer 0 Toggle output every 500s Mode register: CE, OM, ORPI, FRR, CLK, RST Reference register: DTRR 500s = 1/40MHz * (prescale+1) * (DTRR+1)

PWM in 5211

4 PWM outputs 8 channels

Counter (8 bits) Period/duty Even+odd channels 16 bit pwm

4 clock sources A, SA, B, SB

set 6 -- 10

PWM in 5211

InitializationMCF_GPIO_PTAPAR = 0 | MCF_GPIO_PTAPAR_PTAPAR0(3);

MCF_PWM_PWMPOL = 0 | MCF_PWM_PWMPOL_PPOL1;

MCF_PWM_PWMCLK = 0|MCF_PWM_PWMCLK_PCLK1;

MCF_PWM_PWMPRCLK = PRE_SCALE;

MCF_PWM_PWMSCLA = SCALE;

MCF_PWM_PWMPER1 = 255;

Set duty cycleMCF_PWM_PWMDTY(channel) = duty_cycle;

Enable pwm MCF_PWM_PWME = 0|MCF_PWM_PWME_PWME1

set 6 -- 11