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ELEC 3400 VI. Operational Amplifiers

HKUST 2011 Fall 6 1 Ki

1. MOS Differential Pair with Resistive Loads

A very important amplifier stage is the differential pair. It consists ofa current source (sink) biasing a pair of matched input transistors, thatis, (W/L)1 = (W/L)2, and each transistor drives a load. The inputtransistors can either be NMOS or PMOS transistors, and twoimplementations withresistive loads(R1 = R2 = R) are shown below.

Let us consider the implementation with NMOS input transistors for

discussion. The transistor Mb biased with a gate voltage Vb serves asthe current sink Ib. To bias the differential pair properly, a dc voltageis applied to both V i+ and Vi to keep M1 and M2 working in theactive region. Because this voltage is common to both input nodes, itis called thecommon mode voltageVcm.

1M

ddV

1R 2R

2M

bMbV

1M

ddV

1R 2R

iV

oV oV

iV2M

bMbV

iV iV

oVoV

xV

xV

1M

ddV

1R 2R

2M

bMbV

iV iV

oVoV

cmV

xV

bI

I I

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Since (W/L)1 = (W/L)2, by symmetry, the drain currents of M1 andM2 are equal:

Id1 = Id2 = I = Ib/2.

Both Vo+ and Vo are then equal, and the output common modevoltage Vocm is

Vo+= Vo = Vocm= Vdd IbR.

In general, all transistors should operate in the active region. Forsimplicity, let all transistors have the same gate overdrive voltage Vov.Hence, for the above equations to hold, the lowest Vcm is

Vcm = Vgs1 + Vov = Vtn + 2Vov

For Vcm+= Vdd, Vds1 = Vov when Vg1 = Vdd. Now, Vx = Vg1 Vgs1 =Vdd Vtn Vov. For M1 to remain in the active region, we require

IbR < Vdd Vov Vx = Vtn,

or R < 2Vtn/Ib.

The input common mode range is defined as the extreme inputvoltages such that all transistors in the amplifier are still operating in

the active region, and is thus Vcm to Vcm+.

Example:Given nCox=50A/V

2, Vtn=0.8V, (W/L)b=80, (W/L)1=(W/L)2=40,n=0/V. Also, Vdd=5V, Vb=1V and Vcm=2V. Find R such that theoutput swing is the largest. With this R, what is Vcm+and Vcm?

Solution:

Ib = 5080(1 0.8)2 = 80A

I = Ib/2 = 40A

With (W/L)1 + (W/L)2 = (W/L)b, we have Vov1 = Vov2 = Vovb = 0.2V.Given Vcm= 2V, we have

Vx = Vg1 Vgs1 = 2 1 = 1V.

To maximize the output swing, Vocm= 1 + (51)/2 = 3V, and

R = (Vdd Vocm)/I = 2/40 = 50k.


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With Vocm = 3V, the highest Vx to keep M1 and M2 in the activeregion is 3 0.2 = 2.8V. The corresponding Vcm+is then

Vcm+ = Vx(highest) + Vgs1 = 2.8 + 1 = 3.8V.

Also, Vcm = Vx(lowest) + Vgs1 = 0.2 + 1 = 1.2V.The input common mode range is then 1.2V to 3.8V.

2. Diff. Pair with Resistive Loads: Large Signal Analysis

Suppose Vi stays constant and Vi+ increases. Then I1 increases and I2decreases (because I1 + I2 = Ib, a constant), driving the drain of M1down and the drain of M2 up. Therefore, Vd1 is the negative output

node Vo, and Vd2 is the positive output node Vo+.

1M

ddV

1R 2R

2MiV iV

oVoV

cmV

xV

bI

1I 2I

cmV

2/vid 2/vid

For normal operation, a differential input signal vid is applied acrossVi+and Vi, such that

Vg1 = Vi+= Vcm+ 2

vid

Vg2 = Vi = Vcm2

vid

and Vi+ Vi = vid

Clearly,

Vo+ = Vdd I2R

and Vo = Vdd I1R


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The differential output signal is

Vo+ Vo = vod = (I1 I2)R.

At this point, we skip the computation details and only state the

results of I1 and I2 as follows:

I1 =2

Ib +2

Ib2

ov

id

V2

v1

ov

id

V

v

and I2 =2

Ib 2

Ib2

ov

id

V2

v1

ov

id

V

v

The differential current is

id = I1 I2 =

2

ov

id

V2

v1

ov

id

V

vIb

A typical plot is shown below.

0 5.0 20.1ovid V/v

b2,1 I/I

5.00.1

5.0

0.11I

2I

2

Observe that the transconductance of M1 and M2 is

gm1 = gm2 =tnGS

b

VV

)2/I(2

=

ov

b

V

)2/I(2

With vid

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and I2 =2

Ib gm12

vid

The differential current is thus

I1 I2 = id = gm1vid

Recall

vod = Vo+ Vo = (I1 I2)R

= gm1vidR

Adm =id

od

v

v= gm1R.

Hence, a linear amplifier is obtained. To increase the linear range ofthe input signal, Vov should be as large as possible.

3. Diff. Pair with Resistive Loads: Small Signal Analysis

The small signal model of the differential pair is shown below.

@vo: gm1(vi+ vx) +1ds

xo

r

vv +R

vo = 0 (1)

@vo+: gm1(vi vx) +1ds

xo

r

vv +R

vo = 0 (2)

@vx:R

vo +R

vo =dsb

x

r

v(3)

dsbr

)vv(g

xi

1m

R R

iv

ov ov

1dsr

)vv(g

xi

1m xv

iv

1dsr

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(1) gm1vi+=1ds

o

r||R

v +1ds1

x

r||)g/1(

v(4)

(2) gm1vi =1ds

o

r||R

v +1ds1

x

r||)g/1(

v(5)

(4) (5) gm1(vi+ vi) =1ds

oo

r||R

vv

With vid = vi+ vi and vod = vo+ vo, the differential mode gain is

Adm =id

od

v

v=

ii

oo

vv

vv= gm1(R||rds1)

(3) in (4)+(5) gm1(vi++ vi) =1dsr||R

R

dsb

x

r

v+

1ds1

x

r||)g/1(

v2(6)

Note that Vi+and Vi are applied differentially, with Vi+= Vcm + vid/2and Vi = Vcm vid/2. With vi+= vid/2 and vi = vid/2, and (6) gives

vx = 0 (7)

and vo+ = gm1(R||rds1)2

vid (8)

vo = gm1(R||rds1)

2

vid . (9)

Equation (7) means that vx can be considered as the virtual ground.As such, the differential pair with resistive load can be analyzed usingahalf circuit.

where vo = 2

vod = gm1(R||rds1)2

vid

R

2

vv idi

ov

1dsri1vg

gndvx

Adm =id

od

v

v= gm1(R||rds1)

The input and output impedance can easily be found to be:Ri =

Ro = 2(R||rds1)


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4. Differential Pair with Active Loads: Small Signal Analysis

The resistive loads can be replaced by PMOS transistors biased in theactive region. The gain will thus be enhanced. A useful structure is toreplace the resistive loads by a PMOS current mirror, and produce adifferential pair with a single-ended output. Note that Mb is relabeledas M5, and Vx as V1.

1M

ddV

oV

2MiV iV

5MbV

3M 4M

1V

2V

Principle of operation: For simplicity in symbol, vi is used instead ofvid. Now, a voltage of Vi+ = Vcm + vi is applied at the gate of M1,and a voltage of Vi = Vcm vi is applied at the gate of M2. I1 is thenlarger than Ib/2, and I2 is smaller than Ib/2. The increase in I1 issupplied by M3, which is then mirrored to M4. Therefore, at Vo, acurrent larger than Ib/2 is sourced by M4, and a current smaller thanIb/2 is sunk by M2. The excess current that appears at Vo drives Vo

high.

To analysis the gain of the differential amplifier, the small signalmodel is drawn, as shown below. Besides the gain A = vo/vi (= Adm),we also want to compute v1/vi, to verify that v1 can actually beconsidered as a virtual ground.


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2dsr1dsr

4dsr

5dsr

)vv(g

1

1m

3mg/1 24vg

)vv(g

1

2m

3dsr

1v

2v ov

Assumptions: gm1 = gm2, rds1 = rds2, gm3 = gm4, rds3 = rds4, gmirdsj >> 1v+= v = vi/2

Adm = vv

vo =i

o

v

v= gm1(rds2||rds4)

Due to the diode-connected transistor of M3, the left branch is not thesame as the right branch. With this asymmetry, the validity of usingthe half-circuit technique becomes questionable, and the small signal

analysis becomes quite tedious and not much insight can be gained inthe operation of the differential pair. However, observe that v1 =[1/(2gm1rds1)]vo is very small compared to vo. We may assume indeedv1 = 0, that is, by assuming that v1 is an ac ground. With thisassumption, the analysis is much simplified, and good approximatedresult can be obtained.

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5. Gain Analysis using Current Steering Principle

By assuming that v1 is an ac ground, a simpler way to compute the

gain of the differential pair is to use the current steering principle,which account for steering the changes in currents due to the inputs

vi+ and vi to the change in current at vo, and multiply it with the

output resistance at vo.

Let Vi+ = Vcm +2

vid

1M

ddV

ov

2M

2

vid

5MbV

3M 4M

2

vid

2

gv 1mid2gv 1mid

2

gv 1mid

Vi = Vcm 2

vid

The increase in current of M1, M3 and M4 are i/2 = vidgm1/2, while

the decrease in current of M2 is i/2 = vidgm1/2. Hence, the changein voltage at the output node is

vo = iRo = vidgm1(rds2||rds4)and

Adm =id

o

v

v= gm1(rds1||rds3).

This is the same result as obtained using the small signal model and

making appropriate approximations.


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6. Generic Two-Stage Operational Amplifiers

In ELEC 2200, we learned that an operational amplifier (op amp) has

a differential input and a single-ended output. One may suggest using

a differential pair with active loads as the op amp, but a simple

analysis would show that the output swing is very limited, as

discussed in pp. 62. Moreover, the gain of a single-stage amplifier is

not high enough. Even a gain of 500 V/V (54dB) is difficult to get. To

achieve a gain of 10,000 V/V (80dB), a two-stage design is needed.

A generic two-stage op amp is obtained by cascading a differential-

to-single-ended amplifier (1st

stage) with an inverting amplifier (2nd

stage). Depending on the load (resistive or capacitive), a third bufferstage may be added to deliver the power needed. To ensure stability, a

compensation network is needed (to be covered in ELEC 4420).

1A 2A 1

amplifierendedsingle

to-aldifferentistage1st

amplifiernvertingistage2nd

(optional)stagebuffer

oncompensati

V

VoV

For simplicity, let the buffer stage be left out. For each amplifier

stage, if the input impedance is zero and the output impedance

infinite, the gain is A = A1A2. In general, both the input and output

impedances are finite, and the gain is given by

Adm = vv

vo =

2i1o

2iRR

R

L2oL

RR

R

A1A2

The reduction in gain is known as the loading effect.

)vv(A1

1iR

1oR

2iR1o2vA

2oRv

v

ov1ov

LR


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For CMOS op amps, the input can be a pair of NMOS or PMOS

transistors. The NMOS case is shown below.

The V+ and V are referenced to the output of the whole op amp, not

the output of the differential amplifier. As an inverting amplifier is

cascaded to the differential stage, V+ is now at the gate of M2, and V

the gate of M1 (compare the connection shown in pp.6-10).

Although the output impedances of both the differential and inverting

amplifiers are finite, the input impedances are infinite, so no loading

effect occurs, and the gain is given by

Adm = vv

vo = A1A2

The compensation network with Cc and Rz is used to make the op

amp stable.

7. Transistor Sizing of 2-Stage Op Amp

Consider the 2-stage op amp with PMOS input transistors. In general,

Vtn |Vtp|, n |p|, nCoxpCox, and we define k = n/p (>1).

VV

dd

V

1M

3M 4M

5M

2M

7M

6M

zR

cC

1dsV

|V| 3gs

oV1V

bV

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The bias currents are related to the speed of the op amp, which will be

discussed in ELEC 4420. Let the bias current for the differential pairbe 2MI and that of the inverting amplifier be NI. The sizes of the

transistors are designed to have the same Vov. Therefore,

(W/L)3 = (W/L)4 = M

(W/L)1 = (W/L)2 = k(W/L)3 = kM

(W/L)5 = 2(W/L)1 = 2kM

(W/L)6 = N

(W/L)7 = k(W/L)6 = kN

If (W/L)4 : (W/L)7 M : N, then Vgs7 Vgs3, giving Vds3 Vds4, and

the two drain currents Ids3 and Ids4 will not be equal, thus causing an

offset voltage at the input, and a systematic error occurs.

Even with (W/L)4 : (W/L)7 = M : N, a systematic error still occurs,

because the output voltage Vo does not necessarily settle at Vdd/2

when vid = 0. The exact value of Vo can be computed approximately

by considering the bias current of the inverting amplifier NI:

NI =2

1 nCox7L

W

(Vgsn Vtn)

2(1 + nVdsn)

=2

1 pCox6L

W

(|Vgsp| |Vtp|)

2(1 + |pVdsp|)

ddV

1M 2M

3M 4M

5M

6M

7M

V V oV

bV

MI2 NI

MI NIMI

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With (W/L)6 = k(W/L)7 and Vgsn Vtn = |Vgsp| |Vtp| = Vov, we have,

1 + nVdsn = 1 + |pVdsp| nVo = |p|(Vdd Vo)

Vo =||

||pn

p

Vdd

The output offset voltage is thus

Vo(os) =||

||

pn

p

Vdd

2

1Vdd =

|)|(2

||

pn

np

Vdd

and the input offset voltage is

Vos =

dm

o

A

)os(V.

To finalize the exact value of L (and thus W), we may need to

consider noise issues (to be covered in ELEC 4420). A rule of thumb

for analog designs is to use 1.5 to 3 times the minimum length of the

process, for better matching accuracy, and smaller effect due to

channel length modulation. For example, if a 0.5 process is used, theminimum length is 0.5m (= 2), and we may choose L = 0.75m to1.5m.

Example: Compute the gain of the following 2-stage op amp.

V

ddV

oV

3M

1M

2M

aM b

M

bR

4M

V150 150

50

300

25

5M

6M

7M

30075

10050

A100

bI

zR

cC

LC

A50A50

25/4

cM

aR

A100

200 A 200 A

1V

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For the following computation, let

nCox = 100A/V2, pCox = 33.3A/V

2

n = |p| = = 0.05/V Vtn = |Vtp| = 0.8V

Vdd = 5V, Ra = 4k, Rb = 72kRecall in the active region, Vds > VgsVtn, and

Id =2

1 nCoxL

W(Vgs Vtn)

2(1 + nVds)

gm =

gs

d

V

I

=

tngs

d

VV

I2

doxn I

L

WC2

dsr

1

=ds

d

V

I

= Id

dsV1

rds dI

1

.

Bias Calculation

Remember when computing the DC biasing, the channel length

modulation parameters may be set to = 0/V, and it can be showneasily that

Ib = 50AVova = 400mV

Vovb = 200mV

and

5L

W

=6L

W

= 4c

W

L

Id5 = 450A = 200A

Id1 = Id2 = 200A/2 = 100A

gm1 = gm2 =d1

ov1

2I

V=

2 100

0.2

= 1m A/V

(Note that n = 3p, and all transistors are scaled according to thesame "current density" and should have the same Vov as Vovb).

rds1 = rds2 =1dI

1

=

1

0.05 100 = 200k

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DC Gain Analysis

The small signal model of the 2-stage amplifier is

Av1 =id

1

v

v

= gm1(rds2||rds4)

= 1m(200k||200k) = 100 V/V (=40dB)

Av2 =1

o

v

v= gm7(rds6||rds7)

gm6 = g m7 =d6

ov6

2I

V=

2 200

0.2

= 2m A/V

rds6 = rds7 =7dI

1

=1

0.05 200 = 100k

Av2 = 2m(100k||100k) = 100 V/V (=40dB)

Adm =id

o

v

v= Av1Av2 = 10,000 V/V (= 80dB)

The input resistance of the op amp is clearly

Rin =

and the output resistance is

Rout = rds6||rds7

id1m vg 2dsr 4dsr

1v

m6 1g v 6dsr 7dsr

ov

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8. Op Amp Circuits

8.1 Integrator

An op amp can be connected to do integration.

)t(vo)t(vi

R

C

)t(i

)t(vc

R

)t(vi = i(t) =dt

)t(dvC c

=dt

)t(dvC o

, vo(t) = dt)t(vRC

1i .

Hence, the output voltage is the integral of the input voltage. If vi(t)

is sinusoidal, i.e., vi(t) = Vicost, we may use phasor to analyze thecircuit.

oViV

R

sC

1

R

Vi =sC/1

V0 = sCVo

o

Vo =sCR

1 Vi

=CRj

1

Vi

In terms of transfer function, we write

H(s) =

)s(V

)s(V

i

o =

sCR

1

which can be expressed as

H(s) =o/s

1

=

s

o (o =CR

1)

or H(j) =o/j

1

= )90180( ooo

= oo 90

.

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The corresponding Bode plot is

H

o

|H|log20

log

log

o90

dec/dB20

The magnitude plots of o/s and o/s are the same, but the phaseplots are different.

H

log

o90H

log

o90

so

so

N.B.(1) Recall in sinusoidal analysis, d/dt corresponds to j, then

written as s, i.e., d/dt s. So "s" represents differentiation.Now, 1/s can be regarded as the inverse operation of d/dt.Hence, 1/s is integration.

(2) The action of integration can be regarded as accumulating thecharge passed through R and storing it in C.

(3) In practice, the above circuit will not work since the gain at DCis infinite. Any noise at DC will drive the circuit to saturation.For the circuit to function properly, we need to put a largeresistor R2 across C to limit the gain. A common, but

erroneous, saying is that there is no DC path to ground at v.

(4) By adding R2 across C, the integrator is turned into a first order

low pass filter.


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8.2 First Order Lowpass Filter

For the integrator with a resistor connected across the capacitor, wecan compute the corresponding transfer function.

)s(Vi)s(Vo

2R

C

1R

H(s) =)s(V

)s(V

i

o =1

sC1

2

R

||R

=2

2

1 sCR1

R

R

1

=

2ps

1

2

1

1

R

R

( p2 =

2CR

1) .

Clearly, this is a first order function, and the Bode plots are asfollows.

)(log

)(log

2p

|H|log20

H/

o90

o0

t

2p

o

180 o270

12R/R

2p1.0

2p10

t

In fact, we call it a first order lowpass function because signalbelow f2 (=p2/2) has approximately constant gain (R2/R1), while

signal at high frequencies are being attenuated. Hence, the circuitonly allows low frequency to pass through, and it is known as a 1storder lowpass filter. Also, f2 is known as the3dB bandwidth of the

circuit.


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Now, by changing the value of R2, we may adjust the DC gain of the

function. At the same time, the 3dB frequency will change. But if wemultiply the gain and the bandwidth together, we get

gain bandwidth = GBW =12

R

R

2CR

1=

1CR

1= t .

We call GBW thegain bandwidth product of the filter, and GBW isequal tot, theunity gain frequencyof the filter.

Observe that at high frequencies, especially for >>2 ,

H(s) 21

2

sCR

1

R

R =

1sCR

1 =

st

.

Hence, at high frequencies, the circuit functions as an integrator.

Next, refer to the transfer function of an integrator H'(s):

H'(s) =st

.

Since, H'(s) is the ratio of output over input, the correspondingmagnitude |H'(j)| can be regarded as the gain of the circuit at thefrequency (or f =/2), and we have

|H(j)| = t .or gain freq. = unity gain freq.

Hence, on the 20dB/dec line (the magnitude plot of an integrator),the product of the gain and the frequency is always a constant. Whenthe gain is unity, the corresponding frequencyt (or ft =t/2) is the

unity gain frequency. For the 1st order lowpass filter, the slopingportion is 20dB/dec, and so similar terminology is used.

)(log

s'pdifferent2

|H|log20

t

s'Rdifferent 2

1sCR1)s('H

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8.3 Differentiator

Rearrange the position of R and Cof an integrator turns the circuitinto a differentiator:

i(t) =R

)t(v0 o =dt

)t(dvC c =

dt

)t(dvC i

, vo(t) =dt

)t(dvRC i .

If sinusoidal steady state is considered, then we should use phasor:I =

R

0 oV =)Cj/(1

iV

, Vo = jRC Vi .

In terms of transfer function, we have

H(s) =)s(V

)s(V

i

o = sRC =1p

s (p1 =

RC

1) .

The Bode plots are shown below.

The gain of this differentiator at high frequency has to be limited toavoid noise problem, and a small capacitor should be added as shown.

)t(vi )t(vo

R

C

cv

)t(i

1p1p1.0 1p10

dB20dB40

|H|log20

1p1p1.0 1p10o90

H/

)t(vi)t(vo

R1C

2C

12 CC

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8.4 First Order Highpass Filter

The transfer function and Bode plots of a 1st order highpass filter are:

)s(Vi)s(Vo

R1C

2C

)(log

)(log

RC1

1

|H|log20

H/

o

90

o0

RC1

2

21C/C

o180

RC10

2RC1.0

2

H(s) = )s(V

)s(V

io = RsC1

RsC

21

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