INV

EN

TIV

E

CONFIDENTIAL

65nm Design Issues

Y2010

Large scale, complex chip design

• Previous large scale, complex chips• Chip:1M instances, 500 pins, 20 Macros

• 90nm process technology• 3 libraries and corners, 1 rc corner=3 runs

• New large scale, complex chips• Chip: 5à 20 blocks per chip

• Blocks: 1M-5M instances,1000 pins, 100 macros• 65nm, 45nm, 32nm process technology• 3-5 libraries and 5-10 RC corners = 15-50 runs+

Design Closure

•What it means for designers

• 20+ floor plans for feasibility study

• Excessive runtimes due to big data

• More complex hierarchical designs

• Multi-dimensional timing closure

Process Variation

• Transistor & interconnect dimensions are shrinking rapidly

• Process control for small geometries is difficult

• Encounter Statistical STA (SSTA)

– Accounts for variability of process parameters (∆L, ∆W, ∆Tox, etc.)

– Eliminates need for multi-corner analysis & aggressive guard-band

40 45 50 60 65 70 75 80µ+3σ Arrival

Time

Probability

Worst Case

Best Case

Encounter SSTA removes excess

guard-band

Process A

Lmean = 1 µm

Lσ

= 0.01 µm

Delta-L of

nominal = 1%

Process B

Lmean = 65 nm

Lσ

= 0.01 µm

Delta-L of

nominal = >15%Even if variability is constant between process generations, the net-effect gets worse

Impact of IR Drop on Noise

– Noise glitch without IR drop – No issue

– IR drop on supply

– Combined effect – Now the glitch might propagate.

– The combined effects can result in increased delays and nonfunctional circuitry due to weakened drivers and glitches crossing the logic switching threshold.

Vdd

Gnd

Logic switching threshold

Vdd

Gnd

Logic switching threshold

Vdd

Gnd

Logic switching threshold

Low-None-Low-None-n/a-None-SmallArea optimization

High

High

High

-None-

-None-

Architecture

Methodology Impact

High

High

Medium

Low

Low

Design

High

High

Medium

Low

-None-

Verification

High

High

High

Medium

Low

Implementation

SomeSomeLargeDynamic & Adaptive Voltage Frequency

Scaling (DVFS)

SomeSomeLargePower shut-off (PSO)

LittleSomeLargeMulti-supply voltage

(MSV)

LittleLittleMediumClock gating

LittleLittleMediumMulti-Vt optimization

Areapenalty

Timingpenalty

Power Savings

Power reductiontechnique

Power Tradeoffs with Traditional Methodologies

High

High

High

Medium

Low

None

None

Verification

impact

High

High

Medium-high

Medium

Low

Low

None

Methodology

impact

Medium

High

High

Low

None

None

None

Simulation

impact

<10%10%-10XSubstrate Biasing

<10%0%40-70%2-3XDynamic and Adaptive

Voltage Frequency Scaling (DVFS and AVS)

5-15%4-8%~0%10-50XPower shut-off (PSO)

<10%0%40-50%2XMulti-supply voltage (MSV)

-10%to 2%

0%20%0XClock gating

2%0%0%6XMulti-Vt optimization

-10%0%10%1.1XArea optimization

Area

penalty

Timing

penalty

Dynamic

power

Leakage

powerPower reduction

technique

Too Many Choices for Power Reduction, Too Hard to Decide

Source – Customer interviews, Conference papers (ISSCC), magazine articles

Encounter Low Power

Flow

Low Power Made Easy!

Basic

Advance

d

Low Power Techniques Used In Today’s SoC

Gated clock

41%

Multi Supply

Voltage

9%

Multi VT

20%

Operand

Isolation

4%

Substrate

Biasing

1%Voltage &

frequency

scaling

5%

Undecided

3%

Power Shut Off

(Power Gating)

17%

Source: 2007 Low Power workshop attendees survey

0 5 10 15 20 25 30

>250nm

180nm

130nm

90nm

65nm

45nm

Number of respondents

Next design

Current design

Last design

Current design-based solutions are fragmented

Verification

FormalAnalysis

Acceleration & Emulation

Simulation

Veri

ficati

on

Co

vera

ge

Testb

en

ch

Au

tom

ati

on

Design Creation

Synthesis

ConstraintGeneration

Design for Test

SVP

Eq

uiv

ale

nce C

heckin

g

Co

nstra

int V

alid

atio

n

SpecificationFunction, timing, power

RTL Coding

IterateIterate

Physical Implementation

Chip IntegrationPrototyping

Physical Synthesis

Routing

DF

T An

aly

sis

Sign-off

AT

PG

Co

nstra

int V

alid

atio

n

LE

C/C

LP

LV

S/D

RC

/Ext

GDSII

Constraints Netlist

How do you verify power functionality

without changing RTL??

MSVSRPGPSO

DVFS

Command file•Domains

•Level shifters

•Isolation

•SRPG

Command file•Domains

•Level shifters

•Isolation

•SRPG

Command file•Domains

•Level shifters

•Isolation

•SRPG

Command file•Domains

Command file•Domains

•Modes for ATPG

Command file•Domains

•Level shifters

•Isolation

•SRPG

Command file•Domains

•Level shifters

•Isolation

•SRPG

Which one of these is “golden”?

Did we really build the chip that the

design team wanted?

MultiSupply VoltageState Retention Power GatesPower ShutOffDynamic Voltage Frequency Scaling

Manufacturability challenges

0.25µ 0.18µ

0.13µ 90nm 65nm

Layout

Layout Silicon Image

Decreasing feature size

• 193nm wavelength of light for 65nm structures Layout ≠ printed

– Bridging, necking, line

end shortening

• Multiple objects contributes to the

lithography effects

Advanced node design

Encounter Digital Implementation SystemRefining and redefining digital implementation

•10-15% smaller die-size area

•New foundation memory architecture

•Up to 60% power reduction

•Automated advanced design flows

Large scale chip design closureDie-size exploration, Floorplan synthesis and ranking

Hierarchy, ART, MMMC, Flip-Chip/RDL, SDP, Multi-CPU

Low power design MVth, MSV, multi-domain, low power clocking,DVFS,

power shut-off, biasing power diagnostics, CPF flow

Advanced node design45/32nm, DFM/DFY, litho aware implementation, SSTA,

CMP, thermal analysis, model-based design and verification

Mixed signal design A/d, D/a, A/D, MS interoperability, MS constraint

generation and management, data exchange integrity

Sig

no

ff an

aly

sis

Tim

ing

, SI, p

ow

er, E

M, T

herm

al, E

RA

/pw

rg

rid,

CP

E, S

pic

e, d

eb

ug

, sta

tic, d

yn

am

ic, s

tatis

tical

•End-to-end multi-core backplane

•Flexible, extensible design system

•Complete native MMMC flow

•Silicon accurate QoS (var/dfm/signoff)

Low-None-Low-None-n/a-None-SmallArea optimization

High

High

High

-None-

-None-

Architecture

Methodology Impact

High

High

Medium

Low

Low

Design

High

High

Medium

Low

-None-

Verification

High

High

High

Medium

Low

Implementation

SomeSomeLargeDynamic & Adaptive Voltage Frequency

Scaling

SomeSomeHugePower shut-off

LittleSomeLargeMulti-supply voltage

LittleLittleMediumClock gating

LittleLittleMediumMulti-Vt optimization

Areapenalty

Timingpenalty

Power Savings

Power reductiontechnique

Power Tradeoffs with A CPF-Based Methodology

Medium

Medium

Medium

Medium

Medium

Low

Medium

Medium

Medium

Medium

MediumLow

Cadence Low Power Solution

A Common Power Format Communicates the Power Intent Throughout the Flow

• Common Power Format (CPF) = Single specification of power intent used throughout design, verification, and implementation

• ASCII file that captures:

• Power design intent

–Power domain

• Logical: hierarchical modules as

domain members

• Physical: power/ground nets and

connectivity

• Analysis view: timing library sets for

power domains

–Power logic

• Level shifter logic

• Isolation logic

• State-retention logic

• Switch logic & control signals

–Power modes

• Definitions

• Transition expressions

• Modal analysis

–Technology information

• Level shifter cells

• Isolation cells

• State-retention cells

• Switch cells

• Always-on cells

Po

wer Im

ple

men

tatio

n

Larg

e-S

cale

Desig

ns

Man

ufa

ctu

ring

Mix

ed-S

ignal

GDSII

Cadence Digital Implementation

Solution

Power Implementation Power Implementation part of back-end user-segment flow

Design Logical Signoff

Desig

n w

ith

Verific

atio

n

Desig

n w

ith

Po

wer

Desig

n w

ith

Te

st

Desig

n w

ith

Ph

ysic

al

Design Management Cadence Logic Design Team

Solution

Design with PowerDesign with Power part of front-end user-segment flow

The Only Complete Low-Power Solution

Cadence

Low Power

Solution

Complete low power flow

Low Power Methodology Kit

Streamlining low power adoption

The CPF-Enabled Cadence Low Power solution The Only Holistic Solution in the Market Today!

including PSO patternsRTL

Testbench

MSMV, PSO,SRPG, MMMC,DVFS,AON,

gate(1)

gate(2)

LE

C &

CL

P C

hecks

CPF

CPF Quality Checker

Logic Simulation

Implementationgate(3)

Timing/ SI Sign-Off

Plan & Metrics

RTL Simulation

l CPF consistency, functional & structural checks using CLP

l Functional validation of virtual LP behavior: PSO, retention, isolation

l Auto generation of power mode coverage, and iso, retention, level shifter control signal coverage

l PSO-aware formal assertion verification

l Power domain/mode aware P&R, w/o dont_touchl Power switch, LS, clamp insertion/optimizationl MMMC/DVFS support

l Power domain/mode aware delay calc, including MMMC/DVFS

l Power domain/mode aware IR drop analysis (static and dynamic)

l Power-up analysis of power switches and impact on neighbors

l Power domain/mode aware synthesis & power analysisl Auto insertion, mapping & opto of iso, LS, SRPGl Multi-Mode synthesis

l Power domain aware test synthesis, insertion of iso/LS on DFT nets

l Auto mapping of power modes to test modesl Fault model/coverage of LP structures incl. SRPG

Formal

ABV

IR drop/power Sign-Off

Design for Test

Synthesis + Pwr Est.

original fixed xor

NanoRoute litho hotspot prevention

• Local area litho prevention/optimization

• No impact to timing and die size and no new hotspots

Necking

Line end

Advanced node design

65nm node– 1st iteration: >90% hot spots

eliminated

– 2nd iteration: 100% hot spots eliminated

45nm node– 1st iteration: >85% hot spots

eliminated

– 2nd iteration: >94% hot spots eliminated

NanoRoute litho-driven routingPatent pending

Machine used: Linux 2 2.19GHz CPU. 16G memory.

0

50

100

150

200

250

300

350

400

450

65nm 45nmTech node

Hotspots @ +/-20nm defocus and +/-5% dose

Original After 1st iteration After 2nd iteration

0

50

100

150

200

250

300

350

400

450

65nm 45nm

Original After NR prevention After LPA HIF fix

Hotspots @ +/-20nm defocus and +/-5% dose

Advanced node design

• Full chip prototyping

• Design exploration

• Floorplan synthesis

• Die size reduction

• Full flow MMMC

• Variation and DFM aware

• Post-mask ECO flow

• Flip-Chip/RDL design

• Active logic Reduction

Technique (ART)

• New foundational

memory architecture

• Multi-CPU backplane

• In-system signoff

• Early rail analysis

• SMART routing

• Multi-objective opt

Enabling the largest, most complex designs

Planning/Prototype

Complexity

QoS closure

Scalability

X

Better quality of silicon

Faster time to market

Design Closure

Large scale chip design solution

Bus routing guides

• Bus guides are floorplan objects to guide routing/pins for selected nets

• Specify layer or layer range

– Routing outside bus guides has higher cost

– Warning issued if routing is outside bus guides

Using guidesNo bus guides Using guidesNo bus guides

Design Closure

Global debug and diagnostics

• Integrated and complete diagnostics

• Intuitive, easy to use, graphical/visual/report based

Global Timing Debug• Available since 2006

• Failed path/constraint

checking and optimization

• Detailed path analysis

• Cross-probing with physs

•MMMC analysis/debug

Global Clock Debug

• Visually check/debug clock

•Instance and path finding

• Cross-probing physical/log

•Expand/collapse clks for

hierarchical viewing

Global Power Debug

•Complete power debug

• Diagnose top consuming

nets, consumption by hier,

domain, instance, clks…

•What-if analysis and opt

•Uses signoff engines

Design Closure

Package aware IO planning and flip-chip

• Multiple I/O methodology support

– Area or peripheral I/O

• Concurrent opt of I/O and core

• Congestion analysis/ route feasibility and “what-if” analysis

• Automatic RDL and 45º routing

• >40 customer tapeouts

Design Closure

Incisive Enterprise Manager for verification engineers

ExecutablevPlan

Verificationgoals

Xtreme®

Palladium

Incisive Formal Verifier (IFV)

Failure data and total coverage

Sessionspecification

Deployjobs

Verificationjobs

Incisive Enterprise Manager

TotalCoverage:• Functional• Code• Assertions• Power

Automatedanalysis

Incisive Simulation

Low Power Checks

Conformal Low Power VerifyStructural, Rule, and Functional Checks – CPF Enabled

Level shifters

– Placement

– Location

– Connectivity

Isolation cells

– Placement

– Isolation type

– Isolation function

State retention cells

– Placement

– Retention function

Miscellaneous

– Floating nets / pins

– Control Polarity

RTL/Logical Netlist

Level shifters

– Placement/Location

– Power connectivity

Isolation cells

– Placement/type

– Power connectivity

– Isolation function

State retention cells

– Placement

– Power connectivity

– Retention function

Power and Ground Switch

– Power/Ground

Connectivity

– Enable Control Polarity

Miscellaneous

– Shorts b/n VDD/VSS

– Always-on buffers

Physical Netlist

Functional simulation

Logic Synthesis & DFT

Low Power Checks

CPF Quality Check

Gate netlist

Transistor net.

Logic simulation

LEF.

Physical implementation

Low Power Checks

Physical netlist

– Transistor Stacking

– Un-buffered Input

– Macro Power Associations

Transistor Netlist

RTL

CPF

Дизайн-центр Помещение РазработчикиОборудование

Cadence VCAD

Среда проектирования иподдержка

Cadence VCAD

Ведение проекта

Cadence VCAD: преимущества сервисных услуг

∆ ∆ ∆ ∆ tdesign

env. Setup

Время

Цель

Self-builtCapabilities

Integrated TeamCapabilities

Результат

НастройкаСреды

проектирования

∆ ∆ ∆ ∆ tFirst Product

- Экономия времени- Оптимизация затрат

- Снижение рисков

Обширный набор сервисных услуг

Проверенные

маршруты и

методологии

проектирования

Профессиональные услуги вобласти разработки и IP

Проектированиеза 1 проход

Cadence, VCAD service.

• VCAD 65nm experience:• Short design info:

• - 65nm technology

• - main clock frequency 438MHz (worst corner)

• - ~16M placeable instances

• - 12 metal layers

• - flip-chip design w/ 4440 bumps, die size 14.9x14.9mm2

• - 6 partitions (3 partitions with master and one clone, 1 partition with master and three clones)

• - few hundred of RAMs, few analog IPs

Major challenges for 65nm compare to 90nm:

1. Timing analysis: need to make more timing and RC corner analysis for Setup and especially for Hold.

2. Litho-Analysis and CMP-analysis – should be done, at least once for 65nm. VCAD offer is to run these checks on our side, just to make sure that everything is fine.

3. Power should be considered: Power-aware Timing/SI (skew/jitter/setup/hold) including Chip-package effects.

4. Low Power aspects should be simulated in analog simulator.

5. Very high-speed design below 90nm should go through dynamical power analysis, using correct and robust VCD/activity file.

Questions?