64K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS ...DECEMBER 2012 A0-A15 CS1 OE WE 64K x 16 DECODER MEMORY...

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Integrated Silicon Solution, Inc. — www.issi.com 1 Rev. B 12/18/12 IS62WV6416DALL/DBLL IS65WV6416DALL/DBLL 64K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM FEATURES High-speed access time: 35ns, 45ns, 55ns CMOS low power operation: 15 mW (typical) operating 1.5 µW (typical) CMOS standby TTL compatible interface levels Single power supply 1.65V--2.2V VDD (62WV6416DALL) 2.3V--3.6V VDD (65WV6416DBLL) Fully static operation: no clock or refresh required Three state outputs Data control for upper and lower bytes Industrial and automotive temperature support 2CS Option Available Lead-free available DESCRIPTION The ISSI IS62/65WV6416DALL and IS62/65WV6416DBLL are high-speed, 1M bit static RAMs organized as 64K words by 16 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high- performance and low power consumption devices. When CS1 is HIGH (deselected) or when CS2 is LOW (deselected) or when CS1 is LOW, CS2 is HIGH and both LB and UB are HIGH, the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IS62/65WV6416DALL and IS62/65WV6416DBLL are packaged in the JEDEC standard 48-pin mini BGA (6mm x 8mm) and 44-Pin TSOP (TYPE II). FUNCTIONAL BLOCK DIAGRAM DECEMBER 2012 A0-A15 CS1 OE WE 64K x 16 MEMORY ARRAY DECODER COLUMN I/O CONTROL CIRCUIT GND VDD I/O DATA CIRCUIT I/O0-I/O7 Lower Byte I/O8-I/O15 Upper Byte UB LB CS2

Transcript of 64K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS ...DECEMBER 2012 A0-A15 CS1 OE WE 64K x 16 DECODER MEMORY...

Page 1: 64K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS ...DECEMBER 2012 A0-A15 CS1 OE WE 64K x 16 DECODER MEMORY ARRAY COLUMN I/O CONTROL CIRCUIT GND VDD I/O DATA CIRCUIT I/O0-I/O7 Lower Byte

Integrated Silicon Solution, Inc. — www.issi.com 1Rev. B12/18/12

IS62WV6416DALL/DBLLIS65WV6416DALL/DBLL

64K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM

FEATURES

• High-speedaccesstime:35ns,45ns,55ns

• CMOSlowpoweroperation:

15mW(typical)operating

1.5µW(typical)CMOSstandby

• TTLcompatibleinterfacelevels

• Singlepowersupply

1.65V--2.2VVdd (62WV6416dALL)

2.3V--3.6VVdd (65WV6416dBLL)

• Fullystaticoperation:noclockorrefresh required

• Threestateoutputs

• Datacontrolforupperandlowerbytes

• Industrialandautomotivetemperaturesupport

• 2CSOptionAvailable

• Lead-freeavailable

DESCRIPTION

TheISSIIS62/65WV6416DALLandIS62/65WV6416DBLLarehigh-speed,1MbitstaticRAMsorganizedas64Kwordsby16bits.ItisfabricatedusingISSI'shigh-performanceCMOStechnology.Thishighly reliableprocesscoupledwith innovative circuit design techniques, yields high-performanceandlowpowerconsumptiondevices.

WhenCS1 isHIGH(deselected)orwhenCS2 isLOW (deselected)orwhen CS1isLOW,CS2isHIGHandbothLBandUBareHIGH,thedeviceassumesastandbymodeatwhichthepowerdissipationcanbereduceddownwithCMOSinputlevels.

EasymemoryexpansionisprovidedbyusingChipEnableandOutputEnableinputs.TheactiveLOWWriteEnable(WE)controlsbothwritingandreadingofthememory.AdatabyteallowsUpperByte(UB)andLowerByte(LB)access.

TheIS62/65WV6416DALLandIS62/65WV6416DBLLarepackagedintheJEDECstandard48-pinminiBGA(6mmx8mm)and44-PinTSOP(TYPEII).

FUNCTIONAL BLOCK DIAGRAM

DECEMBER 2012

A0-A15

CS1OEWE

64K x 16MEMORY ARRAYDECODER

COLUMN I/O

CONTROLCIRCUIT

GND

VDD

I/ODATA

CIRCUIT

I/O0-I/O7Lower Byte

I/O8-I/O15Upper Byte

UBLB

CS2

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2 Integrated Silicon Solution, Inc. — www.issi.com Rev. B

12/18/12

IS62WV6416DALL/DBLLIS65WV6416DALL/DBLL

PIN CONFIGURATIONS

48-Pin mini BGA (6mm x 8mm)(Package Code B)

PIN DESCRIPTIONSA0-A15 AddressInputs

I/O0-I/O15 DataInputs/Outputs

CS1,CS2 ChipEnableInput

OE OutputEnableInput

WE WriteEnableInput

LB Lower-byteControl(I/O0-I/O7)

UB Upper-byteControl(I/O8-I/O15)

NC NoConnection

Vdd Power

GND Ground

48-Pin mini BGA (6mm x 8mm)2 CS Option (Package Code B2)

44-Pin mini TSOP (Type II)(Package Code T)

1 2 3 4 5 6

A

B

C

D

E

F

G

H

LB OE A0 A1 A2 CS2

I/O8 UB A3 A4 CS1 I/O0

I/O9 I/O10 A5 A6 I/O1 I/O2

GND I/O11 NC A7 I/O3 VDD

VDD I/O12 NC NC I/O4 GND

I/O14 I/O13 A14 A15 I/O5 I/O6

I/O15 NC A12 A13 WE I/O7

NC A8 A9 A10 A11 NC

1 2 3 4 5 6

A

B

C

D

E

F

G

H

LB OE A0 A1 A2 NC

I/O8 UB A3 A4 CSI I/O0

I/O9 I/O10 A5 A6 I/O1 I/O2

GND I/O11 NC A7 I/O3 VDD

VDD I/O12 NC NC I/O4 GND

I/O14 I/O13 A14 A15 I/O5 I/O6

I/O15 NC A12 A13 WE I/O7

NC A8 A9 A10 A11 NC

12345678910111213141516171819202122

44434241403938373635343332313029282726252423

A4A3A2A1A0CS1I/O0I/O1I/O2I/O3VDD

GNDI/O4I/O5I/O6I/O7WEA15A14A13A12NC

A5A6A7OEUBLBI/O15I/O14I/O13I/O12GNDVDD

I/O11I/O10I/O9I/O8NCA8A9A10A11NC

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Integrated Silicon Solution, Inc. — www.issi.com 3Rev. B12/18/12

IS62WV6416DALL/DBLLIS65WV6416DALL/DBLL

ABSOLUTE MAXIMUM RATINGS(1)

Symbol Parameter Value Unit Vterm TerminalVoltagewithRespecttoGND –0.5toVdd+0.5 V Vdd VddRelatestoGND –0.3to4.0 V tstg StorageTemperature –65to+150 °C Pt PowerDissipation 1.0 WNotes:1.StressgreaterthanthoselistedunderABSOLUTEMAXIMUMRATINGSmaycausepermanentdamageto

thedevice.Thisisastressratingonlyandfunctionaloperationofthedeviceattheseoranyotherconditionsabovethoseindicatedintheoperationalsectionsofthisspecificationisnotimplied.Exposuretoabsolutemaximumratingconditionsforextendedperiodsmayaffectreliability.

CAPACITANCE(1,2)

Symbol Parameter Conditions Max. Unit

Cin InputCapacitance Vin = 0V 6 pF

Ci/O Input/OutputCapacitance VOut = 0V 8 pFNotes:1.Testedinitiallyandafteranydesignorprocesschangesthatmayaffecttheseparameters.2. Testconditions:TA = 25°C, f=1MHz,Vdd=3.3V.

TRUTH TABLE

I/O PIN Mode WE CS1 CS2 OE LB UB I/O0-I/O7 I/O8-I/O15 VDD Current

NotSelected X H X X X X High-Z High-Z isB1, isB2

X X L X X X High-Z High-Z isB1, isB2

X X X X H H High-Z High-Z isB1, isB2

OutputDisabled H L H H L X High-Z High-Z iCC H L H H X L High-Z High-Z iCC

Read H L H L L H dOut High-Z iCC H L H L H L High-Z dOut H L H L L L dOut dOut

Write L L H X L H din High-Z iCC L L H X H L High-Z din L L H X L L din din

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4 Integrated Silicon Solution, Inc. — www.issi.com Rev. B

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IS62WV6416DALL/DBLLIS65WV6416DALL/DBLL

AC TEST LOADS

Figure 1.

R1

5 pFIncluding

jig andscope

R2

OUTPUT

VTM

Figure 2.

AC TEST CONDITIONS Parameter Unit Unit Unit (2.3V-3.6V) (3.3V + 5%) (1.65V-2.2V)

InputPulseLevel 0.4VtoVdd-0.3V 0.4VtoVdd-0.3V 0.4VtoVdd-0.3V

InputRiseandFallTimes 1V/ns 1V/ns 1V/ns

InputandOutputTiming VDD/2 VDD+0.05 0.9V andReferenceLevel(VRef)2

OutputLoad SeeFigures1and2 SeeFigures1and2 SeeFigures1and2

R1( Ω ) 317 317 13500

R2( Ω ) 351 351 10800

Vtm(V) 3.3V 3.3V 1.8V

R1

30 pFIncluding

jig andscope

R2

OUTPUT

VTM

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Integrated Silicon Solution, Inc. — www.issi.com 5Rev. B12/18/12

IS62WV6416DALL/DBLLIS65WV6416DALL/DBLL

DC ELECTRICAL CHARACTERISTICS (OverOperatingRange)

VDD = 2.3V-3.6V

Symbol Parameter Test Conditions Min. Max. Unit

VOH OutputHIGHVoltage Vdd = Min.,iOH = –1.0mA 1.8 — V

VOL OutputLOWVoltage Vdd = Min.,iOL = 2.1mA — 0.4 V

ViH InputHIGHVoltage 2.0 Vdd + 0.3 V

ViL InputLOWVoltage(1) –0.3 0.8 V

iLi InputLeakage GND≤ Vin ≤ Vdd –1 1 µA

iLO OutputLeakage GND≤ VOut ≤ Vdd, OutputsDisabled –1 1 µANote:1. ViL (min.)= –0.3VDC;ViL(min.)=–2.0VAC(pulsewidth<10ns).Not100%tested. ViH (max.)= Vdd + 0.3V dC;ViH (max.)= Vdd + 2.0V AC(pulsewidth<10ns).Not100%tested.

DC ELECTRICAL CHARACTERISTICS (OverOperatingRange)

VDD = 3.3V + 5% Symbol Parameter Test Conditions Min. Max. Unit VOH OutputHIGHVoltage Vdd = Min.,iOH = –1mA 2.4 — V VOL OutputLOWVoltage Vdd = Min.,iOL = 2.1mA — 0.4 V ViH InputHIGHVoltage 2 Vdd + 0.3 V ViL InputLOWVoltage(1) –0.3 0.8 V iLi InputLeakage GND≤ Vin ≤ Vdd –1 1 µA iLO OutputLeakage GND≤ VOut ≤ Vdd, OutputsDisabled –1 1 µA

Note:1. ViL (min.)= –0.3VDC;ViL(min.)=–2.0VAC(pulsewidth<10ns).Not100%tested. ViH (max.)= Vdd + 0.3V dC;ViH (max.)= Vdd + 2.0V AC(pulsewidth<10ns).Not100%tested.

DC ELECTRICAL CHARACTERISTICS (OverOperatingRange)

VDD = 1.65V-2.2V

Symbol Parameter Test Conditions VDD Min. Max. Unit

VOH OutputHIGHVoltage iOH = -0.1mA 1.65-2.2V 1.4 — V

VOL OutputLOWVoltage iOL = 0.1mA 1.65-2.2V — 0.2 V

ViH InputHIGHVoltage 1.65-2.2V 1.4 Vdd + 0.2 V

ViL(1) InputLOWVoltage 1.65-2.2V –0.2 0.4 V

iLi InputLeakage GND≤ Vin ≤ Vdd –1 1 µA

iLO OutputLeakage GND≤ VOut ≤ Vdd, OutputsDisabled –1 1 µANote:1. ViL (min.)= –0.3VDC;ViL(min.)=–2.0VAC(pulsewidth<10ns).Not100%tested. ViH (max.)= Vdd + 0.3V dC;ViH (max.)= Vdd + 2.0V AC(pulsewidth<10ns).Not100%tested.

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IS62WV6416DALL/DBLLIS65WV6416DALL/DBLL

POWER SUPPLY CHARACTERISTICS(1) (OverOperatingRange)

-35 -45 -55 Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Unit

iCC VddDynamicOperating Vdd = Max., Com. — 8 — 6 — 5 mA SupplyCurrent iOut = 0 mA,f=fmAX Ind. — 12 — 8 — 7 CE = ViL Auto. — 15 — 12 — 12 Vin ≥ Vdd – 0.3V, or typ.(2) 5 Vin ≤ 0.4V

iCC1 Operating Vdd = Max., Com. — 2.5 — 2.5 — 2.5 mA SupplyCurrent iOut = 0 mA,f=0 Ind. — 2.5 — 2.5 — 2.5 CE = ViL Auto. — 5 — 5 — 5 Vin ≥ Vdd – 0.3V, or Vin ≤ 0.4V

isB2 CMOSStandby Vdd = Max., Com. — 2 — 2 — 2 µA Current(CMOSInputs) CS1 ≥ Vdd – 0.2V, Ind. — 4 — 4 — 4 CS2≤0.2V, Auto — 18 — 18 — 18 Vin ≥ Vdd – 0.2V, or typ.(2) 0.6 Vin ≤ 0.2V, f=0

OR

ULBControl Vdd=Max.,CS1=ViL, Cs2=ViH

Vin ≤0.2V,f=0;UB / LB=Vdd–0.2V

Note:1.Atf=fmAX,addressanddatainputsarecyclingatthemaximumfrequency,f=0meansnoinputlineschange.2.TypicalvaluesaremeasuredatVdd=3.0V,TA=25oCandnot100%tested.

OPERATING RANGE (VDD) Range Ambient Temperature VDD (45 nS) VDD (35 nS) Commercial 0°Cto+70°C 2.3V-3.6V 3.3V+5% Industrial –40°Cto+85°C 2.3V-3.6V 3.3V+5%

OPERATING RANGE (VDD) Range Ambient Temperature VDD Speed Commercial 0°Cto+70°C 1.65V-2.2V 45ns Industrial –40°Cto+85°C 1.65V-2.2V 55ns Automotive –40°Cto+125°C 1.65V-2.2V 55ns

OPERATING RANGE (VDD) Range Ambient Temperature VDD (45 nS) Automotive –40°Cto+125°C 2.3V-3.6V

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Integrated Silicon Solution, Inc. — www.issi.com 7Rev. B12/18/12

IS62WV6416DALL/DBLLIS65WV6416DALL/DBLL

READ CYCLE SWITCHING CHARACTERISTICS(1) (OverOperatingRange)

35 ns 45 ns 55 ns Symbol Parameter Min. Max. Min. Max. Min. Max. Unit

trC ReadCycleTime 35 — 45 — 55 — ns

tAA AddressAccessTime — 35 — 45 — 55 ns

tOHA OutputHoldTime 10 — 10 — 10 — ns

tACs1/tACs2 CS1/CS2AccessTime — 35 — 45 — 55 ns

tdOe OEAccessTime — 10 — 20 — 25 ns

tHzOe(2) OEtoHigh-ZOutput 0 10 0 15 0 20 ns

tLzOe(2) OEtoLow-ZOutput 3 — 5 — 5 — ns

tHzCs1/tHzCs2(2) CS1/CS2toHigh-ZOutput 0 10 0 15 0 20 ns

tLzCs1/tLzCs2(2) CS1/CS2toLow-ZOutput 5 — 5 — 10 — ns

tBA LB,UBAccessTime — 35 — 45 — 55 ns

tHzB LB,UBtoHigh-ZOutput 0 15 0 15 0 20 ns

tLzB LB,UBtoLow-ZOutput 0 — 0 — 0 — ns

Notes: 1. Testconditionsassumesignaltransitiontimesof5nsorless,timingreferencelevelsof0.9V/1.5V,inputpulselevelsof0.4to

Vdd-0.2V/Vdd-0.3VandoutputloadingspecifiedinFigure1.2. TestedwiththeloadinFigure2.Transitionismeasured±500mVfromsteady-statevoltage.Not100%tested.

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8 Integrated Silicon Solution, Inc. — www.issi.com Rev. B

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IS62WV6416DALL/DBLLIS65WV6416DALL/DBLL

DATA VALIDPREVIOUS DATA VALID

tAA

tOHAtOHA

tRC

DOUT

ADDRESS

AC WAVEFORMS

READ CYCLE NO. 1(1,2) (AddressControlled)(CS1=OE=ViL, Cs2=WE=ViH, UB orLB = ViL)

tRC

tOHAtAA

tDOE

tLZOE

tACE1/tACE2

tLZCE1/tLZCE2

tHZOE

HIGH-ZDATA VALID

tHZCS1/tHZCS2

ADDRESS

OE

CS1

CS2

DOUT

LB, UB

tHZBtBAtLZB

AC WAVEFORMS

READ CYCLE NO. 2(1,3) (CS1, CS2, OE,ANDUB/LB Controlled)

Notes: 1. WEisHIGHforaReadCycle.2. Thedeviceiscontinuouslyselected.OE,CS1,UB,orLB=ViL. Cs2=WE=ViH.3. AddressisvalidpriortoorcoincidentwithCS1LOWtransition.

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Integrated Silicon Solution, Inc. — www.issi.com 9Rev. B12/18/12

IS62WV6416DALL/DBLLIS65WV6416DALL/DBLL

WRITE CYCLE SWITCHING CHARACTERISTICS(1,2)(OverOperatingRange)

35 ns 45 ns 55 ns Symbol Parameter Min. Max. Min. Max. Min. Max. Unit tWC WriteCycleTime 45 — 45 — 55 — ns

tsCs1/tsCs2 CS1/CS2toWriteEnd 35 — 35 — 45 — ns

tAW AddressSetupTimetoWriteEnd 35 — 35 — 45 — ns

tHA AddressHoldfromWriteEnd 0 — 0 — 0 — ns

tsA AddressSetupTime 0 — 0 — 0 — ns

tPWB LB,UBValidtoEndofWrite 35 — 35 — 45 — ns

tPWe WEPulseWidth 35 — 35 — 40 — ns

tsd DataSetuptoWriteEnd 20 — 20 — 25 — ns

tHd DataHoldfromWriteEnd 0 — 0 — 0 — ns

tHzWe(3) WELOWtoHigh-ZOutput — 20 — 20 — 20 ns

tLzWe(3) WEHIGHtoLow-ZOutput 5 — 5 — 5 — ns

Notes:

1. Testconditionsassumesignaltransitiontimesof5nsorless,timingreferencelevelsof0.9V/1.5V,inputpulselevelsof0.4VtoVdd-0.2V/Vdd-0.3VandoutputloadingspecifiedinFigure1.

2. TheinternalwritetimeisdefinedbytheoverlapofCS1LOW,CS2HIGHandUBorLB,andWELOW.AllsignalsmustbeinvalidstatestoinitiateaWrite,butanyonecangoinactivetoterminatetheWrite.TheDataInputSetupandHoldtimingarereferencedtotherisingorfallingedgeofthesignalthatterminatesthewrite.

3. TestedwiththeloadinFigure2.Transitionismeasured±500mVfromsteady-statevoltage.Not100%tested.

Notes: 1. WRITEisaninternallygeneratedsignalassertedduringanoverlapoftheLOWstatesontheCS1,CS2andWEinputsandat

leastoneoftheLBandUBinputsbeingintheLOWstate.2. WRITE=(CS1)[(LB)=(UB)](WE).

AC WAVEFORMSWRITE CYCLE NO. 1(1,2) (CS1Controlled,OE=HIGHorLOW)

DATA-IN VALID

DATA UNDEFINED

tWC

tSCS1

tSCS2

tAW

tHA

tPWE

tHZWE

HIGH-Z

tLZWEtSA

tSD tHD

ADDRESS

CS1

CS2

WE

DOUT

DIN

LB, UBtPWB

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IS62WV6416DALL/DBLLIS65WV6416DALL/DBLL

WRITE CYCLE NO. 2 (WEControlled:OEisHIGHDuringWriteCycle)

WRITE CYCLE NO. 3 (WEControlled:OEisLOWDuringWriteCycle)

DATA-IN VALID

DATA UNDEFINED

tWC

tSCS1

tSCS2

tAW

tHA

t PWE

tHZWE

HIGH-Z

tLZWEtSA

tSD tHD

ADDRESS

OE

CS1

CS2

WE

LB, UB

DOUT

DIN

DATA-IN VALID

DATA UNDEFINED

tWC

tSCS1

tSCS2

tAW

tHA

tPWE

tHZWE

HIGH-Z

tLZWEtSA

tSD tHD

ADDRESS

OE

CS1

CS2

WE

LB, UB

DOUT

DIN

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Integrated Silicon Solution, Inc. — www.issi.com 11Rev. B12/18/12

IS62WV6416DALL/DBLLIS65WV6416DALL/DBLL

WRITE CYCLE NO. 4 (UB/LBControlled)

DATA UNDEFINED

t WC

ADDRESS 1 ADDRESS 2

t WC

HIGH-Z

t PBW

WORD 1

LOW

WORD 2

t HD

t SA

t HZWE

ADDRESS

CS1

UB, LB

WE

DOUT

DIN

OE

DATAINVALID

t LZWE

t SD

t PBW

DATAINVALID

t SDt HD

t SA

t HA t HA

HIGHCS2

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IS62WV6416DALL/DBLLIS65WV6416DALL/DBLL

DATA RETENTION SWITCHING CHARACTERISTICS

Symbol Parameter Test Condition Min. typ.(1) Max. Unit

Vdr VddforDataRetention SeeDataRetentionWaveform 1.2 3.6 V

idr DataRetentionCurrent Vdd=1.2V,CS1 ≥Vdd–0.2V Com. — 0.4 2 µA Ind. 4 Auto. 18

tsdr DataRetentionSetupTime SeeDataRetentionWaveform 0 — ns

trdr RecoveryTime SeeDataRetentionWaveform trC — ns

Note:1.TypicalvaluesaremeasuredatVdd=3.0V,TA=25oCandnot100%tested.

DATA RETENTION WAVEFORM (CS1 Controlled)

DATA RETENTION WAVEFORM (CS2 Controlled)

VDD

CS1 ≥ VDD - 0.2V

tSDR tRDR

VDR

CS1GND

Data Retention Mode

VDD

CS2 ≤ 0.2V

tSDR tRDR

VDR

CS2

GND

Data Retention Mode

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Integrated Silicon Solution, Inc. — www.issi.com 13Rev. B12/18/12

IS62WV6416DALL/DBLLIS65WV6416DALL/DBLL

ORDERING INFORMATION

IS62WV6416DALL (1.65V - 2.2V)

Industrial Range: -40°C to +85°C Speed (ns) Order Part No. Package

55 IS62WV6416DALL-55BLI miniBGA(6mmx8mm),Lead-free

IS62WV6416DALL-55TLI TSOPTYPEII,Lead-free

IS62WV6416DBLL (2.3V-3.6V)

Industrial Range: -40°C to +85°C Speed (ns) Order Part No. Package

45(35)1 IS62WV6416DBLL-45TI TSOPTYPEII IS62WV6416DBLL-45TLI TSOPTYPEII,Lead-free

IS62WV6416DBLL-45BI miniBGA(6mmx8mm) IS62WV6416DBLL-45BLI miniBGA(6mmx8mm),Lead-free IS62WV6416DBLL-45B2LI miniBGA(6mmx8mm),2CS,Lead-freeNote:1.Speed=35nsforVdd=3.3V±5%.Speed=45nsforVdd=2.3V-3.6V

IS65WV6416DBLL (2.3V-3.6V)

Automotive Range: -40°C to +125°C Speed (ns) Order Part No. Package

45 IS65WV6416DBLL-45CTLA3 TSOPTYPEII,Lead-free,CopperLead-frame IS65WV6416DBLL-45BLA3 miniBGA(6mmx8mm),Lead-free

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IS62WV6416DALL/DBLLIS65WV6416DALL/DBLL

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Page 15: 64K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS ...DECEMBER 2012 A0-A15 CS1 OE WE 64K x 16 DECODER MEMORY ARRAY COLUMN I/O CONTROL CIRCUIT GND VDD I/O DATA CIRCUIT I/O0-I/O7 Lower Byte

Integrated Silicon Solution, Inc. — www.issi.com 15Rev. B12/18/12

IS62WV6416DALL/DBLLIS65WV6416DALL/DBLL

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