6.012 Design Problem, Spring 2006 - MIT OpenCourseWare · 2020-01-04 · 6.012 Design Problem...

6.012 - Microelectronic Devices and Circuits Spring 2006 Design Problem Circuit

Full schematic

Q19

Q21

Q27

Q26

Q28

Q29

vOUT

+

-

B

vIN2

Q16

+ 1.5 V

- 1.5 V

Q12Q11

B

vIN1

+

-

+

-

Q13 Q14

Q15

Q10Q9

Q18

Q20

Q17

Q25

Q24A

Q23Q22

Q5C

D

C

A

B

Q6

Q7D

Q8

Q1

Q2

Q3

Q4

Bias chains Source-coupled pair gain stage with Lee active load

Cascode* differential gain stage with cascode current

mirror active load

Complementary emitter-follower

output stages

Push-pull output stage

* Common source stage followed by common base stage. 6.012 Design Problem Spring 2006 - Slide 1

Circuit drawn with alternative MOSFET symbols:Some find the MOSFET symbols used in this version of the schematic with the

arrow on the source, rather than the gate, more intuitive when looking at aschematic. The rest of the foils in this set use the original symbols, so this figure help you adapt those foils if you prefer these alternative symbols.

Q19

Q21

Q27

Q26

Q28

Q29

vOUT

+

-

B

vIN2

Q16

+ 1.5 V

- 1.5 V

Q12Q11

B

vIN1

+

-

+

-

Q13 Q14

Q15

Q10Q9

Q18

Q20

Q17

Q25

Q24A

Q23Q22

Q5C

D

C

A

B

Q6

Q7D

Q8

Q1

Q2

Q3

Q4

Bias chains Source-coupled pair gain stage with Lee active load

Cascode* differential gain stage with cascode current

mirror active load

Complementary emitter-follower

output stages

Push-pull output stage

6.012 Design Problem •Common source stage followedby common base stage. Spring 2006 - Slide 2

Conceptual schematic: full circuit

Q21

Q26

Q28

Q29

vOUT

+

-vIN2

+ 1.5 V

- 1.5 V

vIN1

+

-

+

-

Q13 Q14

Q25

Active Load

(Current mirror

cascode load)IBIAS1

IBIAS2

IBIAS3

Active load

(Lee load)

Q19

Q16

Q18

Q17

C

Source-coupled pair Source-coupled pair Complementary Push-pull gain stage with stage followed by emitter-follower output Lee active load common gate stage output stages stage

with cascode current mirror active load

6.012 Design Problem Spring 2006 - Slide 3

Conceptual schematic: difference-mode inputs

+

-

Q13Q26

Q28

roQ24

gCL,diff

gLL,diff Q17

vod

+

-

100!vid/2 Q19

Common Source

Common Gate

Emitter Follower

Emitter Follower

Common Source

Avd = vod/vid


gLL,com

vic

+

-

Q13Q26

Q28

roQ24

2roQ15

gCL,com

Q17

voc

+

-

100! Q19

Conceptual schematic: common-mode inputs

Common Source

Common Gate

Emitter Follower

Emitter Follower

Source Degeneration

(parallel feedback)

Avc = voc/vic


+ 1.5 V

A

B

Q1

Q2

Q3

Q4

- 1.5 V

A

B

Q1

Q4

- 1.5 V

RREF1

+ 1.5 V

≈

Q5C

Q6

Q7D

Q8

- 1.5 V

+ 1.5 V

- 1.5 V

+ 1.5 V

RREF2

RREF3

RREF3

RREF2

D

C

Left to right through the design problem circuit:1. Biasing: the bias chains

Points to ponder:- What is the drain current of a minimum size n-channel MOSFET when (VGS-VT) = (VGS-VT)min? What is it for a minimally biased p-channel MOSFET? - How can Q1 and Q4 both be at this minimum bias point?


Left to right through the design problem circuit:1. Biasing: looking at how each of the four stages is biased

Q21

Q26

Q28

Q29

vOUT

+

-vIN2

+ 1.5 V

- 1.5 V

Q12Q11

vIN1

+

-

+

-

Q13 Q14

Q10Q9

Q20Q25

Q23Q22

D

Q19

Q16

Q18

Q17

C

IBIAS1

IBIAS2

IBIAS3

Stage 1: Biased Stage 2: Biased Stage 3: Biased Stage 4:by the current by Q9, Q10, Q11, by IBIAS2 and Biased bysource, IBIAS1 and Q12. IBIAS3. Q25and Q26.

Point to ponder:6.012 Design Problem - Stages 2 and 4 are biased by the preceding stages. Spring 2006 - Slide 7

Left to right through the design problem circuit:1. Biasing: power dissipation A constraint on the bias currents is the total power dissipation

specification of 7.5 mW. This means that the total bias currentmust be less that 2.5 mA (i.e, 3 V x 2.5 mA = 7.5 mW).

Q19

Q21

Q27

Q26

Q28

Q29

vOUT

+

-

B

vIN2

Q16

+ 1.5 V

- 1.5 V

Q12Q11

B

vIN1

+

-

+

-

Q13 Q14

Q15

Q10Q9

Q18

Q20

Q17

Q25

Q24A

Q23Q22

Q5C

D

C

A

B

Q6

Q7D

Q8

Q1

Q2

Q3

Q4IA IB IC ID IG IHIFIE

!

IA

+ IB

+ IC

+ ID

+ IE

+ IF

+ IG

+ IH" 2.5 mA

!

PQ

= IA

+ IB

+ IC

+ ID

+ IE

+ IF

+ IG

+ IH( ) " 3 Volts


Left to right through the design problem circuit:2. First gain stage: gain of source-coupled pair with Lee load

A Lee Load is an active load that looks different in common anddifference mode. A full analysis can be found in the handout"Two Active Loads" posted on Stellar.

vIN2

Q12Q11

B

vIN1

+

-

+

-

Q13 Q14

Q15

Q10Q9

vOUT1

+

-

vOUT2

+

-

+ 1.5 V

- 1.5 V

+

-vgs13 gm13vgs13

go13

2gm9

+

-

v ic

+

-

voc

2r015

gm13v idgo13 2go9

+

-v id

+

-vod

Difference mode:

Common mode:


Left to right through the design problem circuit:2. First gain stage: gain of source-coupled pair with Lee load

Difference mode: Common mode:

gm13v idgo13 2go9

+

-v id

+

-vod

+

-vgs13 gm13vgs13

go13

2gm9

+

-

v ic

+

-

voc

2r015

!

vod

="g

m13

g013

+ 2g09

vid

=

2 ID13

VGS13

"VTn( )

ID13

VA13

+ 2I

D132

VA 9

vid

=

2V

A 9V

A13

VA 9

+ VA13

#

$ %

&

' (

VGS13

"VTn( )

vid

=2V

A ,eff 9,13

VGS13

"VTn( )

vid

!

voc"#g

015

4gm9

vic

=V

GS9#V

Tp( )2V

A15

vic

Combined:

!

vout1

="g

m13

go13

+ 2go9

#v

in1" v

in2( )2

"g

015

4gm9

#v

in1+ v

in2( )2

="V

A .eff 9,13

VGS13

"VTn( )

# vin1" v

in2( ) "V

GS13"V

Tn( )2V

A15

#v

in1+ v

in2( )2

vout2

=g

m13

go13

+ 2go9

#v

in1" v

in2( )2

"g

015

4gm9

#v

in1+ v

in2( )2

=V

A .eff 9,13

VGS13

"VTn( )

# vin1" v

in2( ) "V

GS13"V

Tn( )2V

A15

#v

in1+ v

in2( )2

Points to ponder:- The outputs go to the gates of other MOSFET, so they do not load this stage. What does this about getting the maximum difference mode out of this stage?- How can Q9 through Q15 all be biased at their minimum bias point?


Left to right through the design problem circuit:2. First gain stage, cont: common-mode input range

Point to ponder:- What is vDS and what is vGD at the boundary between the saturation and linear regions?

- -

vc

down

vC

up

Q13, Q14 forced

out of

saturation

if vC too highvC

down

vC

up

+ +

- -

vGS stays constant

Q15 forced out

of saturation

if vc too low

vGS vGS

+ +

vSG stays constant

-

+

Q12Q11

B

Q13 Q14

Q15

Q10Q9

+ 1.5 V

- 1.5 V


Left to right through the design problem circuit:3. Second gain stage: source-coupled cascode, current mirror load

Comments/Observations:- This stage is essentially a normalsource-coupled pair with a currentmirror load, but there are differences.. - The first difference is that two drivertransistors are cascode pairs. The stagethus has two sub-stages, the first being asource-coupled pair which is loaded bythe second, which is a common-gatepair. The combination of a commonsource stage followed by a common gatestage is called a "cascode. - The second difference is that thecurrent mirror load is also cascoded. - The third difference is that the stage isnot biased with a current mirror, but isinstead biased by the first gain stage.

Q19

Q21

Q16

Q18

Q20

Q17

Q23Q22

0.75 V

-0.75 V

vOUT

+

-

vIN2

+

-vIN1

+

-

- 1.5 V

+ 1.5 V

rin3

Point to ponder:- Notice that output of the stage is loaded by the input resistance of the third stage.In the first stage there was no loading. How does this effect the gain and how we maximize it?


Left to right through the design problem circuit:3. Second stage: gain of a simple current mirror with loading

vIN2

Q1

V+

Q2

vIN1

+

-

+

-

Q3 Q4

Q6

V-

vOUT

+

-

VREF

+

-

rload

The output voltage is, in general:

*

Focusing on the differentialgain and writing it in terms of

!

Avd

=g

m3

g01

+ g03

+ gload

=K

3V

GS3"V

TN( )

ID

VA ,eff( ) + g

load

the bias point:

Substituting for ID and dividing by K3:

Point to ponder:

!

vout

=g

m3

g01

+ g03

+ gload

v1" v

2( ) +g

06

2gm3

v1+ v

2( )

!

Avd

=V

GS3"V

TN( )

VGS3

"VTN( )

2

2VA ,eff

+g

load

K3

#

$ % %

&

' ( (

- When the output is not loaded the voltage gain, 2VA,eff/(VGS3 - VTN), does not depend on the K's of the transistors, but when it is loaded by rload, making K bigger can increase the gain.


Left to right through the design problem circuit:

Replacing all the transistors in a current mirrorby cascode pairs significantly increases theoutput resistances and the maximum gain:

3. Second stage: the impact of having

Q19

Q21

Q16

Q18

Q20

Q17

Q23Q22

0.75 V

-0.75 V

vOUT

+

-

vIN2

+

-vIN1

+

-

- 1.5 V

+ 1.5 V

rin3

cascode pairs

Points to ponder:- What is the value of gload? - Is it feasible to bias Q16 and Q17 to get the largest gain? How close can one come? - Changing the bias on Q16/Q17 means that of Q9/Q10/Q11/Q12 must change. Is this OK? - How much can K be increased? Is there any disadvantage to making K this big? - Over what range can vOUT swing (positive and negative)?

+

-

Q1

gl

V-

VIN+vin

Q2

V+

+

-VOUT+vout

Common-

sourceCommon-

gate

!

Av,Cascode

=v

out

vin

= "g

m1

gl+ g

02

g01

gm2

, rout

= r01

gm 2

g02

A Cascode Pair:


+

-

Q1

gl

V-

VIN+vin

Q2

V+

+

-VOUT+vout

Common-

sourceCommon-

gate

Left to right through the design problem circuit:3. Second stage: the cascode

vgs1

gm1vgs1

ro1

+

-

ro2

gm2vgs2

+

-

vgs2

+

-

voutrl

Schematic:

L.E.C.:

!

Av

=v

out

vin

="g

m1

gl+

g01

gm2

+ g02( )

gl+ g

02( )#

o

"gm1

gl+ g

01

g02

gm2

Point to ponder:- Av of a common-source stage, with a much larger output resistance.

!

rout

=g

m2+ g

02+ g

01

g02

g01

" r01

gm2

g02


Left to right through the design problem circuit:3. Second stage: looking more at the cascode

The cascode stage looks like a common source stage made of a special "cascode" transistor, QCC:

!

gm,CC

= gm1

ro,CC

" r01

gm2

go2

VA,CC

"VA1

gm2

go2

or #CC

= #1

go2

gm2

+

-

QCC

gl

V-

VIN+vin

V+

+

-VOUT+vout

Cascode

equivalent

QCC:

=

vgsCC

gmCCvgsCC

roCC

+

-

g

s s

d

+

-

Q1

gl

V-

VIN+vin

Q2

V+

+

-VOUT+vout

Common-

sourceCommon-

gate


Q19

Q21

Q16

Q18

Q20

Q17

Q23Q22

0.75 V

-0.75 V

vOUT

+

-

vIN2

+

-vIN1

+

-

- 1.5 V

+ 1.5 V

rin3

=

QCC1 = Q16/Q18 QCC2 = Q17/Q19 QCC3 = Q22/Q20

vIN2

QCC1

V+

QCC2

vIN1

+

-

+

-

QCC3QCC4

V-

vOUT

+

-

rin3

Left to right through the design problem circuit:3. Second gain stage: substituting the cascode equivalents

QCC4 = Q23/Q21

Common Common source gate


Left to right through the design problem circuit:3. Second gain stage: substituting the cascode equivalents

!

gm,CC

go,CC

QCC1

gm16

go16

go18

gm18

QCC2

gm17

go17

go19

gm19

QCC3

gm22

go22

go20

gm20

QCC4

gm23

go23

go21

gm21

!

vout

= Avd

vid

+ Avcv

ic= A

vdv

in1" v

in2( ) + Avc

vin1

+ vin2( )

2

vIN2

QCC1

V+

QCC2

vIN1

+

-

+

-

QCC3QCC4

V-

vOUT

+

-

rin3

Avd = vout/(vin1 -vin2) with vin1 = vid/2, vin2 = -vid/2:

!

Avd

=2g

m,CC 2

go,CC 2

+ go,CC 4

+ gin3

=2g

m17

go17

go19

gm19

" # $

% & ' + g

o23g

o21

gm21

" # $

% & ' + g

in3

Avd continued on next foil 6.012 Design Problem Spring 2006 - Slide 18

Left to right through the design problem circuit:3. Second gain stage: completing the gain derivation Avd cont.:

Lesson: Bias the FETs at (VGS-VT)min. Then make gin3 as small as possible and K17 as large as you can.*

!

Avd

=

22I

D

VGS17

"VTp( )

ID

VA17

#I

D

VA19

#V

GS19"V

Tp( )2I

D

+I

D

VA 23

#I

D

VA 21

#V

GS21"V

Tn( )2I

D

+ gin 3

=2

VGS17

"VTp( )

#2

VGS19

"VTp( )

2VA17

VA19

+V

GS 21"V

Tn( )2V

A 23V

A 21

+g

in 3

ID

$

% & &

'

( ) )

=2

VGS"V

T( )min

#2

VGS"V

T( )min

VA

2+

2gin 3

K17

VGS"V

T( )min

2

$

%

& &

'

(

) )

A with vin1 vc = vout =vin2 = vic,:

!

Avc"

1

2

Lesson: Not much can be done about Avc.

6.012 Design Problem Spring 2006 - Slide 19 * This may not be the peak gain, but it will be OK.

Left to right through the design problem circuit:4. Third and fourth stages: emitter-followers

Q27

Q26

Q28

Q29

vOUT

+Q25

Q24A

B

- 1.5 V

+ 1.5 V

vIN

+

- -

100!

Comments/Observations:- These stages involve four emitterfollower building blocks arranged astwo parallel cascades of two emitterfollower stages each. These stagesoffer the most design challenges andtrade-offs of any of the stages in thedesign problem.- They must be biased properlytaking into account KVL and KCLconstraints. - Although they have voltage gains ofalmost one, they have a big effect onthe overall voltage gain of theamplifier because they load the secondgain stage.- They determine the outputresistance of the amplifier.

Point to ponder:- Am I having fun yet? (This is where the fun begins.)


Left to right through the design problem circuit:4. Third and fourth stages, cont.: biasing - getting the currents right

!

IE 28

= IE 29

Constraint at output node:

Constraint at input node: Equivalently:

!

IB 25

= IB 26

Sum at emitter of Q25:

!

IBIAS2

= IE 25

+ IE 29

"p

+1( )

= "n

+1( )IB 25+ I

E 29"

p+1( )

= "n

+1( ) IB 25

+I

E 29

"n

+1( ) "p+1( )

#

$ % %

&

' ( (

Sum at emitter of Q26:

!

IBIAS3

= "p

+1( ) IB 26

+ IE 28

"n

+1( ) = "p

+1( ) IB 26

+I

E 28

"n

+1( ) " p+1( )

#

$ % %

&

' ( (

Combining everything:

!

IBIAS3

IBIAS2

= "p

+1( ) "n

+1( ) # "p"

n

!

IE 25

"n

+1( ) = IE 26

"p

+1( )

Q27

Q26

Q28

Q29Q25

Q24A

B

- 1.5 V

+ 1.5 V

vIN

+

-

100!|IE29|IE28

IOUT = 0IIN = 0

IB25 =

|IB26|

IBIAS3

IE28/("n+1)

|IE29|/("p+1)

IBIAS2

|IE26|

IE25

Lesson: The bias currents are not totally unconstrained. 6.012 Design Problem Spring 2006 - Slide 21

Q27

Q26

Q28

Q29

Q25

Q24A

B

- 1.5 V

+ 1.5 V

100!

VBE28

+

-VBE25

VEB26

+

-

+

-

VEB29

+

-

and |IE26

|/(βp

Left to right through the design problem circuit:4. Third and fourth stages, cont.: biasing - getting the voltages right

KVL constraint:

!

VBE 28

+ VEB 29

"VBE 25

"VEB 26

= 0

Relating voltages to currents:

!

VBE 25

= kT q( ) ln IE 25

"25

IESn[ ]

VEB 26

= kT q( ) ln IE 26

"26

IESp[ ]

VBE 28

= kT q( ) ln IE 28

"28

IESn[ ]

VBE 29

= kT q( ) ln IE 29

"29

IESp[ ]

Combining everything, including the fact that I

ESp=I

ESn=I

ES, and the results |I

E28|=I

E29

+1)=IE25

/(βn+1), yields:

!

IE 28

IE 25

="

p+1( )

"n

+1( )

#28#

29

#25#

26

6.012 Design Problem Lesson: The BJT areas matter. Spring 2006 - Slide 22

Point to ponder:- What do the results on this foil and thelast mean, and are there any other thingsto consider when biasing these stages?

Left to right through the design problem circuit:4. Third and fourth stages, cont.: input resistance, rin

We will use the approximation that the two emitter-follower paths can be modeled asbeing in parallel for purposes of calculating the input resistance.

Q26

Q28

Q24A

- 1.5 V

+ 1.5 V

rin1 200!

Inparallel

rin ≈ rin1|| rin2

Q27

Q29

Q25

B

- 1.5 V

+ 1.5 V

200!

rin2

Point to ponder:- Remember that the ratio of IBIAS3 to IBIAS4 is constrained. - Is there a penalty for picking a bias that maximizes rin? What else would be impacted?


Left to right through the design problem circuit:4. Third and fourth stages, cont.: output resistance, rout

Q26

Q28

Q24A

- 1.5 V

+ 1.5 V

rout1

2roS2

* We will use the approximation that the two emitter-follower paths can bemodeled as being in parallel for purposes of calculating the output resistance.

Point to ponder:- Remember that the ratio of IBIAS3 to IBIAS4 is constrained.

Inparallel

rout ≈ rout1|| rout2

Q27

Q29

Q25

B

- 1.5 V

+ 1.5 V

rout2

2roS2

- Is there a trade-off between power dissipation and rout? Is there an optimum bias? 6.012 Design Problem Spring 2006 - Slide 24

Left to right through the design problem circuit:4. Third and fourth stages, cont.: rin and

rout of an emitter follower

* Reviewing the input and output resistancesof a single emitter follower stage.

Right: Emitter-follower stageBelow: LECs for finding rin and rout

rin

r! "ib ro

rl

+

-

vin

iin = ib

roBias

r! ro

+

-vt

rt "ib

ib

itroBias rout

IBIAS

Q25

- 1.5 V

+ 1.5 V

rt

rl

+

-

+

-vt

vout

!

rin

= r" + # +1( ) rl|| r

o|| r

Bias( )

$ r" + # +1( )rl

!

rout

=1 go

+ gBias

+ " +1( ) r# + rt( )[ ]

$ r# + rt( ) " +1( )

Point to ponder:- Looking in the resistance is multiplied by (β+1); looking back it is divided by(β+1) .


Left to right through the design problem circuit:4. Third and fourth stages, cont.: the voltage

gain, Av, of an emitter follower

* Reviewing the voltage gain of anemitter follower stage.

Right: Emitter-follower stageBelow: LEC for finding Av

IBIAS

Q25

- 1.5 V

+ 1.5 V

rt

rl

+

-

+

-vt

vout

Point to ponder:

!

vout

= " +1( )ibrl

|| ro

|| rBias( )

vin

= ibr# + " +1( )ib

rl

|| ro

|| rBias( )

Av

=v

out

vin

=" +1( ) r

l|| r

o|| r

Bias( )r# + " +1( ) r

l|| r

o|| r

Bias( )

$" +1( )rl

r# + " +1( )rl

- The voltage gains of the third-stage emitter followers (Q25 and Q26) will likely be veryclose to one, but that of the stage-four followers might be noticeably less than one.

r! "ib ro

rl

+

-

vin

iin = ib

+

-

vout = AvvinroBias


Left to right through the design problem circuit:4. Third and fourth stages, cont.: output voltage swing

Points to ponder:

Q27

Q26

Q28

Q29

Q25

Q24

A

B

Q19

Q21

Q16

Q18

Q20

Q17

Q23Q22

C

D

vIN2

+

-vIN1

+

-

- 1.5 V

+ 1.5 V

-

Gate node

voltage fixed

Gate node

voltage fixed

+

-

VGS stays constant

Q27 forced out

of saturation

if vOUT too low

VGS

+

VSG stays constant

vOUT

down

vOUT

up

Q24 forced out

of saturation

if vOUT too high

VSG

Q21 forced out

of saturation

if vOUT too low

Q19 forced out

of saturation

if vOUT too high

- How far + and - can the node connecting the drains of Q19 and Q21 swing? - How low can the voltage on the drain of Q27 go? How high for the drain of Q24? - How much do vBE28 and vEB29 increase as |vOUT| inceases?


Left to right through the design problem circuit:4. Third and fourth stages: putting it all together

Comments/Observations:- These stages involve four emitterfollower building blocks arranged astwo parallel cascades of two emitterfollower stages each. These stages offerthe most design challenges and trade-offs of any of the stages in the designproblem.- They must be biased properly takinginto account KVL and KCLconstraints. - Although they have voltage gains ofalmost one, these stages have a bigeffect on the overall voltage gain of theamplifier because they load the secondgain stage.- These stages determine the outputresistance of the amplifier.- IBIAS3 and IBIAS4 set the bias levels of Q25 and Q26. The bias levels of Q28 and Q29 are set by the γ's. - A reasonable choice is to make γ

28 = γ

29, and γ

25 = [(β

n+1)/(β

p+1)]γ

26,in which

case: IE28/

IE25

= γ28

/γ25

Q27

Q26

Q28

Q29

vOUT

+Q25

Q24A

B

- 1.5 V

+ 1.5 V

vIN

+

- -

100!

Point to ponder:- Now that I know everything,how can I meet the specs?


Left to right through the design problem circuit:6. Overall gain expression

!

vout

= Avd

vid

+ Avcv

ic= A

vdv

in1" v

in2( ) + Avc

vin1

+ vin2( ) 2

The defining relationships:

The difference-mode gain:

!

Avd

= Avd1" A

vd 2" A

v3" A

v4

=#g

m13

2 g013

+ 2go9( )

"#2g

m17

g017

g019

gm19

$

% &

'

( ) +

g023

g021

gm23

$

% &

'

( ) + g

in 3

" 1 "*

n+1( )2r

l

r+ 28+ *

n+1( )2r

l

!

Avc

= Avc1" A

vc2" A

v3" A

v4=#g

015

4gm9

"#1

2" 1 "

$n

+1( )2rl

r% 28+ $

n+1( )2r

l

The common-mode gain:

!

rl

=100"

Point to ponder:- The follower stages treat the difference and common mode outputs the same. - Let's put it all together and see what your design can do!


Left to right through the design problem circuit:5. DC offset of a differential amplifier (OP-amp)

Procedure for finding the DC offset: I. Identify the high impedance node* in the amplifier, and calculate what

the voltage on that node is when the output voltage is zero.

Q19

Q21

Q27

Q26

Q28

Q29

vOUT

+

-

B

vIN2

Q16

+ 1.5 V

- 1.5 V

Q12Q11

B

vIN1

+

-

+

-

Q13 Q14

Q15

Q10Q9

Q18

Q20

Q17

Q25

Q24A

Q23Q22

Q5C

D

C

A

B

Q6

Q7D

Q8

Q1

Q2

Q3

Q4

High impedance node

Node voltage when vOUT = 0: VNODE-I = VBE25 - VEB29 ≈ 0 V

* Example: The output node of a CMOS inverter is an high impedance node.When both MOSFETs were saturated the voltage on this node could take ona range of values, and we couldn't say what vOUT was when vIN was VDD/2.


Left to right through the design problem circuit:5. DC offset of a differential amplifier (OP-amp)

Procedure for finding the DC offset: II. Disconnect the circuit following the high impedance node and

calculate the voltage on the node when vIN1 = vIN2 = 0, assuming perfect symmetry and matching. Call this voltage VNODE-II.

Q19

Q21 VNODE = ?

+

-

Q16

+ 1.5 V

- 1.5 V

Q12Q11

B

Q13 Q14

Q15

Q10Q9

Q18

Q20

Q17

Q23Q22

Q5C

D

C

A

B

Q6

Q7

D

Q8

Q1

Q2

Q3

Q4

vIN1 = 0 vIN2 = 0

High impedance node

Both inputs zero

Complementary node

With perfect matching and symmetry,the voltage on the highimpedance node will equal that on the complementary node. In this case VNODE-II = -1.5V + VGS22


Left to right through the design problem circuit:5. DC offset of a differential amplifier (OP-Amp)

Procedure for finding the DC offset: III. Knowing the differential voltage gain of the stage, Avd, we can

calculate the DC off-set at the output by subtracting the voltage calculated in Step I, which we can call VNODE-I, from the voltage calculated in Step II, VNODE-II. When vIN1- vIN2 = (VNODE-I - VNODE-II)/Avd, VOUT is on the same order

and thus essentially zero. We will define this value of vIN1- vIN2 to be the DC offset, certainly compared to (VNODE-I - VNODE-II).

DC offset = (VNODE-I - VNODE-II)/Avd

vOUT

+

-

vIN1

RL

Avd

R

vIN2

R

+

!

Example: In the design problem, if Avd.turns out to be -1 x 104, and (VNODE-I-VNODE-II) is -0.9V, then the DC offset is 90 µV.


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6.012 Microelectronic Devices and Circuits Fall 2009

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