6. Basic Machine Organizaton
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Transcript of 6. Basic Machine Organizaton
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6. Basic Machine Organizaton
6.2 Computer OrganizationComputer Studies (Advanced Level)
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Computer Organization
A computer has no intelligence. It follows the commands you specify in the program.
Program: A sequence of instructions. The CPU executes them one-by-one.
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Programming Language
Machine-Level: used by the computer trains of 0’s and 1’s Assembly level source code -> assemble -> object code
High-Level and Mid-Level Nearer to natural language Need compilation Source code -> compile -> object code
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Why Assembly Language? (1)
Machine program is difficult to write, debug, understand and error-prone.
Use symbols or mnemonics to replace the 0’s and 1’s. E.g.: assembly : MOV A, 1 machine : 0011 0101 0001 Using machine language, one has to determine the
address of “A” manually.
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Why Assembly Language? (2)
Using Assembly Language, you need an assembler to translate an assembly program to a machine program.
Assembly Language 1-1 correspondence with the machine program. Directly communicates with the computer has precise control of the computer machine dependent
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Computer Architecture
Memory (RAM, ROM)
Processor I/O Unit
DiskModern CRTterminal Keyboard
Control
Data
Address
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Processor
ALU (Arithmetic Logic Unit)system clockregistersInstruction register(IR)Instruction decoder(ID)internal system bus
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Bus and register
ControlData
Address
SystemBus
Controller(System Clock)
MDR(Data Buffer)
MAR(Address Buffer)
Registers
Program counter(PC)
CCR
ALU
Internal Bus
ID
InstructionRegister(IR)
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Basic Instruction Formats
An instruction is divided into different fields:
Opcode: Operation to perform, e.g. additionOperand 1 to Operand N: The data which the
operation will act on.
Opcode | Operand 1 | … | Operand N
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Basic Instruction Formats
The number of operands N varies for different computers. In 8088, N can be 0, 1, or 2.
N=2: E.g. “ADD AX, BX” means “AX<-(AX)+(BX)” Note: “(AX)” means the content of the register “AX”
N=1: e.g. “PUSH AX” means “Stack <- (AX)”
N=0: e.g. “RET means return from procedure
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Instruction Execution Cycle
1. Instruction Fetch a) The address of the current instruction to execute is stored in a
CPU’s internal register called the Program Counter (PC). (much like a “pointer” to point at the next instruction)
b) Put this address into Memory Address Register (MAR) and initiates a Read Cycle.
C) The instruction is read into another CPU’s internal register called the Memory Data Register (MDR).
D) the data in MDR is then forwarded to the Instruction Register (IR) via the internal bus.
Note: MAR = Address Buffer, MDR = data buffer
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Instruction Fetch
e) at the same time, PC is incremented to point at the next instruction:
PC-------> 1003 ADD AH, 2 Current1007 JL TARGET Next1009 …
… …1033 … TARGET
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Notes of Instruction Fetch
Note:Increment PC by how much?
It depends on the size of the current instruction (what if irregular)
Assume the next instruction follows the current instruction. (What if we have a branch instruction? E.g.if (A>0)…else…
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Instruction execution cycle
2. Instruction Decode: Generate the control signals to accomplish the
tasks of the instruction.
3. Data Fetch (for operands)
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Instruction Fetch - Execution
4. Execution: ALU Set the condition codes (flags) to indicate the
characteristics of last execution’s result. E.g. overflow, negative
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Execution
Note: Condition Code Register (CCR) is more
commonly known as the Processor Status Word (PSW)
Branch instructions check the status of the PSW A branch is either taken or not taken. If it is taken,
the branch address is loaded into the PC. Effectively, the sequential flow of instruction (or control) is interrupted.
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E.g.1
ControlData
Address
SystemBus
Controller(System Clock)
MDR(Data Buffer)
MAR(Address Buffer)
Registers
PC: 1003
CCR
ALU
Internal Bus
ID
InstructionRegister(IR)
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E.g.1
ControlData
Address
SystemBus
Controller(System Clock)
MDR(Data Buffer)
MAR1003
Registers
PC: 1007
CCR
ALU
Internal Bus
ID
InstructionRegister(IR)
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E.g.1
ControlData
Address
SystemBus
Controller(System Clock)
MDRADD AH, 2
MAR1003
Registers
PC: 1007
CCR
ALU
Internal Bus
ID
InstructionRegister(IR)
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E.g.1
ControlData
Address
SystemBus
Controller(System Clock)
MDRADD AH, 2
MAR1003
Registers
PC: 1007
CCR
ALU
Internal Bus
ID
IR:ADD AH, 2
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E.g.1
ControlData
Address
SystemBus
Controller(System Clock)
MDRADD AH, 2
MAR1003
Registers
PC: 1007
CCR: -ve
ALU
Internal Bus
ID
IR:ADD AH, 2
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E.g.1
ControlData
Address
SystemBus
Controller(System Clock)
MDRADD AH, 2
MAR1007
Registers
PC: 1009
CCR: -ve
ALU
Internal Bus
ID
IR:ADD AH, 2
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E.g.1
ControlData
Address
SystemBus
Controller(System Clock)
MDR:JL TARGET
MAR1007
Registers
PC: 1009
CCR: -ve
ALU
Internal Bus
ID
IR:ADD AH, 2
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E.g.1
ControlData
Address
SystemBus
Controller(System Clock)
MDR:JL TARGET
MAR1007
Registers
PC: 1009
CCR: -ve
ALU
Internal Bus
ID
IR:JR TARGET
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E.g.1
ControlData
Address
SystemBus
Controller(System Clock)
MDR:JL TARGET
MAR1007
Registers
PC: 1033
CCR: -ve
ALU
Internal Bus
ID
IR:JR TARGET
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E.g.2
PC-------> 1003 MOV AH, SRC Current1007 JL TARGET Next1009 …
1033 … TARGET1063 20 SRC
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E.g.2
ControlData
Address
SystemBus
Controller(System Clock)
MDRMOV AH, SRC
MAR1003
Registers
PC: 1007
CCR
ALU
Internal Bus
ID
InstructionRegister(IR)
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E.g.2
ControlData
Address
SystemBus
Controller(System Clock)
MDRMOV AH, SRC
MAR1003
Registers
PC: 1007
CCR
ALU
Internal Bus
ID
IR:MOV AH, SRC
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E.g.2
ControlData
Address
SystemBus
Controller(System Clock)
MDRMOV AH, SRC
MAR1063
Registers
PC: 1007
CCR
ALU
Internal Bus
ID
IR:MOV AH, SRC
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E.g.2
ControlData
Address
SystemBus
Controller(System Clock)
MDR:20
MAR1063
Registers
PC: 1007
CCR
ALU
Internal Bus
ID
IR:MOV AH, SRC