Internal and External memory

Memory Hierarchy is to obtain the highest possible access speed while minimizing the total cost of the memory system

MEMORY HIERARCHY

Semiconductor Memory TypesMemory Type Category Erasure Write Mechanism Volatility

Random-access memory (RAM) Read-write memory Electrically, byte-level Electrically Volatile

Read-only memory (ROM)

Read-only memory Not possible

Masks

Nonvolatile

Programmable ROM (PROM)

Electrically

Erasable PROM (EPROM)

Read-mostly memory

UV light, chip-level

Electrically Erasable PROM (EEPROM) Electrically, byte-level

Flash memory Electrically, block-level

Internal and External memory

Memory Cell Operation

6

Block Diagram of Memory

• Example: 2MB memory, byte-addressable—N = 8 (because of byte-addressability)—K = 21 (1 word = 8-bit)

2k wordsN-bit per word

Memory Unit

N-bit Data Input(for Write)

N-bit Data Output(for Read)

K-bit address lines

Read/WriteChip Enable

N

N

K

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Memory Model• 32-bit address space can address up to 4GB (232)

different memory locations

Flat Memory ModelFlat Memory Model

0x0A0xB60x410xFC

LowerMemoryAddress

0x00000000

HigherMemoryAddress

0x00000001

0x00000002

0x00000003

0xFFFFFFFF 0x0D

8

Memory Description• Capacity of a memory is described as

—# addresses x Word size—Examples:

Memory # of addr # of data lines

# of addr lines

# of total bytes

1M x 8 1,048,576 8 20 1 MB2M x 4 2,097,152 4 21 1 MB1K x 4 1024 4 10 512 B

4M x 32 4,194,304 32 22 16 MB16K x 64 16,384 64 14 128 KB

Some basic concepts• Maximum size of the Main Memory• byte-addressable• CPU-Main Memory Connection

Up to 2 k addressableMDR

MAR

k-bitaddress bus

n-bitdata bus

Control lines( , MFC, etc.)

Processor Memory

locations

Word length = n bits

WR /

10

MAR and MDRMAR and MDR

Memory Address Register (MAR)Contains Address in memory to find or place data

Memory Data Register (MDR)Contains Actual Data to be placed in location given in MAR, or which has been retrieved from location given in MAR

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RAM: Random Access MemoryRAM: Random Access Memory

Random – any piece of data can be accessed in a constant time regardless of physical location (unlike tapes, magnetic or optical discs)

Difference – in technical design DRAM (Dynamic RAM)

Most common, cheapVolatile: must be refreshed (recharged with power) 1000’s of times each second

SRAM (static RAM)Faster to access than DRAM and more expensive than DRAMVolatilesmall amount used in cache memory for high-speed access

12

RAM: SampleRAM: Sample

DRAM modules used as primary memory in PCs, workstations, servers.

13

Static Random Access Memory (SRAM)

BitLineBitLine

Wordline (WL)

• Two transistor inverters are cross connected to implement a basic flip-flop.

• When word line is at ground level, the transistors are turned off and the latch retains its state

• Read operation: In order to read state of SRAM cell, the word line is activated to close switches T1 and T2. Sense/Write circuits at the bottom monitor the state of b and b’

Stating RAM Structure

15

Dynamic Random Access Memory (DRAM)

• 1-transistor DRAM cell• During a write, put value on bitline and then set WL=1• Storage decays, thus requires periodic refreshing (read-sense-

write)

SRAM v DRAM• Both volatile

—Power needed to preserve data• Dynamic cell

—Simpler to build, smaller—More dense—Less expensive—Needs refresh—Larger memory units

• Static—Faster—Cache

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How to Address Memory

1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit

1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit

1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit

1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit

0

1

2

3

D7 D6 D5 D4 D3 D2 D1 D0

4x8 Memory4x8 Memory2-to-42-to-4

DecoderDecoderA0

A1

CS

ChipSelect

Internal organization of memory chips (Contd.,)

FF

circuitSense / Write

Addressdecoder

FF

CS

cellsMemory

circuitSense / Write Sense / Write

circuit

Data input /output lines:

A0

A1

A2

A3

W0

W1

W15

7 1 0

WR /

7 1 0

b7 b1 b0

•••

•••

•••

•••

•••

•••

•••

•••

•••

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Building Memory in Hierarchy• Design a 1Mx8 using 1Mx4 memory chips

D3D2D1D0

A19A18A17

A0

1Mx41Mx4

R/WCS

D7D6D5D4

A19A18

1Mx41Mx4

R/WCS

A17

A0CS

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Building Memory in Hierarchy• Design a 2Mx4 using 1Mx4 memory chips

A19A18A17

A0

1Mx41Mx4

R/WCS

A19A18A17

A0

1Mx41Mx4

R/WCSA20 1-to-2

Decoder

CS

10

D3D2D1D0

Note that 1-to-2 decoder is the wireitself (or use an inverter)

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Memory controller (contd..)

Processor

RAS

CAS

R/ W

Clock

AddressRow/Column

address

Memorycontroller

R/ W

Clock

Request

CS

Data

Memory

Simplified DRAM Read Timing