55nm SiGe BiCMOS for Optical, Wireless and High-Performance

Analog ApplicationsPascal Chevalier

STMicroelectronicspascal.chevalier@st.com

WS12: EuMIC - SiGe for mm-Wave and THz

SiGe for mm-Wave and THz / P. Chevalier 2September 6, 2015

Outline

• Introduction

• SiGe HBT scaling

• 55nm BiCMOS

• Summary & perspectives

SiGe for mm-Wave and THz / P. Chevalier 3September 6, 2015

Outline

• Introduction

• SiGe HBT scaling

• 55nm BiCMOS

• Summary & perspectives

SiGe for mm-Wave and THz / P. Chevalier 4September 6, 2015

BiCMOS drivers

• Ethernet bandwidth explosion drives BiCMOS roadmap for:– Dense CMOS (skyrocket of digital need)– High-Q passives– High-speed SiGe HBT

• Other millimeter-wave applications benefit from this push:– Move up in frequency spectrum with highly integrated

solutions becomes possible– Current applications can be improved (gain, noise,

power consumption,…)

Introduction

SiGe for mm-Wave and THz / P. Chevalier 5September 6, 2015

BiCMOS enablers

• CMOS node choice based on:– CMOS area (density 5.5 from 120nm to 55nm)

– CMOS speed (digital signal processing)

• High-Q passives impose:– Modifications to the native CMOS BEOL

(thick Cu layers for T-lines, inductors,…)

• HBT architecture choice depends on:– Targeted performance (fT, fMAX, BVCEO,…), which drives

the operation frequency

– Integration constraints & manufacturability

Introduction

SiGe for mm-Wave and THz / P. Chevalier 6September 6, 2015

15y BiCMOS scaling history at ST

0

50

100

150

200

250

300

350

400

450

0

50

100

150

200

250

300

350

400

BiCMOS7RF BiCMOS055BiCMOS9MWBiCMOS9BiCMOS7

f T a

nd

fM

AX (

GH

z)

fT

fMAX

BiCMOS6G

CMOS

WE

CM

OS

no

de &

WE (

nm

)

RF mmW to THz

Digital BEOL (from CMOS) mmW BEOL

Introduction

SiGe for mm-Wave and THz / P. Chevalier 7September 6, 2015

Outline

• Introduction

• SiGe HBT scaling

• 55nm BiCMOS

• Summary & perspectives

SiGe for mm-Wave and THz / P. Chevalier 8September 6, 2015

DPSA-SEG architecture

• Double Polysilicon Self-Aligned architecture with Selective Epitaxial Growth of the base

E CC B

Deep Trench Isolation (DTI)

B

As in-situ

doped EmitterB in-situ doped

SiGe:C Base

B doped

Polybase

Shallow Trench Isolation (STI)

Localized Collector

Pedestal

oxide Silicide

Buried Layer

Epitaxial Collector

Collector

Sinker

• Substrate• …… N+ buried layer (M1)• …… N epitaxy• …… Deep trench isolation (M2)• Shallow trench isolation• …… N+ sinker (M3)• Wells• Gate oxides (GO1 & GO2)• Gate polysilicon• …… Bipolar opening (M4)• …… SIC implant (M5)• …… Polybase deposition• …… Emitter window (M6)• …… SiGe:C base epitaxy (SEG)• …… Emitter deposition• …… Polyemitter patterning (M7)• …… Polybase patterning (M8)• Gate patterning• Extensions and source/drains• Spike activation anneal• Salicide• Contacts• Cu BEOL

- Emitter-base HBT module inserted between gate poly deposition and patterning, which minimizes impact of HBT thermal budget on CMOS devices

SiGe HBT scaling

SiGe for mm-Wave and THz / P. Chevalier 9September 6, 2015

DPSA-SEG architecture

• Double Polysilicon Self-Aligned architecture with Selective Epitaxial Growth of the base

• Substrate• …… N+ buried layer (M1)• …… N epitaxy• …… Deep trench isolation (M2)• Shallow trench isolation• …… N+ sinker (M3)• Wells• Gate oxides (GO1 & GO2)• Gate polysilicon• …… Bipolar opening (M4)• …… SIC implant (M5)• …… Polybase deposition• …… Emitter window (M6)• …… SiGe:C base epitaxy (SEG)• …… Emitter deposition• …… Polyemitter patterning (M7)• …… Polybase patterning (M8)• Gate patterning• Extensions and source/drains• Spike activation anneal• Salicide• Contacts• Cu BEOL

- Emitter-base HBT module inserted between gate poly deposition and patterning, which minimizes impact of HBT thermal budget on CMOS devices

SiGe:C/Si base

EmitterPolybase

CMOS

spacers

Contact

Collector

Emitter

inside

spacers

B9MW

SiGe HBT scaling

SiGe for mm-Wave and THz / P. Chevalier 10September 6, 2015

Vertical scaling principles

• Challenge of vertical scaling is to increase fT ( 1/EC) without penalizing too much fMAX ( fT/(RB.CBC))

• Doping & thicknesses of the layers drive the R.C trade-offs Process thermal budget is critical

Depth

Concentr

atio

n

ReferenceAs

B

C

As

Ge

Reduced arsenic/boron spacing to reduce basewidth (WB), emitter resistance (RE)

and transit time (E)

Higher speed

Narrower boron profile to reduce basewidth and base

transit time (B)

Larger collector doping to reduce collector resistance

(RC) & transit time (BC)

Larger Ge slope to increase electric field and reduce base

transit time (B)

SiGe HBT scaling

SiGe for mm-Wave and THz / P. Chevalier 11September 6, 2015

Lateral scaling principles

• Lateral scaling allows reducing all capacitances & resistances but RE: Downscaling of emitter, polyemitter and inside spacer widths is beneficial to RB

• Downscaling of base/collector width is beneficial to CBC

Shrink of the BiCMOS9MW HBT

(WE reduces from

130nm to 90nm)

Shrink of the BiCMOS9MW HBT

(WE reduces from

130nm to 90nm)

SiGe HBT scaling

SiGe for mm-Wave and THz / P. Chevalier 12September 6, 2015

Results example of scaling

• Results illustrate the impact of BC / CBC & B / RB trade-offs, RBx (extrinsic), and the benefit of lateral scaling, on fT & fMAX

250 275 300 325300

325

350

375

high

Collector doping erma bu dget

x

Ma

x.

os

cil

lati

on

fre

q.

f MA

X (

GH

z)

Current gain transition freq. fT (GHz)

low

Collector doping (BVCBO)

- Low: 5.9 V

- High: 5.2 V

250 275 300 325300

325

350

375

low

high

Collector doping Thermal budget

x

Ma

x.

os

cil

lati

on

fre

q.

f MA

X (

GH

z)

Current gain transition freq. fT (GHz)

highlow

Thermal budget (spike temp.)

- High: 1080°C

- Low: 1050°C

250 275 300 325300

325

350

375

high

low

low

high

Collector doping Thermal budget

Base doping

Ma

x.

os

cil

lati

on

fre

q.

f MA

X (

GH

z)

Current gain transition freq. fT (GHz)

highlow

Base doping (Boron dose)

- High: 2.5E13 at/cm²

- Low: 1.5E13 at/cm²

250 275 300 325300

325

350

375

high

low

small

large low

high

Collector doping Thermal budget

Base doping Emitter width

Ma

x.

os

cil

lati

on

fre

q.

f MA

X (

GH

z)

Current gain transition freq. fT (GHz)

highlow

Emitter width (WE)

- Large: 0.17 µm

- Small: 0.10 µm

CBEBC HBT

L = 5 µm, VCB = 0.5 V

[Chevalier12]

SiGe HBT scaling

SiGe for mm-Wave and THz / P. Chevalier 13September 6, 2015

Scaling outcome

• fT and fMAX have been increased by a factor of about 6 from 0.35µm to 55nm CMOS nodes (in ~15 years)– Scaling strategy described previously for DPSA-SEG architecture is part

of the work done to move from BiCMOS9MW to BiCMOS055

0.1 1 10 1000

100

200

300

400

BiCMOS6G

BiCMOS7

BiCMOS7RF

BiCMOS9

BiCMOS9MW

BiCMOS055

f T (

GH

z)

Collector current density JC (mA/µm²)

0.1 1 10 1000

100

200

300

400

BiCMOS6G

BiCMOS7

BiCMOS7RF

BiCMOS9

BiCMOS9MW

BiCMOS055

f MA

X (

GH

z)

Collector current density JC (mA/µm²)

SiGe HBT scaling

SiGe for mm-Wave and THz / P. Chevalier 14September 6, 2015

Benefits of scaling: MAG

250 300 350 400 4503

4

5

6

7

8

9

MA

GM

AX @

120 G

Hz (

dB

)

at

VC

E =

1.2

V

fMAX

(GHz) at VCB

= 0.5 V

Data

Linear fit

• As expected MAG (given here at 120 GHz) is well correlated to fMAX

[Chevalier12]

SiGe HBT scaling

SiGe for mm-Wave and THz / P. Chevalier 15September 6, 2015

Benefits of scaling: NFmin

200 250 300 3501.0

1.5

2.0

2.5 F

min @ 60 GHz

Linear fit of Fmin

@ 60 GHz

Fmin

@ 100 GHz

Linear fit of Fmin

@ 100 GHz

Fm

in @

pe

ak

fT

fT (GHz) at V

CB = 0.5 V

• As expected minimum noise factor is well correlated to fT

)log(10 minmin FNF [Chevalier12]

SiGe HBT scaling

SiGe for mm-Wave and THz / P. Chevalier 16September 6, 2015

Benefits of scaling: Power

280 300 320 340 3601

2

3

4

5

6

7

0

5

10

15

20

25

30

0.09 µm0.12 µm0.13 µm WE (µm)

GT @

1d

B (

dB

), O

P1

dB

(d

Bm

)

Maximum oscillation frequency fMAX

(GHz)

OP1dB (dBm)

GT

OP1dB (mW/mm)

PAE

OP

1d

B (

mW

/µm

), P

AE

(%

)

• Power performance in class A at 94 GHz– Transducer gain GT improves with fMAX

– Output power (OP1dB) density remains constant

VBE ~ peak fT & fMAX

VCE = 1.2 V

[Chevalier12]

SiGe HBT scaling

SiGe for mm-Wave and THz / P. Chevalier 17September 6, 2015

Benefits of scaling: CML gate delay

2.0 2.5 3.0 3.5 4.02.0

2.5

3.0

3.5

4.0

Min

. G

ate

De

lay

Dm

in (

ps)

1/fMAX

(ps)

Data

Linear fit

• CML ring oscillator gate delay correlated to 1/fMAX

– 23-stage CML ring oscillator (LE = 1.5 µm, Vdd = 2.5 V, 400 mV differential voltage swing) with 1/217 static CML frequency divider

23 bipolar CML stages

Frequency divider (217):

17 bipolar stages

[Chevalier12]

SiGe HBT scaling

SiGe for mm-Wave and THz / P. Chevalier 18September 6, 2015

Outline

• Introduction

• SiGe HBT scaling

• 55nm BiCMOS

• Summary & perspectives

SiGe for mm-Wave and THz / P. Chevalier 19September 6, 2015

Technology overview

55nm triple-gate oxide CMOS baselineLP & GP HVT, SVT & LVT1 CMOS w/ 2.5V IOs + LP LVT & HVT SRAM

High-Performance Analog GO1 LP LVT CMOS1,2

Natural bipolar transistors, resistors & capacitors + 6 k/sq. HIPO resistor1

55-nm SiGe BiCMOS technology = BiCMOS055

Core process: 53 masks / Options: Up to +8 masks

SiGe NPN HBTs

(High-SpeedMedium-Voltage & High-Voltage1)

Varactors(MOS & Diode)

14V isolated GO2 MOS2

Thick copper BEOL 5 fF/µm² MIM1

Thin Film Resistor1,2

Transmission linesInductors

+ + +

(1) Option (2) Available end of 2015

55nm BiCMOS

SiGe for mm-Wave and THz / P. Chevalier 20September 6, 2015

Technology cross-sections

HS NPN

Si/SiGe HBTLP NMOS &

PMOS

GP NMOS &

PMOS

MIM

capacitor

HS SiGe HBT

0.45 µm² SRAM

M5

M4

M3

M2

M1

M7

M6

M8

RF MOM

capacitor

GO2 NMOS

& PMOS

Pull up transistors

(PMOS)

M1

M2

M3Shared

contact

Regular

contact

Collector

Emitter

Base

NiSi

Polybase

55nm BiCMOS

SiGe for mm-Wave and THz / P. Chevalier 21September 6, 2015

CMOS LP devices

55nm BiCMOS

-500 -400 -300 -200 -100-12

-11

-10

-9

-8

-7

LVT

SVT

HVT

Target

C065LPGP

B55

P-I

OF

F L

P (

log

(A)/

µm

)

P-ION

LP (µA/µm)

300 400 500 600 700 800-12

-11

-10

-9

-8

-7

SVT

HVT

Target

C065LPGP

B55

N-I

OF

F L

P (

log

(A)/

µm

)

N-ION

LP (µA/µm)

LVT

• CMOS centering for all the families (LP/GP) & flavors (HVT/SVT/LVT) demonstrated by the IOFF-ION plots

[Chevalier14]

SiGe for mm-Wave and THz / P. Chevalier 22September 6, 2015

CMOS GP devices

55nm BiCMOS

-600 -500 -400 -300 -200-10

-9

-8

-7

-6

-5

LVT

SVT

HVT

Target

C065LPGP

B55

P-I

OF

F G

P (

log

(A)/

µm

)

P-ION

GP (µA/µm)

600 700 800 900 1000 1100-10

-9

-8

-7

-6

-5

LVT

SVT

HVT

Target

C065LPGP

B55

N-I

OF

F G

P (

log

(A)/

µm

)

N-ION

GP (µA/µm)

• CMOS centering for all the families (LP/GP) & flavors (HVT/SVT/LVT) demonstrated by the IOFF-ION plots

[Chevalier14]

SiGe for mm-Wave and THz / P. Chevalier 23September 6, 2015

CMOS logic devices

55nm BiCMOS

5 10 15 200.01

0.1

1

10

100

1000

LP

GP

Target

C065LPGP

C055LP

B55

I ST

AT (

nA

)

TP (ps)

Wn=0.36µm, Wp=0.5µm, L=0.06µm

73 stages, 11 dividers

• CMOS centering is also assessed by the ring oscillator results

[Chevalier14]

SiGe for mm-Wave and THz / P. Chevalier 24September 6, 2015

SRAM bit cells

55nm BiCMOS

0 5 10 15 20 250

10

20

30

40

50

60

70

80

90

100

VMIN

(1.02 V)

VNOM

(1.20 V)

VMAX

(1.38 V)

Yie

ld (

%)

Wafer Slot

10 20 30 40 50 60-13

-12

-11

-10

-9

0.45LH0.50H

0.50S

Target

B55

C055LP

I SB (

log

(A)/

cell)

IREAD

(µA/cell)

• ISB vs IREAD aligned on C055LP

• Good yield and VDD stability, even for the smallest (0.45 µm²) bit cell of 5.25 Mb

0.45LH

[Chevalier14]

SiGe for mm-Wave and THz / P. Chevalier 25September 6, 2015

NPN SiGe HBTs – HF

55nm BiCMOS

0.01 0.1 1 10 1000

100

200

300

400

HS (VCB

= 0.5V)

MV (VCB

= 1.0V)

HV (VCB

= 2.5V)

f MA

X (

GH

z)

JC (mA/µm²)

0.01 0.1 1 10 1000

50

100

150

200

250

300

350

HS (VCB

= 0.5V)

MV (VCB

= 1.0V)

HV (VCB

= 2.5V)

f T (

GH

z)

JC (mA/µm²)

• 326 GHz fT / 376 GHz fMAX & 1.5 V BVCEO

demonstrated for the HS NPN

[Chevalier14]

SiGe for mm-Wave and THz / P. Chevalier 26September 6, 2015

NPN SiGe HBTs – HF

55nm BiCMOS

1 10 1000

50

100

150

200

250

300

350

400

fMAX

fitted from f • U

fMAX

measured from f •U

fT fitted from f / Im(1/h

21)

fT measured from f / Im(1/h

21)

f T a

nd

fM

AX (

GH

z)

at V

BE=

0.8

8V

Frequency f (GHz)

• fT and fMAX extractions

[Chevalier14]

SiGe for mm-Wave and THz / P. Chevalier 27September 6, 2015

NPN SiGe HBTs – Synthesis

55nm BiCMOS

NPN HS NPN MV NPN HV

Max fT (GHz)326

(VCB = 0.5V)178

(VCB = 1V)64

(VCB = 2.5V)

Max fMAX (GHz)376

(VCB = 0.5V)384

(VCB = 1V)269

(VCB = 2.5V)JC (mA/µm²)

at max fT & fMAX19 6.1 1.9

BVCBO (V) 5.4 7.3 14.4

BVCEO (V) 1.5 1.9 3.2

[Chevalier14]

SiGe for mm-Wave and THz / P. Chevalier 28September 6, 2015

HS NPN ring oscillators

55nm BiCMOS

2.25 2.30 2.35 2.40 2.45 2.50340

350

360

370

380

390

400

2.5

2.6

2.7

2.8

2.9

3.0

fMAX

fM

AX (

GH

z)

Ring oscillator gate delay D(ps)

1 / fMAX

1 / f

MA

X (

ps)

2.29 2.30 2.31 2.32 2.33 2.34 2.35 2.36 2.37 2.380

5

10

15

20

Fre

qu

en

cy

Ring oscillator gate delay D (ps)

Median = 2.343

Min = 2.297

Max = 2.376

= 0.80%

• 2.34 ps gate delay D for the reference with very good on wafer uniformity

• 2.28 ps D for 343 GHz fT / 391 GHz fMAX

23-stage CML RO (LE = 1.5 µm) with 1/217 static CML frequency divider

[Chevalier14]

SiGe for mm-Wave and THz / P. Chevalier 29September 6, 2015

HS NPN DC characteristics

55nm BiCMOS

0.0 0.2 0.4 0.6 0.8 1.0 1.210

-1410

-1310

-1210

-1110

-1010

-910

-810

-710

-610

-510

-410

-310

-210

-110

0

0

200

400

600

800

1000

1200

1400

1600

1800

2000 0.14.9µm²

30000.14.9µm²

(IC & I

B divided by 3000)

I C a

nd I

B (

A)

VBE

(V)

VCB

= 0 V

IB

Cu

rren

t ga

in

IC

0.0 0.5 1.0 1.50

2

4

6

8

10

I C (

mA

)

VCE

(V)

IB max

= 17 µA

• Good DC characteristics & yield

• Peak of current gain (~1900) is reached at VBE ~ 0.7 V

SiGe for mm-Wave and THz / P. Chevalier 30September 6, 2015

AMOS varactors

55nm BiCMOS

• P+ Poly / NWell GO1 & GO2 MOS varactors benefit from short MOS gate lengths

• GO2 (2.5V) varactors with minimum (GO1) gate lengths:

1 10 1008

10

12

14

0

20

40

60

80

100 C

Ca

pa

citan

ce C

at 1.8

V (

fF)

Frequency (GHz)

Qualit

y facto

r Q

Q

L=0.06µm, W=2µm, N=4, Mult=2

(drawn dimensions)

ParametersGO2 Varactors

P+ Poly / NWell

Capacitance range (Cmin / Cmax)

5 fF / 1 pF

Typical tuning ratio at 25 GHz & C=100 fF

3 (max 5)

Max Q at 25 GHz, C=100 fF, 2.5 V

30

Freq. of resonance at C=100 fF, 2.5 V

> 110 GHz

[Chevalier14]

SiGe for mm-Wave and THz / P. Chevalier 31September 6, 2015

Inductors & TL

55nm BiCMOS

0 200 400 600 800 10000

10

20

30

0

20

40

60

80

100 Q

MAX

Qu

alit

y fa

cto

r Q

MA

X

Inductance value LS (pH)

Fre

qu

en

cy F

at Q

MA

X (

GH

z)

F

• Transmission lines (TL) & inductors benefit from the specific thick BEOL (V7 + M8)

– 50 M8+Al TL: = 0.51 dB/mm at 60 GHz

– Inductors: 65 pH to 1.6 nH with Q > 10

1 turn4.25 turns

[Chevalier14]

SiGe for mm-Wave and THz / P. Chevalier 32September 6, 2015

Outline

• Introduction

• SiGe HBT scaling

• 55nm BiCMOS

• Summary & perspectives

SiGe for mm-Wave and THz / P. Chevalier 33September 6, 2015

Summary

Summary & perspectives

0

200

400

600

800

1000

1200

0

100

200

300

400

500

600

300 mm200 mm

55 nm90 nm

HS

NP

N p

ea

k f

T a

nd

fM

AX(G

Hz)

fT

fMAX

130 nm

BiC

MO

S9

MW

(

ST

)

INT

EL

BIC

MO

S9

HP

(

IBM

)

SG

13G

2 (

IHP

)

BiC

MO

S0

55

(S

T)

Sta

nd

ard

ce

lls

de

ns

ity

(K

ga

te/m

m²)

Wafer size

CMOS node

HS cells: ST data

HD cells: ST data

BIC

MO

S8

XP

(

IBM

)

IBM data

• BiCMOS055 provides a unique CMOS / SiGe HBT / passive devices combination

SiGe for mm-Wave and THz / P. Chevalier 34September 6, 2015

Perspectives

• 2nd 55nm BiCMOS generation (faster SiGe HBT)

– Still some margin to improve the performance of DPSA-SEG architecture but a new HBT architecture would be required to reach or exceed 500 GHz fMAX

• 28 nm FDSOI BiCMOS

– Very challenging CMOS / HBT integration requiring the development of a new HBT architecture too

Summary & perspectives

SiGe for mm-Wave and THz / P. Chevalier 35September 6, 2015

Acknowledgment & References

• Acknowledgment – Staff of STMicroelectronics, Crolles from TCAD, Process Development, Process Integration, Physical &

Electrical Characterization, Modeling, Design, … involved in the development of High-Speed BiCMOStechnologies with special thanks to G. Avenier, A. Montagné, G. Ribes, D. Céli, N. Derrier, D. Gloria, B. Sautreuil, and to the former PhD students T. Lacave & E. Canderle

– Thanks to Pr. S. Voinigescu (University of Toronto, ECE), Pr. M. Schröter (University of Dresden / UC San Diego), Pr. C. Gaquière (University of Lille, IEMN) & Pr. T. Zimmer (University of Bordeaux, IMS) and their teams for their support in circuit design, device modeling & characterization

– French Ministry of the Economy & of the Industry and the European Commission for their financial support through the projects:

• SIAM: MEDEA+_2T206 "Silicon analogue to millimetre-wave technologies"

• DOTFIVE: FP7-ICT_216110 "Towards 0.5 terahertz silicon / germanium heterojunction bipolar technology"

• SUCCESS: FP7-ICT_248120 "Silicon-based ultra-compact cost-efficient sensor system design“

• RF2THZ SISoC: CATRENE_CT209 "From RF to MMW and THz Silicon SOC Technologies“

• References– [Chevalier12] P. Chevalier et al, “Scaling of SiGe BiCMOS Technologies for Applications above 100 GHz”,

Compound Semiconductor Integrated Circuits Symposium (CSICS) Digest, 2012

– [Chevalier14] P. Chevalier et al, “A 55 nm Triple Gate Oxide 9 Metal Layers SiGe BiCMOS Technology Featuring 320 GHz fT / 370 GHz fMAX HBT and High-Q Millimeter-Wave Passives”, International Electron Devices Meeting Digest, 2014