50Msps 12-Bit SAR ADC IP Marketing Brief...12-Bit 50Msps Switch Capacitor SAR ADC Technology Global...
Transcript of 50Msps 12-Bit SAR ADC IP Marketing Brief...12-Bit 50Msps Switch Capacitor SAR ADC Technology Global...
![Page 1: 50Msps 12-Bit SAR ADC IP Marketing Brief...12-Bit 50Msps Switch Capacitor SAR ADC Technology Global Foundries 40nm CMOS Process Options 6L1x_1T6x_1T18x_LB Analog Supply Voltage 1.1V/1.8V](https://reader033.fdocuments.us/reader033/viewer/2022061001/60b0853b1952ad2ca638fa41/html5/thumbnails/1.jpg)
50Msps 12-Bit SAR ADC IP
Marketing Brief
Epoch Microelectronics, Inc.Valhalla, NY
© Epoch Microelectronics, Inc. 420 Columbus Avenue, Suite 204, Valhalla, NY 10595
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12-Bit 50Msps SAR ADC: Features/Deliverables
Features:
• Non-binary switch capacitor SAR ADC architecture that relaxes voltage reference
settling requirements
• Incorporates calibration logic to calibrate linearity of SAR ADC
• Includes delay lock loop for internal high speed clock generation
Deliverables:
• White Box:
• Cadence library including schematics, layout, and test benches
• GDS2, CDL netlist, DRC/LVS/ERC reports
• Verilog and .LIB files
• Evaluation report
• Black Box:
• GDS2, CDL netlist, DRC/LVS/ERC reports
• Verilog and .LIB files
• Encrypted SPICE netlist
• Evaluation report
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12-Bit 50Msps Switch Capacitor SAR ADC
Technology Global Foundries
40nm CMOS
Process Options 6L1x_1T6x_1T18x_LB
Analog Supply Voltage 1.1V/1.8V
Digital Supply Voltage 1.1V
Sampling Rate 50Msps
Input Voltage Swing 2.2Vppd
ENOB 9.4bit (10.2 @40Msps)
SNDR 58.1dB (63dB @40Msps)
Active Chip Area 0.15mm2
Power (Analog) 4.1mW
Power (Digital) 6.1mW
Status Respin needed – See
Errata Slide
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Measured Spectrum: TT Sample @ 12.5Msps
ENOB = 9.3 (uncalibrated) / 10.3 (calibrated)
Measurement Conditions: Vin = 2.2Vppd, Fs = 12.5Msps, Temp = Room, ADC Calibration = Disabled
Calibrated/adjusted ADC
0 1 2 3 4 5 6
x 106
-120
-100
-80
-60
-40
-20
0
Frequency (Hz)
Am
plitu
de
(d
B)
FFT Spectrum
SFDR = 72.2dB
SNDR = 63.9dB
SNR = 64.7dB
THD = -71.7dB
HD2 = -82.4dB
HD3 = -72.2dB
ENOB = 10.3Bits
0 1 2 3 4 5 6
x 106
-120
-100
-80
-60
-40
-20
0
Frequency (Hz)
Am
plitu
de
(d
B)
FFT Spectrum
SFDR = 71.2dB
SNDR = 58.0dB
SNR = 58.4dB
THD = -68.6dB
HD2 = -84.3dB
HD3 = -72.5dB
ENOB = 9.3Bits
Uncalibrated ADC
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Measured Spectrum: TT Sample @ 20Msps
ENOB = 9.3 (uncalibrated) / 10.1 (calibrated)
Measurement Conditions: Vin = 2.2Vppd, Fs = 20Msps, Temp = Room, ADC Calibration = Disabled
Calibrated/adjusted ADCUncalibrated ADC
0 1 2 3 4 5 6 7 8 9 10
x 106
-120
-100
-80
-60
-40
-20
0
Frequency (Hz)
Am
plitu
de
(d
B)
FFT Spectrum
SFDR = 70.3dB
SNDR = 57.5dB
SNR = 57.9dB
THD = -68.2dB
HD2 = -79.1dB
HD3 = -73.4dB
ENOB = 9.3Bits
0 1 2 3 4 5 6 7 8 9 10
x 106
-120
-100
-80
-60
-40
-20
0
Frequency (Hz)
Am
plitu
de
(d
B)
FFT Spectrum
SFDR = 74.2dB
SNDR = 62.4dB
SNR = 62.8dB
THD = -72.2dB
HD2 = -80.3dB
HD3 = -74.2dB
ENOB = 10.1Bits
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Measured Spectrum: TT Sample @ 30Msps
ENOB = 9.4 (uncalibrated) / 10.1 (calibrated)
Measurement Conditions: Vin = 2.2Vppd, Fs = 30Msps, Temp = Room, ADC Calibration = Disabled
Calibrated/adjusted ADCUncalibrated ADC
0 5 10 15
x 106
-120
-100
-80
-60
-40
-20
0
Frequency (Hz)
Am
plitu
de
(d
B)
FFT Spectrum
SFDR = 70.8dB
SNDR = 58.3dB
SNR = 58.7dB
THD = -68.0dB
HD2 = -75.8dB
HD3 = -73.2dB
ENOB = 9.4Bits
0 5 10 15
x 106
-120
-100
-80
-60
-40
-20
0
Frequency (Hz)
Am
plitu
de
(d
B)
FFT Spectrum
SFDR = 73.9dB
SNDR = 62.3dB
SNR = 62.8dB
THD = -71.8dB
HD2 = -73.9dB
HD3 = -76.3dB
ENOB = 10.1Bits
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Measured Spectrum: TT Sample @ 40Msps
ENOB = 9.4 (uncalibrated) / 10.2 (calibrated)
Measurement Conditions: Vin = 2.2Vppd, Fs = 40Msps, Temp = Room, ADC Calibration = Disabled
Calibrated/adjusted ADCUncalibrated ADC
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
x 107
-120
-100
-80
-60
-40
-20
0
Frequency (Hz)
Am
plitu
de
(d
B)
FFT Spectrum
SFDR = 71.4dB
SNDR = 58.5dB
SNR = 58.9dB
THD = -68.7dB
HD2 = -81.3dB
HD3 = -71.4dB
ENOB = 9.4Bits
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
x 107
-120
-100
-80
-60
-40
-20
0
Frequency (Hz)
Am
plitu
de
(d
B)
FFT Spectrum
SFDR = 72.1dB
SNDR = 63.0dB
SNR = 63.8dB
THD = -70.5dB
HD2 = -81.2dB
HD3 = -72.1dB
ENOB = 10.2Bits
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Measured Spectrum: TT Sample @ 50Msps
ENOB = 9.0 (uncalibrated) / 9.4 (calibrated)
Measurement Conditions: Vin = 2.2Vppd, Fs = 50Msps, Temp = Room, ADC Calibration = Disabled
Calibrated/adjusted ADCUncalibrated ADC
0 0.5 1 1.5 2 2.5
x 107
-120
-100
-80
-60
-40
-20
0
Frequency (Hz)A
mp
litu
de
(d
B)
FFT Spectrum
SFDR = 65.2dB
SNDR = 58.1dB
SNR = 60.0dB
THD = -62.5dB
HD2 = -66.0dB
HD3 = -65.2dB
ENOB = 9.4Bits
0 0.5 1 1.5 2 2.5
x 107
-120
-100
-80
-60
-40
-20
0
Frequency (Hz)
Am
plitu
de
(d
B)
FFT Spectrum
SFDR = 65.3dB
SNDR = 56.2dB
SNR = 57.5dB
THD = -62.2dB
HD2 = -65.3dB
HD3 = -65.6dB
ENOB = 9.0Bits
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Measured ENOB vs Sampling Frequency
Measurement shows degradation at 50Msps
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Measured SNDR vs Sampling Frequency
Measurement shows degradation at 50Msps
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Errata
(1) ADC calibration logic does not have enough range (i.e. bit length) and
MSB correction value saturates to maximum code. Verilog needs to be
updated and synthesis/P&R must be repeated to fix this issue.
(2) DLL DCO reset pulse is too long which results at shorter
sampling/conversion cycles not allowing time to settle at 50Msps
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Thank you!
© Epoch Microelectronics, Inc. 420 Columbus Avenue, Suite 204, Valhalla, NY 10595
Ken Suyama
Email: [email protected]
Phone: 914-332-8570x222