Device

OUT

FBGND

CIN

R1

CBYP

COUT

IN

EN

VIN

VOUT

R2

VEN

VIN

50 V

Product

Folder

Sample &Buy

Technical

Documents

Tools &

Software

Support &Community

TPS7A41SBVS183A –DECEMBER 2011–REVISED AUGUST 2015

TPS7A41 50-V Input Voltage, 50-mA, Very High Voltage Linear Regulator1 Features 3 Description

The TPS7A41 device is a very high voltage-tolerant1• Wide Input Voltage Range: 7 V to 50 V

linear regulator that offers the benefits of a thermally-• Accuracy: enhanced package (MSOP-8), and is able to– Nominal: 1% withstand continuous DC or transient input voltages

of up to 50 V.– Over Line, Load, and Temperature: 2.5%• Low Quiescent Current: 25 µA The TPS7A41 is stable with any output capacitance

greater than 4.7 µF and any input capacitance• Quiescent Current at Shutdown: 4.1 µAgreater than 1 µF (over temperature and tolerance).• Maximum Output Current: 50 mA Thus, implementations of this device require minimal

• CMOS Logic-Level-Compatible Enable Pin board space because of its miniaturized packaging(MSOP-8) and a potentially small output capacitor. In• Adjustable Output Voltage: about 1.175 V to 48 Vaddition, the TPS7A41 offers an enable pin (EN)• Stable with Ceramic Capacitors:compatible with standard CMOS logic, to enable a

– Input Capacitance: ≥ 1 µF low-current shutdown mode.– Output Capacitance: ≥ 4.7 µF The TPS7A41 has an internal thermal shutdown and

• Dropout Voltage: 290 mV current limiting to protect the system during faultconditions. The MSOP-8 packages has an operating• Built-In Current Limit and Thermal Shutdowntemperature range of TJ = –40°C to 125°C.Protection

• Package: High Thermal Performance MSOP-8 In addition, the TPS7A41 is ideal for generating aPowerPAD™ low-voltage supply from intermediate voltage rails in

telecom and industrial applications; not only can it• Operating Temperature Range: –40°C to 125°Csupply a well-regulated voltage rail, but it can alsowithstand and maintain regulation during very high2 Applications and fast voltage transients. These features translate

• Microprocessors, Microcontrollers Powered by to simpler and more cost-effective electrical surge-protection circuitry for a wide range of applications.Industrial Busses with High Voltage Transients

• Industrial AutomationDevice Information(1)

• Telecom InfrastrucurePART NUMBER PACKAGE BODY SIZE (NOM)

• AutomotiveTPS7A41 HVSSOP (8) 3.00 mm × 3.00 mm

• LED Lighting(1) For all available packages, see the orderable addendum at

• Bias Power Supplies the end of the data sheet.

Typical Application Diagram

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,intellectual property matters and other important disclaimers. PRODUCTION DATA.

TPS7A41SBVS183A –DECEMBER 2011–REVISED AUGUST 2015 www.ti.com

Table of Contents7.4 Device Functional Modes.......................................... 91 Features .................................................................. 1

8 Application and Implementation ........................ 102 Applications ........................................................... 18.1 Application Information............................................ 103 Description ............................................................. 18.2 Typical Application ................................................. 114 Revision History..................................................... 2

9 Power Supply Recommendations ...................... 125 Pin Configuration and Functions ......................... 310 Layout................................................................... 136 Specifications......................................................... 3

10.1 Layout Guidelines ................................................. 136.1 Absolute Maximum Ratings ..................................... 310.2 Layout Example .................................................... 136.2 ESD Ratings.............................................................. 410.3 Thermal Considerations ........................................ 136.3 Recommended Operating Conditions....................... 410.4 Power Dissipation ................................................. 146.4 Thermal Information .................................................. 410.5 Package Mounting ................................................ 146.5 Electrical Characteristics........................................... 5

11 Device and Documentation Support ................. 156.6 Dissipation Ratings ................................................... 511.1 Community Resources.......................................... 156.7 Typical Characteristics .............................................. 611.2 Trademarks ........................................................... 157 Detailed Description .............................................. 811.3 Electrostatic Discharge Caution............................ 157.1 Overview ................................................................... 811.4 Glossary ................................................................ 157.2 Functional Block Diagram ......................................... 8

12 Mechanical, Packaging, and Orderable7.3 Feature Description................................................... 8Information ........................................................... 15

4 Revision HistoryNOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Original (December 2011) to Revision A Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementationsection, Power Supply Recommendations section, Layout section, Device and Documentation Support section, andMechanical, Packaging, and Orderable Information section. ................................................................................................ 1

• Changed maximum Recommended Operation Conditions values for VIN, VOUT, and VEN. .............................................. 4

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FB

NC

GND

OUT

EN

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NC

IN

TPS7A41www.ti.com SBVS183A –DECEMBER 2011–REVISED AUGUST 2015

5 Pin Configuration and Functions

DGN Package8-Pin HVSSOP

Top View

Pin FunctionsPIN

I/O DESCRIPTIONNAME NO.

Regulator output. A capacitor greater than 4.7 µF must be tied from this pin to ground toOUT 1 O assure stability.This pin is the input to the control-loop error amplifier. It is used to set the output voltage ofFB 2 I the device.

3NC 6 — Not internally connected. This pin must either be left open or tied to GND.

7GND 4 — Ground

This pin turns the regulator on or off.If VEN ≥ VEN_HI the regulator is enabled.EN 5 I If VEN ≤ VEN_LO, the regulator is disabled.If not used, the EN pin can be connected to IN. Make sure that VEN ≤ VIN at all times.

IN 8 I Input supplySolder to printed-circuit-board (PCB) to enhance thermal performance.NOTE: The PowerPAD is internally connected to GND.PowerPAD — — Although it can be left floating, it is highly recommended to connect the PowerPAD to theGND plane.

6 Specifications

6.1 Absolute Maximum RatingsOver operating free-air temperature range (unless otherwise noted). (1)

MIN MAX UNIT

IN pin to GND pin –0.3 55 V

OUT pin to GND pin –0.3 55 V

OUT pin to IN pin –55 0.3 V

Voltage FB pin to GND pin –0.3 2 V

FB pin to IN pin –55 0.3 V

EN pin to IN pin –55 0.3 V

EN pin to GND pin –0.3 55 V

Current Peak output Internally limited

Operating junction temperature, TJ –40 125 °CTemperature

Storage, Tstg –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolute-maximum rated conditions for extended periods may affect device reliability.

Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 3

TPS7A41SBVS183A –DECEMBER 2011–REVISED AUGUST 2015 www.ti.com

6.2 ESD RatingsVALUE UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2500V(ESD) Electrostatic discharge VCharged-device model (CDM), per JEDEC specification JESD22- ±500C101 (2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditionsover operating junction temperature range (unless otherwise noted)

MIN NOM MAX UNITVIN 7 50 VVOUT 1.161 48 VVEN 0 50 VIOUT 0 50 mA

6.4 Thermal InformationTPS7A41

THERMAL METRIC (1) DGN (HVSSOP) UNIT8 PINS

RθJA Junction-to-ambient thermal resistance 66.7 °C/WRθJC(top) Junction-to-case (top) thermal resistance 54.1 °C/WRθJB Junction-to-board thermal resistance 38.1 °C/WψJT Junction-to-top characterization parameter 2 °C/WψJB Junction-to-board characterization parameter 37.8 °C/WRθJC(bot) Junction-to-case (bottom) thermal resistance 15.5 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics applicationreport, SPRA953.

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6.5 Electrical CharacteristicsAt TJ = –40°C to 125°C, VIN = VOUT(NOM) + 2 V or VIN = 7 V (whichever is greater), VEN = VIN, IOUT = 100 µA, CIN = 1 μF, COUT = 4.7 μF, andFB tied to OUT, unless otherwise noted.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITVIN Input voltage range 7 50 VVREF Internal reference TJ = 25°C, VFB = VREF, VIN = 9 V, IOUT = 25 mA 1.161 1.173 1.185 V

Output voltage range (1) VIN ≥ VOUT(NOM) + 2 V VREF 48 VNominal accuracy TJ = 25°C, VIN = 9 V, IOUT = 25 mA –1 1 %VOUTVOUT

VOUT(NOM) + 2 V ≤ VIN ≤ 24 V (2)Overall accuracy –2.5 2.5 %VOUT100 µA ≤ IOUT ≤ 50 mA

ΔVO(ΔVI) Line regulation 7 V ≤ VIN ≤ 50 V 0.03 %VOUT

ΔVO(ΔVL) Load regulation 100 µA ≤ IOUT ≤ 50 mA 0.31 %VOUT

VIN = 17 V, VOUT(NOM) = 18 V, IOUT = 20 mA 290 mVVDO Dropout voltage

VIN = 17 V, VOUT(NOM) = 18 V, IOUT = 50 mA 0.78 1.3 VVOUT = 90% VOUT(NOM), VIN = 7 V, TJ ≤ 85°C 51 117 200 mA

ILIM Current limitVOUT = 90% VOUT(NOM), VIN = 9 V 51 128 200 mA7 V ≤ VIN ≤ 50 V, IOUT = 0 mA 25 65 μA

IGND Ground currentIOUT = 50 mA 25 μA

ISHDN Shutdown supply current VEN = 0.4 V 4.1 20 μAI FB Feedback current (3) –0.1 0.01 0.1 µAIEN Enable current 7 V ≤ VIN ≤ 50 V, VIN = VEN 0.02 1 μAVEN_HI Enable high-level voltage 1.5 VIN VVEN_LO Enable low- level voltage 0 0.4 V

VIN = 12 V, VOUT(NOM) = VREF, COUT = 10 μF, 58 μVRMSBW = 10 Hz to 100 kHzVNOISE Output noise voltage

VIN = 12 V, VOUT(NOM) = 5 V, COUT = 10 μF, 73 μVRMSCBYP(4) = 10 nF, BW = 10 Hz to 100 kHz

VIN = 12 V, VOUT(NOM) = 5 V, COUT = 10 μF,PSRR Power-supply rejection ratio 65 dBCBYP(4) = 10 nF, f = 100 Hz

Shutdown, temperature increasing 170 °CTSD Thermal shutdown temperature

Reset, temperature decreasing 150 °COperating junction temperatureTJ –40 125 °Crange

(1) To ensure stability at no-load conditions, a current from the feedback resistive network greater than or equal to 10 μA is required.(2) Maximum input voltage is limited to 24 V because of the package power dissipation limitations at full load (P ≈ (VIN – VOUT) × IOUT = (24

V – VREF) × 50 mA ≈ 1.14 W). The device is capable of sourcing a maximum current of 50 mA at higher input voltages as long as thepower dissipated is within the thermal limits of the package plus any external heatsinking.

(3) IFB > 0 flows out of the device.(4) CBYP refers to a bypass capacitor connected to the FB and OUT pins.

6.6 Dissipation RatingsDERATING FACTOR TA ≤ 25°C POWER TA = 70°C POWER TA = 85°C POWER

BOARD PACKAGE RθJA RθJC ABOVE TA = 25°C RATING RATING RATING

High-K (1) DGN 55.9°C/W 8.47°C/W 16.6 mW/°C 1.83 W 1.08 W 0.833 W

(1) The JEDEC High-K (2s2p) board design used to derive this data was a 3-inch x 3-inch multilayer board with 2-ounce internal power andground planes and 2-ounce copper traces on top and bottom of the board.

Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 5

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10

20

30

40

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−40 −25 −10 5 20 35 50 65 80 95 110 125Temperature (°C)

I FB (

nA)

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50

60

70

80

90

100

0 10 20 30 40 50Output Current (mA)

I GN

D (

µA)

− 40°C+ 25°C+ 85°C+ 105°C+ 125°C

1.075

1.125

1.175

1.225

1.275

5 10 15 20 25 30 35 40 45 50Input Voltage (V)

VF

B (

V)

−40°C+25°C+85°C

+105°C+125°C

G002

0

20

40

60

80

100

5 10 15 20 25 30 35 40 45 50Input Voltage (V)

I Q (

µA)

−40°C+25°C+85°C+105°C+125°C

IOUT = 0 mA

G003

Time (100 s/div)m

V = 12V, V = 5V

1mA

C = 10 F, C = 10nF

I = 1mA 29mAD ® ®

m

IN OUT

OUT BYP

OUT

IOUT

VOUT

10mA/div

50mV/div

−10

−7.5

−5

−2.5

0

2.5

5

7.5

10

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VO

UT

(NO

M) (

%)

−40°C+25°C+85°C

+105°C+125°C

G001

TPS7A41SBVS183A –DECEMBER 2011–REVISED AUGUST 2015 www.ti.com

6.7 Typical CharacteristicsAt TJ = –40°C to 125°C, VIN = VOUT(NOM) + 2 V or VIN = 9 V (whichever is greater), VEN = VIN, IOUT = 100 µA, CIN = 1 μF, COUT =4.7 μF, and FB tied to OUT, unless otherwise noted.

Figure 2. Line RegulationFigure 1. Load Transient Response

Figure 3. Feedback Voltage Figure 4. Quiescent Current vs Input Voltage

Figure 5. Feedback Current Figure 6. Ground Current

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10 100 1k 10k 100k 1M 10MFrequency (Hz)

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VIN = 12VVOUT = 5VCOUT = 10µFCBYP = 10nF

0.001

0.01

0.1

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10

10 100 1k 10k 100k 1M 10MFrequency (Hz)

Noi

se (

µV/

Hz

)

IOUT = 100µA,VNOISE = 60µVRMSIOUT = 50mA,VNOISE = 100µVRMS

VIN = 12VVOUT = VREFCOUT = 10µFCBYP = 10nF

0

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I CL

(mA

)

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+ 125°C

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V)

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+ 105°C+ 125°C

0

0.5

1

1.5

2

2.5

−40 −25 −10 5 20 35 50 65 80 95 110 125

Vsub (EN_LO)

Vsub (EN_HI)

Temperature (°C)

VE

N(V

)

TPS7A41www.ti.com SBVS183A –DECEMBER 2011–REVISED AUGUST 2015

Typical Characteristics (continued)At TJ = –40°C to 125°C, VIN = VOUT(NOM) + 2 V or VIN = 9 V (whichever is greater), VEN = VIN, IOUT = 100 µA, CIN = 1 μF, COUT =4.7 μF, and FB tied to OUT, unless otherwise noted.

Figure 8. Enable Threshold VoltageFigure 7. Dropout Voltage

Figure 10. Current LimitFigure 9. Output Spectral Noise Density

Figure 11. Power-Supply Rejection Ratio

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UVLO

Thermal

Shutdown

Current

Limit

EnableError

Amp

IN

EN

OUT

FB

Pass

Device

TPS7A41SBVS183A –DECEMBER 2011–REVISED AUGUST 2015 www.ti.com

7 Detailed Description

7.1 OverviewThe TPS7A4101 belongs to a new generation of linear regulators that use an innovative BiCMOS processtechnology to achieve very high maximum input and output voltages.

This process not only allows the TPS7A4101 to maintain regulation during very fast high-voltage transients up to50 V, but it also allows the TPS7A4101 to regulate from a continuous high-voltage input rail. Unlike otherregulators created using bipolar technology, the TPS7A4101 ground current is also constant over its outputcurrent range, resulting in increased efficiency and lower power consumption.

These features, combined with a high thermal performance MSOP-8 PowerPAD package, make this device idealfor industrial and telecom applications.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Enable Pin OperationThe TPS7A4101 provides an enable pin (EN) feature that turns on the regulator when VEN > 1.5 V.

7.3.2 Thermal ProtectionThermal protection disables the output when the junction temperature rises to approximately 170°C, allowing thedevice to cool. When the junction temperature cools to approximately 150°C, the output circuitry is enabled.Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit maycycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage as a result ofoverheating.

Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequateheatsink. For reliable operation, limit junction temperature to a maximum of 125°C. To estimate the margin ofsafety in a complete design (including heatsink), increase the ambient temperature until the thermal protection istriggered; use worst-case loads and signal conditions. For good reliability, trigger thermal protection at least 35°Cabove the maximum expected ambient condition of your particular application. This configuration produces aworst-case junction temperature of 125°C at the highest expected ambient temperature and worst-case load.

The internal protection circuitry of the TPS7A41 device has been designed to protect against overload conditions.The protection circuitry was not intended to replace proper heatsinking. Continuously running the TPS7A4001device into thermal shutdown degrades device reliability.

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7.4 Device Functional Modes

7.4.1 Normal OperationThe device regulates to the nominal output voltage under the following conditions:• The input voltage is at least as high as VIN(min).• The input voltage is greater than the nominal output voltage added to the dropout voltage.• The enable voltage has previously exceeded the enable rising threshold voltage and has not decreased

below the enable falling threshold.• The output current is less than the current limit.• The device junction temperature is less than the maximum specified junction temperature.

7.4.2 Dropout OperationIf the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all otherconditions are met for normal operation, the device operates in dropout mode. In this mode of operation, theoutput voltage is the same as the input voltage minus the dropout voltage. The transient performance of thedevice is significantly degraded because the pass device (as a bipolar junction transistor, or BJT) is in saturationand no longer controls the current through the LDO. Line or load transients in dropout can result in large outputvoltage deviations.

7.4.3 DisabledThe device is disabled under the following conditions:• The enable voltage is less than the enable falling threshold voltage or has not yet exceeded the enable rising

threshold.• The device junction temperature is greater than the thermal shutdown temperature.

Table 1 lists the conditions that lead to the different modes of operation.

Table 1. Device Functional Mode ComparisonPARAMETER

OPERATING MODEVIN VEN IOUT TJ

VIN > VOUT(nom) + VDO andNormal mode VEN > VEN_HI IOUT < ILIM T J < 125°CVIN > VIN(min)

Dropout mode VIN(min) < VIN < VOUT(nom) + VDO VEN > VEN_HI — TJ < 125°CDisabled mode — VEN < VEN_LO — TJ > 170°C(any true condition disables the device)

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VOUT

VREF

- 1R = R1 2

VOUT

R + R1 2

³ 10 Am, where

Device

OUT

FBGND

C

10 F

IN

mR

1

C

10 nF

BYP

C

10 F

OUT

m

IN

EN

VIN

VOUT

R2

TPS7A41SBVS183A –DECEMBER 2011–REVISED AUGUST 2015 www.ti.com

8 Application and Implementation

NOTEInformation in the following applications sections is not part of the TI componentspecification, and TI does not warrant its accuracy or completeness. TI’s customers areresponsible for determining suitability of components for their purposes. Customers shouldvalidate and test their design implementation to confirm system functionality.

8.1 Application Information

8.1.1 Adjustable OperationThe TPS7A4101 has an output voltage range of approximately 1.175 V to 48 V. The nominal output voltage ofthe device is set by two external resistors, as shown in Figure 12.

Figure 12. Adjustable Operation for Maximum AC Performance

R1 and R2 can be calculated for any output voltage range using the formula shown in Equation 1. To ensurestability under no-load conditions, this resistive network must provide a current greater than or equal to 10 μA.

(1)

If greater voltage accuracy is required, take into account the output voltage offset contributions because of thefeedback pin current and use 0.1% tolerance resistors.

8.1.2 Transient Voltage ProtectionOne of the primary applications of the TPS7A4101 is to provide transient voltage protection to sensitive circuitrythat may be damaged in the presence of high-voltage spikes.

This transient voltage protection can be more cost-effective and compact compared to topologies that use atransient voltage suppression (TVS) block.

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Where:VOUT

R + R1 2

³ 10 A, andm

VOUT

VREF

- 1R = R1 2

Device

OUT

FBGND

C

10 F

IN

m R1

C

10 nF

BYP

C

10 F

OUT

m

IN

EN

VIN VOUT

R2

VEN

TPS7A41www.ti.com SBVS183A –DECEMBER 2011–REVISED AUGUST 2015

8.2 Typical Application

Figure 13. Example Circuit to Maximize Transient Performance

8.2.1 Design RequirementsFor this design example, use the following parameters listed in Table 2.

Table 2. Design ParametersPARAMETER VALUE

VIN 12 V, with 50 V surge toleranceVOUT 5 V (ideal), 4.981 V (actual)IOUT 28 mA

Accuracy 5 %R1, R2 162 kΩ, 49.9 kΩ

8.2.2 Detailed Design ProcedureThe maximum value of total feedback resistance can be calculated to be 500 kΩ. Equation 1 was used tocalculate R1 and R2, and standard 1% resistors were selected to keep the accuracy within the 5% allocation. 10-uF ceramic input and output capacitors were selected, along with a 10-nF bypass capacitor for optimal ACperformance.

8.2.2.1 Capacitor RecommendationsLow equivalent series resistance (ESR) capacitors should be used for the input, output, and bypass capacitors.Ceramic capacitors with X7R and X5R dielectrics are preferred. These dielectrics offer more stablecharacteristics. Ceramic X7R capacitors offer improved over-temperature performance, while ceramic X5Rcapacitors are the most cost-effective and are available in higher values.

High ESR capacitors may degrade PSRR.

8.2.2.2 Input and Output Capacitor RequirementsThe TPS7A4101 high voltage linear regulator achieves stability with a minimum output capacitance of 4.7 µF andinput capacitance of 1 µF; however, TI highly recommends using 10-μF output and input capacitors to maximizeAC performance.

8.2.2.3 Bypass Capacitor RequirementsAlthough a bypass capacitor (CBYP) is not needed to achieve stability, TI highly recommends using a 10-nFbypass capacitor to maximize AC performance (including line transient, noise and PSRR).

8.2.2.4 Maximum AC PerformanceTo maximize line transient, noise, and PSRR performance, TI recommends including 10-μF (or higher) input andoutput capacitors, and a 10-nF bypass capacitor; see Figure 12. The solution shown delivers minimum noiselevels of 58 μVRMS and power-supply rejection levels above 36 dB from 10 Hz to 10 MHz.

8.2.2.5 Transient ResponseAs with any regulator, increasing the size of the output capacitor reduces over/undershoot magnitude butincreases duration of the transient response.

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Time (1ms/div)

100mV/div

VIN

VOUT

VOUT100mV/div

C = 0nFBYP

C = 10nFBYP

V = 5V, I = 28mA,

V Slew Rate = 220V/ms

V = 12V 55V

C = 10 Fm

D ®

OUT

IN

OUT

IN

OUT

50V/div

TPS7A41SBVS183A –DECEMBER 2011–REVISED AUGUST 2015 www.ti.com

The presence of the CBYP capacitor may greatly improve the TPS7A4101 line transient response, as noted inFigure 1.

8.2.3 Application Curve

Figure 14. Line Transient Response vs CBYP

9 Power Supply RecommendationsThe input supply for the LDO should not exceed its recommended operating conditions (7 V to 50 V). The inputvoltage should provide adequate headroom for the device to have a regulated output. If the input supply is noisy,additional input capacitors with low ESR can help improve the output noise performance. The input and outputsupplies should also be bypassed with 10-µF capacitors located near the input and output pins. There should beno other components located between these capacitors and the pins.

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1

2

3

4

8

7

6

5

OUT

FB

NC

GND

IN

NC

EN

Input GND Plane

Output GND Plane

VinThermal

Pad

Cout

R2

Sense Line

Vout

Cin

R1

NC

TPS7A41www.ti.com SBVS183A –DECEMBER 2011–REVISED AUGUST 2015

10 Layout

10.1 Layout GuidelinesTo improve AC performance such as PSRR, output noise, and transient response, TI recommends designing theboard with separate ground planes for IN and OUT, with each ground plane connected only at the GND pin ofthe device. In addition, the ground connection for the output capacitor should connect directly to the GND pin ofthe device.

Equivalent series inductance (ESL) and ESR must be minimized to maximize performance and ensure stability.Every capacitor (CIN, COUT, CBYP) must be placed as close as possible to the device and on the same side of thePCB as the regulator itself.

Do not place any of the capacitors on the opposite side of the PCB from where the regulator is installed. The useof vias and long traces is strongly discouraged because they may impact system performance negatively andeven cause instability.

If possible, and to ensure the maximum performance denoted in this product data sheet, use the same layoutpattern used for TPS7A41 evaluation board, available at www.ti.com.

10.2 Layout Example

Figure 15. Recommended Layout Example

10.3 Thermal ConsiderationsThermal protection disables the output when the junction temperature rises to approximately 170°C, allowing thedevice to cool. When the junction temperature cools to approximately 150°C, the output circuitry is enabled.Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit maycycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage as a result ofoverheating.

Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequateheatsink. For reliable operation, junction temperature should be limited to a maximum of 125°C. To estimate themargin of safety in a complete design (including heatsink), increase the ambient temperature until the thermalprotection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection shouldtrigger at least 35°C above the maximum expected ambient condition of the particular application. Thisconfiguration produces a worst-case junction temperature of 125°C at the highest expected ambient temperatureand worst-case load.

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P = (V V ) I-D IN OUT OUT

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Thermal Considerations (continued)The internal protection circuitry of the TPS7A4101 has been designed to protect against overload conditions. Itwas not intended to replace proper heatsinking. Continuously running the TPS7A4101 into thermal shutdowndegrades device reliability.

10.4 Power DissipationThe ability to remove heat from the die is different for each package type, presenting different considerations inthe PCB layout. The PCB area around the device that is free of other components moves the heat from thedevice to the ambient air. Performance data for JEDEC low- and high-K boards are given in the DissipationRatings. Using heavier copper increases the effectiveness in removing heat from the device. The addition ofplated through-holes to heat dissipating layers also improves the heatsink effectiveness.

Power dissipation depends on input voltage and load conditions. Power dissipation (PD) is equal to the product ofthe output current times the voltage drop across the output pass element, as shown in Equation 2:

(2)

10.5 Package MountingSolder pad footprint recommendations for the TPS7A4101 are available at Mechanical, Packaging, andOrderable Information and at www.ti.com.

14 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated

TPS7A41www.ti.com SBVS183A –DECEMBER 2011–REVISED AUGUST 2015

11 Device and Documentation Support

11.1 Community ResourcesThe following links connect to TI community resources. Linked contents are provided "AS IS" by the respectivecontributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms ofUse.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaborationamong engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and helpsolve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools andcontact information for technical support.

11.2 TrademarksPowerPAD, E2E are trademarks of Texas Instruments.All other trademarks are the property of their respective owners.

11.3 Electrostatic Discharge CautionThese devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.

11.4 GlossarySLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable InformationThe following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and revision ofthis document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 15

PACKAGE OPTION ADDENDUM

www.ti.com 25-Jun-2015

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead/Ball Finish(6)

MSL Peak Temp(3)

Op Temp (°C) Device Marking(4/5)

Samples

TPS7A4101DGNR ACTIVE MSOP-PowerPAD

DGN 8 2500 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM -40 to 125 SBB

TPS7A4101DGNT ACTIVE MSOP-PowerPAD

DGN 8 250 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM -40 to 125 SBB

(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availabilityinformation and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement thatlead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used betweenthe die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weightin homogeneous material)

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finishvalue exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

PACKAGE OPTION ADDENDUM

www.ti.com 25-Jun-2015

Addendum-Page 2

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device PackageType

PackageDrawing

Pins SPQ ReelDiameter

(mm)

ReelWidth

W1 (mm)

A0(mm)

B0(mm)

K0(mm)

P1(mm)

W(mm)

Pin1Quadrant

TPS7A4101DGNR MSOP-Power PAD

DGN 8 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1

TPS7A4101DGNT MSOP-Power PAD

DGN 8 250 180.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 25-Jun-2015

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TPS7A4101DGNR MSOP-PowerPAD DGN 8 2500 346.0 346.0 35.0

TPS7A4101DGNT MSOP-PowerPAD DGN 8 250 203.0 203.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 25-Jun-2015

Pack Materials-Page 2

IMPORTANT NOTICE

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