Microcontroller Intel 8051[Instruction Set]

Structure of Assembly Language[ label: ]mnemonic[operands][ ;comment ]

Example:

MOVR1, #25H; load data 25H into R1*

8051 Assembly LanguageRegisters*MOV Instruction:

MOVdestination, source

Example:MOV A, $55HMOV R0, AMOV A, R3

Instruction GroupsThe 8051 has 255 instructionsEvery 8-bit opcode from 00 to FF is used except for A5.

The instructions are grouped into 5 groupsArithmeticLogicData TransferBooleanBranching

Arithmetic InstructionsADD8-bit addition between the accumulator (A) and a second operand.The result is always in the accumulator.The CY flag is set/reset appropriately.

ADDC8-bit addition between the accumulator, a second operand and the previous value of the CY flag.Useful for 16-bit addition in two steps.The CY flag is set/reset appropriately.

Arithmetic InstructionsDADecimal adjust the accumulator.Format the accumulator into a proper 2 digit packed BCD number.Operates only on the accumulator.Works only after the ADD instruction.

SUBBSubtract with Borrow.Subtract an operand and the previous value of the borrow (carry) flag from the accumulator.A A - - CY.The result is always saved in the accumulator.The CY flag is set/reset appropriately.

Arithmetic InstructionsINCIncrement the operand by one.The operand can be a register, a direct address, an indirect address, the data pointer.

DECDecrement the operand by one.The operand can be a register, a direct address, an indirect address.

MUL AB / DIV ABMultiply A by B and place result in A:B.Divide A by B and place result in A:B.

Logical OperationsANL / ORLWork on byte sized operands or the CY flag.ANL A, RnANL A, directANL A, @RiANL A, #dataANL direct, AANL direct, #dataANL C, bitANL C, /bit

Logical OperationsXRLWorks on bytes only.

CPL / CLRComplement / Clear.Work on the accumulator or a bit.CLRP1.2

Logical OperationsRL / RLC / RR / RRCRotate the accumulator.RL and RR without the carryRLC and RRC rotate through the carry.

SWAP ASwap the upper and lower nibbles of the accumulator.

No compare instruction.Built into conditional branching instructions.

Data Transfer InstructionsMOV8-bit data transfer for internal RAM and the SFR.MOV A, RnMOV A, directMOV A, @RiMOV A, #dataMOV Rn, AMOV Rn, directMOV Rn, #dataMOV direct, AMOV direct, RnMOV direct, directMOV direct, @RiMOV direct, #dataMOV @Ri, AMOV @Ri, directMOV @Ri, #data

Data Transfer OperationsMOV1-bit data transfer involving the CY flagMOV C, bitMOV bit, C

MOV16-bit data transfer involving the DPTRMOV DPTR, #data

Data Transfer InstructionsMOVCMove Code ByteLoad the accumulator with a byte from program memory.Must use indexed addressing

MOVCA, @A+DPTRMOVCA, @A+PC

Data Transfer InstructionsMOVXData transfer between the accumulator and a byte from external data memory.MOVXA, @RiMOVXA, @DPTRMOVX@Ri, AMOVX@DPTR, A

Data Transfer InstructionsPUSH / POPPush and Pop a data byte onto the stack.The data byte is identified by a direct address from the internal RAM locations.

PUSHDPLPOP40H

Data Transfer InstructionsXCHExchange accumulator and a byte variableXCHA, RnXCHA, directXCHA, @Ri

XCHDExchange lower digit of accumulator with the lower digit of the memory location specified.XCHD A, @RiThe lower 4-bits of the accumulator are exchanged with the lower 4-bits of the internal memory location identified indirectly by the index register.The upper 4-bits of each are not modified.

Boolean OperationsThis group of instructions is associated with the single-bit operations of the 8051.This group allows manipulating the individual bits of bit addressable registers and memory locations as well as the CY flag.The P, OV, and AC flags cannot be directly altered.

This group includes:Set, clear, and, or complement, move.Conditional jumps.

Boolean OperationsCLRClear a bit or the CY flag.CLR P1.1CLR C

SETBSet a bit or the CY flag.SETB A.2SETB C

CPLComplement a bit or the CY flag.CPL 40H; Complement bit 40 of the bit addressable memory

Boolean OperationsORL / ANLOR / AND a bit with the CY flag.ORLC, 20H; OR bit 20 of bit addressable ; memory with the CY flag

ANLC, /34H; AND complement of bit 34 of bit addressable memory with the CY flag.MOVData transfer between a bit and the CY flag.MOVC, 3FH; Copy the CY flag to bit 3F of the bit addressable memory.MOVP1.2, C; Copy the CY flag to bit 2 of P1.

Boolean OperationsJC / JNCJump to a relative address if CY is set / cleared.

JB / JNBJump to a relative address if a bit is set / cleared.JBACC.2,

JBCJump to a relative address if a bit is set and clear the bit.

Branching InstructionsThe 8051 provides four different types of unconditional jump instructions:Short Jump SJMPUses an 8-bit signed offset relative to the 1st byte of the next instruction.Long Jump LJMPUses a 16-bit address.3 byte instruction capable of referencing any location in the entire 64K of program memory.

Branching InstructionsAbsolute Jump AJMPUses an 11-bit address.2 byte instructionThe upper 3-bits of the address combine with the 5-bit opcode to form the 1st byte and the lower 8-bits of the address form the 2nd byte.The 11-bit address is substituted for the lower 11-bits of the PC to calculate the 16-bit address of the target.The location referenced must be within the 2K Byte memory page containing the AJMP instruction.

Indirect Jump JMPJMP@A + DPTR

Branching InstructionsThe 8051 provides 2 forms for the CALL instruction:Absolute Call ACALLUses an 11-bit address similar to AJMPThe subroutine must be within the same 2K page.Long Call LCALLUses a 16-bit address similar to LJMPThe subroutine can be anywhere.

Both forms push the 16-bit address of the next instruction on the stack and update the stack pointer.

Branching InstructionsThe 8051 provides 2 forms for the return instruction:Return from subroutine RETPop the return address from the stack and continue execution there.Return from ISV RETIPop the return address from the stack.Restore the interrupt logic to accept additional interrupts at the same priority level as the one just processed.Continue execution at the address retrieved from the stack.The PSW is not automatically restored.

Branching InstructionsThe 8051 supports 5 different conditional jump instructions.ALL conditional jump instructions use an 8-bit signed offset.

Jump on Zero JZ / JNZJump if the A == 0 / A != 0The check is done at the time of the instruction execution.

Jump on Carry JC / JNCJump if the C flag is set / cleared.

Branching InstructionsJump on Bit JB / JNBJump if the specified bit is set / cleared.Any addressable bit can be specified.

Jump if the Bit is set then Clear the bit JBCJump if the specified bit is set.Then clear the bit.

Branching InstructionsCompare and Jump if Not Equal CJNECompare the magnitude of the two operands and jump if they are not equal.The values are considered to be unsigned.The Carry flag is set / cleared appropriately.

CJNEA, direct, relCJNEA, #data, relCJNERn, #data, relCJNE@Ri, #data, rel

Branching InstructionsDecrement and Jump if Not Zero DJNZDecrement the first operand by 1 and jump to the location identified by the second operand if the resulting value is not zero.

DJNZRn, relDJNZdirect, rel

No OperationNOP

Addressing ModesFive addressing modes are available:ImmediateRegisterDirectIndirectIndexed

There are three more modes:RelativeAbsoluteLongThese are used with calls, branches and jumps and are handled automatically by the assembler.

Immediate AddressingThe data is directly specified in the instruction.Useful for getting constants into registers.Immediate data must be preceded with a # sign.

MOVR0, #0F0H; Load R0 with the value F0H

The immediate value is a maximum of 8-bits.One exception, when dealing with the DPTR register it can be 16-bits.

MOVDPTR, #2000H; Load the value 2000H into the DPTR register

Register Addressing ModeDirect access to eight registers R0 through R7.MOVA, R0MOVR1, AADDA, R1

Not all combinations are valid.MOVR2, R1; Invalid

There are 4 banks of registers accessible through register addressing.Only one bank can be accessed at a time controllable through bit RS0 and RS1 of the PSW.MOVPSW, #00011000BSet RS0:RS1 to 11, therefore, accessing register bank 3.

Direct AddressingDirect addressing can access any on-chip hardware register.All on-chip memory locations and registers have 8-bit addresses.

Can use the 8-bit address in the instruction.MOVA, 4H; Amem[04H]

Or can use the register name.MOVA, R4

Dont get confused with Immediate mode.No # sign.

Indirect AddressingR0 and R1 may be used as pointer registers where their contents indicate an address in internal RAM where the data is to be read or written.

MOVR1, #40H ; Make R1 point to location 40

MOVA, @R1 ; Move the contents of 40H to A

MOV@R0, R1 ; Move contents of R1 into the ; memory location pointed to by R0.

Indirect AddressingCan also be used for accessing external memory:Can use R0 and R1 to point to external memory locations 00H to FFH.

MOVX A, @R1; Move contents of external memory location whose address is in R1 into A

Can also use DPTR to point to all 64k of external memory.MOVX A, @DPTR

Indexed AddressingUse a register for storing a pointer to memory and another register for storing an offset.The effective address is the sum of the two:EA = Pointer + Offset

MOVC A, @A+DPTR; Move byte from memory located at DPTR+A to A.

Program Control InstructionsUnconditional Branchajmp addr11 ; absolute jumpljmp addr16 ; long jumpsjmp rel ; short jump to relative addressjmp @A+DPTR ; jump indirect

Conditional branchjz, jnz rel ; short conditional jump to rel. addrdjnz rel ; decrement and jump if not zerocjne rel ; compare and jump if not equal

Subroutine Callacall addr11 ; absolute subroutine calllcall addr16 ; long subroutine callret ; return from subroutine callreti ; return from ISV

Target AddressTarget address can be,absolute: A complete physical addressaddr16: 16 bit address, anywhere in the 64kaddr11: 11 bit address, anywhere within 2k page.rel: relative (forward or backward) -128 bytes to +127 bytes from the current code locationTarget address calculation for relative jumpsPC of next instruction + rel addressFor jump backwards, drop the carryPC = 15H, SJMP 0FEHAddress is 15H + FEH = 13HBasically jump to next instruction minus two (current instruction)

Conditional Jumpsjz, jnz : Conditional on A=0Checks to see if A is zerojz jumps if A is zero and jnz jumps is A not zeroNo arithmetic op need be performed (unlike 8086/8085)djnz : dec a byte and jump if not equal to zerodjnz Rn, reldjnz direct, reljnc : Conditional on carry CY flagjc reljnc relcjne : compare and jump if not equalcjne A, direct, relcjne Rn, #data, relcjne @Rn, #data, rel

Loop using djnzAdd 3 to A ten times mov A, #0 ; clear A mov R2, #10 ; R2 10, can also say 0AHAGAIN: add A, #03 ; add 3 to A djnz R2, AGAIN ; repeat until R2==0 mov R5, A ; save the result in R5

Loop within loop using djnz mov R3, #100loop1: mov R2, #10 ; trying for 1000 loop iterationsloop2: nop ; no operation djnz R2, loop2 ; repeat loop2 until R2==0 djnz R3, loop1 ; repeat loop1 until R3==0

Unconditional JumpsLJMP addr16Long jump. Jump to a 2byte target address3 byte instruction

SJMP relJump to a relative address from PC+127 to PC-128Jump to PC + 127 (00H 7FH)Jump to PC 128 (80H FFH)

Call InstructionsSubroutines:Reusable code snippetsLCALL addr16Long call.3 byte instruction.Call any subroutine in entire 64k code spacePC is stored on the stackACALL addr112 byte instructionCall any subroutine within 2k of code spaceOther than this, same behavior as LCALLSaves code ROM for devices with less than 64K ROMRETReturn from a subroutine call, Pops PC from stack