4C2 - Microelectronic Circuits I - TCDnaharte/index_files/4C2_2009_notes.pdf4C2 - Microelectronic...

4C2 - Microelectronic Circuits I

Organisation:

There will be 3 lectures plus 1 tutorial per week during Hilary Term for the course

Microelectronic Circuits I (4C2).

Examination:

The subject 4C2 is jointly examined with 4C6. The paper will be divided into two

sections. 10% of the overall mark is from an assignment for 4C2 during Hilary Term.

The remainder of the mark is from the written exam and assignment from 4C6.

Course Objectives:

• To develop an electrical understanding of the metal-oxide-semiconductor (MOS)

field effect transistor

• To treat the fundamental static and dynamic performance of simple CMOS circuits

noting design trade-offs

• To build up a knowledge of CMOS logic structures

• To consider the limitations of CMOS and alternatives

• To extend our knowledge of dynamic performance to more complex logic structures

and systems

• To introduce some principles of system design

Course Content:

• The MOSFET: physical principles of device operation; current voltage relation-

ships, device models; second order effects

• Static Circuit Analysis: MOS inverters; the CMOS inverter transfer characteristic

and its switching level; NAND and NOR gates; noise margin; transmission gate

• Dynamic Circuit Analysis: circuit lay-out, MOS transistor capacitances; inverter

step response; gate delays; power dissipation

Dr. Naomi Harte Microelectronic Circuits I, 2009 1

• Technology Scaling: 45 nanometers and beyond: Limitations and emerging tech-

nologies

• CMOS Logic Functions: generalized CMOS combinational logic; XOR and trans-

mission gate logic; sequential logic elements,SRAM, DRAM

• CMOS Subsystem performance:RC gate delay models

Reading list:

• S. M. Kang and Y. Leblebici. CMOS Digital Integrated Circuits: Analysis and De-

sign, McGraw-Hill, 1996.

• Neil Weste, CMOS VLSI design : a circuits and systems perspective, Pearson

Addison Wesley, 2005.

• Jan M. Rabaey, Digital integrated circuits : a design perspective, Prentice-Hall ,

1996.

• Ken Martin, Digital integrated circuit design, Oxford University Press, 2000.

• Richard Muller and Theodore Kamins, Device electronics for integrated circuits,

John Wiley, 2003.

The author acknowledges the use of material from the following sources:

Dr. B.F. Foley, 4C2 Course Notes.

S. M. Kang and Y. Leblebici. CMOS Digital Integrated Circuits: Analysis and Design, McGraw-Hill, 1996.

Jan M. Rabaey, Digital integrated circuits : a design perspective, Prentice-Hall , 1996.

http://ece-www.colorado.edu/ bart/book/book/title.htm


1 The MOS Transistor - Qualitative Overview

This section describes the basic electrical operation of the Metal Oxide Semiconductor

Transistor from a simple physical viewpoint.

Objectives:

• To gain an understanding of the internal physical process

• To gain an understanding of the core electrical characteristics

• To establish a framework for a later appreciation of second order effects.

Figure 1: NMOS Device

1.1 Basic Structure

Figure 1 shows the physical structre of an n-type MOS transistor. The device has two

N+ (heavily doped) regions, referred to as the Source and Drain, embedded in a lightly

doped P-type substrate known as the bulk or body. A thin layer of silicon dioxide is

grown over the region between the source and drain. This in turn is covered by a layer of

conductive material, originally metal (hence Metal-Oxide Semiconductor) but generally

polysilicon (polycrystaline silicon). This conductive layer is the Gate of the device. L, the

channel length, is the distance between the source and drain regions. The width of the

channel is denoted W . The arrangement of N+ regions of source and drain with a p-type


substrate is called an n-channel MOSFET or NMOS for short. A p-channel MOSFET,

or PMOS, is formed with P+ source and drain regions and an n-type substrate. We will

firstly consider an NMOS device and later in the course we will look at PMOS.

We will build up a picture of how we control current in this device by first considering

the different aspects seperately and then together. Consider again two N+ regions, re-

ferred to as the Source and Drain, embedded in a lightly doped P-type substrate known

as the bulk or body. The basic idea is to produce a current, the drain current ID, in

response to an applied voltage VDS. This is shown in Figure 2

Figure 2: Basic Structure

The N+ regions: ID should be carried by mobile negative charge internally. Only mo-

bile positive chage + is available centrally (balanced by fixed negative charge -). There-

fore, ID is zero (apart from leakage in the order of 10−15 which we can ignore)

Consider then that the structure is extended to permit electrical control of the conduc-

tion properties of the central region as in Figure 3. This is starting to look like a device

Figure 3: Extension


you will have previously encountered. This metal-oxide semiconductor structure consti-

tutes a parallel place capacitor and gives the device the name of MOS. See Figure 4 and

Figure 5

Figure 4: Two Terminal MOS Structure

Figure 5: Simplified 2 terminal device constitutes a parallel plate capacitor

Note that strictly speaking the device has four terminals

• G Gate

• S Source

• D Drain

• B Bulk (or substrate)

Fow now we will simplify things by interconnectinng S and B (see Figure 6) thus reducing

it to a three terminal device.


Figure 6: Simplification

Figure 7: Potential difference applied to capacitor

1.2 Channel Formation

Recall that a potential difference applied to a capacitor results in a positive/negative

charging of the plates. See Figure 7.

Q ∝ V [Q = CV ] (1)

With this in mind, consider applying an increasing voltge VGS across the gate-substrate

capacitor as in Figure 8.

Figure 8: Channel formation with increasing VGS

Small VGS


The top plate is positively charged. Some holes have been repelled from the semi-

conductor under the oxide. Excess negative ions yield a net negative charge.

VGS = VT

VGS will reach a value such that the region is fully depleted of holes. This occurs at

VGS equal to VT , called the Threshold Voltage

VGS exceeds VT

The bottom plate has to find additional negative charge to balance the top plate. P-

type still has some free electrons - thermal generation of electron-hole pairs. These free

electrons are attracted into the region directly under the oxide. We now have mobile

charge of same sign as N+ regions. Hence we have conditions established for ID

The region of mobile electrons under the oxide is termed the conduction channel or

inversion layer.

Clearly the larger (VGS - VT ), the larger the available Qmobile.

Warning:

The impression has been given that VT is a sort of binary concept.

VGS < VT ⇒ Qmobile = 0 (2)

VGS > VT ⇒ Qmobile ∝ (VGS − VT ) (3)

While the transition from no channel to channel is sharp, it is not a step function. In

the vicinity of VGS � VT there is some mobile channel charge. Even for VGS < VT ,

there is a small quantity of mobile channel charge, though not enough for normal digital

applications. (Can be enough for low-performance digitnal and analogue applications

but this is not of interest to us in this course). The significant advantage of such sub-

threshold operation is that this small value of current results in extremely low power

dissipation.

1.3 Drain Current

Taking a MOS transistor with enough VGS to produce a conducting channel (i.e. greater

than VT the threhsold voltage), we now consider the internal processes resulting from

increasing VDS. Consider stages 1-5 shown in Figure 9


Case 1: VDS = 0 ID = 0

The conducting channel is depicted by the rectangle. Charge distribution is uniform.

Case 2: Small VDS

Small VDS appears directly across channel. This sets up electric field E as shown. Elec-

trons develop average drift velocity νd resulting in current ID. Charge flows from Source

to Drain.

Note that as the drain voltage is increased, the inversion layer charge and the channel

depth at the drain end start to decrease. The incremental channel resitance rd has in-

creased.

Case 3: Increasing VDS

ID also increases but not as much as the first increase. The channel tapers further. rd is

increasing. This is the linear region of operation.

Case 4: VDS = VGS − VT

At this point, the potential difference gate to channel at the drain end is reduced to zero

(equals (VGS −VT )−VDS). Hence Qmobile = 0 and rd → ∞. The channel becomes closed

off at the drain end. This condition is referred to as pinch-off.

Case 5: VDS > VGS − VT

Drain current limited to its value at pinch-off and further increases in VDS brings (virtually)

no increase in drain current, i.e. ID saturates. This region of operation is referred to as

saturation region.

What keeps ID going in the saturation region?

• VT is not absolute. So at VDS = VGS − VT there is still some Qmobile

• As the channel tapers, E increases (ID must be the same at every point in the

channel)

This combination of small Qmobile and large E maintains ID


Figure 9: Drain Current with increasing VDS

1.4 Summary

This section of the course has considered the generation of a drain current in an n-

channel MOS transistor.

Figure 10: NMOS transistor operation and circuit symbol

1. VGS < VT means there is no conduction channel. Mobile charge under the oxide

does not match the source/drain charge. ID = 0 except under electrical breakdown.


2. VGS > VT but VDS < VGS − VT means that we have a conducting channeland ID

increases with increasing VDS, but the channel tapers hence reducing Qmobile.

3. VGS > VT AND VDS > VGS − VT means the channel has tapered to the ”pinch-off”

stage. ID saturates and will not increase with further increases in VDS.

Recommended reading for this section: You may need to revise concepts intro-

duced in 3rd year regarding p-n junction behaviour under forward and reverse bias, de-

pletion regions, doping etc. A good source for this is Rabaey et al, chapter 2. section

2.2. You should also refer to 3rd year notes. You have covered the operation of the MOS

transistor in 3C2. Look back over you notes if this is all foreign!

To support the material in this section, please read:

• Kang et al, Chapter 3, section 3.3

• Rabaey et al, Chapter 2, section 2.3.1-2.3.2

Checkout http://jas.eng.buffalo.edu/education/mos/mosfet/mosfet.html for an interst-

ing java demo of how VGS and VDS control the channel and current flow in the NMOS

device.


2 The MOS Transistor - Quantitative Overview

This section presents a basic set of equations describing the electrical operation of the

MOS transistor - a device model. The process involves applying laws of physics and

making assumptions regarding their validity.

Objectives:

• To note the main determinants of VT

• To present a first order analysis of ID versus VDS

• To discuss the design significance.

2.1 Threshold Voltage VT

It may be shown that the two main positive contributions to VT are:

VT = −2φF − QBO

COX

(4)

The first term results from the depletion region barrier potential and represents the

voltage drop across the depletion region at inversion. Consider the diagram in Figure 11.

Figure 11: Depletion region barrier potential

In the first case shown,

φS1 = φF =KT

qln(

ni

NA) (5)

In the second:

φS2 = −φF (6)


The second term is in effect the voltage across the oxide capacitance. We can define

COX =εox

tox(7)

as the capacitance per unit area (looking down on the device) where εox is the oxide

permittivity and tox is the thickness of the oxide.

QBO = −√

2qNAεsi(−2φF ) (8)

There are two main negative contributions to VT , a work function term and a term due

to contaminants. Manufacturers can control the value of VT though ion implantation as

depicted in Figure 12.

Generally speaking, for a particular fabrication technology, the manufacturer tends to

produce VT as a specific fraction of the intended supply voltage. Typically:

VT � 1

5VDD (9)

Figure 12: Depletion region barrier potential

2.2 Drain Current Derivation

Consider an NMOS transistor with VGS > VT and 0 < VDS < VGS−VT shown in Figure 13.

y is a reference axis in the channel direction.

Let Vy be the channel potential at y. Note that at y = 0, Vy = 0V and at y = L,

Vy = VDS.

Let Qy be the mobile charge per unit area at y (looking down). This can be expressed

as:

Qy = Cox[(VGS − VT ) − Vy] (10)


Figure 13: Drain Current Derivation

Let ρy denote the charge per unit volume which is expressed as:

ρy =Qy

x(11)

Due to the electric field at y, Ey, there is a drift current given by the volume of charge

flowing past y in unit time. This can be expressed as:

ID = ρy(Wx)υDY (12)

with υDY denoting the average drift velocity at y. We know that

υDY = μnEy

with μn the electron mobility and Ey = dVy

dy. Substituting these along with Eq. 11 into

Eq. 12 we get:

ID =Qy

x(Wx)μn

dVy

dy(13)

Now substituting Eq. 10 for Qy and rearranging:

IDdy = WμnCox[(VGS − VT ) − Vy]dVy (14)∫ L

0

IDdy = WμnCox

∫ VDS

0

[(VGS − VT ) − Vy] dVy (15)

IDL = WμnCox

[(VGS − VT )VDS − V 2

DS

2

](16)

Hence:

ID = μnCoxW

L


DS

2

](17)

It can be shown that the function reaches a maximum at VDS = VGS − VT which is

precisely where the assumed linear region terminates and saturation takes over. Thus


IDsat is found by substituting VDS = VGS − VT into the above result of Eq. 17 yielding:

ID =μnCox

2

W

L[VGS − VT ]2 (18)

2.3 Drain Current Characteristics

Traditionally the drain current characteristics map ID onto VDS for uniformly increased

values of VGS. Referring to Figure 14, note:

• the lower the value of VGS, the earlier the transition from linear to saturation

• the distribution of individual graphs is quadratic

Figure 14: Drain Voltage and Drain Current Relationship

2.4 Design Considerations - the conductance parameter

The constant linking current and voltage squared is termed the conductance parameter

and is denoted:

βn = μnCoxW

L(19)

Note the usual dimensions of mAV 2 or μA

V 2 . Note further that β′n = μnCox is termed the

process parameter and is determined by silicon properties and the fabrication process.

The aspect ratio WL

is set by the circuit designer. It is the principal tool available when

trying to get a circuit configuration to meet a set of performance criteria - speed, area,

power dissipation.


Typically, a particular manufacturer’s process is characterised by specific values for the

smallest allowed transistor, e.g.

Lmin = 0.13μm (20)

Wmin = 2Lmin (21)

Very often a design might start with minimum sized transistors with channel width W

then being used as the parameter which can be tuned to achieve desired or optimum

performance

Recommended reading for this section:


• Rabaey et al, Chapter 2, 2.3.2, particularly ”Current Voltage Relations”


3 Transistor types and Refinements

Having looked at the N-channel MOS transistor, we deal now with its P-channel counter-

part.

Objectives:

• To treat the operation of the P-channel MOS transitor and its basic electrical model

3.1 The P-Channel MOS Transistor

The basic idea is to get mobile positive charge flowing source to drain in response to

VSD. To form a conducting channel, the gate potential has to be dropped below the

Figure 15: PMOS Device Channel Formation

source/substrate (VSG positive). Referring to Figure 15, it can be seen that when VSG =

VT the region below the oxide is fully depleted. Then when VSG > VT a channel is

formed. Applying a VSD as shown results in a hole drift from source to drain. By setting

up a current analysis similar to that used for the NMOS device we can establish that:

1. Small VSG, i.e. < VT

ID = 0 and the device is OFF

2. VSG > VT and VSD < (VSG − VT )


ID = βp

[(VSG − VT )VSD − V 2

SD

2

](22)

The device is in the linear region

3. VSG > VT and VSD > (VSG − VT )

ID =βp

2[VSG − VT ]2 (23)

The device is in the saturation region. Recall that βp = μpCoxWL

. (Have a go at

deriving these)

Figure 16: PMOS device

Note that:

When N- and P-channel transistors are made in the same fabrication process that Cox

will be the same and also Lmin,n = Lmin,p. Typically μn = fμp where 2.0 ≤ f ≤ 2.5. For

convenience we will take μn = 2μp.

Many textbooks and CAD programs maintain the notation of VGS and VDS for the p-

channel. These quantities will then be negative as will VT in such a scheme.

3.2 The Depletion Mode Transistor

So far we have discussed enhancement mode devices in so far as they have positive

threshold voltages. We have also noted that the threshold voltage can be adjusted

through ion implantation. If VT is adjusted so that it becomes negative, we have what is

termed a depletion mode transistor. The equations governing ID are precisely as before.

The symbol for an NMOS depletion mode transistor is shown in Figure 17.

In the early days of MOS technology, before ion implantation technology, the basic N-


Figure 17: NMOS Depletion Mode Circuit Symbol

channel device was depletion mode. It still finds some application though mainly as

resistors.



• Rabaey et al, Chapter 2, section 2.3.4


4 Transistor Models and Parameters

Recognising the importance of CAD (Computer Aided Design) in the design of integrated

circuits, we treat some elements at the interface between a ”paper and pen” approach

and the CAD approach with reference to MOS transistors

Objectives:

• To outline the accuracy versus speed issue

• To explain the difference between physical and empirical models

• To discuss the determination of model parameter values

• To describe the CAD tool SPICE

4.1 CAD Issues

The basic idea underlying the CAD approach is that each electronic device is repre-

sented by a set of equations encapsulating its electrical behaviour. In predicting the

performance of an electronic circuit, all the CAD program is actually doing is solving

a complex set of current-voltage equations. From a user point of view, we would ex-

pect a reasonable degree of accuracy from our CAD program and the calculations to be

achieved with reasonable speed.

The accuracy depends on two main elements:

• the accuracy of the numerical equation solving routine

• the accuracy of the device models

The accuracy of the device model further depends on two considerations:

• the accuracy of the parameter values, e.g. β, VT

• the accuracy of the device equations

As discussed more fully in Section 5, the basic MOS equations become compromised

as devices become smaller and second order effects become significant. Device equa-

tions need to be extended, but when they are extended the resulting system of equations

becomes more complex and takes longer to solve.


Thus there is an accuracy versus speed compromise to be made. Typically, a CAD

program gives the user a choice as to how the wish to represent a device, e.g. at

Level 1..N, where Level 1 is the basic model and Level N might be a complex model

incorporating many second order effects.

4.2 Types of Model

There are two main types of device model, physical and empirical.

4.2.1 Physical Model

Device equations are derived from the application of semiconductor physics.

• parameters have a physical significance, e.g. VT

• equations have a predictive quality

• any correlation between parameters is governed by the physics (e.g. temperature)

• modifying the equations for 2nd order effects can be difficult and very complex

4.2.2 Empirical Model

Device equations are based on fitting trial analytic expressions to measurement data.

For example, for the alpha-power model of

IDsat = k [VGS − VT ]α (24)

while α has a degree of meaning, it is hard to say what k might mean physically.

• must be careful in relation to predictiveness

• parameters can be unpredictably correlated

• can use relatively simple analytic formulae

In practice, many device models are semi-empirical.

4.2.3 Basic Parameter Evaluation

While it should in principle be possible to assign values to device parameters such as VT

or β from the underlying physics, in practice this is actually done through measurements

carried out on devices of known size.


Example:

VGS = 5V , VDS = 1V , ID = 87.5μA

VGS = 5V , VDS = 2V , ID = 150.0μA

Determine VT and B.

Solution


(Answer: VT = 1V and β = 25μA/V 2)

4.3 Measurement Noise

The previous section assumed a perfect match between measured data and the model.

Rarely will this be the case in real life. The usual technique is to find a least squared

error fit between the model and the data.

Example:

Given measurement data (I1, V1), (I2, V2), ..., (IN , VN) for a saturated transistor and given

threshold voltage VT , find β to minimise the least square error.

Figure 18: Measurement Noise


(Answer: β = 2

N∑1

Ii[Vi − VT ]2

N∑1

[Vi − VT ]4)

4.4 SPICE

Simulation of circuits can be performed at a number of different levels of abstraction

(recall introduction lecture). ModelSim is an example of a logic simulator, and simu-

lates the functional behaviour of circuits described by a HDL such as VHDL or Verilog.

SPICE (Simulation Program with Integrated Circuit Emphasis) is a circuit simulator which

employs device models and a netlist to predict voltage and current values to check per-

formance.

SPICE has existing models for a wide variety of semiconductor devices. Many levels

of MOSFET models are implemented: MOS1 is described by a square-law I-V charac-

teristic, MOS2 is an analytical model, while MOS3 is a semi-empirical model. MOS2

and MOS3 include second-order effects such as channel-length modulation, subthresh-

old conduction, scattering-limited velocity saturation, small-size effects, and charge-

controlled capacitances. The more advanced models are derived from the BSIM (Berke-

ley Short-channel IGFET Model) and now include BSIM3 and BSIM4. These more de-

tailed models are required for sub 100-μm devices. An IC designer would typically use

SPICE for DC and transient analysis.

(Check out http://www-device.eecs.berkeley.edu/ bsim3/)


5 Scaling Issues

This section considers the consequences of reducing the dimensions of the MOSFET.

This scaling has been a driving force in making the MOS transistor dominant for inte-

grated circuits. However, continued reductions in dimensions can cause some undesir-

able side-effects and make some assumptions about the operation of the devices invalid

as physical limitations are approached.

Objectives:

• To introduce possible strategies for MOS scaling

• To consider some of the challenges as MOS dimensions continue to shrink

• To examine at least one effect of scalng on the model.

5.1 Technology Scaling

In 1965, Intel co-founder Gordon Moore saw the future. His prediction, popularly known

as Moore’s Law, states that the number of transistors on a chip doubles about every

two years. This drive to increase the number of transistors on a device requires the

size of those transistors to reduce in order to maintain constant functionality. In reality,

applications are also demanding greater functionality and hence the pressure to reduce

transistor size to allow higher density chips is endless.

The reduction in the dimensions of a MOSFET has been dramatic during the last

three decades. Starting at a minimum feature length of 10μm in 1970, the gate length

was gradually reduced to 0.15μm minimum feature size in 2000, resulting in a 13% reduc-

tion per year. In 2006, Intel started shipping in volume dual-core microprocessors based

on their 65ηm process technology on 300mm wafers. (Note 65ηm is 0.065μm) Note that

a process is defined by the average feature size. The minimum feature size can be

smaller. For instance the minimum feature size on 90 nanometer chips can be close to

45 nanometers. In October 2007, Intel launched their first high-volume 45 nanometer

(nm) manufacturing factory in Arizona, USA.

Proper scaling of MOSFET requires a reduction in all dimensions including gate

length and width, the gate/source and gate/drain alignment, the oxide thickness and

the depletion layer widths. Scaling of the depletion layer widths also implies scaling of


the substrate doping density. Scaling can be considered in terms of a scaling factor

S > 1 applied to physical dimensions of the device as shown in Figure 19.

Figure 19: Scaling of typical MOSFET by scaling factor of S

Three strategies for scaling are possible: constant field scaling and constant voltage

scaling and lateral scaling.

5.2 Constant Field Scaling

Constant field scaling (sometimes referred to as full scaling) attempts to preserve the

magnitude of the internal electric fields in the device when the physical dimensions (W

L tox xj) are scaled down by a factor S. The voltages VGS, VDS and VT must be scaled

down to achieve this. The substrate doping must also be scaled. Hence this is not a

purely geometric scaling.

5.3 Constant Voltage Scaling

In constant voltage scaling, all dimensions are reduced by a factor of S. The power sup-

ply and terminal voltages remain unchanged. This has the attraction of providing voltage

compatibility with older circuit technologies. The disadvantage of constant voltage scal-

ing is that the electric field increases as the minimum feature length is reduced. This

leads to velocity saturation, mobility degradation, increased leakage currents and lower

breakdown voltages.


Table 1: Effect of Scaling on device characteristics

Parameter Constant E Constant V Lateral

Channel Length L 1S

1S

1S

Channel Width W 1S

1S

1

Gate Oxide Thickness tox1S

1S

1

Substrate Doping NA S S 1

Supply Voltage Vdd1S

1 1

Junction Depth xj1S

1S

1

Depletion layer Thickness d 1S

1S

1

Oxide Capacitance Cox S S 1

Conductance Paramater β S S S

Field along channel Ech 1 S S

Current IDsat ∝ βV 2 1S

S S

# of devices N = 1/WL S2 S2 S

Power Dissipation P = IDsatVDS1

S2 S S

5.4 Lateral Scaling

In lateral scaling, only the channel length is scaled (a gate-shrink).

5.5 Scaling in Reality

Lateral scaling is used (was used by IBM in 0.25μm process) but is limited in terms of the

increased number of devices on a chip. Up until a few years ago, constant voltage scaling

was more widely used due to pressure to keep voltage levels constant. However due to

the increase in power dissipation and non-linear effects such as velocity saturation, it

has its limits. Hence, constant field scaling has become more widespread. It too has

its challenges as dimensions continue to shrink but still offers the best gains - greater

number of transistors on a chip, lower current and hence low power dissipation. The

effects of the different scaling strategies on the device characteristics is summarised in

Table 1.

We will consider some of these issues in more detail. Research directions to main-

tain scaling improvements in MOSFET range from improved materials to lithography

techniques to exciting new MOS structures. Many of these are outside the scope of this


course but we will consider a number of important issues:

• Reduced gate oxide thickness

• Interconnect delays

• Subthreshold currents

• Velocity saturation

5.6 Gate Oxide Leakage

The gate oxide acts as an insulator between the gate and the channel. As the gate

oxide thickness tox approaches a thickness of around 1.2ηm , breakdown of the oxide

and oxide reliability becomes a problem. Higher fields in the oxide increase the quantum

mechanical phenomenon of tunneling of carriers from the channel into the oxide. These

carriers slowly degrade the quality of the oxide and can lead to failure of the oxide. This

effect is referred to as time dependent destructive breakdown (TDDB). This leakage

current increase power consumption in the ”off” state.

Insulators (referred to as high-k dielectrics) that have a larger dielectric constant than

silicon dioxide, such as group IVb metal silicates e.g. hafnium and zirconium silicates

and oxides have been investigated to provide an alternative. NEC have recently used a

hafnium-based material. With a larger dielectric constant, the same gate oxide capaci-

tance can be obtained with a thicker oxide. The challenge is to obtain the same stability,

reliability and breakdown voltage as silicon dioxide.

While hafnium and zirconium oxides have good dielectric properties, these com-

pounds are not compatible with the polysilicon material in the gate. Threshold voltage

pinning results when a high-K gate dielectric, including oxides of hafnium and zirco-

nium, is combined with a polysilicon gate electrode. Defects at the gate dielectric/gate

electrode interface cause relatively high threshold voltages, which causes reduced drive

current and impaired performance. Thus the search for a better dielectric material for

the oxide has also necessitated the investigation of new metals for the gate electrode in

NMOS and PMOS devices.

In 2007, Intel announced their 45nm technology employing ”Hi-k metal gate” technol-

ogy. The silicon dioxide has been replaced with a thicker hafnium-based high-k material

in the gate dielectric, reducing leakage by more than 10 times compared to the silicon

dioxide. Because this high-k gate dielectric is not compatible with polysilicon, they use


new metal gate materials. The specific combination of different metal materials for the

transistor gate electrodes that Intel uses is unclear though it may be TiN.

5.7 Interconnect

Traditionally switching time was roughly proportional to the gate capacitance (more on

this later in the course). However, with transistors becoming smaller and more transis-

tors being placed on the chip, interconnect capacitance (the capacitance of the wires

connecting different parts of the chip) is becoming a large percentage of the overall ca-

pacitance. As the copper wires that connect different parts of the chip become thinner,

resistance increases. Signals have to travel through the interconnect, which leads to in-

creased delay and lower performance as this interconnect delay starts to dominate gate

delays.

5.8 Subthreshold Current

The basic assumption of our MOS capacitor analysis thus far, is that no inversion layer

charge exists below the threshold voltage VT . This leads to zero current below the thresh-

old. The actual sub-threshold current is not zero but reduces exponentially below the

threshold voltage as:

ID ∝ exp[VGS − VT

vt] (25)

(where vt indicates the thermal voltage from thermodynamics, not to be confused with

VT ). The sub-threshold behavior is critical for dynamic circuits since one needs to ensure

that no charge leaks through transistors biased below threshold.

5.9 Velocity Saturation

The relationship υDY = μnE holds true for low values of electric field. At high field values,

the drift velocity reaches a maximum value due to carrier scattering and hence υ → υmax

which is of the order 107cm/s. Note that υmax is basically the same for both electrons

and holes.

We have already noted that in a conducting transistor as the channel tapers, the electric

field increases. The effect is accentuated in short channel devices in which the basic

field strength is higher.

Thus for many of today’s short channel devices, when the full supply voltage VDD is

applied across the channel, the device will be subject to velocity saturation. It may be


Figure 20: Electric Field

shown that:

IDsat = WυmaxCoxVdsat (26)

where Vdsat = VGS − VT to a first approximation.

Note:

• IDsat is no longer proportional to the square of VGS − VT

• For equal values of W , there is no difference between n and p-channel devices

• IDsat does not depend on channel length

To account for transistors partially subject to velocity saturation, the following equation

has been found particularly useful, the so-called power law:

IDsat = k [VGS − VT ]α (27)

where α is essentially a measure of the degree of velocity saturation:

α = 2 ⇒ no velocity saturation

α = 1 ⇒ full velocity saturation

Note the unusual dimensions of constant k of mA/V α


Beware when reading chapters in texts printed more than 5 years ago. Things have

moved on in the world of MOS scaling. More recent articles, e.g. from IEEE Circuits and

Devices Magazine, are a better source of up to date information. (you have access in


TCD through ieeexplore.ieee.org). Also check out websites of the large seminconductor

fabricators, e.g. www.intel.com.



6 Inverters

The inverter is the most basic digital circuit element. But what precisely constitutes an

inverter from an electrical point of view? This question is addressed by referring to the

concept of a functioning digital system.

Objectives:

• to set up a simple model of a large digital system

• to define what is meant electrically by a system working properly

• to define precisely VOL and VOH

6.1 Inverter Basics

Figure 21: Inverter

From a logical perspective, an inverter transforms a ”1” into a ”0” and a ”0” into a ”1”.

Normally, we consider a ”0” to be physically encapsulated into a low voltage VL and a ”1”

into a high voltage VH

Figure 22: Inverter

The way most (synchronous) digital systems work (see Figure 22) is that the data is

taken from a register (set of flip-flops), passed through some combinatorial (also called


combinational) logic block and then clocked into some register or memory location. Ex-

amples of combinatorial logic would include an arithmetic logic unit, an address decode

etc.

Both the sequential logic (register) and the combinatorial logic comprise primitive

gates such as NAND, NOR, Inverters etc. Later on we will see that from an electrical

point of view, primitive gates can be reduced to equivalent inverters - disregarding logic

functionality. Thus, electrically, a large digital system can be modelled by a long cascade

of inverters.

Consider now a long sequence of identical (for convenience) inverters operated from

a 0V/VDD power supply. Suppose that the primary input V1 is either 0V or VDD represent-

ing a 0 or a 1. What happens to the voltage levels as we progress through the cascade?

Clearly there should be a high at every second node and a low at every (second) inter-

mediate node.

Figure 23: Inverter

Figure 23 demonstrates what can happen. In (a), the high level keeps dropping and

the low level keeps rising, and eventually the two cannot be distinguished. In (b), the high

level drops to a constant level and the low level rises to a constant level; these constant

levels continue to replicate. Hence we can encounter two situations:

• high/low levels converging resulting in system malfunction

• a pair of self replicating level emerges.

A properly functioning system is characterised by a pair of inverters for which

Vi+2 = Vi (28)


6.2 Voltage Transfer Characteristic

The input-output voltage relationship of an inverter is called the Voltage Transfer Char-

acteristic (VTC). Consider the VTC of the ideal inverter as shown in Figure 24. For any

Figure 24: Ideal Inverter Voltage Transfer Characteristic

input 0 to VDD/2 the output is equal to VDD. For any input greater than VDD/2, the output

is 0V . Here the input voltage where the output switches from high to low, referred to as

the inverter threshold voltage Vth, is shown equal to VDD/2.

Figure 25: Typical Inverter Voltage Transfer Characteristic

Figure 25 shows the transfer characteristic for a realistic inverter. Here we can see

that an input voltage from 0V to VIL will give a high output. An input voltage ranging from

VIH to VOH will give a low output. Inbetween we find the transition region which is not a

useful region for our desired operation and hence to be avoided.

Consider connecting two inverters in series where the input to the first inverter is low.

The high output of this first inverter must be in the range VIH to VOH to guarantee a

replicating pair of voltage levels and a valid inverter. We can define these four important

voltages formally as:


• VOL: Minimum output voltage where the output level is LOW

• VOH: Maximum output voltage where the output level is HIGH

• VIL: Maximum input voltage which can be interpreted as LOW

• VIH : Minimum input voltage which can be interpreted as HIGH


7 Resistive Load Inverters

We now commence out formal treatment of MOS transistor circuits by examinig digital

functionality as previously defined. Some relevant design issues are introduced.

Objectives:

• to apply the methodology for testing a circuit for valid digital operation

• to introduce static circuit analysis for MOS circuits

• to demonstrate some basic design trade-offs

7.1 General Method

Figure 26: General method

Consider the circuit as shown in Figure 26. L represents an unspecified load device.

It could be a resistor but it could also be an active device such as a transistor. We do,

however, need to know the electrical characteristic of L, i.e.

IL = f(VL)

is assumed known. If L is a resistor, IL = VL

R= VDD−Vo

R.

The general intent of this circuit arrangement is that:

if Vi is low, Vo is high.

if Vi is high, Vo is low.

The voltage values for low and high must be consistent and self-replicating for valid

electrical functionality. The general method for analysing the circuit is to note:


IL = ID

f(VDD − Vo) = (Vi, Vo)

Then for the two possible input voltages Vi, we have to figure out whether the transistor

is off, linear, or saturated, and then insert the corresponding function .

7.2 Resistive Load NMOS

The best way to understand the method is by reference to a specific example as shown

in Figure 27.

Figure 27: Resistive Load NMOS

Given VT = 1V , β = 100μA/V 2, find VOH and VOL for:

(a) R = 100kΩ (b) R = 10kΩ

An intuitive starting point is to postulate that a low input voltage value would be Vi < VT .

Hence:

if Vi < VT ⇒ T is OFF ⇒ ID = 0

⇒ IR = 0

⇒ Vo = VDD Thus our high output level is:

VOH = VDD (29)

Now if our input voltage Vi = VOH = VDD, then T will conduct but in what mode? Is

VDS < (VGS − VT ) or is VDS > (VGS − VT )?

With the known applied voltages we can rewrite this question. Is

Vo < (VDD − VT ) or is Vo > (VDD − VT )?

Since the intention is that with Vi at a high level, that the output should be low, it would

be sensible to surmise that Vo < (VDD − VT ) and that the transistor T is in a linear mode

of operation.


Then working from: IR = IDlin

This is a standard quadratic in Vo, yielding:

VOL = Vi − VT +1

βR−

√(Vi − VT +

1

βR

)2

− 2VDD

βR(30)

(Note that you take the root giving a low output voltage not greater than VDD)

Note that in our case where Vi = VDD, this becomes:

VOL = VDD − VT + 1βR

−√(

VDD − VT + 1βR

)2

− 2VDD

βR

For (a) where R = 100kΩ


For (b) where R = 10kΩ

Hence from this we see that the product βR is an important design parameter for

correct operation from the inverter.

This example has considered the values of VOH and VOL for this circuit. It is possible to

also work out values for VIH and VIL . We won’t derive these here but for completeness

these can be expressed as:

VIL = VDD − 1

2βR(31)

VIH = VT +

√8

3

VDD

βR− 1

2βR(32)

7.3 Static Average Power Dissipation/Consumption

Average power dissipation is a very important specification in modern design. The power

consumption in individual gates will contribute to the overall power consumption in a de-

vice. This in turn affects packaging and cooling requirements for a device and hence

the cost of a chip. The power consumption will affect the feasability and reliability of a

design. It has implications for battery life and size in consumer devices. Consider the

power consumption of our inverter. Assuming the circuit spends half the time in the high

(Vo = VOH) state and the other half in the low (Vo = VOL) state, what is the average power

consumption of this gate?


Pav =1

2VDD[IDDH + IDDL] (33)

=1

2VDD

[0 +

VDD − VOL

R

](34)

Pav =VDD

2

(VDD − VOL)

R(35)

Hence increasing R can reduce the power consumption of the gate. However a larger

load resistor requires a larger silicon area.

7.4 PMOS Resistive Load Inverter

Figure 28: Resistive Load PMOS

1. If Vi is high, such that VSG < VT (i.e. Vi > VDD − VT ), then:

T is OFF, ⇒ ID = 0

⇒ Vo = 0V

⇒ VOL = 0V

2. If Vi is low, such that Vi = 0V , then:

VSG = VDD − Vi = VDD

⇒ T is ON

⇒ more likely that VSD < VGS − VT , i.e. T is in the linear region. Taking a transistor with

the same parameters as the previous example (R = 100kΩ, VT = 1V , β = 100μA/V 2)

and using a similar analysis, it is possible to show that Vo = 4.9V for this circuit. Thus we

have a circuit which acts as an inverter with VOL = 0V and VOH = 4.9V . Compare the

NMOS and PMOS resistive load inverters looked at, as summarised in Table 2.


Table 2: Comparison of NMOS and PMOS resistive load inverters

Level NMOS Inverter PMOS Inverter

VOL 0 < VOL < VT 0V

VOH VDD VDD − VT < VOH < VDD

The NMOS inverter has ideal behaviour in terms of VOH whilst the PMOS inverter

has ideal behaviour in terms of VOL. The CMOS (Complimentary MOSFET) inverter

combines the strengths of the two inverters and will be examined in the next section in

detail.


• Kang et al, Chapter 5, section 5.1, 5.2 (note they use kn for the conductance pa-

rameter β)

• Rabaey et al, Chapter 3, section 3.1, 3.2.1-3.2.2


8 CMOS Inverter - Static

Complementary MOS (CMOS) refers to circuit congifurations employing a combination

of N-channel and P-channel transistors. We wish to demonstrate the basic operation of

a CMOS inverter in steady state, with reference to its transfer characteristics.

Objectives:

• to explain the basic digital operation of a CMOS inverter

• to explain the near-ideal performance with respect to levels, transfer characteristic

and power dissipation.

• to demonstrate some design considerations

8.1 Circuit Configuration

Figure 29: CMOS Inverter

Figure 29 shows the basic configuration of the CMOS inverter. The inverter com-

prises one P-channel and one N-channel transistor (no resistor). Note carefully the gate,

source and drain nodes for each transistor and how the gate and drain voltages are re-

lated to input Vi, output Vo and supply VDD. In particular note the following:

VSG = VDD − Vi

VSD = VDD − Vo

VGS = Vi

VDS = Vo


Consider the possible operating modes for TN :

1. Off if VGS < VT , i.e. Vi < VT .

2. Linear if Vi > VT and VDS < (VGS − VT ), i.e. Vo < Vi − VT .

3. Saturated if Vi > VT and Vo > Vi − VT .

Consider the possible operating modes for TP :

1. Off if VSG < VT , i.e. VDD − Vi < VT or equivalently Vi > VDD − VT .

2. Linear if VSG > VT and VSD < (VSG −VT ), i.e. VDD −Vo < VDD −Vi−VT or equivalently

Vo > Vi + VT

3. Saturated if VSG > VT and Vo < Vi + VT .

In the above, we have adopted the reasonable assumption that VT (TN ) = VT (TP ) =

VT .

Figure 30: Connecting two CMOS inverters

Consider Figure 30 showing one CMOS inverter connected to another. Since IGP =

IGN = 0, we see that IL = 0. Hence:

IDP = IDN (36)

8.2 Basic Digital Operation

We consider the operation of the CMOS inverter where (a) Vi is low, and (b) Vi is high.

At this stage we do not know what a low or high level is, but a reasonable starting point

is to again assume:


Vi low ⇔ Vi < VT

(a) Vi low

Referring to Figure 31, if Vi is low and less than VT , then TN is OFF. Looking then at TP ,

since Vi is low, then VSG = VDD − Vi is high and TP is in principle ON.

Compare VSD = VDD − Vo to VSG − VT to see whether linear or saturation is more likely.

With VSG relatively high, and assuming Vo tends to be high (Remember the circuit is to

invert the input!), we have VSD relatively low. Hence it is more likely that VSD < VSG −VT .

Hence:

More likely that TP is LINEAR.

Figure 31: CMOS Inverter, Vi LOW

Hence IDN = IDP . But since Vi < VT , IDN = 0.

⇒ IDPlinear= 0

Working with this then:

βP

[(VSG − VT )VSD − V 2

SD

2

]= 0

This quadratic has two solutions, the useful one being VSD = 0. But we know from

inspection that VSD = VDD − Vo. Hence when Vi < VT :

Vo = VDD

In summary then:

if Vi < VT ,

then TN is OFF, TP is LINEAR

VOH = VDD


(b) Vi high

Take a high input to be Vi = VDD due to previous result. Referring to Figure 32, with

Vi = VDD, TN is in principle ON. Since VSG = 0 which is < VT , TP will be OFF.

Figure 32: CMOS Inverter, Vi HIGH

Since VGS − VT is relatively high and VDS should be low, then TN is more likely in the

linear region of operation.

IDN linear= IDP = 0 since VSG < VT

Working with this then:

βN


DS

2

]= 0

⇒ VDS = 0

⇒ Vo = 0V

In summary then:

if Vi = VDD,

then TP is OFF, TN is LINEAR

VOL = 0V

8.3 Basic Properties

This circuit arrangement constitutes a valid inverter since:


Table 3: CMOS Inverter Operation

Vi TN TP Vo

< VT OFF ON, Linear VDD

> (VDD − VT ) ON, Linear OFF 0V

VOL = 0V

VOH = VDD

We can see from Table 3 that with Vi = 0V or Vi = VDD we always have either TN or TP

OFF. Hence:

IDD = 0

⇒ Pav = 0 (37)

The steady-state or static power dissipation is zero. (There is in reality a small leakage

current which becomes a problem at smaller dimensions - recall our discussion in previ-

ous section on Scaling).

TN will remain OFF with 0V ≤ Vi ≤ VT .

TP will remain OFF with VDD − VT ≤ Vi ≤ VDD.

Hence the circuit can deal with a noise voltage of up to VT and still function in an ideal

manner. Hence VT provides noise immunity.

8.4 Complete Voltage Transfer Characteristic

What about operation when the voltage levels are not within this range?

With Vi > VT but now with Vo > Vi − VT , transistor TN moves into the saturation re-

gion. From earlier we have seen that as long as Vo > Vi + VT , that TP is still linear. The

relationship between Vo and Vi in this region may be determined from:

IDNSat= IDP Lin

⇒ Vo = Vi + VT +√

(VDD − Vi − VT )2 − βR(Vi − VT )2

where βR = βN

βP

This means that Vo will fall quadratically with increasing Vi.


With Vi < (VDD − VT ) but now with Vo < Vi + VT , transistor TP moves into the satu-

ration region. From earlier we have seen that as long Vo < Vi − VT that TN is still linear.

The relationship between Vo and Vi in this region may be determined from:

IDNLin= IDP Sat

⇒ Vo = Vi − VT −√

(Vi − VT )2 − 1βR

(VDD − Vi − VT )2

where βR = βN

βP

This means that Vo will rise quadratically with increasing Vi.

When:

Vo < Vi + VT ⇒ TP is saturated

Vo > Vi − VT ⇒ TN is saturated

In this case then

IDNSat= IDPSat

βN

2[Vi − VTN ]2 = βP

2[VDD − Vi − VTP ]

allowing for the possibility in this case of unequal thresholds.

Note this is independent of Vo, i.e. it defines a unique point for Vi at which the output

Vo drops abruptly. This is the inverter threshold voltage Vth mentioned earlier. Again

defining βR = βN

βPand substituting for Vi we can see:

√βR(Vth − VTN) = VDD − Vth − VTP

Vth = VDD−VTP +√

βRVTN

1+√

βR

These results allow us to extend Table 3. This table is cross-referenced to Figure 33

where the regions of operation are labelled

8.5 Discussion

Note the near ideal form of the transfer characteristic. Normally the threshold voltages

will be equal for the PMOS and NMOS transistors, hence VTN = VTP = VT . Also, typ-

ically βN = βP and Vth = VDD

2. Hence βR can be used to control the inverter switching


Table 4: Complete CMOS Inverter Operation

Vi TN TP Vo Region

0 ≤ Vi < VT OFF ON, Linear VDD A

VT ≤ Vi < Vth Saturation ON, Linear falling B

Vth Saturation Saturation Vth C

Vth < Vi ≤ (VDD − VT ) ON, Linear Saturation rising D

(VDD − VT ) < Vi ≤ VDD ON, Linear OFF 0V E

Figure 33: Complete CMOS Inverter Voltage Transfer Characteristic

threshold. Consider:

βR = βN

βP=

μN CoxWNLN

μP CocWPLP

= μN WN

μP WP

Typically μN = 2μP and:

⇒ βR = 2WN

WP

Thus to achieve βR = 1, an electrically balanced inverter, we need WP = 2WN . Hence

in any IC, more area is taken up by the P-channel devices, the greater channel width


Figure 34: Different NMOS to PMOS ratios

compensating for the poor hole mobility. Inverters with different βR = 1 ratios are called

skewed inverters.

While the above analysis suggests the output voltage falls abruptly at the inverter thresh-

old Vth, (switching threshold), the second order effect of channel length modulation re-

sults in a finite Vi, Vo slope in this central region. Nevertheless a centre region with a

large slope is used extensively in analogue circuit applications.

A comment on terminology you may come across: The circuit topology for this CMOS

inverter in complementary push-pull in the sense that for high input, the NMOS transistor

pulls down the output while the PMOS transistor acts as a load. Then with low input, the

PMOS transistor pulls up the output while the NMOS transistor acts as the load.

The main attractions of this CMOS inverter over other configurations is the negligible

steady-state power dissipation and the full voltage swing from 0 to VDD with a sharp VTC

transition.


Many of the text books use a negative threshold voltage convention for PMOS and hence

the analysis will not follow exactly the analysis here. This may prove confusing unless

you are really comfortable with the material presented here. We have followed the ap-

proach in the Kang book but with our own convention for polarity.


• Kang et al, Chapter 5, section 5.4 (with the warning above!!)


9 CMOS Combinatorial Logic

At this stage we wish to expand our knowledge of CMOS logic circuits beyond the in-

verter. In addition to the classic method of implementing logic functions from gate primi-

tives (NAND, NOR), we will see how to realise functions directly with transistor congifu-

rations.

Objectives:

• to demonstrate in CMOS the logic primitives NAND/NOR

• to extract a set of configuration rules for generating an arbitrary function

• to illustrate the application of these design rules

9.1 Combinatorial Logic

Combinatorial logic (also called combinational logic) is a type of logic circuit whose out-

put is a function of the present input only. This is in contrast to sequential logic, in which

the output depends not only on the present input but also on the history of the input. In

other words, sequential logic has memory while combinatorial logic does not.

Combinatorial logic is used in circuits to do boolean algebra on input signals and on

stored data. We have already considered that a digital system (or circuit) will normally

contain a mixture of combinatorial and sequential logic. For example, the part of an arith-

metic logic unit (ALU) that does mathematical calculations is constructed in accord with

combinatorial logic, although the ALU is controlled by a sequencer that is constructed in

accord with sequential logic. Recall that all boolean algebra can be reduced to NAND

and NOR operations.

9.2 General Form

Figure 35 shows the general form for the CMOS logic function circuits we will look at in

detail in the next sections. A and B are inputs while X is the output. Here we show just

two inputs but we will extend this to the general case of multiple inputs. The comple-

mentary nature of the operation of such circuits has already been seen for the CMOS

inverter and will be used here again. When either of the inputs is high, the n-net can


Figure 35: General CMOS Logic

(depending on the connection of the N transistors) create a conducting path between

the output node X and ground, and the p-net is cut-off. If both inputs are low, the n-net

is cut-off and the p-net can (depending on the connection of the P transistors) create a

conducting path between the the output X and the supply voltage VDD. This complemen-

tary circuit structure allows that for any given input combination the output is connected

either to ground or VDD. With this general structure in mind, we will examine the specific

examples of NAND and NOR gates.

9.3 2-Input NAND gate

Figure 36 is a CMOS NAND gate. We will consider the digital operation of this circuit

to show this is indeed the case. A and B are inputs while X is the output. Note that

for clarity the input A is not shown as joined though they are the same wire, likewise B.

We are not interested in the full electrical operation over the range 0V to VDD. We are

interested in the digital operation when each input is either low (0V ) or high (VDD).

Consider the transistors in terms of a switch using the notation TNA to denote an

n-channel with input A, TPB a p-channel with input B etc. From this it is possible to

construct a truth table. Firstly, recall the behaviour of each transistor in this case:


Figure 36: 2 Input NAND

Table 5: Truth Table NAND

A B TNA TNB TPA TPB X

0 0 OFF OFF ON ON 1

0 1 OFF ON ON OFF 1

1 0 ON OFF OFF ON 1

1 1 ON ON OFF OFF 0

Knowing the inputs A and B, we can directly determine the ON/OFF state of the

transistors TNA, TNB, TPA, TPB. The state of the output X can be determined by the

observation that:

X=1 if TPA is ON or TPB is ON.

X=0 if TNA is ON and TNB is ON.

Note: from the ON/OFF states of the four transistors we never find conditions for X=0 at

the same time as conditions for X=1.

We note the overall truth table is that of a NAND function. Note the symbol for this

device in Figure 37.

9.4 2-Input NOR gate

Consider now changing the parallel-series connections of the last circuit. The circuit in

Figure 38 is a NOR gate. We will consider the digital operation to verify this.

Similar to the previous circuit we can construct the truth table for this circuit. The

same rules apply regarding the operation of the transistors. The state of the output X


Figure 37: 2 Input NAND

Figure 38: 2 Input NOR

can be determined by the observation that:

X=1 if TPA is ON and TPB is ON.

X=0 if TNA is ON or TNB is ON.

We note the overall truth table is that of a NOR function. Note the symbol for this

device in Figure 39.

Table 6: Truth Table NOR

A B TNA TNB TPA TPB X

0 0 OFF OFF ON ON 1

0 1 OFF ON ON OFF 0

1 0 ON OFF OFF ON 0

1 1 ON ON OFF OFF 0


Figure 39: 2 Input NOR

9.5 Configuration Rules.

We have convered three gate primitives as shown in Figure 40:

Figure 40: Basic CMOS gates

• Inverter (often referred to as INV)

• NAND (can think of and AND followed by INV)

• NOR (can think of and OR followed by INV)

We see that the general form of the CMOS gate considered in Figure 35 can be observed

in each case. What changes for each logic function is the connection of the NMOS or

PMOS transistors. These are the connection rules:

• AND function ⇒ TN ’s in series, TP ’s in parallel.

• OR function ⇒ TN ’s in parallel, TP ’s in series.


• The circuit has implicit overall inversion.

To see how these three rules work in practice, consider the following CMOS logic

circuit:

Figure 41: Example CMOS circuit

We can analyse this circuit by inspection:

In both cases we see that the output X is A.[B + C]. Note the following:

The N and P networks result in the same logic expression; there must be no conflict

between them.

The resulting logic expression is more complex than that of the primitive gates but the

circuit architecture is similar to that of a primitive gate.


9.6 Design Examples

We will consider two classes of example:

(a) those that fit the generic CMOS model (having an overall inversion) and

(b) those that have to be adapted to the overall model.

(a) Generic model fit: Consider implementing:

X = A.B + C.D

We can draw this circuit:


Consider if we were to implement this same function with gate primitives we would

get:

The generic CMOS circuit above only requires 8 transistors versus 14 transistors for

this implementation, hence it requires less silicon area.

(b) Does not fit generic model. Consider implementing:

X = A.B + C.D

One possible solution is to note:

i.e. the previous circuit with an inverter on the output.

A second way involves the application of De Morgan’s Laws so as to arrive at an

expression that fits the generic model:


We can draw this circuit as:

Note that often the inverted variables will be available and hence the 4 inverters may

not be required.

9.7 Discussion

Given the problem of designing a CMOS circuit to implement some combinatorial logic

problem, we have considered two basic approaches:

1. Primitive Gates. The logic problem is converted into a truth table, Karnaugh Maps

may be used to simplify the corresponding Boolean Equation which is typically given as

a sum of products (or product of sums). e.g. x=A.B+C.D. This may then be implemeted

with NAND (NOR) gates and inverters as necessary.

2. Direct CMOS. Again a simplified Boolean expression is generated, only now it is

converted directly into a CMOS transistor circuits using the connection rules covered in

this section. Typically this latter approach will result in a circuit requiring fewer transistors

and hence less silicon area and power.

9.8 Brief note on De Morgan’s Laws

Recall how you can use De Morgan’s laws to manipulate logic:

A.B = A + B

A + B = A.B


10 Transmission Gate Logic

The transmission gate is a logic element particular to CMOS. It can be applied to certain

logic design problems resulting in a significant saving in the number of transistors used.

Objectives:

• to describe the concept of the transmission gate (TG) and detail its digital operation

• to illustrate its use in logic design.

10.1 Transmission Gate Concept

The TG shown in Figure 42 has a single data in and data out line denoted Vi/Vo. It also

has a digital control line Vc which determines how the TG functions.

If Vc = 1, the TG functions in transmit mode and Vo = Vi.

IF Vc = 0, the TG functions in non-transmit mode and Vo is unspecified irrespective of Vi.

Hence in transmit mode, input data is passed to the output. When in non-transmit mode,

the output would normally take on the value of some other device also connected to the

output node.

Figure 42: General Transmission Gate

10.2 CMOS Transmission Gate

Recall from our examination of resistive load inverters that NMOS transistors pass 0 well

but 1 badly. Likewise PMOS transistors pass 1 well but 0 poorly. The CMOS TG com-

prises two transistors, one n-channel and one p-channel in parallel. Up to this point, we


considered the MOS transistor as a 3-terminal device by connecting the bulk/substrate

to the source. In the TG, the NMOS substrate is connected to ground and the PMOS

substrate is connected to VDD. This means that the source and drain are not determined

until the voltages are applied to the transistors. This exploits the symmetry of the tran-

sistors and the fact that either n-region can act as source or drain in the NMOS (and

likewise either p-region can be the source or drain in the PMOS). The control signal Vc

is applied to the gate of the N-channel while its complement Vc is applied to the gate of

the P-chanel transistor.

Figure 43: CMOS Transmission Gate

Note that the circuit is passive; there is no energy source VDD connected. This means

that a complete system cannot be built entirely from TGs as logic levels would inevitably

degrade. Somewhere there has to be some conventional CMOS logic and this will have

the effect of forcing the steady-state current to zero.

Case Vc = 0, Vc = 1:

This forces both TN and TP off; there is no electrical connection between Vo and Vi and

Vo is unspecified. This is a high impedance state.

Figure 44: CMOS Transmission Gate with Vc at 0


Case Vc = 1, Vc = 0:

The idea here is to turn on the transistors in such a manner that Vo electrically follows Vi.

Consider the two possibilities for Vi:

(a) Vi == 0 as shown in Figure 45

Suppose that Vo is above 0V initially. Any transient current which flows must flow right

to left as shown, essentially discharging any load capacitance. This current fixes the

source and drain nodes of each transistor as shown. Consider TN :

VGS = VDD is large.

Because Vo is dropping, VDS = Vo − Vi is small.

Therrefore TN is more likely to be in a linear mode of operation rather than saturation.

Eventually i → 0:

⇒ IDlin= 0

⇒ VDS = 0

⇒ Vo = Vi = 0V

Figure 45: CMOS Transmission Gate with Vc at 1, Vi at 0

(a) Vi == VDD as shown in Figure 46

If Vo < VDD, i is as shown thus fixing the source and drain as shown in each transistor

and charging the load capacitor. Consider TP :

VSG = VDD, VSD = VDD − Vo is small.

Therefore TP is in a linear mode of operation. But eventualy IDlin= 0.

⇒ VSD = 0

⇒ Vo = Vi = VDD

Thus in summary (noting Z indicates high impedance):


Figure 46: CMOS Transmission Gate with Vc at 1,, Vi at VDD

Table 7: Transmission Gate

Vc Vi Vo

0 0 Z

0 1 Z

1 0 0

1 1 1

10.3 XOR Gate

Consider the following circuit.

Figure 47: CMOS Transmission Gate as XOR

If A = 1, A = 0, then TGo transmits while TG1 blocks.

⇒ X = B

If A = 0, A = 1, then TGo blocks while TG1 transmits.

⇒ X = B


Hence overall the expression this gate implements is:

X = A.B + A.B = A ⊕ B

This is the exclusive-OR function. With primitive gates, this could be implemented as

follows:

This approach requires 4X4 transistors = 16 transistors while the transmission gate

implementation requires only 4. This example illustrates the usefulness of the TG in

”data selection” types of problems. Consider a 4X1 data multiplexer defined as follows:

Figure 48: Multiplexer Example


Again if this were to be implemented through conventional logic design:

X = S1S0D0 + S1S0D1 + S1S0D2 + S1S0D3

requiring:

2X 3-input NOR=12T

1X 2-input NAND=4T

1 inverter = 2T

Total = 18T.

(Note this is indicative, depending on how you break down the expression you can get a

different number of transistors)

10.4 Discussion

Transmission Gates may be employed with Boolean equations of the type:

X = A(G) + A(H)


if A=1, select G; If A=0, select H. Note that A and A must both be present to enable one

transmission gate. If no transmission gate is enabled, then the output is undefined which

is not normally a state we wish to encounter.

Recommended reading for this section: Many of the text books consider the oper-

ation of the transmission gate over a full range of Vi from 0toVDD and thus the treatment

is more detailed that here. However the application of the TG to XOR and multiplexer

functions is still relevant and worth reading about (though have not found many definitive

sources).

• Kang et all, chapter 7, section 7.5 but page 300 for XOR only


11 CMOS - Dynamic Analysis

This section looks at the dynamic behaviour of the CMOS inverter. A first order analysis

of propagation delay of a CMOS inverter is discussed, having first explored the delay

mechanics qualitatively.

Objectives:

• to specify the elements than contribute to capacitive load

• to describe the dynamics of a capacitatively loaded inverter subject to an abrupt

input transition.

• to estimate the propagation delay

11.1 Introduction

The switching characteristic of digital integrated circuits in general and in particular the

inverter, essentially determine the overall operating speed of a digital system. In CMOS

systems, delay-producing mechanisms are expressed in the form of a capacitances -

charge storage elements. When a node has to change state, the node capacitance has

to be either charged or discharged. Parasitic capacitance is a term used to describe

capacitance that is not taken into account when considering ideal circuit elements. This

extra capacitance usually has detrimental effects. Consider an inverter followed by an-

other inverter as shown in Figure 49. The convention is to consider the delays in terms

of time taken to charge the capacitave load CL.

Figure 49: Capacitative load to model delays


The propagation delay is defined as the time delay between the input reaching 50%

of its final value and the output reaching 50% of its final value. We consider two delays:

tplh : the output changes low to high.

tphl : the output changes high to low.

From this, it is possible to then define the average propagation delay of the inverter as:

tp =tplh + tphl

2(38)

When one inverter (gate) is connected to another inverter (gate), there are three contri-

butions to the load capacitance CL

1. The input capacitance of the loading inverter. This capacitance is due to the

thin-oxide capacitance over the gate area.

Figure 50: Input Capacitance

Cin = Cgate(TN) + Cgate(TP )

= CoxWNLN + CoxWP LP where Cox = εox

tox

2. The capacitance of the interconnect

This represents the parasitic capacitance contribution of the metal (polysilicon) connec-

tion between the two inverters. Each interconnection line (wire) is a 3-d structure in metal

and/or polysilicon. Consider a wire segment of length lint, it can be assumed to be run-

ning parallel to the chip surface and is separated from the ground plane by a dielectric

(oxide) layer. The accurate estimation of interconnect capacitances with respect to the

ground plane, and each other, is a complex task. For the purpose of our discussion, we

will simply observe that the interconnect is in effect the top plate of a parallel capacitor

and that for a standard width of interconnect then:

Cint ∝ lint


Figure 51: Interconnect Capacitance

3. The output capacitance of the driving inverter. CD(TN ) can be considered as the

voltage dependent drain-substrate junction capacitance. This capacitance is due to de-

pletion charge surrounding the drain depletion region embedded in the substrate. Note

this is a reverse-bias pn junciton uner normal operating conditions. For the inverter:

Figure 52: Output Capacitance

Cout = CD(TN) + CD(TP )

both of which depend on the width of the channel. The basic trouble here is that these

capacitances are voltage dependent. However, we will assume a constant equivalent

capacitance.

Hence the overall load capacitance can be expressed:

CL = Cout + Cint + Cin (39)

11.2 Response to abrupt Input

Consider a capacitively loaded inverter subject to an abrupt input transition 0V → VDD.

Initially CL is charged to VDD and must be discharged to 0V . At the moment of switching:

TP Linear → OFF and plays no further role

TN turns ON, initially in SAT since VDS = VDD > VGS(VDD) − VT


Figure 53: Aprupt change in Input Voltage

The resulting iD discharges CL according to:

iD = −CLdVo

dt

As Vo discharges, it eventually passes through VDD−VT and at this point in time, TN goes

from the saturation to linear mode of operation. iD continues to flow and the capacitor

continues to discharge until Vo reaches 0V . Then iD goes to zero and the discharge is

complete.

11.3 Approximate Analysis

A full analysis of the propagation delay tphl is quite complex since TN spends part of

tphl in the saturation mode and part of tphl in the linear mode of operation. We can

however make a starting estimate by calculating an average value for iD during tp and

then assuming iD remains constant at this average value.

Figure 54: Output changing from high to low


ID =1

2(iD(atVo = VDD) + iD(atVo = 0.5VDD)) (40)

=1

2(iDSAT

+ iDLIN(VDS = 0.5VDD)) (41)

=1

2

[βN

2(VDD − VT )2 + βN

((VDD − VT )

VDD

2− 1

2(VDD

2)2

)](42)

=βN

4

[(VDD − VT )2 + (VDD − VT )VDD − V 2

DD

4

](43)

From earlier:

ID = −CLdVo

dt∫ tphl

0dt = − ∫ 0.5VDD

VDD

CL

IDdVo

⇒ tphl = 0.5CLVDD

IDnoting that ID is now assumed constant from our assumption.

Hence we can write the propagation delay as:

tphl =0.5CLVDD

βN

4

[(VDD − VT )2 + (VDD − VT )VDD − V 2

DD

4

] (44)

For reasons we will explain later, we chose to write this equation in the form:

tphl =

[2CL

βN(VDD − VT )

]⎡⎣ VDD

(VDD − VT ) + VDD − 14

V 2DD

(VDD−VT )

⎤⎦ (45)

The second term on the right is dimensionless and we evaluate for a typical case of

VT = 0.2VDD. Substituting, we get:

tphl = 1.68CL

βNVDD

(46)

11.4 Other delays characterising the CMOS Inverter

We have looked at the propagation delay time, the time taken for the output signal to

respond to a change in input signal for the inverter. Another important delay is the rise or

fall time of the inverter demonstrated in Figure 55. The rise time trise is the time required


Figure 55: Rise and Fall Times

for the output voltage Vo to increase from the V10% level to the V90% level. Similarly the

fall time tfall is defined as the time required for the output voltage to drop from the V90%

level to the V10% level. For an inverter where the low level is 0V and the high level is the

supply voltage VDD the voltage levels V10% and V90% are defined:

V10% = 0.1VDD

V90% = 0.9VDD

Note that sometimes the rise and fall times use a 20% and 80% level.

11.5 Discussion

The analysis we have employed for the dynamic behaviour of the CMOS inverter allows

the following observations:

• tp ∝ CL as might be expected

• tp ∝ 1β

or equivalently tp ∝ LW

emphasising that to minimise the delay, we need

to minimise L. For design purposes, tp can be reduced by increasing W . Note

however that this increases Cout.

• tp ∝ 1VDD−VT


• Kang et al, Chaper 3, section 3.6 for detailed material on capacitances in MOSFET

• Kang et al, Chapter 6, section 6.1-6.3 though the derivations are in more detail.


12 MOSFET Capacitances

In moving to analysing the transient response of CMOS circuits, it is necessary to con-

sider the parasitic capacitances related to the MOS transistor. A simple model was used

to determine a load capacitance for a cascaded inverter in the previous chapter. We will

now take a closer look at MOSFET capacitances. Note this chapter follows Section 3.6

of Kang.

Objectives:

• to identify sources of capacitance in the MOSFET

• to consider the causes of these capacitances

12.1 Models of capacitance

Exact modelling of on-chip capacitance for CMOS requires extremely complex models.

Hence we will use simplified models that capture the general behaviour of the MOS

transistor and that can be built should more detailed models be required.

Figure 56: Cross sectional view and top view of NMOS (from Kang)

Figure 56 shows a cross sectional view and top (or mask) view of an NMOS transistor.

Note the actual channel length is L whilst the channel mask length is LM . This accounts


for overlap in the gate-source and the gate-drain regions. The source and drain diffusion

regions are surrounded by a p+ doped region acting as a channel stop implant, isolating

the NMOS from other devices on the substrate.

Figure 57: Parasitic capacitances for MOSFET, lumped representation (from Kang)

Figure 57 shows how parasitic capacitances in the MOSFET can be represented

as lumped capacitances observed between the device terminals. This representation

facilitates our simplified analysis. The capacitances can be divided into two categories:

• oxide related capacitances

• junction capacitances

12.2 Oxide capacitances.

As shown in Figure 56, the gate physically overlaps both the source and drain at their

edges. Related capacitances can be denoted CGD(overlap) and CGS(overlap). Assum-

ing both diffusion regions have the same width W , these overlap capacitances can both

be equated to CoxWLD. Note these capacitances are independent of voltage.

Cgs, Cgd, and Cgb are capacitances resulting from the interaction of the gate voltage

and the channel. Recall that each of the source, drain and bulk (substrate) are connected

to the channel region. Hence there is capacitance associated with the gate and each

of these regions. For this simplified treatment, the capacitance can be approximated by

considering the channel in cut-off, linear and saturation.

Cut-Off:


Table 8: Approximate Oxide Capacitance Values for MOS operating regions

Total Capacitance Cut-Off Linear Saturation

Cgb CoxWL 0 0

Cgd CoxWLD12CoxWL + CoxWLD CoxWLD

Cgs CoxWLD12CoxWL + CoxWLD

23CoxWL + CoxWLD

The surface is not inverted and hence there is conducting channel connecting the chan-

nel surface to the source and drain. The gate-to-source and gate-to-drain capacitances

will be zero. The gate-to-substrate capacitance is approximated by CoxWL.

Linear Mode:

The inverted channel extends from the source to the drain region. The conducting layer

shields the substrate from the gate electric field, resulting in Cgb of zero. The distributed

gate-to-channel capacitance can be considered as shared equally between source and

drain giving:

Cgs∼= Cgd

∼= 0.5CoxWL

Saturation Mode:

Recall that in saturation, the inversion layer does not extend to the drain but becomes

pinched-off. The gate-to-drain capacitance will be zero in this case (Cgd = 0). The

source is still linked to the conducting channel and its shielding effect forces the gate-to-

substrate capacitance to zero (Cgb = 0). The distributed gate-to-channel capacitance as

seen between the gate and source can be approximated as:

Cgs∼= 2

3CoxWL

12.3 Junction Capacitances

The junction capacitances are the voltage dependent source-substrate and drain-substrate

junction capacitances. These are denoted Csb and Cdb and are due to the depletion

charge surrounding the respective diffusion regions embedded in the substrate. In nor-

mal operation these p-n junctions are reversed biased and the capacitance is a function


of the terminal voltages.

An analysis of the region as an abrupt p-n junction yields an equation for the junction

capacitance as:

Cj(V ) =ACj0

(1− VΦ0

)m

where Cj0 is the zero-bias junction capacitance per unit area, A is the area of the junc-

tion, Φ0 is the built-in junction potential, and m is the grading coefficient with m = 0.5 for

an abrupt p-n junction profile.

Required reading for this section:

This section is based on Kang’s book and the section below should be referred to to

supplement the above material.



13 Gate Delays

Simulation of circuits is necessary but every good designer should have a method for

calculating delays using a pen and paper type approach. Being able to get a quick esti-

mate of how a change in a circuit should affect delays allows more meaningful changes

to circuit simulations that can take hours (as opposed to using blind hope to change

parameters, hoping your circuit will meet timing). This section introduces the use of

approximate RC delay models to estimate delays.

Objectives:

• Introduce RC delay models

• Examine RC delay model for inverter

• Introduce Elmore Delay model

• Examine delay of 2-Input NAND

13.1 Switch level RC delay models

RC delay models can be used to approximate the non-linear I-V and C-V characteristics

as constant values over the switching range of a gate. These models do NOT accurately

predict detailed behaviour but are useful for approximate analysis of circuits

The RC delay model models a transistor as a switch in series with resistors. An

nMOS transistor of minimum width Wmin and minimum length Lmin is said to have a

resistance of R. An nMOS transistor of k times minimum width has resistance of Rk. A

pMOS transistor of minimum width and length will have resistance 2R due to the lower

mobility. Assume always that μn = 2μp. This gives a resistance of 2R compared to the

nMOS value of R. Consider the unit inverter below:


An approximate value for R can be taken from the derivative of the linear drain current

as:

A transistor has capacitance due to the gate and depletion regions. We define C

to be the gate capacitance of a unit transistor, either nMOS or pMOS. A transistor of k

times unit width has capacitance of kC. The source or drain (min width again) can also

be assumed to have capacitance of C. This allows the basic RC circuit model for both

an nMOS and pMOS transistor to be drawn.

Delay of Inverter.

The propagation delay of logic gates can be estimated from these RC models. Consider

how to estimate the delay of inverter with a fanout-of-1. This inverter has an nMOS with

unit size and a pMOS with width 2Wmin to achieve equal resistance. The inverter can be

redrawn using the RC models. (note the depletion capacitances at the source are not

charged/discharged and are hence not shown). If the input goes high, the nMOS will be

ON and the pMOS will be OFF, allowing the circuit to be redrawn without the switches,

or any capacitance that is shorted between two constant supplies.


The propagation delay is approximated as the RC time constant of the resistor charg-

ing or discharging the diffusion and load capacitances. This gives a delay of 6RC

13.2 More complex gates

The RC models can also be used to predict delays in more complex gates. Transis-

tors in series combine like resistors in series, i.e. their resistance is the sum of their

resistances. Likewise, transistors in parallel will combine like resistors in parallel. With

multiple resistors in parallel, their resistance is lower if they are all ON. Thus in many

cases the worst case (WC) delay will occur when only one of many parallel resistors is

ON, giving effective resistance of just one transistor.

Example - 3-input NAND.

Consider a 3-input NAND gate. Determine suitable transistor widths to give effective rise


and fall resistance equal to that of the unit inverter.

With the 3 nMOS in series, the total resistance is 3R. In the worst case, only one of

the three pMOS will be ON.

Example - 3-input NAND capacitances.

Redraw the previous 3-input NAND gate with date and depletion capacitances. Can


assume diffusion nodes contacted except for the series transistors.

Note that in redrwawing this we have left out source capacitances attached to the

power supply as both terminals are shorted together. Remaining capacitances have

been lumped to ground.

13.3 Elmore Delay Model

Viewing ON transistors as resistors, a chain of transistors can be modelled as an RC

ladder as shown below.


The Elmore delay model estimates the delay of and RC ladder as the sum over each

node in the ladder of the resistance Rn−i between that node and a supply multiplied by

the capacitance on that node, i.e.:

tp =∑

i

Rn−iCi =N∑

i=1

Ci

i∑j=1

Rj (47)

Example - 2-input NAND driving h identical NAND gates

Sketch a 2-input NAND gate with transistor widths chosen to achieve effective rise and

fall resistance equal to a unit inverter. Compute the rising and falling propagation delays

(in terms of R and C) of the NAND gate driving h identical NAND gates using the Elmore

delay model. If RC = 5ps for a 180μm process, what is the delay of a fanout-of-3 NAND

gate.


Extra Note added:

When there are multiple transistors in the CMOS circuit in the examples here, we have

used the assumption of contacted diffusion nodes except for the series transistors. Thus

where the source and drain of two transistors are connected in series, we have shown

just one capacitance value.

Required reading for this section:

• Weste et al, Chapter2 Section 2.6, Chapter 4, Section 4.2


14 Power Dissipation

We have seen that a major attraction of CMOS gates is that they consume virtually no

power when in a static state. Hence, for many years power dissipation was almost a

secondary concern in CMOS design after area and speed. Now however with smaller

and smaller transistors, higher clock frequencies, and more transistors packed onto a

single chip, power consuption is a crucial element in any digital system.

Objectives:

• To identify the main contributing factors

• To quantify static and dynamic power contributions

• To consider techniques used for low power design

14.1 Contributing Components

Power consumption in CMOS circuits comes from two components:

• Static Dissipation due to:

– subthreshold conduction

– tunneling current through gate oxide

– leakage currents

• Dynamic Dissipation due to:

– charging and discharging of load capacitances

– short circuit currents when NMOS and PMOS networks are partially on

The total power can therefore be expressed as:

Ptotal = Pstatic + Pdynamic (48)

We will examine these individual components and discuss techniques commonly used

to minmise power consumption in circuit design.


14.2 Static Dissipation

From our study of the CMOS inverter, we have seen that in the case of low or high

output, either the PMOS or NMOS transistor is in the OFF state and no current flows.

Hence, when no transistor is switching, the current is zero and the power dissipation is

also zero. Due to secondary effects such as sub-threshold conduction, tunneling and

leakage, small amounts of static current can actually flow in the OFF transistor. The

subthreshold current has been seen in equation (25) to be exponentially dependent on

threshold voltage. It has thus increased dramatically as threshold voltages have scaled

down. We have also considered gate oxide leakage (again refer back to Section (5)).

The static power can be expressed as the product of the total leakage current and

the supply voltage VDD as:

Pstatic = IstaticVDD (49)

In older processes, these components of static power were sufficiently small as to be

considered to be zero and CMOS was said to have zero DC power. Since going beyond

120 − 130ηm, this static power has become a primary design issue. The first test on

any new IC is typically to measure this static current when all data inputs are inactive. If

the values is larger than expected, it can indicate a fault in the chip. This stage of chip

testing, to check the corrent functionality when the chip is returned from manufacturing,

is commonly referred to as validation.

14.3 Dynamic Dissipation

The main source of dynamic power dissipation comes from the charging and discharging

of load capacitances during switching. Each time a CMOS inverter changes state, the

capacitative load has to be either charged or discharged.

ichg results in dissipation in TP .

idis results in dissipation in TN .


To derive an expression of Pdynamic, consider the energy dissipation in each transistor

due to this current.

Let EP denote the energy dissipation in TP due to ichg

Let EN denote the energy dissipation in TN due to idis

Consider the dissipation in TP :

EP = 12CLV 2

DD

Thus resulting from ichg, the energy stored on CL is 12CLV 2

DD. This energy is then dissi-

pated in TN when idis flows, i.e.:

EN = 12CLV 2

DD

Assuming a switching frequency fsw,then the average power dissipation is:


Pdynamic = CLfswV 2DD (50)

Realistically (and hopefully by design!), gates in a system will not switch every clock

cycle. It can however be convenient to relate the swithcing frequency fsw to the clock

frequency f by an activity factor α. The clock has an activity factor of 1. Data will

generally have a maximum activity factor of 0.5 since it transistions only once each cycle.

In this case, the dynamic power can be rewritten as:

Pdynamic = αCLfV 2DD (51)

Short-circuit power dissipation is the other contributing factor for dynamic power. In-

put waveforms are typically non-ideal with finite rise and fall time. During the rise time,

both transistors conduct resulting in what is termed short-circuit current. The power

dissipation due to this current is typically much lower than that due to capacitve load

charging and discharging.

14.4 Low Power Design

Total power dissipation is the sum of the static and dynamic components. Dynamic

power, always having been the more significant factor, has traditionally been the target

in low power design techniques. There is no silver bullet for low-power design. Good low

power design is influenced both by an understanding of the CMOS hardware involved

and the actual digital system being implemented. Dynamic power has been seen to be

related to:

• activity factors

• load capacitance

• power supply

• operating frequency

Activity factor reduction is very important. Consider an adaptive FIR filter with 100 taps

where filter tap values are being updated every clock cycle according to some SNR (Sig-

nal to Noise Ratio) measured at the output of the system. By using system knowledge,

here whether or not a change in tap value is required to maintain the SNR within a


desired range, the activity factor of the taps could be significantly reduced by not unnec-

cessarily updating every cycle.

The clock signal in a system has an activity factor of 1. Hence the clock network

of a digital system consumes a large amount of power. Clock-gating, where the clock

going to an entire section of the design can be temporarily switched off (gated off), can

significantly reduce the power in large designs.

Voltage supply has a quadratic effect on dynamic power and hence a lower power

supply significantly reduces power. We have seen that scaling transistors reduces the

power when the constant electric field scaling approach is used. It is important to re-

alise that systems will have an analog and a digital component and this scaling is more

pronounced for the digital hardware.

A systems approach to power reduction involves not just understanding the hardware

but also the actual system being implemented. In image and speech processing applica-

tions for example, the Fast Fourier Transform (FFT) requires less arithmetic operations

and hence less power than a Discrete Fourier Transform (DFT). Complex multiplication

at first inspection required 4 multiplies. The number of actual multiplies can be reduced

to 3 (how??). This is significant as multiplication is much more expensive in hardware

(i.e. requires more gates and time) than addition.

Static power dissipation is kept in check by techniques to reduce leakage currents.


Older texts will tend to completely playdown the contribution from static currents. The

treatment in Weste et al is more up to date.

• Weste et al, Chapter 4, section 4.4 (where 4.4.3.2 can be read out of interest but

we have not gone in to depth on this)


15 Sequential CMOS Circuits

We have looked at a number of useful gates for implementing combinatorial CMOS logic.

We now turn our attention to sequential logic.

Objectives:

• to characterise the elements of sequential circuits

• to present the basic electrical operation of the bistable element

15.1 Introduction

In the combinatorial circuits we have investigated, if we neglect propagation delay time,

we have seen that the outputs of such elements change according to some Boolean

function of the input applied at any time. The current output depends only on the current

inputs and the circuit has no memory of previous values. Such elements are also referred

to as non-regenerative circuits.

The other major class of logic circuits is sequential circuits, where the output is de-

termined not only by the current input, but also previously applied inputs. This regen-

erative behaviour is generally caused by either direct or indirect feedback between the

output and the input. Such circuits can be said to have state. Finite state machines and

pipelines are important examples of sequential circuits. Sequential circuitry has memory.

15.2 Bistability

The memory function of the sequential circuit can be achieved in a number of different

ways. The approach we will study uses positive feedback. Here, one or more outputs are

connected back to the inputs. There are three main groups: bistable circuits, monostable

circuits and astable circuits. Monostable circuits have only a single stable operating

point (state). Astable circuits has no stable operating point or state which the circuit can

preserve for a period of time. The bistable circuits, as their name implies, have two stable

states or operation modes. Each of these can be attained under certain input and output

conditions. All basic latch and flip-flop circuits, registers and memory elements used in

digital systems fall into this category. Hence we will examine the eletrical behaviour of

the bistable element and then look at practical applications.


Figure 58: Two cascaded inverters

Consider Figure 58 showing two inverters connected in cascade. This diagram also

shows the VTC of the circuit. The output Vo1 of the first inverter is plotted against its

input Vi1 and the output of the second inverter, Vo2, is shown plotted against its input,

Vi2. However, Vi2 is Vo1. The second inveter VTC is shown rotated to highlight this. If the

ouput of this second inverter is then connected back to the input of the first inverter, the

resulting circuit has only 3 possible operation points (the intersecting points A, B and C)

as shown by combining the two VTCs.

Two of these operating points are stable, A and B. If the circuit is initially in one of

these states, it will preserve this state unless forced externally to change its operating

point. The gain of each inverter circuit is given by the slope of the VTC. Note in this case

that this gain (slope) is smaller that unity at these two points. Even a large deviation from

the operating point is reduced in size and disappeares. Therefore, in order to change the

state by moving from one stable state to the other, a sufficiently larger external voltage

perturbation must be applied so that the voltage gain of the inverter loop becomes larger

than unity.

The voltage gains of both inverters are greater than unity at the third operating point

C. Therefore, even if the circuit is biased at this point initially, any small voltage pertuba-

tion at the input to any of the inverters wil be amplified causing the operating point to shift

to one of the stable operating points A or B. It is highly unlikely the inverter pair can be

biased at C and remain there. This state is therefore technically metastable. (Metasta-


Figure 59: Perturbation in input

bility in electronics is the ability of a non-equilibrium electronic state to persist). These

two cases are shown in Figure 59.

This cross-coupling of the two inverters therefore results in a bistable circuit with each

of the two stable states corresponding to a logic state. The circuit can act as a memory,

storing a 1 or 0 (at point A or B). To change the circuit from A to B or vice versa, it is

possible to temporarily make A or B unstable by increasing the gain to a value larger than

1. This is generally doen by applying some trigger pules at Vi1 or Vi2. Another common

name for a bistable circuit is flip flop.

15.3 Latches and Flip Flops

Firstly a word on terminology. What is the difference between a latch and a flip flop?

Sometimes the distinction between latches and flip flops becomes rather hazy. By some

definitions, a latch is a level sensitive device whilst a flip-flop is an edge sensitive device.

A flip flop therefore will be always be clocked. However you can have clocked latches that

only respond to inputs when the clock is high and flip flops that are always active when

the clock is active and not just on the edge. The distinction is not really that important.

Just pay attention as we move from a simple latch, to a clocked latch, to a clocked flip

flop to a edge-sensitive clocked flip flop....


15.3.1 SR Latches

We have looked at the two inverter circuit and seen it has two stable operating points.

This circuit can preserve its state as long as the power supply is provided; hence the

simple memory functionality of holding its own state. We have also seen that to change

state, we need access to the inputs to somehow trigger the change. Figure 60 shows a

simple CMOS SR latch with two such triggering inputs S (Set) and R (Reset). The circuit

consists of two CMOS NOR2 gates (NOR2 indicating 2-input NOR).

Figure 60: CMOS SR latch circuit based on NOR2 gates

The SR latch circuit has two complementary outputs, Q and Q. The latch is in its set

state when Q is equal to logic high (1) (and hence Q is equal to logic low (0)). The latch

is in its reset state when when Q is equal to logic low (0) (and hence Q is equal to logic

high (1)).

Figure 61: Gate level schematic and block diagram of the NOR-based SR latch

Figure 61 shows the gate level schematic and symbol for this latch. When both input


Table 9: Truth Table for 2-input NOR based SR-latch

S R Qn+1 Qn+1 Operation

0 0 Qn Qn hold

1 0 1 0 set

0 1 0 1 reset

1 1 0 0 not allowed

Table 10: Operation modes of the NMOS transistors for 2-input NOR based SR-latch

S R Qn+1 Qn+1 Operation

1 0 1 0 M1 and M2 on, M3 and M4 off

0 1 0 1 M1 and M2 off, M3 and M4 on

0 0 1 0 M1 and M4 off, M2 on OR

0 0 0 1 M1 and M4 off, M3 on

signal are low, the SR latch will operate like the bistable element previously considered.

It will hold either one of its stable operating points as determined by the previous inputs.

If S is 1 and R is 0, the output Q will be forced to 1 while Q is forced to 0. Hence the

SR latch will be set regardless of its previous state. If S is 0 and R is 1, then the output

Q will be forced to 0 while Q is forced to 1. Hence the SR latch will be reset regardless

of its previous state.

If S and R are both equal to 1, in theory both Q and Q will be forced to 0, conflicting

with the inherent complimentarity of these outputs. This is hence considered a ”not-

allowed” condition. This allows us to summarise the truth table for the SR Latch in the

table shown in Table 9.

The operation of this circuit can be considered in terms of the operating modes of the

NMOS transistors, M1, M2, M3, and M4.

If the set input S is high and the reset R is low, both M1 and M2 will be ON. Hence

node Q will be low. At the same time, M3 and M4 are turned off, meaning that node Q

will be high.

If the set input, S, is low and the reset, R, is high, the situation is reversed.

When both S and R are low, there are two possibilities. Depending on the previous

state of the SR latch, either M2 or M3 will be on while both of the trigger transistors M1

and M4 are off. This will generate a low level at one of the output nodes whilst the other

will be high.


It is also possible to construct the SR latch circuit using NAND2 gates as shown in

Figure 62. In this case, in order to hold a state, both of the external trigger inputs must

be logic 1. The operating point of the circuit can only be changed by pulling the set input

S to zero or pulling the reset input R to zero. This NAND-based SR latch responds to

active low signals in contrast to the NOR-based SR latch which reacted to active-high

signals.

Figure 62: CMOS SR latch circuit based on NAND2 gates

Figure 63 shows the schematic, block diagram and truth table for the NAND-based

SR latch. The small circles at the inputs for S and R in the block diagram indicate that

these inputs are active low signals.

Figure 63: Gate level schematic, block diagram and truth-table of the NAND-based SR latch


15.3.2 Clocked SR Latch

The SR latch we have examined in the previous section is asynchronous and will repsond

to changes in input as soon as they occur (though there is natually a small propagation

delay through the gates). To achieve synchronous operation where ouputs only respond

to changes in input at regular time intervals, a clock signal can be added to the circuit.

The clock signal will be assumed to be a periodic square waveform which is applied to

all clocked logic gates in the digital system at the same time.

Figure 64: Clock controlled NOR-based SR latch

Figure 62 shows the extension of the NOR-based SR-latch of the previous section to

respond to a clock signal. Whenever the clock is logic 0, the inputs have no influence on

the output and the ouputs Q and Q will hold their current state regardless of the value

of S and R. When the clock is high, the inputs on S and R are permitted to reach the

latch and can potentially change the output according to the discussed truth-table. Once

again the input combination of S and R simultaneously equal to 1 is not permitted.

The operation of the circuit may be best understood by looking at the waveform in

Figure 65. The clock signal is denoted CK. Note when the inputs S and R change, the

output Q only reacts when CK is high.

The CMOS circuitry that implements this clocked SR latch is shown in Figure 66. We

will not examine its operation in full. It is also possible to construct a clocked NAND-

based SR latch where the clock signal is instead active low.

15.3.3 Clocked JK Latch (The JK Flip Flop)

The simple SR latch and clocked SR latch (whether NOR or NAND based) suffer from

the problem of having not-allowed input combinations. If these input combinations occur,

the state can become indeterminate. This problem is overcome by adding feedback from

the outputs to the inputs to form a JK latch. The JK latch is commonly called a JK flip


Figure 65: Sample input and output waveforms demonstrating operation of clocked NOR-based

SR latch

Figure 66: CMOS implementation of clocked NOR-based SR latch

flop. Figure 67 shows the schematic for this circuit while Figure 68 shows a NAND gate

implementation.

The J and K inputs correspond to the S and R inputs of the SR latch. When the clock

is active (high), the latch can be set with the input combination of J=1, K=0. It can be

reset with the input combination J=0, K=1. If both inputs are 0, the latch preserves its

current state. If both inputs are high during an active clock phase, the latch will change

its state according to the feedback. The JK latch holds its current output whenever the

clock is inactive (low). The operation of the circuit is summarised in the truthtable in

Table 11.

The JK latch does not have a not-allowed input combination but there remains a

problem. If both the inputs are high during the active phase of the clock, we have seen


Figure 67: Gate-level schematic of clocked NAND-based JK latch circuit

Figure 68: NAND-based clocked JK latch circuit

that the output will toggle until either the clock goes low (inactive), of either input changes.

To avoid this, the clock pulse can be made smaller than the propagation delay of the JK

latch. This means that the clock would have to go low before the output had a chance to

change again. In practice this clock constraint is very difficult to implement practically.

15.3.4 Master-Slave Flip Flop

Most of the timing problems of the JK clocked-latch can be prevented by using two latch

stages in a cascaded configuration. The two cascaded stages are activated with oppo-

site clock phases. This configuration is referred to as the master-slave flip flop. Such

a circuit is shown in Figure 69. The input latch, or master, is activated when the clock

is high. During this phase, the inputs J and K allow data to be entered into the flip flop

and the first stage outputs are controlled according to the previous JK latch truth ta-

ble. When the clock goes low, the master latch becomes inactive and the second stage

latch, the slave, becomes active. The output levels are determined in this phase by the

master-stage outputs set in the previous stage.

The master and slave stages are decoupled from each other with the opposite clock-

ing scheme. Hence a change in the J and K inputs is never reflected directly at the out-


Table 11: Detailed Truth Table for JK flip-flop

J K Qn Qn S R Qn+1 Qn+1 Operation

0 0 0 1 1 1 0 1 hold

1 0 1 1 1 0

0 1 0 1 1 1 0 1 reset

1 0 1 0 0 1

1 0 0 1 0 1 1 0 set

1 0 1 1 1 0

1 1 0 1 0 1 1 0 toggle

1 0 1 1 0 1

Figure 69: Master-slave flip flop consisting of NAND-based JK latches

put. This behaviour can be best seen by referring to the input output waveforms shown

in Figure 70. Note the final output responds to changes in the master stage outputs on

the low cycle of the clock.

15.3.5 CMOS D-latch and edge-triggered flip flop

Whilst the master-slave configuration solved some issues with timing in latch circuits, it

is still possible to encounter the problem of ”one’s catching”. When the clock is high, a

glitch (narrow spike) in J or K could set or reset the master latch, causing an unwanted

transition which then gets propagated to the slave stage. This problem is addressed by

the construction of a master-slave edge-triggered flip flop.

We have already discussed how the transmission gate can reduce the number of

transistors used in CMOS combinatorial logic circuits. (recall the XOR, multiplexers).

Sequential circuits built from TGs are also generally simpler and require fewer transis-

tors. The circuit in Figure 71 shows a D-latch. It is a modification of the NOR-based

clocked SR latch. The circuit has a single input D which is fed to the S input. D is


Figure 70: Sample input and output waveforms for master-slave flip flop

also inverted and fed to the R input of the latch. The output Q assumes the value of D

whenever the clock is active (high). When the clock goes inactive (low), the output will

preserve its state. Thus the clock acts as an enable allowing the data at D to appear on

the output.

Figure 71: Gate level schematic and block diagram view of D-latch

The D-latch is a widely used element in digital CMOS circuitry. It is mainly used as

a delay element and for temporary data storage to facilitate synchronous operation of

designs. Figure 72 shows a CMOS implementation of the D-latch using transmission

gates and two inverters. The TG at the input is activiated by the clock signal. The other


TG, in the inverter loop, is enabled by the inverted clock signal. The input signal gets

latched into the circuit when the clock is high, and this value gets preserved as the state

of the inverter loop when the clock is low.

Figure 72: CMOS implementation of D-latch

A good way to consider the operation of this circuit is to think of the TGs as switches

as shown in Figure 73. The corresponding timing diagram is shown. The shaded por-

tions show the time intervals during which the input and output should be valid. The

input D must be stable for a short time before (setup time) and for a short time after (hold

time) the negative clock transition. This latch is not edge-triggered, it is transparent: the

output changes directly with the input while the clock is high.

Figure 73: Simplified view of the D-latch and timing diagram demonstrating setup and hold times


To be useful for counting and data storage, an edge triggered D latch would be useful.

One such example is shown in Figure 74. This is a master-slave D flip flop constructed

by cascading two D-latch circuits. The master stage is driven by the clock signal. The

slave stage is driven by the inverted clock. Therefore, the master stage is positive edge

sensitive and the slave stage is negative edge sensitive.

Figure 74: CMOS negative (falling) edge-triggered master-slave D flip flop.

When the clock in high, the master stage follows the D input and the slave holds its

previous state. As the clock transitions from 1 to 0, the master latch ceases to sample

the input and stores the D value at the time of the clock transition. At the same time, the

slave latch becomes transparent and passes the stored value Qm from the master stage,

to Qs the output of the slave stage. When the clock changes again from 0 to 1, the slave

locks in this master latch output and the master once again starts to sample the input D.

This D-type flip flop essentially samples the input at every falling edge of the clock pulse.

The waveforms in Figure 75 will help show the behaviour of this circuit.

Recommended reading for this section: This section closely follows the treatment

in chapter 8 of Kang et al. with some sections omitted (most diagrams are taken directly

from the book). The explanation of bistability is better in Rabaey though.

• Kang et al, Chapter 8

• Rabaey et al, Chapter 6, section 6.2.1 for bistability


Figure 75: Example of input and output waveforms for negative edge-triggered master-slave D

flip flop.


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