41494066 Low Power Vlsi in CMOS
-
Upload
punith-gowda-m-b -
Category
Documents
-
view
228 -
download
0
Transcript of 41494066 Low Power Vlsi in CMOS
![Page 1: 41494066 Low Power Vlsi in CMOS](https://reader030.fdocuments.us/reader030/viewer/2022021119/577d33a31a28ab3a6b8b4f94/html5/thumbnails/1.jpg)
8/8/2019 41494066 Low Power Vlsi in CMOS
http://slidepdf.com/reader/full/41494066-low-power-vlsi-in-cmos 1/28
LOW POWER VLSI
By,K.Nagendra
06S11A0421
![Page 2: 41494066 Low Power Vlsi in CMOS](https://reader030.fdocuments.us/reader030/viewer/2022021119/577d33a31a28ab3a6b8b4f94/html5/thumbnails/2.jpg)
8/8/2019 41494066 Low Power Vlsi in CMOS
http://slidepdf.com/reader/full/41494066-low-power-vlsi-in-cmos 2/28
Why worry about power?
--Heat DissipationMicroprocessor power Consumption
![Page 3: 41494066 Low Power Vlsi in CMOS](https://reader030.fdocuments.us/reader030/viewer/2022021119/577d33a31a28ab3a6b8b4f94/html5/thumbnails/3.jpg)
8/8/2019 41494066 Low Power Vlsi in CMOS
http://slidepdf.com/reader/full/41494066-low-power-vlsi-in-cmos 3/28
Why we go to Low Power..
PORTABILITY:
Enhanced run-time, Reduced weight, Reduced
volume, Low cost operation
High Performance:
Low-cost cooling, Low-cost packaging, Low-cost
operation
RELIABILITY: Avoid thermal problems
Avoid scaling related problems
![Page 4: 41494066 Low Power Vlsi in CMOS](https://reader030.fdocuments.us/reader030/viewer/2022021119/577d33a31a28ab3a6b8b4f94/html5/thumbnails/4.jpg)
8/8/2019 41494066 Low Power Vlsi in CMOS
http://slidepdf.com/reader/full/41494066-low-power-vlsi-in-cmos 4/28
Speed/Power performance for
available Technologies
![Page 5: 41494066 Low Power Vlsi in CMOS](https://reader030.fdocuments.us/reader030/viewer/2022021119/577d33a31a28ab3a6b8b4f94/html5/thumbnails/5.jpg)
8/8/2019 41494066 Low Power Vlsi in CMOS
http://slidepdf.com/reader/full/41494066-low-power-vlsi-in-cmos 5/28
Where Does Power Go In CMOS
Dynamic Power Consumption :
Charging and Discharging Capacitors
Short Circuit Currents :
Short circuit path between supply rails during
switching
Leakage:
Leakage diodes and transistorsPtotal = PDYN + PSC + PLeakage
=CLVDDF+VDDIPEAK{(Tr + Tf )/2}F+VDD ILEAK
![Page 6: 41494066 Low Power Vlsi in CMOS](https://reader030.fdocuments.us/reader030/viewer/2022021119/577d33a31a28ab3a6b8b4f94/html5/thumbnails/6.jpg)
8/8/2019 41494066 Low Power Vlsi in CMOS
http://slidepdf.com/reader/full/41494066-low-power-vlsi-in-cmos 6/28
Dynamic Power Consumption
Energy/transition = CL
* Vdd
2
![Page 7: 41494066 Low Power Vlsi in CMOS](https://reader030.fdocuments.us/reader030/viewer/2022021119/577d33a31a28ab3a6b8b4f94/html5/thumbnails/7.jpg)
8/8/2019 41494066 Low Power Vlsi in CMOS
http://slidepdf.com/reader/full/41494066-low-power-vlsi-in-cmos 7/28
Dynamic Power Consumption
Power = Energy / Transition * transition rate
=
So, power is proportional to Vdd , f ,CL
Power dissipation is data dependentFunction of switching activity
CL* Vdd
2* f
![Page 8: 41494066 Low Power Vlsi in CMOS](https://reader030.fdocuments.us/reader030/viewer/2022021119/577d33a31a28ab3a6b8b4f94/html5/thumbnails/8.jpg)
8/8/2019 41494066 Low Power Vlsi in CMOS
http://slidepdf.com/reader/full/41494066-low-power-vlsi-in-cmos 8/28
Reducing Vdd
Power P is proportional to square of V
VDD has decreased in modern processes
± High VDD would damage modern tiny transistors
± Lower VDD saves power VDD = 5, 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, «
Further decreasing may cause affect to Threshold
voltage
Relatively independent of logic function and style.
Power Delay Product Improves with lowering Vdd.
By reducing Vdd Noise margin will be affected
![Page 9: 41494066 Low Power Vlsi in CMOS](https://reader030.fdocuments.us/reader030/viewer/2022021119/577d33a31a28ab3a6b8b4f94/html5/thumbnails/9.jpg)
8/8/2019 41494066 Low Power Vlsi in CMOS
http://slidepdf.com/reader/full/41494066-low-power-vlsi-in-cmos 9/28
Noise Margin
NML = VIL - VOL
NMH = VOH - VIH
![Page 10: 41494066 Low Power Vlsi in CMOS](https://reader030.fdocuments.us/reader030/viewer/2022021119/577d33a31a28ab3a6b8b4f94/html5/thumbnails/10.jpg)
8/8/2019 41494066 Low Power Vlsi in CMOS
http://slidepdf.com/reader/full/41494066-low-power-vlsi-in-cmos 10/28
Power Consumption is Data
Dependent A B Y
0 0 1
0 1 0
1 0 0
1 1 0
Ex: Static 2 i/p NOR Gate
P(A=1) = ½
P(B=1) = ½
Then
P(out=1) = ¼
P(out=0) = 1-P(out=1)
=1-1/4 = ¾
P(0->1) =P(out=1).P(out=0)
= ¾ * ¼ = 3/16
A
BY
![Page 11: 41494066 Low Power Vlsi in CMOS](https://reader030.fdocuments.us/reader030/viewer/2022021119/577d33a31a28ab3a6b8b4f94/html5/thumbnails/11.jpg)
8/8/2019 41494066 Low Power Vlsi in CMOS
http://slidepdf.com/reader/full/41494066-low-power-vlsi-in-cmos 11/28
Transition Probability of 2-input
NOR Gate
![Page 12: 41494066 Low Power Vlsi in CMOS](https://reader030.fdocuments.us/reader030/viewer/2022021119/577d33a31a28ab3a6b8b4f94/html5/thumbnails/12.jpg)
8/8/2019 41494066 Low Power Vlsi in CMOS
http://slidepdf.com/reader/full/41494066-low-power-vlsi-in-cmos 12/28
Transition Probabilities for Basic
Gates
Switching Activity for Static CMOS
P0 -> 1
= P0
* P1
P0 -> 1
AND(1-Pa * Pb) Pa Pb
OR (1-Pa)(1-Pb)(1-(1-Pa)(1-Pb))
EXOR (1-(Pa + Pb - 2Pa * Pb)) (Pa + Pb -
2Pa * Pb)
![Page 13: 41494066 Low Power Vlsi in CMOS](https://reader030.fdocuments.us/reader030/viewer/2022021119/577d33a31a28ab3a6b8b4f94/html5/thumbnails/13.jpg)
8/8/2019 41494066 Low Power Vlsi in CMOS
http://slidepdf.com/reader/full/41494066-low-power-vlsi-in-cmos 13/28
How about Dynamic Circuits..?
Power is only
dissipated when
out=0
Ceff = P(out=0) * CL
In1
In2 PDN
In3
Me
Mp
Clk
Clk
Out
CL
Two phase operation
Precharge (CLK = 0)
Evaluate (CLK = 1)
![Page 14: 41494066 Low Power Vlsi in CMOS](https://reader030.fdocuments.us/reader030/viewer/2022021119/577d33a31a28ab3a6b8b4f94/html5/thumbnails/14.jpg)
8/8/2019 41494066 Low Power Vlsi in CMOS
http://slidepdf.com/reader/full/41494066-low-power-vlsi-in-cmos 14/28
2 input NOR gate
A B Y
0 0 1
0 1 0
1 0 0
1 1 0
P(A=1) = ½
P(B=1) = ½
P(out=0) = ¾
Ceff = ¾ * CL
Switching activity is
always Higher inDynamic Circuits
![Page 15: 41494066 Low Power Vlsi in CMOS](https://reader030.fdocuments.us/reader030/viewer/2022021119/577d33a31a28ab3a6b8b4f94/html5/thumbnails/15.jpg)
8/8/2019 41494066 Low Power Vlsi in CMOS
http://slidepdf.com/reader/full/41494066-low-power-vlsi-in-cmos 15/28
Transition Probabilities For
Dynamic GATES
Switching Activity for Precharged Dynamic
Gates
P0 -> 1
AND(1-Pa * Pb)
OR (1-Pa)(1-Pb)
EXOR (1-(Pa
+ Pb
- 2Pa
* Pb
))
![Page 16: 41494066 Low Power Vlsi in CMOS](https://reader030.fdocuments.us/reader030/viewer/2022021119/577d33a31a28ab3a6b8b4f94/html5/thumbnails/16.jpg)
8/8/2019 41494066 Low Power Vlsi in CMOS
http://slidepdf.com/reader/full/41494066-low-power-vlsi-in-cmos 16/28
Glitching«
Glitching refers to spurious and unwantedtransitions that occur before a node settledown to its final steady-state value.
Glitching often arises when paths withunbalanced propagation delay convergesat the same point in the circuit.
The dissipation caused by the spurioustransitions can reach up to 25% of the totaldissipation for some circuits.
![Page 17: 41494066 Low Power Vlsi in CMOS](https://reader030.fdocuments.us/reader030/viewer/2022021119/577d33a31a28ab3a6b8b4f94/html5/thumbnails/17.jpg)
8/8/2019 41494066 Low Power Vlsi in CMOS
http://slidepdf.com/reader/full/41494066-low-power-vlsi-in-cmos 17/28
Glitching in Static CMOS
Each gate hasUnit delay
Input A, B, Carrive at sametime.
No glitching indynamic circuits
![Page 18: 41494066 Low Power Vlsi in CMOS](https://reader030.fdocuments.us/reader030/viewer/2022021119/577d33a31a28ab3a6b8b4f94/html5/thumbnails/18.jpg)
8/8/2019 41494066 Low Power Vlsi in CMOS
http://slidepdf.com/reader/full/41494066-low-power-vlsi-in-cmos 18/28
How to Cope With Glitching..?
![Page 19: 41494066 Low Power Vlsi in CMOS](https://reader030.fdocuments.us/reader030/viewer/2022021119/577d33a31a28ab3a6b8b4f94/html5/thumbnails/19.jpg)
8/8/2019 41494066 Low Power Vlsi in CMOS
http://slidepdf.com/reader/full/41494066-low-power-vlsi-in-cmos 19/28
Short Circuit Currents
Short circuit currents are encountered only
in static design.
In static CMOS circuits the flow currentfrom VDD to GND during Switching when
both NMOS and PMOS conducting
Simultaneously.
Such path never exists in a dynamic
circuits.
![Page 20: 41494066 Low Power Vlsi in CMOS](https://reader030.fdocuments.us/reader030/viewer/2022021119/577d33a31a28ab3a6b8b4f94/html5/thumbnails/20.jpg)
8/8/2019 41494066 Low Power Vlsi in CMOS
http://slidepdf.com/reader/full/41494066-low-power-vlsi-in-cmos 20/28
Short Circuit Currents
V out
V in0.5 1 1.5 2 2.5
0 .
5
1
1 . 5
2
2 .
5
NMOS res
PMOS off
NMOS sat
PMOS sat
NMOS off
PMOS res
NMOS sat
PMOS res
NMOS res
PMOS sat
Vin Vout
CL
Vdd
I V D
D
( m
A )
0.15
0.10
0.05
V in (V )5. 04. 03. 02. 01. 00. 0
Vin Vout
CL
Vdd
I V D
D
( m
A )
0.15
0.10
0.05
V in (V )5. 04. 03. 02. 01. 00. 0
Vin Vout
CL
Vdd
I V D
D
( m
A )
0.15
0.10
0.05
V in (V )5. 04. 03. 02. 01. 00. 0
![Page 21: 41494066 Low Power Vlsi in CMOS](https://reader030.fdocuments.us/reader030/viewer/2022021119/577d33a31a28ab3a6b8b4f94/html5/thumbnails/21.jpg)
8/8/2019 41494066 Low Power Vlsi in CMOS
http://slidepdf.com/reader/full/41494066-low-power-vlsi-in-cmos 21/28
Impact of rise/fall time on Short-
Circuit Currents
Large Capacitive Load
The input through the
transient region before the
output start to change
Small capacitive Load
Output fall time is
Substantially smaller than
the input rise time
V in V out
C L
V DD
V in V out
C L
V DD
![Page 22: 41494066 Low Power Vlsi in CMOS](https://reader030.fdocuments.us/reader030/viewer/2022021119/577d33a31a28ab3a6b8b4f94/html5/thumbnails/22.jpg)
8/8/2019 41494066 Low Power Vlsi in CMOS
http://slidepdf.com/reader/full/41494066-low-power-vlsi-in-cmos 22/28
Short-Circuit energy as a function
of slope ratio
Short-Circuit energy dissipation (normalized with
respect to zero i/p rise time energy) for a static
CMOS. The power dissipation due to short circuit
currents is minimized by matching the rise/fall
times of the input and output signals.
Short-Circuit reduced by lower the SupplyVoltage.
![Page 23: 41494066 Low Power Vlsi in CMOS](https://reader030.fdocuments.us/reader030/viewer/2022021119/577d33a31a28ab3a6b8b4f94/html5/thumbnails/23.jpg)
8/8/2019 41494066 Low Power Vlsi in CMOS
http://slidepdf.com/reader/full/41494066-low-power-vlsi-in-cmos 23/28
Leakage
Sub-Threshold current Dominant factor
Vo u t
V d d
S u b - T h r e s h o l d
C u r r e n t
D r a i n J u n c t i o nL e a k a g e
S u b - T h r e s h o l d C u r r e n t D o m i n a n t F a c t o r
![Page 24: 41494066 Low Power Vlsi in CMOS](https://reader030.fdocuments.us/reader030/viewer/2022021119/577d33a31a28ab3a6b8b4f94/html5/thumbnails/24.jpg)
8/8/2019 41494066 Low Power Vlsi in CMOS
http://slidepdf.com/reader/full/41494066-low-power-vlsi-in-cmos 24/28
![Page 25: 41494066 Low Power Vlsi in CMOS](https://reader030.fdocuments.us/reader030/viewer/2022021119/577d33a31a28ab3a6b8b4f94/html5/thumbnails/25.jpg)
8/8/2019 41494066 Low Power Vlsi in CMOS
http://slidepdf.com/reader/full/41494066-low-power-vlsi-in-cmos 25/28
System-Level optimization : Power
Management
In event-driven application, large amounts of power are wasted while the system is in idle-mode.
The power consumption can be reducedsignificantly by using power managementscheme to shunt down idle component.
![Page 26: 41494066 Low Power Vlsi in CMOS](https://reader030.fdocuments.us/reader030/viewer/2022021119/577d33a31a28ab3a6b8b4f94/html5/thumbnails/26.jpg)
8/8/2019 41494066 Low Power Vlsi in CMOS
http://slidepdf.com/reader/full/41494066-low-power-vlsi-in-cmos 26/28
Conclusion
Thus the low power can be achieved bydecreasing Vdd to certain level.
As leakage current cannot be reduced, the short
circuit currents are eliminated by dynamiccircuits.
The power dissipation due to short circuitcurrents is minimized by matching the rise/fall
times of the input and output signals Glitching makes power to dissipate so it is
reduced by cope process
![Page 27: 41494066 Low Power Vlsi in CMOS](https://reader030.fdocuments.us/reader030/viewer/2022021119/577d33a31a28ab3a6b8b4f94/html5/thumbnails/27.jpg)
8/8/2019 41494066 Low Power Vlsi in CMOS
http://slidepdf.com/reader/full/41494066-low-power-vlsi-in-cmos 27/28
References
Digital Integrated Circuits ±JAN M.RABAEY
Encyclopedia of computer science and
technology,1995.
VLSI Design Techniques for Analog and Digital
Circuits ±Randall L.Geiger, Phillip E.Allen.
Basic VLSI Design A.PUCKNELL.
Low-Power CMOS Design ³IEEE journal of solidstate circuit -pages 472-484,Aprill 1992´.
![Page 28: 41494066 Low Power Vlsi in CMOS](https://reader030.fdocuments.us/reader030/viewer/2022021119/577d33a31a28ab3a6b8b4f94/html5/thumbnails/28.jpg)
8/8/2019 41494066 Low Power Vlsi in CMOS
http://slidepdf.com/reader/full/41494066-low-power-vlsi-in-cmos 28/28
THANK
µU¶