411 Performance

7/31/2019 411 Performance

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Circuit Characterization and Performance Estimation 1

CIRCUIT CHARACTERIZATION AND

PERFORMANCE ESTIMATION

Instructor

Dr. smail Enis Ungan


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Resistance Estimation

The resistance of a uniform slab of conducting material is

R = ( /t) ( l/w )

where : resistivity

t: thickness

l : conductor length

w : conductor width

An other expression is

R = Rs (l

/w

)where Rs is the sheet resistance having the units of

/ square ( /! ).

t

w

l


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Resistance of multiple connected slabs is

R = Rs ( 2l/ 2w ) = Rs ( l /w )

t

w

l

l

w


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Resistance of the layer divided into the squares;

w

l

w

l

R = Rs ( l / w )

l

R = 2 x Rs ( l / w )

w

l = 5x w

R = Rs ( l / w ) = 5 Squares xRs


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Typical sheet resistances of the layers in CMOS process;

Metal-1, metal-2 0.07 /!

Polysilicon 20 /!

Diffusion n+ 30 /!

Diffusion p+ 70 /!

nWell 2.5 K /!

Resistance of a non-rectangular shape can be found from a table.

Resistance of contanct and via is dependent on the area and the

contact material. Typical values for 2m x 2m contact are;

Contact to p+ active 35 75 Contact to n+ active 20 50

Contact to polysilicon 20 50

Via to metal-1 0.05 0.08


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Capacitance Estimation

Dynamic response of MOS circuits are dependent on the parasitic

capacitances associated with the MOS device and interconnection

capacitances.

The total load capacitance on the output of a CMOS gate is the

sum of;

Gate capacitances of the other gate inputs

Diffusion capacitances of the drain regions connected to the output.

Routing capacitances of interconnections to the other gates.

During the design, it is essential to know the source of parasitic

loads and their effects on the circuit characteristics.


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Metal Oxide Semiconductor as a Capacitor

MOS capacitor structure is similar to MOSFET without drain

and source diffusion regions.

MOS capacitor capacitance depend on the state of thesemiconductor surface. Depending on the potential difference

between the gate and the bulk, the surface may be in;

accumulation

depletion

inversion

Therefore, capacitance of the MOS capacitor is dependent on

the voltage at the gate.


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Capacitance when accumulation is formed by VG < 0

(for p-type substrate);

p - substrate

gate ( VG < 0 )

tox

VSS

VSS

gate

CO

mobile holes


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Single capacitance is calculated as;

Co = A ( SiO20 ) / toxwhere

A : gate area

SiO2: dielectric constant ( relative permittivity of SiO2)

0 : permittivity of free space


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Capacitance when depletion layer is formed by Vt>> VG> 0;

p - substrate

gate ( VG ~ 0 )

tox

VSSVSS

gate

CO

Cdep

depletion layer d

negatively charged ions

mobile holes


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Two capacitances are calculated as;

Co = A ( SiO20 ) / toxand

Cdep = A ( Si0 ) / d

then

Ceq = Co Cdep / ( Co+ Cdep )

where

d : depletion layer depth

Si: dielectric constant ( relative permittivity of Si)


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Capacitance when inversion layer is formed by VG ~ Vt(for p-type substrate);

p - substrate

gate ( VG ~ Vt )

tox

VSS

gate

CO

depletion layer dinversion layer

mobile electrons (minority carriers)negatively charged ionsmobile holes

VSS

Cdep

shorted


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Source of free carriers at the surface is slow thermal generation

of carriers. Charges on poly are mirrored by charges in

inversion layer. Therefore, thermal generation of carriers will

short out the depletion layer capacitance. Single capacitance is

calculated as;

Co = A ( SiO20 ) / tox If VG changes at a rate faster than 1KHz. Inversion layer

formation can not follow the rate and Cdep appears again as;

Cdep = A ( Si0 ) / dand

Ceq = Co Cdep / ( Co+ Cdep )


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Capacitance variation as a function of VG is;

Normalize

dasC/Co

VG

0 Vt

accumulation depletion inversion

high

frequency

1.0

0.02 - 0.2


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Metal Oxide Semiconductor Device Capacitances

Capacitances in the MOSFET device are;

Cgs, Cgd : Gate to channel capacitances at source and drain regions, resp.

Csb, Cdb : Source and drain-diffusion capacitances to bulk (substrate).

Cgb : Gate to bulk capacitance.

Gate overlap capacitances over source and drain are not shown.

substrate (bulk)

gate

source drain

depletion layer

channel

Cgs

Cgb

Cgd

Csb

Cdb

tox


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Total gate capacitance Cg is;

Cg = Cgb + Cgs + Cgd

Cg behaviour depends on the MOSFET operation regions; Off region;

there is no channel => Cgs = Cgd = 0

there is depletion layer => Cgb = Co Cdep / (Co + Cdep)

Linear region;

Uniform channel formation => Cgs = Cgd = Co / 2, Cgb = 0.

Saturation region;

Drain region is pinched off => Cgd = 0 Thicker channel at source region => Cgs = (2 / 3) Co, Cgb = 0.


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Total gate capacitance Cg is;

OffOff LinearLinear SaturationSaturation

Cgb A / tox 0 0

Cgs 0 A / (2 tox) A 2 / (3 tox)

Cgd 0 A / (2 tox) 0 (finite for short channel)

Cg A //// tox A //// tox A 2 //// (3 tox)

0.9 A / tox(short channel) Therefore, approximate Cg = Co for all operating regions.


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Diffusion-to-substrate junction capacitances

Bottom area junction capacitance

Sidewall area junction capacitances at the periphery

substrate (bulk)

diffusion

CjaCjp'

Cjp'

Cjp'

Cjp'


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Diffusion (source and drain regions)

capacitance; Cd

Cd = Cja x (a b) + Cjp x (2 a + 2 b)

where

Cja : junction capacitance per2

Cjp : periphery capacitance pera : diffusion region width in b : diffusion region length in

a

b

substrate (bulk)

substrate

Junction Perimeter Capacitance, Cjp

poly

poly

Junction Area Capacitance, Cja


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Juntion capacitance under bias is;

Cj = Cj0(1 Vj /b )m

where

m : grading coefficient(0.3 for graded junction, 0.5 for abrupt junction)

b : built-in junction potential (~0.6V)Vj : junction voltage (negative for reverse bias)

Cj0 : zero-bias junction capacitance


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SPICE Modeling of MOS Capacitances

M2001 4 3 5 0 NFET W=4U L=1U AS=15P AD=15P PS=11.5U PD=11.5U...

.MODEL NFET NMOS TOX=200E-8 CGBO=200P CGSO=600P CGDO=600P

+ CJ = 200U CJSW=400P MJ=0.5 MJSW=0.3 PB=0.7...

Calculations; Cox = / TOX

Cg = W L Cox + W CGSO + W CGDO + 2L CGBO

Cdrain = AD CJ (1 + VD / PB )MJ+ PD CJSW (1 + VD / PB )MJSW

Csource = AS CJ (1 + VS / PB )MJ

+ PS CJSW (1 + VS / PB )MJSW


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Routing Capacitances

Single Wire Capacitances

Approximated by using a parallel-plate capacitance model.

Fringing fields at conductor edges occur.

poly

metal-1

substrate

insulator

insulator

insulator


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Multiple Wire Capacitances

Multiple routing layers have capacitances to substrate and also have

capacitances among them (overlapping and side-wall).

Capacitances can be very complex to calculate.

poly

metal-1 metal-1

substrate

insulator

insulator

insulator

poly


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Typical Capacitance values;

Layer to LayerLayer to Layer SeperationSeperation Plate Cap.Plate Cap. Fringe Cap.Fringe Cap.

mm aFaF//22 aFaF//mm

Poly-1 to Subs (tox) 0.040 863

Poly-2 to Subs. (tox) 0.046 750

Poly-1 to Poly-2 0.070 493

Poly-1 to Subs. (fox) 0.600 58 88

Metal-1 to Poly-1/Poly-2 1150 38 88

Metal-1 to Subs. 1500 23 79

Metal-1 to Diff. 900 38 88

Metal-2 to Poly-1 1900 18 87Metal-2 to Subs. 2500 14 81

Metal-2 to Diff. 1900 18 87

Metal-2 to Metal-1 1000 35 100


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Distributed RC Effects

For very long wires with high sheet resistance, RC transmission line effect

is seen. The line is represented by many number of RC sections.

Signal propagation delay between input and output is approximated by;

tdwire = 0.35 R C l2

where R and C are resistance and capacitance per section or unit length of

wire, and lis the number of sections or total unit length of wire.

In order to optimize delay of a long wire, wire is divided in to segments anda buffer is inserted between successive segments.

For a line that is divided into two segments, the total delay is;

tdwire

= 0.7 R C (l / 2)2 + tdbuffer


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Wire Length Design Guide

For sufficiently small wire lengths, RC delays can be ignored. This can be

satisfied when wire delay is much smaller than the typical logic gate delay;

tdwire 0.35 R C l2 l


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Switching Characteristics of Logic Gate

Switching speed of a CMOS gate is limited by the time taken to charge and

discharge the load capacitance, CL, at the gate output.

Analytic delay model:

Fall time analysis;

tf= tf1 + tf2

where tf1 is the period during which output falls down from the level

0.9VDD down to VDD-Vtn. In this period, NMOS is SAT, PMOS is OFF.

And tf2 is the period during which output continues to fall down from the

level VDD-Vtn down to 0.1VDD. In this period, NMOS is LIN, PMOS is OFF.

After the analysis the tfcan be approximated by;tf= k CL / n VDD

where k=3 to 4 for VDD=3V to 5V and Vtn=0.5V to 1V.

S


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Rise time analysis;

tr= tr1 + tr2

where tr1

is the period during which output rises up from the level 0.1VDD to

|Vtp|. In this period, PMOS is SAT, NMOS is OFF.

And tf2 is the period during which output continues to rise up from the level

|Vtp| up to 0.9VDD. In this period, PMOS is LIN, NMOS is OFF.

After the analysis the trcan be approximated by;

tr= k CL / p VDDwhere k=3 to 4 for VDD=3V to 5V and |Vtp|=0.5V to 1V.

For equally sized NMOS and PMOS, tf< trdue to n > p

S i hi Ch i i f L i G


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Delay time is dominated by the output rise and fall times. It is

approximately given by;

tdr= tr/2

tdf= tf/2

Average delay is;

td = (tdr+ tdf)/2

=> td = (tr+ tf)/4

The delay of a gate can be determined by tuning the three parameters of;

(Width of MOSFETs)

VDD

CL

S it hi Ch t i ti f L i G t


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Empirical delay model:

A simulator is used to model the gate. The measured values are back-

substituted into appropriate delay equations.

Gate delay The delay of simple gates may be approximated by the delay of an

equivalent inverter.

In a simple gate circuit, series connected i number of MOSFETs result inan effective of;

1/eff= 1/1 + 1/2 + + 1/i In a simple gate circuit, parallel connected i number of MOSFETs result in

an effective of;

eff= min{1, 2, , i}



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Input waveform slope affects the delay

Input signal is not a step function, it has a finite rise and fall times.

Input capacitance affects the delay

Gate input capacitance is a function of gate input voltage.

MOSFET gate to drain capacitance increases effective input capacitance

(bootstrapping).

Switch-Level RC models This is an RC modeling technique that represents transistors as a resistance

discharging or charging a capacitance.

The models include Simple RC delay model,

RC-tree model



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Simple RC delay model

Delay while output is falling;

tdf= (Rpulldown)(Cout+Cint_pulldown)

where Rpulldown is the total resistance at the pull-down path and Cint_pulldownis the total internal parasitic capacitances at the pull-down path.

Delay while output is rising;

tdr= (Rpullup)(Cout+Cint_pullup)where Rpullup is the total resistance at the pull-up path and Cint_pullup is the

total internal parasitic capacitances at the pull-up path.

Average delay is;td=(tdf+ tdr) / 2



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RC-Tree delay model

Delay while output is falling(rising);

tdf(r) = R1 C1+(R1+R2) C2 + (R1+R2+R3)C3 +

+ (R1+R2+ + Ri)Coutwhere R1 is the effective resistance and C1 is the internal parasitic

capacitance of the MOSFET closest to the VSS(VDD) power rail. And Ri is

the effective resistance and Cout is the loading parasitic capacitance of theMOSFET closest to the output.

Average delay is;

td=(tdf+ tdr) / 2 Effective resistance of the MOSFET is determined by SPICE simulations.



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Macro modeling

Logic gates are simple delay elements. Simulated gate delay characteristics

are approximated as;

td= tinternal + k toutputwhere k is the loading capacitance, toutput is delay per loading capacitance

and tinternal is delay for zero loading capacitance.

Simulator (SPICE) can be used to calibrate the delay equation. Body Effect as a dynamic problem

Place the transistors with the latest arriving signals nearest to the gate

output.

If diffusion is used as wiring then use it for MOSFETs closest to the gate

output.

CMOS Gate Transistor Sizing


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Let a unit sized transistor has length, L, and width, W.

Let the effective resistance of a unit sized transistor is R. So that, a transistor

with length L and width 2W has effective resistance of R/2.

Let Cd and Cg be the drain and gate capacitances of a unit sized transistor. Consider two cascaded inverters; inverter pair. So that, all MOSFET lengths

are L, width of NMOSFETs are W, width of PMOSFETs are 2W. Given

n=2p .

Assume that the capacitance at the first inverter output is the same as the

capacitance at the output of the second inverter. The capacitance is;

C=(Cd+2Cd)+(Cg+2Cg)

Ceq = Cd+Cg

C= 3 Ceq



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The effective resistance of the PMOSFETs is; Rp=(R/2)(n/p)=R

The effective resistance of the NMOSFETs is; Rn=R

Delay of the pair is approximated as;

tdpair=tdf+ tdr

tdpair= Rn (3 Ceq) + Rp (3 Ceq)

tdpair= 6 R Ceq For the width of both NMOSFETs and PMOSFETs of W, the delay is;

tdpair= Rn (2 Ceq) + Rp (2 Ceq)

tdpair= 6 R Ceq Remember that the changes in n and p affect the gate threshold voltage,

Vm.

411 Performance

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