4-to-1 Multiplexer: Module Instantiation Discussion D2.2 Example 5.
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Transcript of 4-to-1 Multiplexer: Module Instantiation Discussion D2.2 Example 5.
4-to-1 Multiplexer:Module Instantiation
Discussion D2.2
Example 5
4-to-1 Multiplexer
• Module Instantiation
• Logic Equation for a 4-to-1 MUX
2 x 1 MUX
y = a*~s + b*s
2 x 1
MUX
a
b
y
s
s y
0 a
1 b
0
1
4-to-1 Multiplexer
z 4 x 1 MUX
s0s1
c0
c1
c2
c3
z s1 s0
0 0 c00 1 c11 0 c21 1 c3
Multiplexers
z
4 x 1 MUX
s0s1
c0
c1
c2
c3
z s1 s0
0 0 c00 1 c11 0 c21 1 c3
0 0
A multiplexer is adigital switch
Multiplexers
z
4 x 1 MUX
s0s1
c0
c1
c2
c3
z s1 s0
0 0 c00 1 c11 0 c21 1 c3
0 1
Multiplexers
z
4 x 1 MUX
s0s1
c0
c1
c2
c3
z s1 s0
0 0 c00 1 c11 0 c21 1 c3
1 0
Multiplexers
z
4 x 1 MUX
s0s1
c0
c1
c2
c3
z s1 s0
0 0 c00 1 c11 0 c21 1 c3
1 1
Creating a 4 x 1 MUX from 2 x 1 MUXs
2 x 1
MUX
v
w
z
s1
s0
2 x 1
MUX
2 x 1
MUX
s0
c0
c1
c2
c3
0
0
0
1
1
1
M1
M2
M3
4 x 1
MUX
c0
c3
z
s1
s1 s0 z
0 0 c0 0 1 c1 1 0 c2 1 1 c3
s0
c1
c2
0
1
2
3
-- Example 5a: 4-to-1 MUX using module instantiationlibrary IEEE;use IEEE.STD_LOGIC_1164.all;entity mux41 is
port( c : in STD_LOGIC_VECTOR(3 downto 0); s : in STD_LOGIC_VECTOR(1 downto 0); z : out STD_LOGIC
);end mux41;architecture mux41 of mux41 is
component mux21aport(
a : in std_logic;b : in std_logic;s : in std_logic;y : out std_logic);
end component;signal v, w: STD_LOGIC;begin
2 x 1
MUX
v
w
z
s1
s0
2 x 1
MUX
2 x 1
MUX
s0
c0
c1
c2
c3
0
0
0
1
1
1
M1
M2
M3
2 x 1
MUX
v
w
z
s1
s0
2 x 1
MUX
2 x 1
MUX
s0
c0
c1
c2
c3
0
0
0
1
1
1
M1
M2
M3
beginM1 : mux21a
port map(a => c(0),b => c(1),s => s(0),y => v
);M2 : mux21a
port map(a => c(2),b => c(3),s => s(0),y => w
);M3 : mux21a
port map(a => v,b => w,s => s(1),y => z
);end mux41;
--Example 4a: --2-to-1 MUX using logic equationslibrary IEEE;use IEEE.STD_LOGIC_1164.all;entity mux21a is
port( a : in STD_LOGIC; b : in STD_LOGIC; s : in STD_LOGIC; y : out STD_LOGIC
);end mux21a;
architecture mux21a of mux21a isbegin
y <= (not s and a) or (s and b);end mux21a;
2 x 1
MUX
v
w
z
s1
s0
2 x 1
MUX
2 x 1
MUX
s0
c0
c1
c2
c3
0
0
0
1
1
1
M1
M2
M3
M1 : mux21aport map(
a => c(0),b => c(1),s => s(0),y => v
);
--Example 4a: --2-to-1 MUX using logic equationslibrary IEEE;use IEEE.STD_LOGIC_1164.all;entity mux21a is
port( a : in STD_LOGIC; b : in STD_LOGIC; s : in STD_LOGIC; y : out STD_LOGIC
);end mux21a;
architecture mux21a of mux21a isbegin
y <= (not s and a) or (s and b);end mux21a;
2 x 1
MUX
v
w
z
s1
s0
2 x 1
MUX
2 x 1
MUX
s0
c0
c1
c2
c3
0
0
0
1
1
1
M1
M2
M3
M2 : mux21aport map(
a => c(2),b => c(3),s => s(0),y => w
);
--Example 4a: --2-to-1 MUX using logic equationslibrary IEEE;use IEEE.STD_LOGIC_1164.all;entity mux21a is
port( a : in STD_LOGIC; b : in STD_LOGIC; s : in STD_LOGIC; y : out STD_LOGIC
);end mux21a;
architecture mux21a of mux21a isbegin
y <= (not s and a) or (s and b);end mux21a;
2 x 1
MUX
v
w
z
s1
s0
2 x 1
MUX
2 x 1
MUX
s0
c0
c1
c2
c3
0
0
0
1
1
1
M1
M2
M3
M3 : mux21aport map(
a => v,b => w,s => s(1),y => z
);
Label1 : mux21aport map(
a => a,b => b,s => s,y => y
);
Aldec Active-HDL Simulation
4-to-1 Multiplexer
• Module Instantiation
• Logic Equation for a 4-to-1 MUX
2 x 1 MUX
y = a*~s + b*s
2 x 1
MUX
a
b
y
s
s y
0 a
1 b
0
1
2 x 1
MUX
v
w
z
s1
s0
2 x 1
MUX
2 x 1
MUX
s0
c0
c1
c2
c3
0
0
0
1
1
1
M1
M2
M3
v = ~s0*c0 + s0*c1 w = ~s0*c2 + s0*c3 z = ~s1*v + s1*w
z = ~s1*(~s0*c0 + s0*c1) + s1*(~s0*c2 + s0*c3)
z = ~s1*~s0*c0 + ~s1*s0*c1 + s1*~s0*c2 + s1*s0*c3
4-to-1 Multiplexer
z 4 x 1 MUX
s0s1
c0
c1
c2
c3
z s1 s0
0 0 c00 1 c11 0 c21 1 c3
z = ~s1*~s0*c0 + ~s1*s0*c1 + s1*~s0*c2 + s1*s0*c3
-- Example 5b: 4-to-1 MUX using logic equationlibrary IEEE;use IEEE.STD_LOGIC_1164.all;entity mux41b is
port( c : in STD_LOGIC_VECTOR(3 downto 0); s : in STD_LOGIC_VECTOR(1 downto 0); z : out STD_LOGIC
);end mux41b;architecture mux41b of mux41b isbegin
z <= (not s(1) and not s(0) and c(0))or (not s(1) and s(0) and c(1))or (s(1) and not s(0) and c(2))or (s(1) and s(0) and c(3));
end mux41b;
Aldec Active-HDL Simulation
