High-Q 3D Embedded Inductors using TSV for RFMEMS Tunable Bandpass Filters (4.65-6.8 GHz)

Wolfgang A. Vitale, Montserrat Fernandez-Bolanos, Adrian M. IonescuNanoelectronic Device Laboratory (NanoLab)

Ecole Polytechnique Federale de Lausanne (EPFL)

Lausanne, CH-1015, Switzerland

Abstract—This paper presents the optimization design of 3Dintegrated inductors exploiting through silicon vias (TSV) tech-nology to improve the quality (Q) factor in the 2-20 GHz range.The embedded inductor allows the heterogeneous integrationwith CMOS and MEMS components in a size-compact and low-cost manufacturing process. Results limited to our manufacturingpossibilities (5.5x15 μ m-area tungsten TSVs, high resistivity (HR)silicon substrate) show Q-factor values as high as 35 at 8 GHz for4.8 nH inductance, and design methods to improve them. Theseinductors are attractive to be used with MEMS capacitors forreconfigurable RFICs, as proposed for a tunable passband filterin the range 4.65 - 6.8 GHz. The filter shows 15% continuouslinear center frequency tuning and over 45% in a digital fashion.The filter is also continuously tunable in bandwidth (up to 40%)while keeping constant the center frequency.

I. INTRODUCTION

Growth of the wireless communication market in the last

years and the need for miniaturization have rapidly increased

the demand for radio-frequency integrated circuits (RFICs)

such as voltage controlled oscillators, low noise amplifier and

tunable filters. Integrated on-chip inductors are key compo-

nents for achieving high RFICs performances. However, in-

ductors with standard planar technology suffer for low quality

factor (Q) due to the substrate and metal losses, making the

devices unreliable for the market.

Possible approaches to deal with this problem consist in us-

ing the impractical off-chip micro-inductors [1] or minimizing

the substrate losses using non-compatible CMOS substrates as

silicon-on-sapphire [2]. Other solutions have been proposed

to improve the performances of on-chip inductors: suspended

inductors [3], [4], [5], layout optimization for spiral inductors

[6], parallel-stacked spiral inductors [7] and vertical solenoid

inductors [8]. Table I compares them in terms of inductance,

area, Q-factor and frequency range.

This paper presents a way to improve the Q-factor of CMOS

compatible on-chip inductors working in a wide range of RF

frequencies (2-20 GHz) through the design, simulation and

analysis of coil embedded inductors (Fig. 1) by means of

Tungsten (W) filled TSV technology in high resistivity (HR)

silicon substrate (Fig. 2).

Even with the design constraints set by the selected tech-

nology, the basic coil structure results on par with the state-

of-the-art. Versatility of the design is highlighted by the broad

range of frequencies which may be covered without significant

detrimental effects on the Q-factor or the compactness. The

Fig. 1. 3D schematic view of the 9 turns, 2 vias series integrated inductorwith a zoom in the TSV coil concept.

TABLE ICOMPARISON OF CMOS-COMPATIBLE ON-CHIP INDUCTORS

Reference Inductance Inductance per Q peak Q > 5(nH) area (nH/mm2) (GHz)

This work1 4.85 75 34.76 0-16.45

This work2 1.69 76.6 29.2 0-40

[3] 2.96 12.33 45 0-10

[4] 4 9.47 88 0-12

[5] 2.6 10.83 51 0-11

[6] 2.2 33.85 24 0-14

[7] 5 102.12 7.06 0.5-3.5

[8] 4.8 411.5 11 4-15

1 number of turns: 16; width: 188μm; spacing: 2μm.2 number of turns: 9; width: 108μm; spacing: 2μm.

design and simulation of a tunable bandpass filter in the range

4.65− 6.8GHz suggest very promising results.

II. INTEGRATED INDUCTOR DESIGN

Exploiting TSV technology [9] allows realizing a coil

structure for the integrated inductor (Fig. 1) in a only 4-

mask process. The devices analyzed in this paper are on going

fabrication, so we limited our design parameters to values

compatible to the selected technology.

The proposed structure provides two main advantages:

drastically decrease the print area of the inductor (as well

as its cost) and simplifying the design process, since the

mutual inductance between each conductor and its neighbours

is constant and easily calculated as in [10].

Being the coil structure directly integrated in the substrate,

a low-loss material is of foremost importance in order to

978-2-87487-027-9 © 2012 EuMA 29 Oct -1 Nov 2012, Amsterdam, The Netherlands

Proceedings of the 42nd European Microwave Conference

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(a)

Rind

Csub Csub

Lind

Rsub Rsub

(b)

Fig. 2. (a) Focused ion beam (FIB) analysis of a 3-D integrated test structure,showing a cross section of the CVD-W filled through silicon vias (TSV)previously fabricated in standard silicon wafer and (b) equivalent circuit usedfor extraction of effective inductance. Source [9].

minimize losses at high frequency. At the same time a CMOS

compatible substrate is desired, therefore surface passivated

HR silicon [11] is the most appropriate solution.

Most important limitations include the resistivity of the sub-

strate (5000Ω · cm), the size of the TSVs, whose technological

process has been optimized for an area of 5.5μm x 15μm,

and the choice of tungsten for TSV material. These parameters

have great influence on the parasitic resistance of the inductor,

and by consequence on its Q-factor.

The length of the TSVs is fixed by the thickness of the

substrate, i.e. 50μm. In Fig. 1 it is shown a 3D view of

a device representing the proposed design: a series inductor

integrated in a coplanar waveguide. In this case an array of

two vias is used for each connection between conductor strips.

The vias used for consecutive connections are placed in a

way such that the direction of the current in a strip is parallel

to the neighbours, in order to maximize the mutual inductance

[10].

III. SIMULATION AND ANALYSIS

Full-wave finite element method (FEM) electromagnetic

simulations of the integrated inductors have been performed

using Ansoft HFSS, in order to obtain the equivalent in-

ductance and the Q-factor respectively from the S- and Y-

parameters.

The equivalent inductance has been extracted fitting the S-

parameters obtained from FEM simulation of the device to

the T-network shown in Fig. 2 (b), including the parasitic

components due to the substrate and the finite conductivity

of the inductor metals.

The Q-factor is obtained from the Y-matrix as follows:

Q = −Re(Y11)

Im(Y11)(1)

A. Effects of Coil Length

Increasing the number of turns is the most straightforward

way to increase the inductance, as shown in Fig. 3 (a). The

frequency in which the Q-factor is peaked is also depicted.

The value of inductance achievable in this way is limited

by the fact that the proportionality factor decreases for higher

lengths. Moreover, even if the Q-factor varies only slightly in

terms of maximum value (with an average of 31.54 ± 2.96keeping constant W = 140μm and S = 2μm), the frequency

in which this peak is reached decreases, limiting the range of

frequencies in which the inductor has acceptable quality factor

according to the application.

B. Effects of Coil Width

Increasing the coil width is another way to increase the

inductance. In Fig. 3 (b) a linear dependence between the

width of the coil and the inductance is observed in the

entire studied range (60 − 220μm) while keeping constant

the number of turns (N = 9) and the spacing (S = 2μm).

Furthermore, it is possible to notice that, similarly to the

effect of coil length, the Q-factor peak is kept almost constant

across different devices (average of 30.28 ± 2.4), but the

detrimental effect in terms of frequency range is aggravated.

For better insights, in Fig. 3 (c) it is shown a comparison

of the effect of coil length and width on the Q-factor. For fair

comparison, the two devices have similar value of inductance

and all other design parameters are unchanged.

The higher peak of the Q-factor (34.76 for the longer

inductor, 28 for the wider) suggests that up to a certain extent

of inductance values it is better increasing the number of turns

than increasing the width. Nevertheless, if higher inductance

(a) (b) (c)

Fig. 3. Effect of (a) coil length and (b) coil width, compared in (c), where the longer device (black line) has an effective inductance of 4.85 nH, while forthe wider one (blue line) the inductance value is 4.19 nH.

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(a) (b) (c)

Fig. 4. Effect of (a) TSV arrays (N range 6-12), (b) metal plate layout optimization (N = 9, W = 80μm, S = 2μm), (c) vias width (5-20μm) on Q-factor.

values are needed and there are layout or technological con-

straints on the density of TSVs, increasing the width is a viable

solution.

C. Design Optimization

In the structures discussed previously, the connection be-

tween turns is made with a single TSV. Arrays of TSVs allow

to improve the Q-factor by reducing the parasitic resistance,

as shown in Fig. 4 (a). Being also the effective inductance

reduced, a tradeoff must be defined for optimization.

Fig. 4 (b) shows the surface current distribution in the

inductor and the improvement in Q removing the edges in

which the current is minimum.

Another way to decrease the parasitic resistance consists in

increasing the width of the vias, as shown in Fig. 4 (c).

The mutual inductance between conductors with parallel

current direction depends on their distance: increasing the

spacing between conductor strips increases also the distance

between TSVs on the same side of the coil, decreasing the total

effective inductance. This effect is shown in Fig. 5, keeping

constant W = 140μm, N = 9. As expected, the peak Q-

factor frequency increases with the spacing, providing another

degree of freedom in the optimization of the device.

Fig. 5. Effect of spacing on inductance and frequency corresponding tomaximum Q-factor (W = 140μm, N = 9).

IV. TUNABLE FILTER DESIGN

In order to show the effectiveness of the small size and

high Q-factor of the previously presented inductors, a tunable

bandpass filter including both frequency and bandwidth tuning

has been designed exploiting one of the devices analyzed in

this work (N = 9, W = 220μm, S = 2μm, 2-TSV array).

Fig. 6. Schematic and layout of the tunable bandpass filter.

Fig. 7. CV-measurements of a previous fabricated RF MEMS capacitiveswitch showing the stable working region before pull-in (Cr < 1.5) and theun-zipping effect region after pull-in, in the downward direction of the curve(with an achieved Cr of 2.5).

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Fig. 6 shows the schematic of the proposed bandpass

filter and its implementation using tunable MEMS capacitors

(previously fabricated and characterized in [12]) and the

3D-embedded inductor. The parallel capacitors Cp and the

embedded inductor Lind provide a lowpass filter whose cut-

off frequency is controlled by tuning the MEMS capacitances.

The series capacitors Cs block low-frequency components,

making the whole circuit behave as a bandpass filter, tuned in

center frequency by varying Cp and in bandwidth by changing

Cs. The whole filter occupies an area of only 2.5 x 1.5mm2

including the biasing for control of MEMS capacitors.

Parallel MEMS capacitors exploit the possibility to be tuned

linearly in two different tuning regions, as shown in Fig. 7.

First, the traditional limited capacitance ratio Cr of MEMS

devices in the up state region (Cr = 1.4) and second, the

zipping effect operation of the device in the down state region

(Cr = 2.5 [13]).

Fig. 8 (a) depicts the center frequency tuning of the filter.

Simulations show two continuous linear tuning ranges from

4.65 − 5.35GHz (15% tuning) and 6.15 − 6.8GHz (10%)

with a relative constant bandwidth of 445MHz±85MHz and

0.975GHz ± 145MHz respectively. A total center frequency

tuning of 45% is achievable between the two frequency tuning

regions. In addition, the designed filter is able to tune its

bandwidth for a relative constant center frequency, as shown in

Fig. 8 (b). For instance at 6.65GHz±0.15GHz the bandwidth

was tuned from 1.11GHz to 1.56GHz which corresponds to

a 40% continuous linear tuning (only by varying the series

capacitors).

In addition, for the entire range the insertion loss (IL) was in

average 1.43 dB± 0.24 dB. Similarly, at 5.52GHz± 0.1GHzthe bandwidth varies from 560MHz to 740MHz (32%) and

IL was 2.7 dB ± 0.34 dB. These results are promising for

upcoming fabrication in comparison with the state-of-the-art

in the same frequency range.

V. CONCLUSION

The paper reported on 3D coil-shape high-Q inductors

embedded on a HR-Si substrate by means of W TSV.

Inductors values from 1.3 to 5 nH are straightforward des-

ignable optimizing the high Q-factor (over 30) and compact

size. Devices are at present on fabrication following a mature

TSV 4-mask technology.

A both center frequency and bandwidth tunable bandpass

filter has been finally proposed in combination with tunable

MEMS capacitors and very promising results in terms of

tunable frequency range (4.65-6.8GHz) with a continuous

tuning of 15% and a bandwidth tuning of over 40% have

been shown. This suggest that the presented high-Q integrated

inductors might be an attractive solution for reconfigurable

RFICs.

ACKNOWLEDGMENT

This work was partially supported by the Thales Company,

France and the FP7 Integrated project e-BRAINS ICT-257488.

Fig. 8. Tuning (a) center frequency through variation of Cp and (b)bandwidth through variation of Cs.

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