3D NAND ScalingRandy Koval

Outline

• Scale of Flash-Based Storage

• Scaling Evolution of Flash Technology

• 3D NAND State-of-the-Art

• Scaling Opportunities/Challenges

• Summary

Expanding Digital Universe

>10 ZB

Digital universe & flash scale at ≥ Moore’s law pace

~10 EB

>100 EB

>5 EB/day

~1 TB

Impact & Requirements of Scale

• Scale enables the data revolution (Scale of generated data, stored data/storage dens, data

processing throughput)

• AI case study – DL techniques improve w/

larger data sets, larger models, deeper networks,

more computational capability, …

• Scale fuels a virtuous cycle accelerated by

AI technologies (transformative effects)

• The most successful scalable technologies

tend to be elegantly simple

3 Decades of FG Flash Scaling

1.5mm

1.0mm

0.8mm

0.6mm

0.4mm

0.25mm

0.18mm

0.13mm

90nm

65nm

50nm

34 nm

25 nm

20 nm

32T

45nm

64T

NOR 2D NAND 3D NAND

Flash Technology Evolution

• Decade long incubation & scaling cycles

• FG technology development continuity

(scaling, rel mechanisms, error management, etc.)

1980 1990 2000 2010 2020

~10 F2 ~4 F2 <1 F2

2D NAND 3D NAND

NOR

NOR

2D NAND3D NAND

2D NAND Scaling Trend

2D NAND scaled for ~10 years then slowed down (~1 Gb/mm2)

1E-4

1E-3

1E-2

1E-1

1E+0

'00 '05 '10 '15 '20

Cell S

ize [

um

2]

Year

25nm

20nm

70nm

2D NAND Scaling Limiters

• Economic -Lithography Scaling (Cost/complexity)

• Physics - Pitch/Area scaling

(Interference, E-field, number fluctuation)

0.0

0.5

1.0

1.5

2.0

5 15 25 35

Vt

dis

trib

uti

on

w

idth

[a.u

.]

Cell feature size [nm]

# C

ell

s

Vt

3D NAND Advantage

• 3D NAND decouples physical/effective cell size:– Eliminates lithography constraint ($)

– Eliminates small pitch

– Eliminates small area effects (few electrons)

• Larger cell size & cell spacing

– Compact Vt distributions

Vt

Cells ~1X nm 2D NAND

3D NAND

3D NAND Architecture

• Vertical (GAA )offers best performance/density

• FG cell offers excellent window, cell isolation, manuf. simplicity

String Orientation

(Vertical, Horizontal)

Storage Node

(Discrete, Cont)

Arr

ay

Rep

lacem

en

t

Gate

Arr

ay

Architecture

(CuA, RG)

3D FG NAND Cell Formation

(a) Tier

deposition

(b) Cell hole etch (c) Recess (d) IPD

(e) FG deposition (f) FG isolation (g) Tunnel-oxide (g) Channel

deposition

3D FG NAND Technology

CMOS Circuits

Contact/Bitline

Wordlines (32 Active)

SGD

SGS

Metal Layer

Source

• NAND String is formed fully above Si.

• Preserves silicon area under for CMOS circuitry

– 2 Metal Layers below array for CMOS connections

Cell Characteristics

• Cell Current

• Program/Erase

• Interference

• Vt distributions

• Data Retention

Cell Current

• 3D NAND string on-current matches 2D NAND

1E-12

1E-10

1E-08

1E-06

0 1 2 3 4 5

Curr

ent

[A]

WL Voltage [V]

Vds = 0.5V

0.0

0.4

0.8

1.2

0 1 2 3 4 5

Curr

ent

[N

orm

]

WL Voltage [V]

3D NAND

20nm 2D NAND

Program/Erase Characteristics

>10V Cell Program/Erase Vt Window

-8

-6

-4

-2

0

2

4

6

0 2 4 6 8

Cell V

t [V

]

Program/Erase Voltage Delta [V]

Program

Erase >10V P/E

Window

Erase Operation

Erase bias applied to the Source

Body biased up by the SGS GIDL current

1E-14

1E-12

1E-10

1E-08

-6 -4 -2 0GID

L C

urr

en

t [A

]

Vgs [V]Vsrc

Vsg

VWL

Vs =0V

Vbl = -2V

SG

N+ Source

Cell to Cell Interference

3D NAND control gate

shielding reduces

interference by ~80%0.0

0.2

0.4

0.6

0.8

1.0

1 2

Net Interference (A.U.)

2D 20nm 3D

2D NAND 3D NAND

MLC Vt Distribution Width

• 3D NAND enables compact Vt distribution

• ~0.5X Vt distribution width at ~0.5X cell Aeff

0.0

0.5

1.0

1.5

2.0

5 15 25 35

Vt

dis

trib

uti

on

w

idth

[a.u

.]

Eff Cell feature size [nm]

2D 20nm3D

Vt Distribution [A.U.]

# o

f C

ells

0.5X3D NAND

# C

ell

s

Vt

Reliability

2D NAND

3D NANDS

igm

a

∆VT [a.u.]

• 3D NAND has improved data retention

• Preserves Vt distribution at low error rate

2D 3D Scaling Benefit

• 3D NAND addresses the scaling limiters

# C

ells

# C

ells

Vt

# C

ells

20nm 2D NAND

1X nm 2D NAND

(10s of e-)

3D NAND

(100s of e-)

3D NAND Summary

• Most dense 32T/64T 3D NAND,

excellent unit-cell characteristics

– On current matched to scaled 2D NAND

– Large (>10V) P/E window

– Physical cell size & reliability mechanisms

matched to ≥50nm 2D NAND equivalent

–4.3 Gb/mm2 (64T)

• 1-time CoT, amortized over several nodes

• Enhanced unit cell characteristics

accommodate b/c & vertical scaling

b/c Scaling

• Large cell size, perf, reliability accommodate b/c scaling.

(Compact Vt distributions, excellent reliability on 3D)

• 3D NAND leverages prior technology advances

(Cell enhancements, ECC capability)

1 b/c

2 b/c

3 b/c

4 b/c

Transition Reliability

margin

Error

mgmt

NOR 1->2 b/c n/a

2D

NAND2->3 b/c

3D

NAND 3->4 b/c

• HM material upgrade required to extend roadmap

(Compatible uniform low defect density channel etch)

Physical Scaling

Electrical Scaling

Ce

ll C

urr

en

t

Channel Hole AR

New channel material?

Sense

margin

Gen1Gen2

Gen3

• Material optimization sustains initial scaling

(Preserve material quality, statistics, sense)

• Future scaling requires improved materials

(>5X mobility, matched NT, conformal at 50:1 AR)

Cell Area Scaling

• 64T 3D NAND Aeff ~ 4e-4 um2

• New materials (films) influence future scaling rate

1.E-04

1.E-03

1.E-02

1.E-01

1.E+00

1.E+01

1995 2000 2005 2010 2015 2020

Ce

ll S

ize

[u

m2]

’95 ’00 ’05 ’10 ’15 ‘20

NOR

2D NAND

3D NAND

2.3 Gb/mm2

4.3 Gb/mm2

Summary

• 3D NAND extends Moore’s law scaling

• 3D NAND unit cell has superior characteristics to

that of 2D NAND, enables possibility of QLC

• b/c scaling & vertical scaling sustain Moore’s law

scaling well into the next decade

• 2 key material upgrades (etch HM, channel)

potentially required to extend roadmap beyond

~10 Gb/mm2

Acknowledgment

• Members of the Intel and Micron

NAND team that performed the work

presented here

• Authors of the various work reported

in the literature that has been

referred to here

A. Goda et al., IEDM 2015

K. Parat and C. Dennison, IEDM 2015