3D Integration Technologies Enabling System in … Summit_Handout_WOLF... · 3D Integration...

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3D Integration TechnologiesEnabling

System in Package Solutions

M.Juergen WolfFraunhofer IZM

All Silicon System Integration Dresden - ASSID

Berlin, Dresden

Germany

© Fraunhofer IZM

M.J. Wolf

European 3D TSV Summit, Grenoble, January 22-23, 2013

Heterogeneous Integration: Driving Forces

Integration densitySignal propagation timePartitioningPower density

Multi Device IntegrationSensor, Transceiver, MPU, GPU, Memory

Mobile CommunicationID cardsAPPLICATION

Application Fields

digital SiPdigital analog SiPmemorywirelessimage sensorMEMS / sensors / Optopower…

Requires …

own technology pathspecific solutionstimelineinfrastructure

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M.J. Wolf


3D Wafer Level System Integration @ Fraunhofer

3D TPM(ASIC+TX+MEMS)

Image Sensor (Sensor+IP+SP)

TSV Interposer (MPU+MEM)

TCI (Sensor+ASIC+TX)

WL Camera

Image Sensor MEMS /ASIC Packaging

ASIC+M

MEMS Packaging

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M.J. Wolf


3D Approaches

Wafer Level (BE)Circuit Level (FE)

Die2Wafer Stacking(w/o TSV)

W2W Stacking (w TSV)

- TSV Interposer -

Thin Chip Integration (TCI)

Interface to

Packag

e /Bo

ard /S

ub

strate

Embedded Wafer Level Packaging(eWLB)

Stacked device layer TSV & Stack formation

--- IC devices w TSV ---

Via FirstVia Middle

Via LastBackside TSV

TMV, TEV, TPV, TGV, TxV

- Glas Interposer -

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M.J. Wolf


TSV Formation

Technology:

• TSV Etching: RIE (Bosch process)

• TSV Isolation: SiO2 (CVD, therm.)

• Barrier/Seed: PVD, CVD, Wet

• TSV Filling: Cu-ECD, W-CVD, doped-Si

Challenges:• Process integration (first, middle, last, BS, …)

• HASR TSV, DTSV (etch, uniformity, fill, yield)

• Design (rules, CAD tools)

• Metrology, test

• Reliability (uniformity, yield)

• Cost (throughput, ...)

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M.J. Wolf


TSV Geometry - Landscape

5 μm

Diameter

10 μm

20 μm

40 μm

250 μm

160 μm

80 μm

10 μm 20 μm 50 μm 100 μm 200 μm 400 μm 700 μm

InterposerIntegrated

Circuits (BEOL)

Integrated Circuits(FEOL)

special apps

Depth

Image Sensorstapered (BS) TSV

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M.J. Wolf


TSV- Formation

TSV-Etch: Baseline process for 20µm/100µm (AR5), 10µm/120µm (AR12) and 5µm/60µm+ (AR12+).

TSV-Isolation: Executed as thermal oxide or by deposition of SA-CVD/ PE-CVD-TEOS liner

Adhesion-/ Barrier-/ Seed Layer: Deposition of metal stack by using high ionized PVD and/ or MOCVD, AR12

TSV-Fill: Cu - Electrolyte with „Bottom-up“ fill characteristic demonstrated TSV-filling up to AR12.

TSV-CMP: Removal of Cu-overburden with stop in oxide liner.

Developoment of improved/ alternate technologies for TSV formation

DRIE: TSV 10/120 and 5/60

TSV 20/100 post CMP

TSV 7,5/100 post ECD

Technology GEN2 TSV and RDL CMP

TSV 4/50 post ECD

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M.J. Wolf


Barrier Seed Deposition High Impuls Sputtering

J. Weichart (OE BZ), K.Viehweger

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M.J. Wolf


TSV Filling ECD - Chemistry

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M.J. Wolf


TSV Filling Copper Deposits Property

Copper grain size structure TSV I: disturbed copper grain structure at top of TSV

TSV III: non-disturbed copper grains throughout the TSV

Additive incorporation controls copper grain size

TSV I TSV III

FIB of 5x25 μm TSV after ECD copper plating

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M.J. Wolf


TSV Filling Copper Deposits Property

TSV III: outstanding low additive incorporation and perfectly well suited for Cu Cu Thermocompression bonding at low T (< 200°C)

TOF-SIMS Impurity analysis of deposited copper

TSV I highTSV I lowTSV IITSV III

TSV III @ 2 mAcm-2: 14 ppm C; 0,5 ppm Cl-; 22ppm O; 0,51 ppm S

FIB after 1h @ 250°C annealing

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M.J. Wolf


TSV Filling ECD

55x120 μm 10x120 20x110 10x100 6x90 2x40 5x25μm15x100 5x50

New Generation applicable for a broad dimensional range

Examples of ECD copper filled TSV III

18 min!60 min!

A.Uhlig

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M.J. Wolf


TSV Filling ECD

A.Uhlig

Process robustness against TSV dimension & pitch

TSV III works for HDI/LDI layout & different A/R

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M.J. Wolf


TSV Via Last Integration – Process Scenario

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M.J. Wolf


Backside TSV for ATLAS Readout-Chip (Pixel Detector)

ATLAS Single Chip Module:

TSVs in ATLAS FE-I3 Readout-Chip

Tapered TSV from Backside (readout) with Cu liner

T. Fritzsch

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M.J. Wolf


Chip Interconnection (D2D, D2W, D2IP, IP2P)

Technology:

• Solder, Cu-Pil, IMC, Cu-Cu, Nano-Interconnects

• Bonding (reflow, TC, diffusion)

• Stacking (D2W, D2W, W2W)

• Interconnect structure (Cu, ...)

• (Self assembly)

Challenges:• Low temperature bonding

• Topography, alignment

• Bonding on carrier vs. wafer

• Test, repair, reliability

• Productivity, throughput, yield

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M.J. Wolf


FC Reflow Soldering: SnAg, SnAgCu (SAC)

Pick & Place & Collective Reflow

• short cycle time

• sufficient solder thickness required

thinned read-out IC on pixel sensor (ATLAS)

flip chip 50 μm pitch SnAg bumps on Cu pads

SnAg bumps for FC on interposerCu pillar bumps for board assembly

H. Oppermann

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M.J. Wolf


Assembly and Packaging: Flip Chip Bonding/ Stacking

Interconnects TC2 daisy chain

Die size; 10x10mm²: 35.904Die size: 20x20mm²: 143.616

Die to Wafer 3D stack constructions using D2W and W2W bonding D2W flip chip bonding (300mm) of 10x10mm chips with

35.904 I/Os (55µm pitch)

Die to Substrate• Void free underfill processes of large die sizes• (≤ 20x20mm2) with underfill gaps of 10 to 50µm using

capillary underfill (CAF) and no flow underfill (NUF).

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M.J. Wolf


New chemistry: Ag/Au alloy

deposition

Process flow similar to

conventional Au Bumping

Skeleton formation due to simple

de-alloying by wet etching of Ag

Average pore sizes adjustable from

20 nm up to 500 nm

TC-Bonding with reduced bonding

parameters

typ. 10 MPa / 200°C / 300s

Sponge-like Au is fully

compressible and able to

compensate topography issues on

chip and substrate

500 nm

500 nm

Chip

Substrat

10µm ... 50µm bump size

Nano-Porous Gold Bumps - Nano Sponge

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M.J. Wolf


Process Readiness for 3D Integration using TSV

Status Q4/12

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M.J. Wolf


TSV - Supply Chain

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M.J. Wolf


Silicon Interposer

Basic Elements of Silicon Interposer• Core/ substrate Si-Wafer• Trough Silicon Via TSV• Wiring/ Redistribution RDL• Contacts/ Bond Interface Bumps • Process flows according to “Via First” Technology

wide IO interface between devices e.g logic, memoryhigh re-routing capabilityFan-out interface from device to package/boardtestabilityintegrated functions (e.g. IPD, optical) thermal management

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M.J. Wolf


Technology and Process Demonstrators “TCx”

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M.J. Wolf


TSV Interposer

Parameter Standard Improved Advanced

TSV diameter/ depth 20µm/100µm 10µm/120µm 5µm/100µm

Line/Space: Polymer (Oxide) 10µm/15µm 8µm/10µm (5µm/5µm) 3µm/3µm (<1 µm)

ILD via: Polymer (Oxide) 30µm 20µm (10µm) 10µm (<5µm)

µ-bump: size/pitch/height 25µm/45µm/30µm 25µm/45µm/30µm 20µm/40µm/30µm

Material

ILD-Layer, polymer/ oxide 5µm 5µm/ 1.5µm 5µm/ 1.0µm

TSV Isolation PE-CVD oxide (1.0µm) SA-CVD oxide (0.8µm) Thermal Oxide (0.5µm)

TSV-Barrier PVD: Ti-TiN PVD: Ti-TiN /CVD: TaN-Ta CVD: TaN-Ta/ Co-CVD

TSV-Seed PVD: Cu PVD: Cu PVD: Cu/ ---

TSV-Fill ECD-Cu ECD-Cu ECD-Cu

Interconnects /Studs Cu, Cu-SnAg, Cu-Ni-Au Cu, Cu-SnAg, Cu-Ni-Au Cu, Cu-SnAg, Cu-Ni-Au

Parameter

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M.J. Wolf


TSV-Interposer Applications

Silicon Interposer Apps#1:



• high TSV count (>10000/cm²)• high density TSV (5-10μm),• small pitch (50μm -20μm)• high density Line/Space (M1: 0,5 μm L/S)• multilayer front/back side (#4),• anorganic dielectric• electrical & optical Interconnect

• med. TSV count• TSV (10-20μm), pitch (>100 μm)• ASR (5-15)• multilayer front/back side• Device integration (MEMS, IPD,…)• Cu pillar interface to board/package

• low TSV count• TSV diam. >50 μm, larger pitch (>150 μm)• special shape (coax, tapered)• 1-2 layer RDL, RF transmission lines• CSP Outline, μBGA

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M.J. Wolf


Interposer Generations - Performance

G1 Interposer TSV, multilayer redistribution (RDL) top/bottem side, w/o 2nd level interconnect (solder ball, Cu pillar)

G2 Interposer + integrated passive devices

G3 Interposer + embedded active devices and /or MEMS

G3+ Interposer + integrated optical & electrical interconnects

G4 Interposer + active cooling (e.g. fluid channels)

Interposer will convert from single carrier substrateTo an integrated active multifunctional packaged device

(IIPWLP –integrated interposer wafer level package)

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M.J. Wolf


Passive Interposer for Hermetic MEMS Packaging

passive Silicon IP

MEMS

Cap

Interposer

MEMSComponent

Seal Ring

Final Package Dimensions after DicingL x W x T 2.2 mm x 1.4 mm x 0.5 mm

8305 Componentsper 200 mm Wafer!

Cap

200 μm

K. Zoschke

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M.J. Wolf


Passive Interposer for Hermetic MEMS Packaging

K. Zoschke

Support Wafer

passive Silicon IP

MEMS

Getter Deposition

MEMS Component Assembly byAu-Au Thermosonic Bonding

Support Wafer Fabrication of Au Pads and Au+Sn frames at Interposer Backside by Semi-additive Structuring

Support Wafer

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M.J. Wolf


Glas Interposer

References: Nobu Imanu, Mark Takahashi

Via Drilling by E-Discharging (fast serial via drilling)

Option for specific applicationsMid size via geometry,med # of vias, panal size processing

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M.J. Wolf


Cost – some remarks

TSV FormationDimension 5/50μm – 10/100 μm -------- scaling down Barrier / seed deposition ----- CVD, HIPIMPS Metal filling -------- ECD: bath stability, high speed filling

Thin Wafer Handling / BS Processingtemporary wafer bonding /de-bonding --- process time,

temperature, cleaning

Assembly / Stackingsmall interconnect structures

(fine pitch, bump height, uniformity)handling of super thinned devices for assemblyintegrated /no underfill, collective bonding

TSV Formation / Thin Wafer Handling / Assembly

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M.J. Wolf


Summary

Consider the changes from „Traditional Packaging“to „3D Heterogeneous System Integration“

TSV Process ReadinessThe technology is ready for ramp-up high volume Manufacturing!

TSV Formation results in supply chainmost important challenge in the infrastructure between Foundries / OSAT

3D Technology using TSV /TxV / IP is a Key Technology for Packaging and System Integration

Each Application requires an own application specific technology path

Interposer becomes a key element for 3D Heterogeneous Integration

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M.J. Wolf


Fraunhofer Competences

Prototyping and low volume manufacturingwith qualified prozesses

Pilot production

Service Provider

Material & Equipment Evaluationand Qualification

Process demonstration, qualification & transfer

Fraunhofer provides an generic 3D Integration Approach

Design / Technology / Analytic / Reliability

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M.J. Wolf


Development of leading edge technologies forWLP & 3D-WL System Integration

Customized solutions for product integrationand process transfer

Supporting equipment and material evaluation for supplier

Prototyping and manufacturing using qualified processes on a latest state of the art process line (200/300mm) for WL packaging, and 3D WL system integration.

Fraunhofer IZM vision is to integrate heterogeneous chip functionalities in one package by using enhanced 3D integration, assembly and interconnect technologies

WLP & 3D Integration @ Fraunhofer IZM

© Fraunhofer IZM

M.J. Wolf


THANK YOU FOR YOUR ATTENTION

Acknowledgement:Fraunhofer IZM, IZFP, A&P ITRSPartners in industrial cooperation programInfineon, NXP, GF, OE, ATOTECH,EVG, SUSS, AMATSPTS, ISYS, …

Contact: M. Juergen [email protected]

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3D Integration Technologies Enabling System in … Summit_Handout_WOLF... · 3D Integration...

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