I- 1Center for Power Electronic SystemsOct. 5th 2007 IBM Symposium

3D integrated POL converter

Presented by: Arthur Ball

I- 2Center for Power Electronic SystemsOct. 5th 2007 IBM Symposium

Motivation for this workToday’s typical approach for >15A output Point of Load converters:

Use PCB material for the entire circuit layout.

Need heat sink or fan.

In some cases, the entire backside of board is a heat sink.

Thermally limited output.

In many cases, the devices could do more but the circuit has to be derated.

I- 3Center for Power Electronic SystemsOct. 5th 2007 IBM Symposium

Limitations of current approach

Simplified schematic:

Issues with current approach:1. Heat sink is often necessary – hurts power density and profile

2. Layout must conform to heat sink – may not be most efficient

3. PCB material contributes very little to circuit cooling

Heat sink

DevicesThermal paste

PCB (e.g. FR4)

I- 4Center for Power Electronic SystemsOct. 5th 2007 IBM Symposium

New approach

DBC Heat spreader

Bare die devices

Thermally-improved way

New way allows for “true” double-sided cooling

Conventional wayHeat sink

DevicesThermal paste

PCB (e.g. FR4)

I- 5Center for Power Electronic SystemsOct. 5th 2007 IBM Symposium

Thermal advantages

1. AlN DBC is 38x more heat conductive than PCB

2. Integrated thermal management replaces heat sink

3. Heat spreads easily in all directions

4. More even temperature distribution on surfacesThis increases effective convection surface area

5. Power path and devices are directly bonded to DBC for rapid heat removal

I- 6Center for Power Electronic SystemsOct. 5th 2007 IBM Symposium

Motivation for this work

The dominant failure in power electronic systems is thermal

I- 7Center for Power Electronic SystemsOct. 5th 2007 IBM Symposium

“Stacked Power” process

LTCC Inductor layer

100 µF decoupling cap layer

AlN DBC heat spreader & interconnect

AlN DBC with embedded devices

Embedded devices allow for layering on both sidesThermal management is integrated using DBC layersExample: Buck POL operating at 1.3 MHz, 5V 1.2VThis is our long-term goal for a fully integrated POL:

AlN DBC heat spreader & interconnect

I- 8Center for Power Electronic SystemsOct. 5th 2007 IBM Symposium

ChallengesHigh power density goal, ~ 150 W/in3 in free space

New processes are needed to achieve integration

High frequency to reduce output cap = 1.3 MHz

Low parasitic inductances for less loss

Making the Interconnections

Connecting the different layers while keeping parasitic inductance low

Interfacing with the load

Making a capacitor layer of high value capacitance

So far we are concentrating only on inductor layer

I- 9Center for Power Electronic SystemsOct. 5th 2007 IBM Symposium

Latest POL Hardware

Circuit size is 20 x 18 x 5 mmThis includes driver and room for a control chip

Inductor is located on bottom sideDevices are embedded inside ceramic active layer (they are not visible here)

I- 10Center for Power Electronic SystemsOct. 5th 2007 IBM Symposium

Active layer: Fabrication

Using 8/15/8 mil AlN Direct Bonded Copper as device carrier

1. Copper is etched to leave traces behind

2. Laser cutter makes holes for device dies, vias and snubber cap

3. Devices and cap wafer are epoxied in place

4. Interconnections are made with more DBC top & bottom

I- 11Center for Power Electronic SystemsOct. 5th 2007 IBM Symposium

Comparing substrates

Tmax = 158 CTavg = 96.8 C

Stacked Power temps are 40% less than PCB versionNo heat sink is needed with “Stacked Power” at 25W

Tmax = 94.1 CTavg = 91.0 C

This one uses PCB This one uses AlN DBC

I- 12Center for Power Electronic SystemsOct. 5th 2007 IBM Symposium

RL

L1

Q1

Q2C1

Electrical constraint

Cdec

Low inductance of this loop is important for high efficiency

Its value must be as low as possible

Cdec value is ~ 22 uF

Previous work

I- 13Center for Power Electronic SystemsOct. 5th 2007 IBM Symposium

Effect of high loop inductance

Vsw (@1.3MHz)

L_loop ≅ 1.8 nH ζ = ~ 0.06, Rac=~0.101ohm

L_loop ≅ 1.23 nH ζ = ~0.25, Rac=~0.351ohm

Vsw (@1.3MHz)

Does Stacked Power allow for a low value?

Both tests using discrete packaged devices: IRF6633 + IRF6691)

From: Yu Meng

IPS 2006

I- 14Center for Power Electronic SystemsOct. 5th 2007 IBM Symposium

Another advantage

Bare dies and cap are shown in cross-sectional viewWe can get L much lower by flipping them relative to each otherLoop inductance calculation using Maxwell 3DLloop = 0.82nH with flip MOSFET pair

Capdec

Solder

Flip MOSFET pair

Ceramic

D

S

D

S

I- 15Center for Power Electronic SystemsOct. 5th 2007 IBM Symposium

Stacked Power comparisonBoth use the same parts Integrated POL shows no loss of efficiency with PCB versionWe are currently working on an even better performing POL

3D POL 5V to 1.2V at 1.3MHzStacked Power POL compared with PCB discrete version

75.00%

77.50%

80.00%

82.50%

85.00%

87.50%

90.00%

92.50%

0 5 10 15 20

Output Current (A)

Effic

ienc

y (%

)

Stacked Pow er

PCB

I- 16Center for Power Electronic SystemsOct. 5th 2007 IBM Symposium

Stacked Power advantages

Substrate is 38x more heat conductive than PCBDevices run cooler by having very effective heat removalIncreases effective surface area for convection to ambient

Thermal management is integrated No heat sink is needed for full 15A output in natural convection!

Integrates active devices and inductor layerIntegration allows for stacked parts/layers in z-direction

Circuit parasitics are reduced for less lossHigher switching frequency possible which reduces POL size

Very high power density of 127 W/in3 achievedThis includes driver, integrated inductor and room for control chip

I- 17Center for Power Electronic SystemsOct. 5th 2007 IBM Symposium

Future work for active layer

Make the smallest package for highest power outputLatest thermal camera shots show no need for a heat sink in natural convection at 20W output and up to 55°C ambient!With the right inductor and 200LFM airflow, we can do 20A output in a much smaller package than we currently have.

Comparing single-layer DBC and 3-layer DBC convertersWhat is the trade-off between thermal performance, packaging and cost?

This technology can be scaled upHigh voltage applications High temperature applications

I- 18Center for Power Electronic SystemsOct. 5th 2007 IBM Symposium

LTCC passives integration• LTCC – Low Temperature Co-fired Ceramics

• Typical sintering temperature ~ 900 ºC compared with HTCC (sinter temperature 1300-1500 ºC)

• Starting material is in sheet form ~ 60-100um thickness

• Laminated to desired thickness before sintering

• Silver and its alloys can be used as conductor

• Conductors are typically in paste form

• Conductors are typically screen-printed on LTCC “green”tapes and co-fired after entire structure is built

[5] http://www2.dupont.com

[5]

I- 19Center for Power Electronic SystemsOct. 5th 2007 IBM Symposium

Motivation: Strengths of ceramic technology over existing technology

PCBCeramic

135 ºC500 ºCSilver alloy Copper

Stable Oxidizes at elevated temperature

17 ppm/K-17 ppm/K4-7 ppm/K0.3 W/mK4 W/mK5.8e7 S/m> 1.7e7 S/m

Temperature CapabilityMetal schemeMetal stability

CTE (metal)CTE (substrate)Thermal cond.

Elec. Cond. Of metal

CTE (silicon) 4 ppm/K4 ppm/K

Possibility of integrating LTCC passives with semiconductor bare die is good

I- 20Center for Power Electronic SystemsOct. 5th 2007 IBM Symposium

LTCC planar inductor

Profile of power inductor has been reduced to < 1mm

Magnetic coreAlumina tile

0.9 mmconductor

1.9 mm

340 μm

125 μm

Plan view Cross-sectional view

5 mm< 1 mm

Discrete inductor

LTCC inductor

I- 21Center for Power Electronic SystemsOct. 5th 2007 IBM Symposium

Thermocouple on top of LTCC inductor

When inductor is shorted

Inductor current waveform

Inductor shorted out

LTCC inductor is able to function at 190 ºC ! LTCC ferrite has relatively high Curie temperature!

Thermal capability of LTCC inductor

I- 22Center for Power Electronic SystemsOct. 5th 2007 IBM Symposium

LTCC inductor I and V @ fs=2MHz, Vin=5V, Vo=1.1V, IDC=5A

-4-202468

1012

-0.1 0 0.1 0.2 0.3 0.4 0.5

time [us]

V L [V

] & I L

[A]

Δi/Δt

VL V(avg)

Inductor Current Inductor voltage

Inductance calculation

tiVL L

ΔΔ

=

I- 23Center for Power Electronic SystemsOct. 5th 2007 IBM Symposium

core

conductor

Conductor width, w

Conductor thickness, e

Core thickness, g

LTCC planar inductor

I- 24Center for Power Electronic SystemsOct. 5th 2007 IBM Symposium

Effective inductance vs. Iout

0

20

40

60

80

100

0 5 10 15 20Iout [A]

L [n

H]

w =1mm inductorw =3.8mm inductor23nH air-gapped inductor

Power stage efficiency vs. Iout

0

20

40

60

80

100

0 0.5 1 1.5 2Iout [A]

Effic

ienc

y [%

]

w=1mm inductorw=3.8mm inductor L223nH air-gapped inductor

Inductor current @ Vin=5V, IDC=0A

-5-4-3-2-101234

0 0.1 0.2 0.3 0.4 0.5

time [us]

I L [A

]

w=1mm inducto rw=3.8mm inducto r23nH inducto r

Inductor current @ Vin=5V, IDC~12.5A

8

10

12

14

16

18

20

0 0.1 0.2 0.3 0.4 0.5time [us]

I L [A

]

w =1mm inductorw =3.8mm inductor23nH inductor>30% >10%

12.5

No Load

Full Load

[1] M. H. F. Lim, J. D. van Wyk, and Z. Liang, “Effect of geometry variation of LTCC distributed air-gap filter inductor on light load efficiency of DC-DC converters”, Ind. Appl. Soc. Conf. 2006, 8-12 Oct 2006, Vol. 4, pp. 1884-1890.

Non-Linear Inductance Property

I- 25Center for Power Electronic SystemsOct. 5th 2007 IBM Symposium

Substrate Inductor with Integrated ShieldNo shield With shield

25nH

Vo-

+ L

C

Q1

Q2IL

Io

RVin

+ VL -Vsw

Iin

Top switchBottom

switch

Gate driverBootstrap diode

Output capacitor

Input capacitor

Bootstrap capacitor

Shield

Inductor substrate

Insulator

Power stage efficiency vs. Iout

70

75

80

85

90

0 2 4 6 8 10 12 14 16Iout [A]

Effic

ienc

y [%

]

shield

no shield

[2] Michele H. Lim, Y. Dong, J. D. van Wyk, F. C. Lee, K. D. T. Ngo, “Shielded LTCC Inductor as Substrate for Power Converter ”, Power Electronics Specialists Conf., 2007, 17 - 21 June 2007.

I- 26Center for Power Electronic SystemsOct. 5th 2007 IBM Symposium

100 nH Inductor Design

Specifications:

L=100nH, IDC=16A, inductor

footprint=28mm x 28mm

thickness < 1.4mm

Inductor electrodes 10mm apart

Inductor electrodes

10mm

28mm

28mm11mm

11mm

11.6mm

13.4mm

Through hole

I- 27Center for Power Electronic SystemsOct. 5th 2007 IBM Symposium

100nH Inductor Design

)38.46(0366.0)8(410 DCDC IIw

lL −++=

22

)(242

22ln(

2 22

222

0

ewew

ewggewgew

++

+

++++

+++

∗πμ

For IDC = 16A, w=2.5mm, e=500um, g=0.433mm

core

conductor

Cross sectional view [4]

1.37 mm0.433 mm

0.433 mm0.5 mm

mHlL /77.1 μ=

For current flowing round a corner,

nHsqLLcorner 21.25.0 ==Let

[3] M.H. Lim, Z. Liang, and J. D. van Wyk, “Modeling of an LTCC Inductor Capable of Improving Converter Light-Load Efficiency ”, Appl. Power Electronics Conf. 2007, 25 Feb - 1 March 2007.

[3]

[4] Prieto, M.J.; Pernia, A.M.; Lopera, J.M.; Martin, J.A.; Nuno, F., “Design and analysis of thick-film integrated inductors for power converters”, IEEE Trans. Ind. Appl., vol. 38, issue 2, March-April 2002 pp. 543 – 552.

I- 28Center for Power Electronic SystemsOct. 5th 2007 IBM Symposium

100nH inductor design

conductor length = 2 x (15.1 + 2.3) + 16.7 = 51.5 mm

L(4corners) = 8.8 nHL(51.5mm) = 91 nH

L(total) = 99.8 nH

Inductor electrodes

I- 29Center for Power Electronic SystemsOct. 5th 2007 IBM Symposium

100nH inductor design

Inductor electrodes

sqmt

Rsheet /1018.15.0107.1

11 47 Ω×=××

=⋅

= −

σ

Rcorner = 0.5*Rsheet μΩ/

= 58.8 uΩ /

Ω=××=×= − mwlRmmR sheet 42.2

5.25.511018.1)5.51( 4

Ω=×+= mmtotalR 66.28.58442.2)( μ

[5] M.H. Lim, Z. Liang, and J. D. van Wyk, “Low profile integratable inductor fabricated based on LTCC technology for microprocessor power delivery applications”, Appl. Power Electronics Conf. 2006, 19 - 23 March 2006, pp. 593-599.

[5]

I- 30Center for Power Electronic SystemsOct. 5th 2007 IBM Symposium

100nH Inductor with Integrated Shield Fabrication

Inductor winding Inductor top layer

Insulator with shield Inductor with shield

I- 31Center for Power Electronic SystemsOct. 5th 2007 IBM Symposium

Inductor current waveform

121314151617181920

-0.5 0 0.5 1 1.5 2time [us]

I [A

]

Inductor voltage waveform

-3-2-1012345

-0.5 0 0.5 1 1.5 2

time [us]

V [V

]

Full load actual L = 105.5 nH

Full load current = 16A

Full load designed L = 99.8 nH

No load actual L = 231.4 nH

LTCC Planar Inductor Test Results

I- 32Center for Power Electronic SystemsOct. 5th 2007 IBM Symposium

78%79%80%81%82%83%84%85%86%87%88%

0 4 8 12 16 20 24Io (A)

Effic

ienc

y

LTCC

Discreet L=100nH

Vin=5V,Vo=1.2V,fs=1.3MHz, 1IRF6633+IRF6691

For Discrete L=100nH: DCR=0.17 mohm

For LTCC: DCR=1.91 mohm

1.8%

[6] J. Sun, IPS presentation, 12 Dec 2006

Inductor electrodes

[6]

LTCC Planar Inductor Test Results

I- 33Center for Power Electronic SystemsOct. 5th 2007 IBM Symposium

LTCC inductor testing

LTCC 100nH inductor used with 1-DBC layer converterOnly changes were

1. removing discrete inductor from board2. Reflowed LTCC inductor on back side of board

Side viewTop view

I- 34Center for Power Electronic SystemsOct. 5th 2007 IBM Symposium

Efficiency results

Excellent light-load efficiency thanks to non-linear inductanceHeavy load performance suffers from high DCR

We are currently making different inductor versions with lower DCR

3D POL 5V to 1.2V at 1.3MHz

75.00%

77.50%

80.00%

82.50%

85.00%

87.50%

90.00%

92.50%

0 2 4 6 8 10 12 14 16 18 20

Output Current (A)

Effic

ienc

y (%

)

discrete

LTCC

I- 35Center for Power Electronic SystemsOct. 5th 2007 IBM Symposium

Thank you for your attention!

Do you have any questions?