3D ICs: The Next Revolution Ho-Ming Tong GM & Chief R&D Office Group R&D December, 2009.
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Transcript of 3D ICs: The Next Revolution Ho-Ming Tong GM & Chief R&D Office Group R&D December, 2009.
3D ICs: The Next 3D ICs: The Next
RevolutionRevolutionHo-Ming TongHo-Ming Tong
GM & Chief R&D OfficeGM & Chief R&D Office
Group R&DGroup R&D
December, 2009December, 2009
2© ASE Group. All Rights Reserved.© ASE Group. All Rights Reserved.
““You Can Resist An Invading Army; You CannYou Can Resist An Invading Army; You Cannot Resist An Idea Whose Time Has Come,”ot Resist An Idea Whose Time Has Come,”Victor Hugo, French Author of Victor Hugo, French Author of • The Hunchback of Notre Dame The Hunchback of Notre Dame • Les MisérablesLes Misérables
19th Century France
Louis XVIII Charles X Louis-Philippe Ier
Second RepublicFirst Republic Third Republic
Victor Hugo (1802-1885)Victor Hugo (1802-1885)
Napoléon Bonaparte (Napoléon Ier)
Louis-Napoléon Bonaparte (Napoléon III)
1800 190018501830 184018201810 1860 1870 1880 1900
3© ASE Group. All rights reserved.© ASE Group. All rights reserved.
3D ICs: The Next Revolution3D ICs: The Next Revolution
IC Trends
Package Trends
2.5D IC Applications
3D IC Challenges & Opportunities
IC-package-system Co-design
4© ASE Group. All Rights Reserved.© ASE Group. All Rights Reserved.
IC TrendsIC Trends
6© ASE Group. All Rights Reserved.© ASE Group. All Rights Reserved.
Moore’s Law Driving Semiconductor
Source: Intelftp://download.intel.com/research/silicon/Gordon_Moore_ISSCC_021003.pdf
8© ASE Group. All Rights Reserved.© ASE Group. All Rights Reserved.
Planar CMOS Transistor Scaling Planar CMOS Transistor Scaling Approaching Practical LimitsApproaching Practical Limits
Ref.: Chen (IBM ’09)
(Atoms Don’t Scale)
9© ASE Group. All Rights Reserved.© ASE Group. All Rights Reserved.
Disruptive Low-power & High Performance Disruptive Low-power & High Performance Technology RequiredTechnology Required
Performance Improvement
At The Expense of Power
Perf
/ W
att (
au)
100 1,000
100.5
0.8
1.1
1.4
1.7
2.0
Goal
45 nm
65 nm
90 nm250 nm
350 nm
130 nm150 nm
W. Haeosch et al IBM J. R & D. (2006)
Lg (nm)
10© ASE Group. All Rights Reserved.© ASE Group. All Rights Reserved.
CMOS Logic & Memory Scaling ContinuesCMOS Logic & Memory Scaling Continues
2009 2011 2013 2015 2017
Ref.: Jammy (SEMATECH ’09)
Deep SubmicronDeep Submicron Nano Fines/WiresNano Fines/Wires Deep Nano ~ AtomicDeep Nano ~ Atomic
11© ASE Group. All Rights Reserved.© ASE Group. All Rights Reserved.
Semiconductor in TransitionSemiconductor in Transition
Source: Samsung
‘95 ‘00 ‘05‘06
‘10‘09
‘15 ‘20 ‘25 ‘30 ‘35
DDR2
DDR2
‘12
‘13
DDR3
DDR3
DDR4
DDR4
12© ASE Group. All Rights Reserved.© ASE Group. All Rights Reserved.
Multi-core Extends Performance Multi-core Extends Performance As Clock Frequency SaturatesAs Clock Frequency Saturates
Ref.: Shapiro (IBM ’09)
Cloc
k Sp
eed
(Arb
.)
13© ASE Group. All Rights Reserved.© ASE Group. All Rights Reserved.
3D IC is Next Revolution in3D IC is Next Revolution inSemiconductor & Package Technology Semiconductor & Package Technology RoadmapsRoadmaps
CMOS
Memory
RF
MEMS
Photonics
Better Performance
Smaller Size
Lower Cost
Massive Bandwidth Reduced Interconnect Delays Power Reduction Higher Functionality/Space Heterogeneous Integration
3D Maximizes Space Utilization
Lower Cost vs. Next-gen Device
Reuse of Proven SIP
14© ASE Group. All rights reserved.© ASE Group. All rights reserved.
Package TrendsPackage Trends
15© ASE Group. All rights reserved.© ASE Group. All rights reserved.
3D SiP Evolution3D SiP Evolution
WLCSPWLCSP
IC
IC
IC
IC
Wirebond BGA FC BGA
Stacked Die PoP EPS 2.5D IC (Si
Interposer)
3D IC
FO-WLP
Wireless Proximity- Capacitive
- Inductive
FO-WLP SiP
Finer Pitch
WLCSP
Heterogeneous Integration
Assembly + Substrate
Heterogeneous Integration
IC + Assembly
16© ASE Group. All rights reserved.© ASE Group. All rights reserved.
2.5D IC2.5D IC
Substrate
TSV
Processor
Rep or RDLBump
BGA Ball
Silicon Interpose
r
ELK/ULK Layers
3D IC3D IC
Substrate
Memory
Bump
TSV
ELK/ULK Layers
Rep or RDL
Processor
BGA Ball
ASE 2.5D & 3D ICsASE 2.5D & 3D ICs
17© ASE Group. All rights reserved.© ASE Group. All rights reserved.
Taipei: 100 Years Ago & NowTaipei: 100 Years Ago & Now
2D IC2D IC
3D IC3D IC
Building101
18© ASE Group. All Rights Reserved.© ASE Group. All Rights Reserved.
PoP
FO-WLP
Stacked Die
2.5D IC
3D IC
SoC
3D SiP Benchmarking:3D SiP Benchmarking:2.5D IC Available Before 3D IC2.5D IC Available Before 3D IC
EDAPerformance
Process(Assy+Test)
Supply Chain
Excellent
Good
Good
Fair
’11 - ‘12
Ready Year Ready by Year
Now - ‘10
‘11 ‘12
Fair
Fair Existing Infrastructu
re
19© ASE Group. All rights reserved.© ASE Group. All rights reserved.
IC-package-system Compatibility KeyIC-package-system Compatibility Keyto 2.5D & 3D ICs Applicationsto 2.5D & 3D ICs Applications
Ch
ip S
ize
100 200 300 400 500 600
PA
PM
PeripheralI/O Controller
Baseband
Networking
BT/WiFi
GPU, CPU,Chipset & FPGA
Memory Application Processor
Transceiver
Discrete
I/O
Switch
High
Hig
h 2.5 & 3D ICs w/ TSVs
ELK / ULK Wafers
(≦ 45 nm Nodes)
20© ASE Group. All Rights Reserved.© ASE Group. All Rights Reserved.
Changing Supply ChainsChanging Supply Chains
3D IC (Via First)
Front-end
Backside GrindingBackside Grinding
Fab + TSVFab + TSVFab + TSVFab + TSV
Die StackingDie Stacking
Assembly & Test
Assembly & Test
Surface TreatmentSurface Treatment
RDLRDL
Micro-bumpMicro-bump
Back-end
2.5D IC (Si Interposer)
TSVTSV
Backside GrindingBackside Grinding
Bottom Side RDLBottom Side RDL
Top Side RDL + Micro-bump
Top Side RDL + Micro-bump
Die StackingDie Stacking
Assembly & Test
Assembly & Test
FabFabFabFab
RepRep
FC BumpingFC Bumping
Middle-end = Front-end + Back-end
21© ASE Group. All Rights Reserved.© ASE Group. All Rights Reserved.
2.5D IC Applications2.5D IC Applications
22© ASE Group. All Rights Reserved.© ASE Group. All Rights Reserved.
Processor
Memory
RF
MEMS
Silicon Interposer
2.5D IC: An Alternative to 3D IC2.5D IC: An Alternative to 3D IC
Pros
Integration Flexibility: Device Function Partitioning & Easy Mix & Match of Package Styl
es Lower Process Risk SoC (2D) Like Integration: More Compatible w/
Current EDA Tool Ease of Production Planning Ease of DFT/BIST/DFY Rework Possibility Short Development Cycle: TTM Lower cost
Lower Power High Performance Compact Size
Cons
Larger X-Y Sizes Higher Power Consumption Compared to
3D IC
Complicated Integration Higher Process Risk EDA Tool Support Issue Single Source for Custom IC DFT/BIST Challenges Challenging Rework Longer Development Cycle
Time Potentially High Product Cost
23© ASE Group. All Rights Reserved.© ASE Group. All Rights Reserved.
2.5 IC Enables Device Function 2.5 IC Enables Device Function Partitioning for Cost PerformancePartitioning for Cost Performance
RFRFNode 2 (> Node 1)Node 2 (> Node 1)
PMUPMUNode 3 (> Node 2)Node 3 (> Node 2)
Silicon Interposer
BBBB
RFRF
PMUPMU
2.5D IC28 nm
(Single-chip Package)
BBBB
Node 1 (= 28 nm)Node 1 (= 28 nm)
24© ASE Group. All Rights Reserved.© ASE Group. All Rights Reserved.
Inductor
Capacitor
Resistor
Diplexer Balance Filter BalunBand Pass Filter
ASE 2.5D IC w/ IPDASE 2.5D IC w/ IPD
25© ASE Group. All Rights Reserved.© ASE Group. All Rights Reserved.
Node 1 > Node 2> Node 3> Node 4
Advanced Wafer Node
FCCSP
2.5D IC
Assem
bly
+ S
ub
str
ate
Cost
40/40 µmL/S 30/30 µm 20/20 µm 15/15 µm - 10/10 µm
Yield* 85% 80~85% 65~75% <65%
2.5D IC Bridges The Interconnect Gap 2.5D IC Bridges The Interconnect Gap Between IC & SubstrateBetween IC & Substrate
HighS
ub
str
ate
C
ap
ab
ilit
ies
Substrate
Substrate
Interposer
Assembly
Assembly
Package Cost(Excl. Die)
Si Interposer
1+2+1 Cost
* Base on The Best Substrate Source
2 Layer Cost
26© ASE Group. All rights reserved.© ASE Group. All rights reserved.
3D IC Challenges & Opportunities: 3D IC Challenges & Opportunities: Cost is EverythingCost is Everything
Assembly
Metrology
Test
Thermal
Design
System
Substrate
Memory
ELK/ULK Layers
TSV
Bump
Processor
27© ASE Group. All Rights Reserved.© ASE Group. All Rights Reserved.
2.5D & 3D ICs Revolutionize Existing 2.5D & 3D ICs Revolutionize Existing Advanced Packaging InfrastructureAdvanced Packaging Infrastructure
FAB Technolo
gy
FC Assembly
Substrate L/S (µm)
Wafer-level L/S (µm/µ
m)
Wafer Probing
Pitch (µm)
FC Bump Pitch (µm)
‘09
28 nm 32 nm45 nm45 nm
‘13‘12‘11‘10
28 nm
D2D & D2W
25/25 20/20 20/20 15/15 10/10
BackSide
15/15 10/10 6/6 6/6 6/6
110 - 30125 - 30125 - 40150 140 - 80
< 505070> 100 80
µBump
µFC
µWLCSP
µSiP
28© ASE Group. All rights reserved.© ASE Group. All rights reserved.
Innovation Required to Reduce Innovation Required to Reduce 3D IC Assembly Cost3D IC Assembly Cost
2007 2008 2009 2010 2011
Standard Reflow
Thermal Compression
Bonding
High
Pit
ch
/Wafe
r Th
ickn
ess
Min
Max
Assembly Cost
FC Bump Pitch
TSV Micro-bump Pitch
Substrate Solutions
2.5D IC
3D IC
29© ASE Group. All rights reserved.© ASE Group. All rights reserved.
Innovations in MetrologyInnovations in Metrology
IC Feature Size
3D X-ray Computed
Tomography
High
Small
Wirebond
FC Bump
TSV
X-R
ay
Resolu
tion
30© ASE Group. All rights reserved.© ASE Group. All rights reserved.
Solder/Cu Pillar Joint (X-ray)
TSV Depth (IR: FOGALE)
TSV Depth (SAWLI: STIL)
TSV CD (AVI: August)
TSV Plating (X-ray: Dage)
TSV Stop-on-metal (E-beam: N/A)
3D IC Metrology Opportunities 3D IC Metrology Opportunities
Microbump Joint (X-ray)
Memory
Processor
X
XX
X
Re-passivation/RDL (August)
Rep/RDL (August)
X
Interface Adhesion (SAT)
Gap Ready
Wafer-level Test (Probe Card)
X
31© ASE Group. All rights reserved.© ASE Group. All rights reserved.
3D IC Yield3D IC Yield
Y1 = Joint Yield
Memory
Processor
X
XXX
XX Y7 = Joint Yield
Y8 = Joint Yield
Y3 = Interface Yield
Y5 = Interface Yield
Y2 = Repassivation/RDL Yield
Y6 = Repassivation/RDL Yield
Y4 = TSV YieldX
Y9 = Substrate Yield
Y10 = Joint Yield
Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10Overall Yield
99.5% 99.5% 99.5% 99.5% 99.5% 99.5% 99.5% 99.5% 99.5% 99.5% 95.0%
99.5% 99.5% 90.0% 90.0% 90.0% 99.5% 99.5% 99.5% 99.5% 99.5% 70.0%
RDL
Scrap or Barely Usable Scrap
ELK/ULK
XX
X
32© ASE Group. All rights reserved.© ASE Group. All rights reserved.
TSV Redundancy Improves YieldTSV Redundancy Improves Yield
Refs.: (Samsung ’09) & Shapiro (IBM ’09)
Electrical Redundancy Achieved by 7 Bars
# Signal TSVs# Redundant TSVs
Assembly Yield (300 TSVs)
4-Die Stack 8-Die Stack
2/1 95% 76%
4/2 99.8% 98%
33© ASE Group. All Rights Reserved.© ASE Group. All Rights Reserved.
3D IC Test Challenges & 3D IC Test Challenges & OpportunitiesOpportunities
Known Good Die RF/At Speed Digital/IPD Test Coverage
TSV Test Finer Pitch (≦50 µm, Area
Array) Thin Wafer Handling (≦ 100 µm)
3D IC Integrated Test Test Access System-level Test
Yield Optimized Assembly & Test Flow
Test Cost Cost Effective Test
Refs.: Verigy, NXP, TI, & ASE Data
Logic
Memory
RF MEMS
Substrate
34© ASE Group. All rights reserved.© ASE Group. All rights reserved.
3D IC Equipment Readiness3D IC Equipment Readiness
Product Type Criteria200 mm Wafer
Readiness300 mm Wafer
ReadinessWafer Thinning / Grinding
50 µm
Via Last
Via Etching20 ~ 50 µm, AR
10
Via Isolation20 ~ 50 µm, AR
10
Via Seedlayer 20 ~ 50 µm, AR 10
Via First
Via Etching5 ~ 10 µm, AR
10
Via Isolation5 ~ 10 µm, AR
10
Via Seedlayer 5 ~ 10 µm, AR 10
Thin Wafer Handling 50 µmVia Surface Finish No Cu DishingRe-distribution (Double Sides)
-
Micro-bumping 30 µm PitchTSV Wafer Probing & Testing
30 µm Pitch
Wafer Singulation -
D2W/W2W BondingSolder / Micro
BumpAssembly -Final Test -
Ready for Mass ProductionReady for Qualification No Solution Yet
Ready for Prototyping
35© ASE Group. All Rights Reserved.© ASE Group. All Rights Reserved.
Resolving 3D IC Thermal Challenges Resolving 3D IC Thermal Challenges Through IC to System Co-designThrough IC to System Co-design
• 3D Floor Planning• Dynamic & Leakage Power Management
High Power Density
3D IC Packaging System• Hot Spots• High Power Density
(Source: Intel)
• Cooling Capacity• Space Constraint• Noise
• Test Socket / Chuck Design• Burn-in Oven Cooling Capacity
Test
• 3D EDA Tool• Thin-film Thermo- Electric Cooler (TFTEC)
• Vapor chamber• Liquid Cooling• Thermo-Electric Cooler (TEC)• Refrigeration Cooling
• Liquid Cooling• Thermo-Electric Cooler (TEC)
• Micro-channel w/ Nanofluid• Nano Materials
Challenges
Possible Solutions
36© ASE Group. All Rights Reserved.© ASE Group. All Rights Reserved.
New System Architecture New System Architecture Required Required for 3D IC Proliferationfor 3D IC Proliferation Key: IC-package-system Co-design
– System Cost– Software– Performance: Clock Feed & Power Feed– Function Partioning– Chip to Chip Interface Standardization– Supply Chain Complexity: Inventories, Liability & Shipment– Alternative Solutions – Test Coverage & Flow
Hot Issues: Memory Interface & 3D System Bus Standards
Refs.: Laukkala & Kujala (Nokia) & Shapiro (IBM)
37© ASE Group. All Rights Reserved.© ASE Group. All Rights Reserved.
IC – package –system Co-designIC – package –system Co-design
38© ASE Group. All Rights Reserved.© ASE Group. All Rights Reserved.
System Partition
IP Reuse
System Architecture
Planning& Spec
Definition
3D IC Integration Requires Concurrent IC – package - system Co-design for Yield & Reliability
Design Entry(RTL)
Logic Synthesis(Gate Level Realization)
Physical Implementation(Floor Plan / P&R)
Chip Finishing(DRC/DFM)
Design Entry(RTL)
Logic Synthesis(Gate Level Realization)
Physical Implementation(Floor Plan / P&R )
Chip Finishing(DRC/DFM)
Foundry TSV Design Reference Flow
System Software & Firmware Development
Chip Fabrication
Chip Test
Chip Fabrication
Chip Test
PKG Process Risk Assessment & Design Rule
PKG Perf. ParameterData base
Package Design
Assembly Tape Out
3D IC Integration Assembly & Test
System IntegrationDesign
System IntegrationTest
IC Design House Wafer foundry Assembly & Test System & Product
P24
39© ASE Group. All Rights Reserved.© ASE Group. All Rights Reserved.
3D IC Concurrent Design Requires 3D IC Concurrent Design Requires Modeling & Validation at Package & Modeling & Validation at Package & System LevelsSystem Levels
Bump CrackMaximum Stress
• Viscoplastic/ Creep Constitutive Model• Darveaux/ Coffin-Manson Fatigue Model
Inter-delamination
Chip
Substrate
Modeling Validation
Thermal Management
Via R, L, C Modeling
40© ASE Group. All Rights Reserved.© ASE Group. All Rights Reserved.
Early Life Performance
(ELP) Reliability Test(System-centric)
• Junction Temperature & Clamping Pressure History under System Operation Conditions• System Reliability (Single or Multiple Die)
Ensuring Package-system Compatibility Ensuring Package-system Compatibility Besides Chip-package CompatibilityBesides Chip-package Compatibility
Customer Requirements &
Customer’s Customer Requirements
• IC Requirements• System Requirements• Hardware to Support System Reliability• Customer QA Requests
System-level Board Reliability Modeling
(Package-centric)
• Mimic Package-on-board• Power cycling of Package on Board• Thermal & Mechanical Stress Simulations• Clamping Pressure & Junction Temperature Safety Zone
+ +
=
Enhanced ELP Reliability Test(System-centric)
Package-on-board Safety Conditions to IC & System Customers
41© ASE Group. All Rights Reserved.© ASE Group. All Rights Reserved.
2.5 IC Enables Device Function 2.5 IC Enables Device Function Partitioning for Cost PerformancePartitioning for Cost Performance
RFRFNode 2 (> Node 1)Node 2 (> Node 1)
PMUPMUNode 3 (> Node 2)Node 3 (> Node 2)
Silicon Interposer
BBBB
RFRF
PMUPMU
2.5D IC28 nm
(Single-chip Package)
BBBB
Node 1 (= 28 nm)Node 1 (= 28 nm)
42© ASE Group. All Rights Reserved.© ASE Group. All Rights Reserved.
Co-design Critical to Ensure Co-design Critical to Ensure Chip-package-system Compatibility for Chip-package-system Compatibility for FCBGA FCBGA
Si Die
ELK/ULKRDL
Rep
Solder Bump
Solder Mask
BT Core
Cu Pad
Underfill
ELK/ULK Layer Crack
!Underfill - Rep Delaminat
ion ! Bump IMC
Crack !
No Longer Dumb Connector
Eutectic Bump
Pb-free Bump (ELK)
Cu Pillar (ULK)
Fatigue Resistance
Good Fair Poor
ELK/ULK Protection
Good Fair Poor
Electro-migration Performan
ce
Poor Fair Good
43© ASE Group. All Rights Reserved.© ASE Group. All Rights Reserved.
Co-design Also Crucial to 3D IC forCo-design Also Crucial to 3D IC forChip-package-system CompatibilityChip-package-system Compatibility
3D IC (Via First)Memory + Processor Stack
Substrate
Back Side Bump
Front-end
Middle-end
Back-end
Processor Die w/ TSVs (Via Last)ELK/ULK Layers
Middle-end
Front-end
Back Side Rep or RDL
Memory
44© ASE Group. All rights reserved.© ASE Group. All rights reserved.
3D IC Co-design Challenges & 3D IC Co-design Challenges & OpportunitiesOpportunities
Logic
Memory
RF MEMS
Substrate
Challenges Gap
Design3D IC EDA Tool Environment3D IC Design Flow from IC to System
No Proven Product
ElectricalTSV Characterization (Electrical + Stress)System-level SI/PI Validation & Sign-off Flow
Validation Flow & Tool
Thermal3D IC Thermal ModelsThermally Aware Design & Management
SupportFlow & Tool
Mechanical System-level Package Reliability No Test Standard
SOC
Interposer + IPDControllerPassivesAnalog
Board
3D IC3D IC
45© ASE Group. All rights reserved.© ASE Group. All rights reserved.
3D IC Applications Abound3D IC Applications Abound
Now2010 ~ 2020
(Driver: Better Life) 2020 ~ 2040
Transportation- Drive to Autonomous Cars- Telematics Infrastructure
Medical Electronics- Imaging- Diagnostics & Therapy- Home Medical
Security- Video Analytics- Video Intelligence
Green Energy Harvesting - Macro: Solar,Wind & Wave- Micro: Piezoelectric, Kinetic &
Thermoelectric- Thin Film Batteries
•Quantum Nucleonic
•Biofuel •Biometics•Bionics: - Robo Sapiens - Cognitronics - Genotyping•Frictionless Vehicl
es•Lab-on-a-chip•Molecular Sensor•Nonobots•Self-illuminating Highway
CMOS Image Sensor Memory
- SRAM/DRAM
- NAND
Application Processor /Baseband
CPU GPU FPGA MEMS …
46© ASE Group. All rights reserved.© ASE Group. All rights reserved.
3D IC Users in The Era of Heterogeneous 3D IC Users in The Era of Heterogeneous IntegrationIntegration
Tra
nsis
tor
Den
sit
yH
igh
Com
pon
en
t D
en
sit
yH
igh
1990 2000 2010 2020 2030 2040
Silico
n Tech
nology
More Than Moore
Quantum Technology
• FO-WLP• EPS• 2.5D IC
•Molecular
SiP
SoC
Package Level
Package & Die Levels
Package, Die & System Levels
System Component Density
Brick Wall•Bio
• 3D IC• Flexible Circuit• MEMS• Opto• Wireless Proximity
•Stacked Die
•PoP
Feature Size
4 nm45 nm
47© ASE Group. All rights reserved.© ASE Group. All rights reserved.
Implanted Wireless DeviceImplanted Wireless Device
World's First ‘Wireless' Pacemaker Talks to your Doctor Daily, Whether You Like It or Not (Though You Probably Do)
by Joseph L. Flatley (8/’09)
48© ASE Group. All Rights Reserved.© ASE Group. All Rights Reserved.
3D IC Innovations Create A New Market 3D IC Innovations Create A New Market PlacePlace
49© ASE Group. All Rights Reserved.© ASE Group. All Rights Reserved.
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