336 IEEE TRANSACTIONS ON COMPUTER-AIDED...

336 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 36, NO. 2, FEBRUARY 2017

FRESH: A New Test Result ExtractionScheme for Fast TSV Tests

Jaeseok Park, Hyunyul Lim, and Sungho Kang, Senior Member, IEEE

Abstract—Three-dimensional integrated circuits (3-D ICs) areconsidered to meet the performance needs of future ICs. The corecomponents of 3-D ICs are through-silicon vias (TSVs), whichshould pass appropriate prebond and post-bond tests in 3-D ICfabrication processes. The test inputs must be injected into theTSVs, and the test results must be extracted. This paper pro-poses a new test result extraction scheme [fast result extractionby selective shift-out (FRESH)] for prebond and post-bond TSVtesting. With additional hardware, the proposed scheme remark-ably reduces the TSV test time. FRESH avoids unnecessary testresult extraction when the number of faulty TSVs in the TSVset is 0 or exceeds the number of TSV redundancies in the set.These early fault analyses are executed in the checkers of TSVgroups. The experimental results show that the proposed schemecan reduce the result extraction time in practical environments.

Index Terms—Three-dimensional integrated circuit (3-D IC),post-bond test, prebond test, test result extraction, through-siliconvia (TVS) repair, TSV test.

I. INTRODUCTION

ALL SEMICONDUCTOR products in production pro-cesses require tests in order to ensure high reliability of

the products with a stable yield. The three-dimensional (3-D)integration technique, which stacks multiple dies in an inte-grated circuit (IC), is very attractive for solving the speed andpower problems of two-dimensional (2-D) ICs, so 3-D ICshave been developed for IC products. However, in 3-D semi-conductor manufacturing processes, the yield, reliability, andheat are significant problems because of the extremely highdensity and complexity of 3-D ICs. Due to these problems,there is growing apprehension that product quality will suf-fer, and many studies have emphasized the urgent need forsolutions [1], [2]. Thus, new methods and concepts are clearlyneeded for 3-D IC testing in order to detect new defects andincrease the quality of ICs [3].

Through-silicon vias (TSVs), which are vertical metal linesand signal paths between layers, are a new core component

Manuscript received December 21, 2015; revised March 21, 2016 andMay 15, 2016; accepted May 19, 2016. Date of publication June 9, 2016;date of current version January 19, 2017. This work was supported in partby the Ministry of Trade, Industry and Energy under Grant 10052875, andin part by the Korea Semiconductor Research Consortium Support Programfor the Development of the Future Semiconductor Device. This paper wasrecommended by Associate Editor P. Girard.

The authors are with the Computer System and Reliable SOCLaboratory, Department of Electrical and Electronic Engineering, YonseiUniversity, Seoul 120-749, South Korea (e-mail: [email protected];[email protected]; [email protected]).

Color versions of one or more of the figures in this paper are availableonline at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TCAD.2016.2578883

of 3-D ICs. TSV defects are a very critical problem in thefunctionality of 3-D ICs, so TSV testing is done to increasedefect detection effectively in a 3-D IC environment. ManyTSV test methodologies have been researched. In general, the3-D IC test is divided into two groups according to the processsteps: 1) prebond and 2) post-bond. Likewise, TSVs are testedin different ways according to the two test steps.

The prebond test is executed on each layer before layer-stacking. TSVs are not connected yet in this step, and signalcommunication on them is not available so the TSV test can-not be executed like the common logic test. To overcome thispoint, test circuits are embedded that can charge and dischargeautonomously to TSVs, and they are used to observe the elec-trical characteristics of TSVs. On the other hand, the layersare already stacked and bonded together in the post-bond teststep so some test values can be injected into the TSVs, andthe results are observed from the TSVs for analysis [4]–[8].

Commonly, a TSV set is composed of a fixed number ofsignal and redundant TSVs. Redundant TSVs are additionalTSVs that are inserted to replace faulty TSVs and can occupythe connections of signal TSVs using the switches or fusesbuilt in each TSV set. After each TSV test, the test resultsare extracted, and then they are analyzed to find which TSVsare faulty. If possible, a TSV repair procedure is executed byusing the redundant TSVs in each TSV set after this test resultanalysis. This repair procedure is one of the solutions to raisethe manufacturing yield. Many TSV repair schemes have beenresearched [7], [9]–[12].

Testing accounts for significant costs in IC manufactur-ing. Furthermore, exponential increases in testing costs areexpected in future manufacturing processes. In particular, thetest time, which is one of the test cost elements, is a corefactor in the time-to-market, so significant efforts have beenmade to reduce test times. Recently, the trend has shown thatthe test time has been reduced using many techniques in spiteof the increased hardware area costs. This results from thelower burden of the hardware area as the IC manufacturingtechnologies become shrinking and improved.

This paper proposes a new test result extraction scheme,which is a fast result extraction by selective shift-out (FRESH),and its structure for TSV tests, including both prebond andpost-bond tests. It prevents unnecessary test result extractionby incorporating early defect checks, which are accomplishedin the checkers near the TSV sets. This reduction of thetest result extraction causes a remarkable reduction in thetest time. Section II reviews previous TSV test schemes, andSection III describes the proposed TSV test scheme and its

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PARK et al.: FRESH: A NEW TEST RESULT EXTRACTION SCHEME FOR FAST TSV TESTS 337

Fig. 1. TSV set structures for repair. (a) Overall TSV set structure. (b) Repairexamples of signal-switching and signal-shifting. (c) TSV placement for easyapplication of repair structures.

hardware structure. Section IV then analyzes the effective-ness of the proposed scheme, and shows that the proposedscheme reduces the test time significantly. Section V concludesthis paper.

II. PREVIOUS WORK AND MOTIVATION

A. TSV Set Structure for Repair

TSVs are simply defined as vertical signal paths betweenthe IC layers. If signal TSVs alone are inserted, a single faultyTSV will invalidate the 3-D IC, seriously affecting the yield.For this reason, redundant TSVs are installed for repair [9].A fixed number of signal and redundant TSVs is organizedinto a bundle, called a TSV set in this paper (Fig. 1). TSVrepair techniques have recently been introduced. There are tworepresentative TSV repair concepts: 1) signal-switching [7]and 2) signal-shifting [10], [11]. In the former category, onlythe faulty TSVs are replaced by the fixed redundancies, sothe redundancies are not prioritized for repair. In the lattercategory, the connections are sequentially shifted from thefaulty to the redundant TSVs. Fig. 1(b) shows repair exam-ples of the two repair structures. Signal-shifting increasesthe number of changed connections, but minimizes the delaygap problem due to the repair step. A repairable TSV setarranges the connections by a switch (composed of transistors

or multiplexers) or a fuse box, as shown in Fig. 1. Whendefects are detected in the TSV sets, the faulty TSVs arereplaced with the redundancies, greatly improving the yieldof 3-D ICs [12].

In the papers of the repair structures, there are some discus-sions about the TSV placement for the application of TSV repairstructures [9], [11], [12]. The TSVs in a TSV set should beplaced in reasonable area to avoid routing problems in buildingTSV repair structures. In the papers which propose the repairstructures, it is assumed that TSVs are inserted commonly inregular TSV arrangement. Moreover, TSVs can be located withconcerns about the repair structure implementation even if TSVsare not available to achieve fully regular TSV arrangement. Theprevious TSV schemes introduce the TSV arrangement whichis composed of the plural TSV blocks as shown in Fig. 1(c). Inthis TSV arrangement, TSVs are replaced to build TSV blockswhich have no delay problem for TSV repair structure afterthe first TSV placement in the 3-D IC design step. FRESH, theproposed TSV test scheme, is applied to the previous TSV setincluding the repair structure, and it also assumes that TSVsare placed in the regular TSV arrangement through the TSVplacement technique introduced in [11].

B. TSV Test

Prior to TSV repair, the TSVs should be tested to locate thefaulty members. In this way, the bad dies are removed beforethe stacking and the good dies are stacked and subjected tothe post-bond tests. The common TSV tests after die stackingare very similar to the general logic test in 2-D ICs. Testsignals are injected into the TSVs on one layer, and the resultsignals are observed on the other layer. However, the prebondtest requires different approaches because the TSVs are notyet connected. The difference between the two TSV tests isindicated in Fig. 2 [13]–[21].

Fig. 2(a) presents the overall structure of the prebond test.The prebond TSV test circuits for injecting or removing elec-trons into/from the TSVs are embedded near the TSV sets,which comprise signal and redundant TSVs. The test con-troller or TAM sends control bits to TSV test circuits. And, testresults return to them. Fig. 2(b) shows a representative prebondTSV test circuit for the prebond test of a single TSV. The pre-bond test circuit is connected to TSV in the test mode whenthe test enable is 1. During the test mode, a current sourcecharges a TSV when the test control signal (TC) which is con-trolled by the test controller is 0. On the other hand, a TSV isdischarged when TC is 1. And, a comparator (Cmp) decideswhether the voltage of the TSV is higher than reference volt-age. For the simpler structure, a comparator can be replacedwith two inverters as mentioned in [19]. Using these compo-nents, the test circuit gathers two types of TSV characteristicinformation through following steps.

Step 1: Reset (TC = 1).Step 2: Charging and comparison 1 (TC = 0).Step 3: Discharging and comparison 2 (TC = 1).After reset (step 1), the TSV is charged by the current

source, and its voltage level is then checked by Cmp (step 2).If the TSV does not have capacitance-related problems,


Fig. 2. Previous TSV test structures. (a) Overall structure for the prebondtest. (b) Example of a prebond TSV test circuit. (c) Signal flow of the commonpost-bond TSV test.

such as short, pinhole defects and improper/insufficientfilling of TSVs, its voltage level should be higher than the ref-erence value. Therefore, 1 is stored in a flip-flop in the case ofno-defect. Then, the TSV is discharged (step 3), and its volt-age level is again compared to the reference. In this case, thevoltage level must be lower than the reference value to con-firm the absence of other problems, such as improper solderingof bumps. Through these two comparisons, two informationbits are compacted into one bit as a test result. The result bitsfrom all TSVs are stored in a flip-flop chain, and are shiftedout serially.

Fig. 2(c) shows the signal flow in a common post-bondTSV test. The test input data are stored in flip-flop chainsby serial shift operations, and are simultaneously injected intothe TSVs. The output data of the TSVs are also collected intoflip-flop chains, extracted by another serial shift operation andanalyzed to identify the faulty TSVs. In the post-bond test,the test input data pass through only the TSVs, and hence,are usually very simple. The commonest formats of the testinput data are all-0 and all-1, although checkerboard data suchas 01010101 or 10101010 are sometimes required to identifyfaults resulting from interactions among the TSVs.

C. Motivation

The results of TSV tests are commonly extracted in series.Therefore, the shift time of the extraction is proportional to the

Fig. 3. Overall structure of FRESH.

length of the flip-flop chain [7], [12], [19], [21]. In fact, the bitsrequiring observation are very few because the TSV defect ratetypically ranges from 0.005% to 5% [12]. Therefore, to reducethe extraction time of the test result, the worthless resultscan be selected before starting the extraction. For example,a no-fault test result need not be extracted because it con-tains no information for the fault location analysis. The testexecution should be further enhanced if irreparable dies aresimply discarded rather than analyzed. Focusing on these pos-sibilities, we develop a new test-result extraction scheme witha fast extraction time. The proposed scheme is discussed inSection III.

III. FRESH: PROPOSED SCHEME

The proposed scheme reduces the test time by avoidingunnecessary extraction of the test results. The need for resultextraction is decided by counting the number of faulty TSVsin a TSV set. The TSV test results are observed only if theTSV set is faulty and repairable. A 3-D layer includes n TSVsets, each containing k TSVs with m TSV redundancies.

A. Overall Structure

Fig. 3 shows the overall structure of the proposed scheme.Each TSV group sends a checker bits (CBs) to the CB com-pactor, which compacts the CBs received from all TSV groups.After analyzing fault condition (FC), the controller extractsthe test results of the TSV groups needing repair procedures.Because the 3-bit select signal from the controller is sharedamong all TSV groups, the result extraction structure can bereused in the post-bond test. Each TSV group receives anenable signal from the controller for partial result extraction.FRESH uses the repair structure composed of independentn groups. FRESH is always available with any repair struc-tures which are built with independent TSV groups as shownin Fig. 3.

B. TSV Group

Fig. 4 shows the inner structure of the ith TSV group, wherewe have added a mode selector and a checker. Test results are


Fig. 4. TSV group structure.

Fig. 5. Mode selector structure.

generated from the TSV test circuits in prebond tests, anddelivered from the TSV set in the post-bond tests. This role isperformed by the routing module (the mode selector), whichconverts the post-bond test results to the bits available to thecorresponding checker. This function is controlled by the threecontroller bits sel_S, sel_O, and sel_E. The checker observesthe test results and generates two bits of data, CB({CBi

1, CBi0})

to prevent unnecessary extractions. A flip-flop chain at thebottom of Fig. 4 is a part of the flip-flop chain in the previousTSV test structure shown in Fig. 2(a), and it stores test resultsof the corresponding group.

1) Mode Selector (For Post-Bond Test Support): The modeselector consists of two stages, as shown in Fig. 5. The firststage distinguishes between the pre- and post-bond tests, andthe second stage inverts the specific bits for the test modes ofthe post-bond test. Sel_S in the first stage exists to distinguishbetween prebond and post-bond test modes. It is turned offin the prebond test mode, and the test results from TSV testcircuits are stored in the flip-flop chain. On the other hand,sel_S is turned on in the post-bond test mode, and the outputsof TSVs are stored in the flip-flop chain. For the post-bondtest, the outputs of TSVs should be transformed into the testresults which are available to the same checker of the pre-bond test, and this transform is executed in the second stage.Sel_O and sel_E are control signals of this stage, and theydetermine whether test results from odd and even numberedTSVs should be inverted or not. This inversion is requiredfor the only post-bond test, and is determined depending ontest input data. In the prebond test, all of sel_S, sel_O, andsel_E are set to 0, and all results from the TSV test circuitspass unchanged through the mode selector. In the post-bondtest, sel_S is fixed to 1, so the values from the TSVs are

TABLE ITRUTH TABLE OF CHECKER

Fig. 6. CB compactor structure.

delivered to the second stage. If the test is all-0, both sel_Oand sel_E are set to 0, and the signals pass through withoutchange. Conversely, in an all-1 test, the controller fixes bothselecting signals of the second stage to 1. Consequently, thesignals are inverted before reaching the checker. Finally, ina checkerboard test, {sel_O, sel_E} is set to {0, 1} or {1, 0}.

2) Checker: A checker analyzes the test results from thecorresponding mode selector and determines whether the testresults of this TSV group are needed. The checker outputsa 2-bit-long CBs ({CB1, CB0}), referring to the truth tableshown in Table I. The conditions in Table I are describedbelow, where Nf and Nr indicate the number of faulty andredundant TSVs, respectively, in the TSV set.

Condition 1 (No Fault—CB = 00): All bits from the modeselector are 0s. Therefore, no faults are detected, so this TSVgroup does not require TSV repair and result extraction.

Condition 2 (Repairable—CB = 01): If the number of faultyTSVs is equal to or less than the number of redundant TSVs inthe set, this TSV set should be repaired to increase the yield.Therefore, the test results should be extracted to identify thefaulty TSVs.

Condition 3 (Unrepairable—CB = 11): If the number offaulty TSVs exceeds the number of redundant TSVs in theset, the TSV set is unrepairable. Thus, the test result need notbe observed.

C. CB Compactor

The CBs from all TSV groups are compressed and stored inthe CB compactor, as shown in Fig. 6. Initially, all CB0s andCB1s are combined into FC which are composed of 2 bits,{FC1, FC0}, through a logical OR function. Therefore, FCinforms the TSV fault status of the whole die while CBinforms that of a group. All of the CB0s are stored in a flip-flop chain to identify the faulty TSV groups. There are threepossible cases.

Case 1 (Defect-Free—FC = 00): No faults are detected inthe TSV groups, so test result extraction is not required.


Fig. 7. Flowchart of the controller function.

Case 2 (Potentially Good—FC = 01): The TSVs in someTSV groups should be repaired. The test results of thefaulty TSV groups must be observed and subjected to repairprocesses.

Case 3 (Bad—FC = 11): More than one TSV group isunrepairable. Thus, no more test work is required.

D. Test Data Extraction and Treatment

1) Flow of the Test Result Extraction: Fig. 7 is a flowchartof the test result extraction by FRESH. The checkers in theTSV groups decide CB ({CB1, CB0}) from the test resultanalysis. The CB compactor then finds FC ({FC1, FC0}) bygathering the CBs from the TSV groups. In the proposed struc-ture, a controller observes the FC before guiding the test resultextraction. First, the controller delivers CB to a built-in self-test (BIST) module or test wrapper. The next function of thecontroller is conditional, as described below.

Case 1 (FC = 01): In this case, partial test result extractionis required, so the controller begins searching for 1s in theregister of the CB compactor. Whenever such a 1 is found,the controller forces the relevant TSV group to output the testresult. This operation is implemented by an enable signal fromthe controller.

Case 2 (FC = 00 or 11): In this case, 00 and 11 indicate thatthe relevant dies are faultless and unrepairable, respectively. Inboth scenarios, the test results do not need to be extracted.

2) Test Data Treatment in Tester or BIST: The controllersends fault information to the BIST or the tester. At first, thecontroller transmits FC, and some additional data should berequired in the “potentially good” case. The data which isrequired to be transmitted additionally is described as bellows.

Case 1 (FC = 01): In this case, the test controller shouldextract test results of faulty TSV sets. The transmission data iscomposed of {FC1, FC0, NF, ADD1, R1, . . . , ADDNF, RNF}where NF, ADDj, and Rj denote the number of faulty TSVsets, the address of the jth faulty TSV set, and the test result

of jth faulty TSV set, respectively. ADDj and Rj are repeatedas many as NF.

Case 2 (FC = 00, 11): No more data are transmitted becauseno test result needs to be extracted. The BIST or the testerdetermines pass or fail of the target die by just those two bits.

The tester or the BIST performs the following steps accord-ing to the received bit stream.

Step 1 (State Recognition): The fault state is determined bytwo bits, FC. If FC is 00 or 11, the tester or the BIST reportsfault state as “defect-free” or “bad,” and finishes this TSV testprocess. However, it analyzes the next test data if FC is 01 toexecute repair processes.

Step 2 (NF Identification): The next data is NF, and this isrequired to know how long data is valid after that.

Step 3 (Test Result Collection and Repair): The tester orthe BIST collects test results, and tester and BIST start repairprocess with this TSV fault information.

E. Application to Post-Bond Test

Many previous post-bond test techniques shift TSV teststimuli in through a serial flip-flop chain even though TSVtest data is very simple as mentioned in Section II-B. Thisinefficient test data insertion results from a fact that testresults should be also shifted out serially in the previousones. However, TSV test inputs are inserted in parallel whenFRESH structure is reutilized in the post-bond test. From thispoint, FRESH can achieve test time reduction even in thepost-bond test.

Signal direction of the TSV groups determines the positionsof the post-bond TSV test results. When the TSVs deliver theirsignals from the lower to the upper layers, the test results arecollected in the flip-flop chains of the upper layer. Conversely,when the TSVs deliver their signals from the upper to thelower layers, the results are stored in the flip-flop chains ofthe lower layer. Since common 3-D ICs locate primary IOson the bottom layer, total fault analysis about plural layersis usually executed in the bottom layer. Because of that, tofind the final FC containing the TSV fault information of bothlayers, the TSV FC of the upper layer should be transferredto the controller of the lower layer. If neither layer containsfaulty TSVs or if at least one layer is unrepairable, the con-troller bypasses the extraction process. Otherwise, if some orall of the faulty TSV sets are repairable, the signal pass isshared by extracting the test results of the upper layer throughthe controller of the lower layer. In this way, the faulty TSVinformation is delivered from the upper layer to the lowerlayer, as shown in Fig. 8.

F. TSV Test Examples With FRESH

1) Prebond Test: Fig. 9 presents three examples of prebondtests implemented by the proposed scheme. Tests were per-formed on four TSV groups, each with five TSVs (includingone redundant TSV). The mode selector signals, sel_S, sel_O,and sel_E, were maintained at 0 in this prebond test, and theresults of the test circuits were conveyed to checkers.

In Example 1, all TSVs in all TSV groups are normal. Thecheckers detect no signals indicating faulty TSVs, and all CBs


Fig. 8. FRESH structure for post-bond test.

Fig. 9. Extraction examples in prebond test implemented by the proposedmethod. (a) Definition. (b) Example 1 (defect-free). (c) Example 2 (bad).(d) Example 3 (potentially good).

are set to 00 under the truth table of Table I. Consequently,the CB compactor is filled with 00s. After observing the FC,the controller recognizes that this die contains no faulty TSVs,so the prebond test is completed with no result extractions.

In Example 2, at least one of the TSV groups is unre-pairable. The presence of a single unrepairable TSV setrenders this die unusable. In this example, group 1 includesone faulty TSV, whereas group 4 contains three faultyTSVs, exceeding the number of redundant TSVs in thegroup. Therefore, the CB of group 2’s checker is compactedas 11 in the CB compactor, indicating that this die has

TABLE IIEXAMPLE OF POST-BOND TEST SEQUENCE WITH PROPOSED SCHEME

Fig. 10. Proposed test result extraction examples in post-bond test.(a) Definition. (b) Example 4 (defect-free). (c) Example 5 (bad). (d) Example 6(potentially good).

unrepairable defects. Consequently, the controller finishes theprebond test without extraction.

Finally, in Example 3, TSV groups 1 and 3 each con-tain one faulty TSV. Therefore, the CB in the checkers ofboth groups is 01. The FC then becomes 01, indicating thatsome of the TSVs in this die need to be repaired. From


TABLE IIIREDUCTION OF TEST RESULT EXTRACTION TIME IN THE PROPOSED METHOD (COMPARED WITH [7], [12], [19], AND [20])

this moment, the controller begins observing the CB0 valuesin the CB compactor register. Referring to the observed val-ues, it extracts only the results of the faulty TSV groups [seepanel of Fig. 9(d)]. The test results of each TSV group areindividually extracted by controlling the enable signal.

2) Post-Bond Test: A post-bond test sequence supported bythe proposed test scheme is presented in Table II. The modeselectors of the TSV groups should be controlled accordingto the test input data, so the selection signals, sel_S, sel_O,and sel_E, are determined just like the values of Table II touse identical checkers. Three examples, similar to the prebondtest examples in Fig. 9, are presented in Fig. 10. The signalsof groups 1–4 are directed from layers 1 to 2, while those ofgroups 5–8 are directed from layers 2 to 1.

Example 4 shows a defect-free case in which every TSVin all TSV groups is normal. The checkers identify no signalsindicating faulty TSVs. Therefore, following the truth table inTable I, all of the CBs in both layers become 00. Consequently,the CB compactor is filled with 00s, and the final CB isalso determined as 00. Having observed the final FC, thecontroller recognizes that this die contains no faulty TSVs.Therefore, the post-bond test is completed with no resultextractions.

In Example 5, one of the TSV groups is unrepairable.Therefore, even though other faulty groups are repairable,this stacked die is unusable in practice. In this example, TSVgroup 7 contains two faulty TSVs, exceeding the number ofredundant TSVs in the group. Therefore, the CB value ofTSV group 7 is determined as 11, and the FC of layer 1becomes 11. The final FC value, 11, informs the controllerthat the die is unrepairable, and the post-bond test terminateswithout extraction.

Finally, Example 6 demonstrates a repairable die in whichtwo of the TSV groups (groups 3 and 6) contain one faultyTSV each. Therefore, the CBs in the corresponding checkersof both groups read 01. Consequently, the FC becomes 01 inboth layers, and the final FC is 01. The controller recognizesthat some of the TSVs in this die need to be repaired. Fromthis moment, it begins observing the CB0 values in the CBcompactor register of both layers. Referring to the observedvalues, it extracts the results of the faulty TSV groups [seepanel of Fig. 10(d)]. Again, the test results of each TSV groupare individually extracted by controlling the enable signal.

IV. RESULTS

The time reduction of extracting the test results by FRESHwas evaluated in TSV test simulations. The results are shownin Table III. The time reduction ratio of the test result extrac-tions was defined as the average proportion of the reducedtime over the time required for test result extraction in previ-ous TSV test techniques (reported in [7], [12], [19], and [21]),and is formulated as

TR = avg ·(

tprevious − tFRESH

tprevious

). (1)

In Table III, Nset and NTSV denote the numbers of TSV setsand TSVs in each set, respectively. The number of redundantTSVs in a TSV set (Nr) was set to 1 or 2. To demonstrate theeffectiveness of FRESH for any 3-D IC process, the defectrate of the TSVs was varied from 0.0001 to 0.03 within thepractical TSV defect rate range mentioned in [12].

In general, the reduction rate increases as the number ofTSVs in a die increases. This trend shows that FRESH ismore effective when the 3-D IC structures use a lot of TSVs.


TABLE IVPROBABILITY ANALYSIS OF DEFECT-FREE OR BAD DIES (Nr = 1)

TABLE VREDUCTION OF TEST RESULT EXTRACTION TIME FOR HUGE NUMBERS OF TSVS (COMPARED WITH [7], [12], [19], AND [20])

And, all the time reduction rates show similar trends as theTSV construction quality changes. To find the reason whythe trends maintain the similar shape, the probabilities ofdie condition need to be analyzed. The time reduction trendstrongly depends on the probability of defect-free or bad die(P00 or P11), because FRESH bypasses the test result extrac-tion in cases of faultless and unrepairable dies, and is thusmaximally effective in such cases. The probability analysisfor target dies containing 30, 40, 50, 60, 70, and 80 TSVsets, each composed of 8 TSVs, is expressed as a percentagein Table IV. As the TSV construction process improves, theprobability of a defect-free die increases, while that of a baddie decreases. Therefore, the reduction rate of the extractiontime increases in both high-quality and very low-quality TSVconstruction processes. In other words, the remarkable incre-ment of probability of bad die case draws the time reductionrate up. When each TSV set contains two redundant TSVs,the probability of a potentially good die rises because TSVsets with two faulty TSVs can be repaired. Thus, the effec-tiveness of FRESH decreases as more redundant TSVs areincluded in each set. However, even in the case of two redun-dant TSVs, the time reduction by FRESH is excellent (seeright side of Table III). Furthermore, increasing the number ofredundant TSVs in a set does not greatly deteriorate the reduc-tion rate in a high-quality 3-D IC manufacturing process. Thetime reduction rates (relative to existing techniques) in 3-DICs containing many TSVs are presented in Table V. Despitethe increased number of redundant TSVs in this comparison,the reduction rates remain very high. This fact implies thatFRESH becomes more efficient as more TSVs are constructedin the 3-D IC.

To verify hardware structures which are required forFRESH, the SAED 32/28 nm EDK, which is an open

TABLE VIHARDWARE OVERHEAD OF MODE SELECTOR AND CHECKER

TABLE VIIADDITIONAL HARDWARE OVERHEAD ANALYSIS

educational design kit, is employed. The cell area was con-verted into the NAND gate area for easy comparison with theareas estimated in different process environments. In this sim-ulation, we assumed that each TSV set contains one redundantTSV. The hardware area of the mode selectors and checkersis influenced by the number of TSVs in each set. In fact,


Fig. 11. Layout of proposed hardware for 320 TSVs.

Fig. 12. Floorplan of regular TSV arrangement.

the actual area is proportional to the number of TSVs, asshown in Table VI. The mode selector is an optional mod-ule which is required to be inserted for the post-bond test,and this option is reflected in Table VII. Under the conditionsof Table VII, the mode selectors and checkers of the third caseof Table VI are inserted in TSV groups because the number ofTSVs in a TSV set is 8. The required information from thecheckers and logic circuit in the partial test result extractioncontrol increases as more TSV sets are included in the die.Accordingly, in Table VII, the area of the controller increasesproportionally to the number of TSV sets. Despite the largehardware overhead in cases of many TSV sets, the hardwareburden is small compared to the whole area of the 3-D IC,which generally includes tens of millions of gates.

The total area which includes flip-flop chains from the previ-ous structure is presented in the placement step. Fig. 11 showsa layout example of the proposed hardware with a core shape.The core-shape layout is formed by auto-placement with 80%utilization and indicates the density of standard cells in thelayout. The hardware in Fig. 11 is designed for an irregulararrangement of 320 TSVs with 40 8-bit checkers and a con-troller. The sizes of the elements are estimated in the fifthcolumn of Table VII. A regular prearrangement of the TSVsis shown in Fig. 12. Here, the TSV keep-out zone is assumedas three times larger than a D-flip-flop in the SAED 32/28 nmEDK process. The intervals (dt) prevent signal interactionamong the TSVs. Assuming that dt equals the width/heightof the TSV keep-out zone, we can place standard cells con-structed by FRESH hardware anywhere in the area, excludingthe TSV keep-out zones. The utilization values were measuredand are listed in the fifth column of Table VII. We find thatall utilizations are close to 16.5%.

V. CONCLUSION

The proposed TSV test result extraction scheme, FRESH,focuses on the unnecessary test result data extraction inprevious TSV test techniques. FRESH eliminates this unneces-sary test result extraction through partial data extraction, andreduces the test time, which is one of the important factorsin test cost. Prior to data extraction, the TSV groups requir-ing extraction are identified by a fault analysis procedure,and requests are conveyed through checkers inserted in theTSV groups. The checkers determine the number of faultyTSVs, and then decide whether the relevant TSV set can berepaired. The data from the checkers are collected in the con-troller, which determines the TSV groups needing test resultextraction. The FRESH structure also supports post-bond TSVtests. This proposed TSV test-result extraction scheme offersa promising solution to the increasing demands of 3-D ICprocessing.

REFERENCES

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Jaeseok Park received the B.S. degree in elec-trical and electronic engineering from YonseiUniversity, Seoul, South Korea, in 2008, where heis currently pursuing the combined Ph.D. degreewith the Department of Electrical and ElectronicEngineering.

His current research interests include design fortestability, built-in self-test, reliability, test algo-rithms, through-silicon via test, through-siliconvia repair, and very large scale integration design.

Hyunyul Lim received the B.S. degree in elec-trical and electronic engineering from YonseiUniversity, Seoul, South Korea, in 2013, where heis currently pursuing the combined Ph.D. degreewith the Department of Electrical and ElectronicEngineering.

His current research interests include low-powerscan testing, delay scan test design, reliability, andvery large scale integration design.

Sungho Kang (M’89–SM’15) received the B.S.degree from Seoul National University, Seoul,South Korea, and the M.S. and Ph.D. degreesin electrical and computer engineering from theUniversity of Texas at Austin, Austin, TX, USA,in 1992.

He was a Research Scientist with theSchlumberger Laboratory for Computer Science,Schlumberger Inc., Austin, TX, USA, and a SeniorStaff Engineer with the Semiconductor SystemsDesign Technology, Motorola Inc., Schaumburg, IL,

USA. Since 1994, he has been a Professor with the Department of Electricaland Electronic Engineering, Yonsei University. His current research interestsinclude very large scale integration/system-on-a-chip design and testing,design for testability, built-in self-test, defect diagnosis, and design formanufacturability.

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