32-BIT MICROCONTROLLER MB91310 Series … microelectronics controller manual fr60 32-bit...

FUJITSU MICROELECTRONICSCONTROLLER MANUAL

FR6032-BIT MICROCONTROLLER

MB91310 SeriesHARDWARE MANUAL

CM71-10119-2E

FR6032-BIT MICROCONTROLLER

MB91310 SeriesHARDWARE MANUAL

For the information for microcontroller supports, see the following web site.This web site includes the "Customer Design Review Supplement" which provides the latest cautions on system development and the minimal requirements to be checked to prevent problems before the system development.

http://edevice.fujitsu.com/micom/en-support/

FUJITSU MICROELECTRONICS LIMITED

PREFACE

Objectives and Intended Reader

Thank you for using Fujitsu Microelectronics semiconductor products.

The MB91310 is a standard single-chip microcontroller that has a 32-bit high-performance RISCCPU as well as built-in I/O resources for embedded controller that requires high-performanceand high-speed CPU processing.

The MB91310 is most suitable for embedded applications, such as TV and PDP controllers, thatrequire a high level of CPU processing power.

The MB91310 is one of the FR60* family of microcontrollers, which are based on the FR30family of CPUs. It has enhanced bus access and is optimized for high-speed use.

This manual is intended for engineers who will develop products using the MB91310 anddescribes the functions and operations of the MB91310. Read this manual thoroughly.

For more information on instructions, see the “Instructions Manual”.

Trademarks

*: FR, the abbreviation of FUJITSU RISC controller, is a line of products of Fujitsu MicroelectronicsLimited.

Other company names and brand names are the trademarks or registered trademarks of theirrespective owners.

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Organization of This Manual

This manual consists of the following 21 chapters and an appendix.

CHAPTER 1 OVERVIEW

This chapter provides basic information required to understand the MB91310, and coversfeatures, a block diagram, and functions.

CHAPTER 2 HANDLING THE DEVICE

This chapter provides precautions on handling the MB91310.

CHAPTER 3 CPU AND CONTROL UNITS

This chapter provides basic information required to understand the functions of theMB91310. It covers architecture, specifications, and instructions.

CHAPTER 4 EXTERNAL BUS INTERFACE

The external bus interface controller controls the interfaces with the internal bus for chipsand with external memory and I/O devices.

This chapter explains each function of the external bus interface and its operation.

CHAPTER 5 I/O PORT

This chapter describes the I/O ports and the configuration and functions of registers.

CHAPTER 6 U-TIMER

This chapter describes the U-TIMER, the configuration and functions of registers, and U-TIMER operation.

CHAPTER 7 16-BIT RELOAD TIMER

This chapter describes the 16-bit reload timer, the configuration and functions of registers,and 16-bit reload timer operation.

CHAPTER 8 PROGRAMMABLE PULSE GENERATOR (PPG) TIMER

This chapter gives an outline of the PPG (Programmable Pulse Generator) timer andexplains the register configuration and functions and the timer operations.

CHAPTER 9 MULTIFUNCTION TIMER

This chapter gives an overview of the multifunction timer and explains the registerconfiguration and functions and the timer operation.

CHAPTER 10 16-BIT PULSE WIDTH COUNTER

This chapter gives an overview of the 16-bit pulse width counter and explains the registerconfiguration and functions and the counter operation.

CHAPTER 11 INTERRUPT CONTROLLER

This chapter describes the interrupt controller, the configuration and functions of registers,and interrupt controller operation. It also presents an example of using the hold requestcancellation request function.

CHAPTER 12 EXTERNAL INTERRUPT AND NMI CONTROLLER

This chapter describes the external interrupt and NMI controller, the configuration andfunctions of registers, and operation of the external interrupt and NMI controller.

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CHAPTER 13 REALOS-RELATED HARDWARE

This chapter explains the delayed interrupt module and bit search module that are REALOS-related hardware.

REALOS-related hardware is used by the real-time OS. When REALOS is used, thehardware cannot be used with the user program.

CHAPTER 14 10-BIT A/D CONVERTER

This chapter gives an overview of the 10-bit A/D converter, register configuration andfunctions, and 10-bit A/D converter operation.

CHAPTER 15 UART

This chapter describes the UART, the configuration and functions of registers, and UARToperation.

CHAPTER 16 I2C INTERFACE

This chapter describes the I2C interface, the configuration and functions of registers, and I2Cinterface operation.

CHAPTER 17 DMA CONTROLLER (DMAC)

This chapter describes the DMA controller (DMAC), the configuration and functions ofregisters, and DMAC operation.

CHAPTER 18 USB FUNCTION

This chapter gives an overview of the USB function, register configuration and functions,operation of the USB function, and supplementary notes on the USB function.

CHAPTER 19 USB HOST INTERFACE

This chapter gives an overview of the USB host interface and explains register configurationand functions.

CHAPTER 20 ON-SCREEN DISPLAY CONTROLLER (OSDC)

This chapter explains the features, block diagram, display functions, control functions, anddisplay control commands of the on-screen display controller (OSDC).

CHAPTER 21 FLASH MEMORY

This chapter provides an outline of flash memory and explains its register configuration,register functions, and operations.

APPENDIX

This appendix consists of the following parts: the I/O map, interrupt vector, dot clockgeneration PLL, USB clock, external bus interface setting, and instruction lists. The appendixcontains detailed information that could not be included in the main text and referencematerial for programming.

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Copyright ©2004-2008 FUJITSU MICROELECTRONICS LIMITED All rights reserved.

• The contents of this document are subject to change without notice.Customers are advised to consult with sales representatives before ordering.

• The information, such as descriptions of function and application circuit examples, in this document are presented solely forthe purpose of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSUMICROELECTRONICS does not warrant proper operation of the device with respect to use based on such information. Whenyou develop equipment incorporating the device based on such information, you must assume any responsibility arising out ofsuch use of the information. FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising outof the use of the information.

• Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as licenseof the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSUMICROELECTRONICS or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual property right or other right by using such information. FUJITSU MICROELECTRONICS assumes noliability for any infringement of the intellectual property rights or other rights of third parties which would result from the useof information contained herein.

• The products described in this document are designed, developed and manufactured as contemplated for general use, includingwithout limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developedand manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety issecured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage orother loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control,medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e.,submersible repeater and artificial satellite).Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims ordamages arising in connection with above-mentioned uses of the products.

• Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from suchfailures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, andprevention of over-current levels and other abnormal operating conditions.

• Exportation/release of any products described in this document may require necessary procedures in accordance with theregulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.

• The company names and brand names herein are the trademarks or registered trademarks of their respective owners.

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READING THIS MANUAL

Terms Used in This Manual

The following defines principal terms used in this manual.

Term Meaning

I-BUS32-bit bus for internal instructions. In the FR family, which is based on an internal Harvard architecture, independent buses are used for instructions and data. A bus converter is connected to the I-BUS.

D-BUS Internal 32-bit data bus. An internal resource is connected to the D-BUS.

F-BUSPrinceton bus on which internal instructions and data are multiplexed. The F-BUS is connected via a switch to the I-BUS and D-BUS. Built-in resources such as ROM and RAM are connected to the F-BUS.

X-BUSExternal interface bus. An external interface module is connected to the X-BUS. Data and instructions are multiplexed on the external data bus.

R-BUS

Internal 16-bit data bus. The R-BUS is connected to the D-BUS via an adapter. I/O, a clock generator, and an interrupt controller are connected to the R-BUS. Since addresses and data are multiplexed on an R-BUS that is only 16 bits wide, more than one cycle is required for the CPU to access these resources.

E-unit Execution unit for operations.

CLKP

System clock. Clock generated by the clock generator for each of the internal resources connected to the R-BUS. This clock has the same frequency as the source oscillation at its maximum, but becomes a 1, 1/2, 1/3, 1/4, 1/5, 1/6, 1/7,... or 1/16 (or 1/2, 1/4, 1/6, ... or 1/32) frequency clock as determined by the divide-by rate specified by the B3 to B0 bits in the clock generator DIV0 register.

CLKB

System clock. Operating clock for the CPU and each of the other resources connected to a bus other than the R-BUS and X-BUS. This clock has the same frequency as the source oscillation at its maximum, but becomes a 1, 1/2, 1/3, 1/4, 1/5, 1/6, 1/7, ... or 1/16 (or 1/2, 1/4, 1/6, ... or 1/32) frequency clock as determined by the divided-by rate specified by the P3 to P0 bits in the clock generator DIV0 register.

CLKT

System clock. Operating clock for the external bus interface connected to the X-BUS. This clock has the same frequency as the source oscillation at its maximum, but becomes a 1, 1/2, 1/3, 1/4, 1/5, 1/6, 1/7, ... or 1/16 (or 1/2, 1/4, 1/6, ... or 1/32) frequency clock as determined by the divide-by rate specified by the T3 to T0 bits in the clock generator DIV1 register.

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CONTENTS

CHAPTER 1 OVERVIEW ................................................................................................... 11.1 Features .............................................................................................................................................. 21.2 Block Diagram .................................................................................................................................... 61.3 External Dimensions ........................................................................................................................... 71.4 Pin Layout ........................................................................................................................................... 81.5 List of Pin Functions ........................................................................................................................... 91.6 Input-output Circuit Forms ................................................................................................................ 16

CHAPTER 2 HANDLING THE DEVICE .......................................................................... 212.1 Precautions on Handling the Device ................................................................................................. 22

CHAPTER 3 CPU AND CONTROL UNITS ..................................................................... 253.1 Memory Space .................................................................................................................................. 263.2 Internal Architecture .......................................................................................................................... 273.3 Programming Model ......................................................................................................................... 333.4 Data Configuration ............................................................................................................................ 403.5 Word Alignment ................................................................................................................................ 413.6 Memory Map ..................................................................................................................................... 423.7 Branch Instructions ........................................................................................................................... 433.8 EIT (Exception, Interrupt, and Trap) ................................................................................................. 47

3.8.1 EIT Interrupt Levels ..................................................................................................................... 483.8.2 Interrupt Control Register (ICR) ................................................................................................... 503.8.3 System Stack Pointer (SSP) ........................................................................................................ 513.8.4 Table Base Register (TBR) ......................................................................................................... 523.8.5 Multiple EIT Processing ............................................................................................................... 563.8.6 EIT Operations ............................................................................................................................ 58

3.9 Operating Modes .............................................................................................................................. 623.10 Reset (Device Initialization) .............................................................................................................. 65

3.10.1 Reset Levels ................................................................................................................................ 663.10.2 Reset Sources ............................................................................................................................. 673.10.3 Reset Sequence .......................................................................................................................... 693.10.4 Oscillation Stabilization Wait Time .............................................................................................. 703.10.5 Reset Operation Modes ............................................................................................................... 72

3.11 Clock Generation Control ................................................................................................................. 743.11.1 PLL Controls ................................................................................................................................ 753.11.2 Oscillation Stabilization Wait Time and PLL Lock Wait Time ...................................................... 773.11.3 Clock Distribution ......................................................................................................................... 793.11.4 Clock Division .............................................................................................................................. 813.11.5 Block Diagram of Clock Generation Controller ............................................................................ 823.11.6 Register of Clock Generation Controller ...................................................................................... 833.11.7 Peripheral Circuits of Clock Controller ......................................................................................... 97

3.12 Device State Control ....................................................................................................................... 1013.12.1 Device States and State Transitions ......................................................................................... 102

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3.12.2 Low-power Modes ..................................................................................................................... 1063.13 Watch Timer ................................................................................................................................... 1113.14 Main Clock Oscillation Stabilization Wait Timer .............................................................................. 117

CHAPTER 4 EXTERNAL BUS INTERFACE ................................................................ 1234.1 Overview of the External Bus Interface .......................................................................................... 1244.2 External Bus Interface Registers .................................................................................................... 129

4.2.1 Area Select Registers 0 to 7(ASR0 to ASR7) ............................................................................ 1304.2.2 Area Configuration Registers 0 to 7 (ACR0 to ACR7) ............................................................... 1324.2.3 Area Wait Register (AWR0 toAWR7) ........................................................................................ 1394.2.4 I/O Wait Registers for DMAC (IOWR0 to IOWR2) ..................................................................... 1474.2.5 Chip Select Enable Register (CSER) ........................................................................................ 1504.2.6 Cache Enable Register (CHER) ................................................................................................ 1524.2.7 Pin/Timing Control Register (TCR) ............................................................................................ 153

4.3 Setting Example of the Chip Select Area ........................................................................................ 1564.4 Endian and Bus Access .................................................................................................................. 157

4.4.1 Big Endian Bus Access ............................................................................................................. 1584.4.2 Little Endian Bus Access ........................................................................................................... 1654.4.3 Comparison of Big Endian and Little Endian External Access .................................................. 170

4.5 Operation of the Ordinary bus interface .......................................................................................... 1784.5.1 Basic Timing .............................................................................................................................. 1794.5.2 Operation of WR + Byte Control Type ....................................................................................... 1804.5.3 Read -> Write Operation ............................................................................................................ 1824.5.4 Write -> Write Operation ............................................................................................................ 1834.5.5 Auto-Wait Cycle ......................................................................................................................... 1844.5.6 External Wait Cycle ................................................................................................................... 1854.5.7 Synchronous Write Enable Output ............................................................................................ 1864.5.8 CSX Delay Setting ..................................................................................................................... 1884.5.9 CSX -> RD/WR Setup and RD/WR -> CSX Hold Setting .......................................................... 1894.5.10 DMA Fly-By Transfer (I/O -> Memory) ....................................................................................... 1904.5.11 DMA Fly-By Transfer (Memory -> I/O) ....................................................................................... 191

4.6 Burst Access Operation .................................................................................................................. 1924.7 Address/data Multiplex Interface .................................................................................................... 1944.8 Prefetch Operation .......................................................................................................................... 1974.9 DMA Access Operation .................................................................................................................. 200

4.9.1 DMA Fly-By Transfer (I/O -> Memory) ....................................................................................... 2014.9.2 DMA Fly-By Transfer (Memory -> I/O) ....................................................................................... 2034.9.3 2-Cycle Transfer (Internal RAM -> External I/O, RAM) ............................................................. 2054.9.4 2-Cycle Transfer (External -> I/O) ............................................................................................. 2064.9.5 2-Cycle Transfer (I/O -> External) ............................................................................................. 207

4.10 Bus Arbitration ................................................................................................................................ 2084.11 Procedure for Setting a Register .................................................................................................... 2104.12 Notes on Using the External Bus Interface ..................................................................................... 211

CHAPTER 5 I/O PORT .................................................................................................. 2135.1 Overview of the I/O Port ................................................................................................................. 2145.2 I/O Port Registers ........................................................................................................................... 216

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CHAPTER 6 U-TIMER ................................................................................................... 2216.1 Overview ......................................................................................................................................... 2226.2 U-TIMER Registers ......................................................................................................................... 2236.3 U-TIMER Operation ........................................................................................................................ 226

CHAPTER 7 16-BIT RELOAD TIMER ........................................................................... 2277.1 Overview of the 16-bit Reload Timer .............................................................................................. 2287.2 16-bit Reload Timer Registers ........................................................................................................ 229

7.2.1 Control Status Register (TMCSR) ............................................................................................. 2307.2.2 16-bit Timer Register (TMR) ...................................................................................................... 2337.2.3 16-bit Reload Register (TMRLR) ............................................................................................... 234

7.3 16-bit Reload Timer Operation ....................................................................................................... 235

CHAPTER 8 PROGRAMMABLE PULSE GENERATOR (PPG) TIMER ...................... 2398.1 Outline ............................................................................................................................................ 2408.2 Block Diagram of the PPG Timer .................................................................................................... 2418.3 Registers of the PPG Timer ............................................................................................................ 243

8.3.1 Control Status Register (PCNH, PCNL) .................................................................................... 2448.3.2 PPG Cycle Setting Register (PCSR) ......................................................................................... 2488.3.3 PPG Duty Setting Register (PDUT) ........................................................................................... 2498.3.4 PPG Timer Register (PTMR) ..................................................................................................... 250

8.4 PWM Mode ..................................................................................................................................... 2518.5 One-shot Mode ............................................................................................................................... 2538.6 Interrupts ......................................................................................................................................... 2558.7 PPG Output of ALL-L and ALL-H .................................................................................................... 2568.8 Precautions on Using the PPG Timer ............................................................................................. 257

CHAPTER 9 MULTIFUNCTION TIMER ........................................................................ 2599.1 Overview of the Multifunction Timer ............................................................................................... 2609.2 Registers of the Multifunction Timer ............................................................................................... 261

9.2.1 Low-Pass Filter Control Register (TxLPCR) .............................................................................. 2629.2.2 Capture Control Register (TxCCR) ............................................................................................ 2639.2.3 Timer Setting Register (TxTCR) ................................................................................................ 2659.2.4 Entire Timer Control Register (TxR) .......................................................................................... 2679.2.5 Timer Compare Data Register (TxDRR) ................................................................................... 2689.2.6 Capture Data Register (TxCRR) ................................................................................................ 2699.2.7 Test Data Register (TTEST) ...................................................................................................... 270

9.3 Multifunction Timer Operation ......................................................................................................... 271

CHAPTER 10 16-BIT PULSE WIDTH COUNTER .......................................................... 27510.1 Overview of the 16-Bit Pulse Width Counter .................................................................................. 27610.2 Registers of the 16-Bit Pulse Width Counter .................................................................................. 277

10.2.1 PWC Control Register (PWCCL) ............................................................................................... 27810.2.2 PWC Control Register (PWCCH) .............................................................................................. 28010.2.3 PWC Data Register (PWCD) ..................................................................................................... 28210.2.4 PWC Control Register (PWCC2) ............................................................................................... 28310.2.5 Upper Value Setting Register (PWCUD) ................................................................................... 284

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10.3 Operation of the 16-Bit Pulse Width Counter .................................................................................. 285

CHAPTER 11 INTERRUPT CONTROLLER ................................................................... 28911.1 Overview of the Interrupt Controller ................................................................................................ 29011.2 Interrupt Controller Registers .......................................................................................................... 292

11.2.1 Interrupt Control Register (ICR) ................................................................................................. 29411.2.2 Hold Request Cancellation Request Level Setting Register (HRCL) ........................................ 296

11.3 Interrupt Controller Operation ......................................................................................................... 29711.4 Example of Using the Hold Request Cancellation Request Function (HRCR) ............................... 303

CHAPTER 12 EXTERNAL INTERRUPT AND NMI CONTROLLER ............................... 30512.1 Overview of the External Interrupt and NMI Controller ................................................................... 30612.2 External Interrupt and NMI Controller Registers ............................................................................. 307

12.2.1 Interrupt Enable Register (ENIR) ............................................................................................... 30812.2.2 External Interrupt Request Register (EIRR) .............................................................................. 30912.2.3 External Interrupt Request Level Setting Register (ELVR) ........................................................ 310

12.3 Operation of the External Interrupt and NMI Controller .................................................................. 311

CHAPTER 13 REALOS-RELATED HARDWARE .......................................................... 31513.1 Delayed Interrupt Module ............................................................................................................... 31613.2 Delayed Interrupt Module Registers ............................................................................................... 31713.3 Operation of the Delayed Interrupt Module ..................................................................................... 31813.4 Bit Search Module .......................................................................................................................... 31913.5 Bit Search Module Registers .......................................................................................................... 32013.6 Bit Search Module Operation .......................................................................................................... 322

CHAPTER 14 10-BIT A/D CONVERTER ........................................................................ 32514.1 Overview of the 10-Bit A/D Converter ............................................................................................. 32614.2 Registers of the 10-Bit A/D Converter ............................................................................................ 328

14.2.1 A/DC Control Register (ADCTH, ADCTL) ................................................................................. 32914.2.2 Software Conversion Analog Input Select Register ................................................................... 33114.2.3 A/D Conversion Result Register (ch.0 to ch.9) .......................................................................... 33214.2.4 A/D Converter Test Register ..................................................................................................... 333

14.3 Operation of the 10-Bit A/D Converter ............................................................................................ 334

CHAPTER 15 UART ........................................................................................................ 33515.1 Overview of the UART .................................................................................................................... 336

15.1.1 Pairing of Send and Receive Transfers in UART Macro ........................................................... 33815.2 UART Registers .............................................................................................................................. 340

15.2.1 Serial Mode Register (SMR) ...................................................................................................... 34115.2.2 Serial Control Register (SCR) ................................................................................................... 34315.2.3 Serial Input Data Register (SIDR)/Serial Output Data Register (SODR) ................................... 34615.2.4 Serial Status Register (SSR) ..................................................................................................... 34715.2.5 DRCL Register .......................................................................................................................... 351

15.3 UART Operation ............................................................................................................................. 35215.4 Occurrence of Interrupts and Timing for Setting Flags ................................................................... 35615.5 Example of Using the UART ........................................................................................................... 359

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15.6 Example of Setting U-TIMER Baud Rates and Reload Values ...................................................... 361

CHAPTER 16 I2C INTERFACE ....................................................................................... 36316.1 Overview of the I2C Interface .......................................................................................................... 36416.2 I2C Interface Registers ................................................................................................................... 366

16.2.1 Bus Status Register (IBSR) ....................................................................................................... 36916.2.2 Bus Control Register (IBCR) ..................................................................................................... 37216.2.3 Clock Control Register (ICCR) .................................................................................................. 37616.2.4 10-bit Slave Address Register (ITBA) ........................................................................................ 37816.2.5 10-bit Slave Address Mask Register (ITMK) ............................................................................. 37916.2.6 7-bit Slave Address Register (ISBA) ......................................................................................... 38116.2.7 7-bit Slave Address Mask Register (ISMK) ............................................................................... 38216.2.8 Data Register (IDAR) ................................................................................................................. 38316.2.9 Clock Disable Register (IDBL) ................................................................................................... 384

16.3 I2C Interface Operation ................................................................................................................... 38516.4 Operation Flowcharts ...................................................................................................................... 390

CHAPTER 17 DMA CONTROLLER (DMAC) .................................................................. 39317.1 Overview of the DMA Controller (DMAC) ....................................................................................... 39417.2 DMA Controller (DMAC) Registers ................................................................................................. 397

17.2.1 Control/Status Registers A (DMACA0 to DMACA4) .................................................................. 39917.2.2 Control/Status Registers B (DMACB0 to DMACB4) .................................................................. 40417.2.3 Transfer Source/Transfer Destination Address Setting Registers

(DMASA0 to DMASA4/DMADA0 to DMADA4) .......................................................................... 41117.2.4 All-Channel Control Register (DMACR) .................................................................................... 413

17.3 DMA Controller Operation .............................................................................................................. 41517.3.1 Setting a Transfer Request ........................................................................................................ 41817.3.2 Transfer Sequence .................................................................................................................... 42017.3.3 General Aspects of DMA Transfer ............................................................................................. 425

17.4 Operation Flowcharts ...................................................................................................................... 43617.5 Data Bus ......................................................................................................................................... 439

CHAPTER 18 USB FUNCTION ....................................................................................... 44318.1 Overview of the USB Function ........................................................................................................ 44418.2 USB Interface Registers ................................................................................................................. 447

18.2.1 Data Transmission Registers (for End Points) .......................................................................... 45018.2.2 Status Registers ........................................................................................................................ 45318.2.3 Control Registers ....................................................................................................................... 460

18.3 Operation of the USB Function ....................................................................................................... 47518.3.1 Flow of Data Transfer ................................................................................................................ 47618.3.2 CPU Access Operation .............................................................................................................. 482

18.3.2.1 DMA Operation ..................................................................................................................... 48518.3.3 Interrupt Sources ....................................................................................................................... 48918.3.4 Setting of End Point Buffer ........................................................................................................ 49018.3.5 Examples of Software Control ................................................................................................... 492

18.4 Supplementary Notes on the USB Function ................................................................................... 50118.4.1 Double Buffer ............................................................................................................................. 502

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18.4.2 Controlling the D+ Terminating Resistor on the Board .............................................................. 50818.4.3 Automatic Response of Macro Program to USB Standard Request Commands ...................... 50918.4.4 USB Function Macro Program Operation in the Default Status ................................................ 51118.4.5 Detection of USB Connector Connection and Disconnection .................................................... 51218.4.6 Accuracy of UCLK48 ................................................................................................................. 51318.4.7 Setting of Transfer Enable bit (BFOK) during Control Transfer ................................................. 51418.4.8 Precautions for Control Transfer ............................................................................................... 51518.4.9 Macro Program Status after USB Bus Reset ............................................................................ 517

CHAPTER 19 USB HOST INTERFACE .......................................................................... 51919.1 Overview of USB Host Interface ..................................................................................................... 52019.2 Registers of USB Host Interface ..................................................................................................... 522

19.2.1 HcRevision Register .................................................................................................................. 52419.2.2 HcControl Register .................................................................................................................... 52519.2.3 HcCommandStatus Register ..................................................................................................... 52719.2.4 HcInterruptStatus Register ........................................................................................................ 52819.2.5 HcInterruptEnable Register ....................................................................................................... 52919.2.6 HcInterruptDisable Register ...................................................................................................... 53019.2.7 HcHCCA Register ...................................................................................................................... 53119.2.8 HcPeriodCurrentED Register .................................................................................................... 53219.2.9 HcControlHeadED Register ....................................................................................................... 53319.2.10 HcControlCurrentED Register ................................................................................................... 53419.2.11 HcBulkHeadED Register ........................................................................................................... 53519.2.12 HcBulkCurrentED Register ........................................................................................................ 53619.2.13 HcDoneHead Register ............................................................................................................... 53719.2.14 HcFmInterval Register ............................................................................................................... 53819.2.15 HcFmRemaining Register ......................................................................................................... 53919.2.16 HcFmNumber Register .............................................................................................................. 54019.2.17 HcPeriodicStart Register ........................................................................................................... 54119.2.18 HcLSThreshold Register ........................................................................................................... 54219.2.19 HcRhDescriptorA Register ........................................................................................................ 54319.2.20 HcRhDescriptorB Register ........................................................................................................ 54419.2.21 HcRhStatus Register ................................................................................................................. 54519.2.22 HcRhPortStatus[1 and 2] Register ............................................................................................ 546

CHAPTER 20 ON-SCREEN DISPLAY CONTROLLER (OSDC) .................................... 54920.1 Features .......................................................................................................................................... 55020.2 Block Diagram ................................................................................................................................ 55220.3 Display Functions ........................................................................................................................... 553

20.3.1 Screen Configuration ................................................................................................................. 55420.3.2 Screen Display Modes ............................................................................................................... 55620.3.3 Screen Output Control ............................................................................................................... 55820.3.4 Screen Display Position Control ................................................................................................ 55920.3.5 Screen Display Position Offset .................................................................................................. 56520.3.6 Font Memory Configuration ....................................................................................................... 56720.3.7 Display Memory (VRAM) Configuration ..................................................................................... 56820.3.8 Writing to Display Memory (VRAM) ........................................................................................... 569

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20.3.9 Palette Configuration ................................................................................................................. 57220.3.10 Text Display ............................................................................................................................... 573

20.3.10.1 Character Size ...................................................................................................................... 57420.3.10.2 Character Colors .................................................................................................................. 57820.3.10.3 Italic Display ......................................................................................................................... 57920.3.10.4 Underline Display ................................................................................................................. 58220.3.10.5 Character Trimming .............................................................................................................. 58320.3.10.6 Line Enlarged Display ........................................................................................................... 59120.3.10.7 Graphic Character Control .................................................................................................... 59520.3.10.8 Blink Control ......................................................................................................................... 60020.3.10.9 Transparent/Translucent Color Control ................................................................................ 604

20.3.11 Character Background Display .................................................................................................. 60720.3.11.1 Shaded Background Succeeding Character Merge Display ................................................ 60920.3.11.2 Shaded Background Succeeding Line Merge Display (Character Background) .................. 61120.3.11.3 Character Background Extended Display ............................................................................. 613

20.3.12 Line Background Display ........................................................................................................... 61520.3.12.1 Shaded Background Succeeding Line Merge Display (Line Background) ........................... 617

20.3.13 Screen Background Display ...................................................................................................... 62420.3.13.1 Screen Background Character Display ................................................................................ 62520.3.13.2 Screen Background Color Display ........................................................................................ 628

20.3.14 Sprite Character Display ............................................................................................................ 62920.4 Control Functions ............................................................................................................................ 632

20.4.1 Dot Clock Control ...................................................................................................................... 63320.4.2 Sync Signal Input ....................................................................................................................... 637

20.4.2.1 Vertical Synchronization Control .......................................................................................... 63820.4.2.2 Horizontal Synchronous Operation ....................................................................................... 64020.4.2.3 Field Control ......................................................................................................................... 642

20.4.3 Display Signal Output ................................................................................................................ 64520.4.4 Display Period Control ............................................................................................................... 64820.4.5 Synchronization Control ............................................................................................................ 65020.4.6 Interrupt Control ......................................................................................................................... 65320.4.7 OSDC Operation Control ........................................................................................................... 656

20.5 Display Control Commands ............................................................................................................ 65820.5.1 List of Display Control Commands ............................................................................................ 65920.5.2 VRAM Write Address Set (Command 0) ................................................................................... 66220.5.3 Character Data Set (Commands 1 and 2) ................................................................................. 66320.5.4 Line Control Data Set (Commands 3 and 4) ............................................................................. 66520.5.5 Screen Output Control (Commands 5-00 and 5-1) .................................................................... 66720.5.6 Display Position Control (Commands 5-2 and 5-3) ................................................................... 66920.5.7 Character Vertical Size Control (Command 6-0) ....................................................................... 67020.5.8 Shaded Background Frame Color Control (Command 6-1) ...................................................... 67120.5.9 Transparent/Translucent Color Control (Command 6-2) ........................................................... 67320.5.10 Graphic Color Control (Command 6-3) ...................................................................................... 67420.5.11 Screen Background Character Control (Commands 7-1 and 7-3) ............................................ 67620.5.12 Sprite Character Control (Commands 8-1, 8-2, 9-0, and 9-1) ................................................... 67820.5.13 Synchronization Control (Command 11-0) ................................................................................ 68120.5.14 Dot Clock Control (Commands 11-1 to 11-3) ............................................................................ 682

xiii

20.5.15 I/O Pin Control (Commands 13-0 and 13-1) .............................................................................. 68520.5.16 Display Period Control (Commands 14-0 to 14-3) ..................................................................... 68720.5.17 Interrupt Control (Command 15-0) ............................................................................................ 69020.5.18 Palette Control (Commands 16-0 to 16-15) ............................................................................... 69120.5.19 OSDC Operation Control (Commands 17-0 and 17-1) .............................................................. 693

CHAPTER 21 FLASH MEMORY ..................................................................................... 69521.1 Outline of Flash Memory ................................................................................................................. 69621.2 Flash Memory Registers ................................................................................................................. 700

21.2.1 Flash Control/Status Register (FLCR) ....................................................................................... 70121.2.2 Flash Memory Wait Register (FMWT) ....................................................................................... 703

21.3 Flash Memory Access Modes ......................................................................................................... 70521.4 Automatic Algorithm of Flash Memory ............................................................................................ 70721.5 Execution Status of the Automatic Algorithm .................................................................................. 71121.6 Writing to and Erasing from Flash Memory .................................................................................... 715

21.6.1 Read/Reset Status .................................................................................................................... 71621.6.2 Data Writing ............................................................................................................................... 71721.6.3 Data Erasure (Chip Erasure) ..................................................................................................... 71921.6.4 Data Erasure (Sector Erasure) .................................................................................................. 72021.6.5 Temporary Sector Erase Stop ................................................................................................... 72221.6.6 Sector Erase Restart ................................................................................................................. 723

21.7 Restriction and Notes ..................................................................................................................... 724

APPENDIX ......................................................................................................................... 725APPENDIX A I/O Map ................................................................................................................................ 726APPENDIX B Interrupt Vector .................................................................................................................... 744APPENDIX C Dot Clock Generation PLL ................................................................................................... 748APPENDIX D USB Clock ............................................................................................................................ 749APPENDIX E USB Low-power Consumption Mode ................................................................................... 751APPENDIX F External Bus Interface Setting ............................................................................................. 752APPENDIX G Pin state list .......................................................................................................................... 754APPENDIX H INSTRUCTION LISTS ......................................................................................................... 756

H.1 FR Family Instruction Lists ............................................................................................................. 761

INDEX................................................................................................................................... 779

xiv

Main changes in this edition

Page Changes (For details, refer to main body.)

23CHAPTER 2 HANDLING THE DEVICE2.1 Precautions Handling the Device

Changed " Precautions at Power-On/Power-Off".Added " Synchronous Mode Software Reset".

24 Added " Low-power Modes".

68CHAPTER 3 CPU AND CONTROL BLOCK3.10.2 Reset Sources

Changed " Watchdog Reset".(watchdog reset postpone register(WPR) → Time Base Counter Clear register(CTBR))

73CHAPTER 3 CPU AND CONTROL BLOCK3.10.5 Reset Operation Modes

Changed " Synchronous Reset Operation".(Reference: → Notes:)

82

CHAPTER 3 CPU AND CONTROL BLOCK3.11.5 Block Diagram of Clock Generation Controller

Changed " Block Diagram".

84CHAPTER 3 CPU AND CONTROL BLOCK3.11.6 Register of Clock Generation Controller

Changed the table of "[bit9,8]WT1,WT0(Watchdog interval Time select)".(WPR → CTBR)

85 Added "Note:" in " Standby Control Register(STCR)".

89Changed " Time-Base Counter Control Register (TBCR)".(Added the Note in "[Bit 9] SYNCR (SYNChronous Reset enable)".)

90 Changed " Time-Base Counter Clear Register (CTBR)".

93 Deleted " Watchdog Reset Postpone Register(WPR)".

97

CHAPTER 3 CPU AND CONTROL BLOCK3.11.7 Peripheral Circuits of Clock Controller

Changed "[Postponing a watchdog reset]".(watchdog reset postpone register(WPR) → Time Base Counter Clear register(CTBR))

106, 107CHAPTER 3 CPU AND CONTROL BLOCK3.12.2 Low-power Modes

Changed " Sleep mode" of " Low-power Modes".(Added the "[Transition to Sleep Mode]" and "[Transition to Stop Mode]".)

245CHAPTER 8 PPG Timer8.3.1 Control Status Register(PCNH,PCNL)

Changed the table in "Bits11 and 10 : CKS1 and CKS0 (Counter Clock Select)".(φ/2 (initial value) → φ (initial value))

310

CHAPTER 12 EXTERNAL INTERRUPT AND NMI CONTROLLER12.2.3 External Interrupt Request Level Setting Register (ELVR)

Added "Note:" in " External Interrupt Request Level Setting Register (ELVR)".

xv

311

CHAPTER 12 EXTERNAL INTERRUPT AND NMI CONTROLLER12.3 Operation of the External Interrupt and NMI controller

Changed " Operating Procedure for an External Interrupt".

338, 339CHAPTER 15 UART15.1 Overview of the UART

Added "15.1.1 Pairing of Send and Receive Transfers in UART Macro".

401

CHAPTER 17 DMA CONTROLLER (DMAC)17.2.1 Control/Status Regis-ters A (DMACA0-4)

Changed Table 17.2-1 in " Control/Status Registers A (DMACA0 to 4)".

435

CHAPTER 17 DMA CONTROLLER (DMAC)17.3.3 General Aspects of DMA Transfer

Deleted "17.3.12 Supplement on External Pin and Internal Operation Tim-ing".

455 CHAPTER 18 USB FUNCTION18.2.2 Status Registers

Changed Figure 18.2-10 and Table 18.2-3 in " ST3".

456 The sentence is changed to Note.

457Changed Figure 18.2-12 and Table 18.2-5 in " ST5".(The sentence is changed to Notes.)

460 CHAPTER 18 USB FUNC-TION18.2.3 Control Registers

Changed Figure 18.2-15 in " CONT1".

461Changed Table 18.2-8 in " CONT1".(The sentence is changed to Notes.)

464 Changed " CONT3".(The sentence is changed to Notes.)

470 Changed Figure 18.2-23 and Table 18.2-16 in " CONT9".

471 Changed Figure 18.2-24 and Table 18.2-17 in " CONT10".

472 The sentence is changed to Notes.

472Changed " TTSIZE".(The sentence is changed to Notes.)

473 Changed " TRSIZE".(The sentence is changed to Notes.)

474Changed the table of " Register Map". (Address: 0006_007E → 0006_FFFE )

732APPENDIX A Changed Table A-1.

(Address:000414H Deleted PFR4 Register.)

733Changed Table A-1.(Address:000485H Deleted the WPR Register.)


xvi

The vertical lines marked in the left side of the page show the changes.

742

APPENDIX A Changed Table A-2.(Address:00060070H - 0006007DH → 00060070H - 0006FFFBH, Address:0006007EH → 0006FFFCH, Address:00060080H - 0007FFFFH → 00070000H - 0007FFFFH, Address:0006FFFCH Added the USBIO register.)

744, 745APPENDIX B Changed Table B-1.

(Changed the RN of External interrupt 4 (USB-function), External interrupt 5 (USB-Host), PPG0, PPG1, and PPG2.)

752 APPENDIX F Changed " CS2 area".

753 Changed Figure F-1.


xvii

CHAPTER 1 OVERVIEW

This chapter provides basic information required to understand the MB91310 series, and covers features, a block diagram, and functions.

1.1 Features

1.2 Block Diagram

1.3 External Dimensions

1.4 Pin Layout

1.5 List of Pin Functions

1.6 Input-output Circuit Forms

1

CHAPTER 1 OVERVIEW

1.1 Features

The FR family is a single-chip microcontroller that has a 32-bit high-performance RISC CPU as well as built-in I/O resources for embedded controllers requiring high-performance and high-speed CPU processing.The FR family is most suitable for embedded applications, for example, TV and PDP control, that require a high level of CPU processing performance.This model is an FR60 family model that is based on the FR30 family of CPUs. It has enhanced bus access and is optimized for high-speed use.

FR CPU

• 32-bit RISC, load/store architecture, five stages pipeline

• Operating frequency of 40 MHz [PLL used, original oscillation at 10 MHz]

• 16-bit fixed-length instructions (basic instructions), one instruction per cycle

• Memory-to-memory transfer, bit processing, instructions, including barrel shift, etc.--instructions appropriate for embedded applications

• Function entry and exit instructions, multi load/store instructions--instructions compatible withhigh-level languages

• Register interlock function to facilitate assembly-language coding

• Built-in multiplier/instruction-level support

• Signed 32-bit multiplication: 5 cycles

• Signed 16-bit multiplication: 3 cycles

• Interrupts (saving of PC and PS): 6 cycles, 16 priority levels

• Harvard architecture enabling simultaneous execution of both program access and dataaccess

• 4-word queues in the CPU provided to add an instruction prefetch function

• Instructions compatible with the FR family

Bus Interface

This bus interface is used for macro connections (USB and OSDC).

• Maximum operating frequency of 20 MHz

• 16-bit data input-output (interface with USB and OSDC)

• Totally independent 8-area chip select outputs that can be defined in the minimum units of64K bytes The CS1, CS2, and CS3 areas are reserved as shown below. CS0 and CS4 to CS7 cannotbe used.

• CS1 area: USB host

• CS2 area: USB function

• CS3 area: OSDC

2

1.1 Features

• Basic bus cycle (2 cycles)

• Automatic wait cycle generator that can be programmed for each area and can insert waitsBecause CS1, CS2, and CS3 are reserved, the setting is fixed.

Built-in RAM

• 16 KB RAM

• This RAM can be used as data RAM and instruction RAM if instruction codes are written toit.

DMAC (DMA Controller)

• 5 channels (channels 0 and 1 are connected to the USB function.)

• 3 transfer sources (internal peripherals, software)

• Addressing mode with 32-bit full address specifications (increase, decrease, fixed)

• Transfer modes (demand transfer, burst transfer, step transfer, block transfer)

• Transfer data size that can be selected from 8, 16, and 32 bits

Bit Search Module (Used by REALOS)

Searches for the position of the first bit varying between 1 and 0 in the MSB of a word

Reload Timer (including One Channel for REALOS)

• 16-bit timer; 3 channels

• Internal clock that can be selected from those resulting from frequency divided by 2, 8, and32

UART

• Full-duplex double buffer

• 5 channels

• Parity or no parity can be selected.

• Either asynchronous (start-stop synchronization) or CLK synchronous communication can beselected.

• Built-in timer for dedicated baud rates

• An external clock can be used as the transfer clock.

• Plentiful error detection functions (parity, frame, overrun)

3

CHAPTER 1 OVERVIEW

I2C Interface

• 4 channels (channel 3 can be used for two ports.)

• Master/slave transmission and reception

• Clock synchronization function

• Transfer direction detection function

• Bus error detection function

• Supports standard mode (Max. 100 Kbps) and high-speed mode (Max, 400 Kbps).

• Arbitration function

• Slave address/general call address detection function

• Start condition repetitious occurrence and detection function

• 10-bit/7-bit slave address

Interrupt Controller

• Total of 5 external interrupts (one unmaskable pin (NMI) and four regular interrupt pins (INT3to INT0))

• Interrupts from internal peripherals

• Priority level can be defined as programmable (16 levels) except for the unmaskable pin

• Can be used for wake-up during stop.

A/D Converter

• 10-bit resolution, 10 channels

• Sequential comparison and conversion type (conversion time: about 10 µs)

• Conversion modes (single conversion mode and scan conversion mode)

• Causes of startup (software and external triggers)

PPG

• 4 channels

• 16-bit data register with 16-bit down counter and cycle setting buffer

• Internal clock: Frequency-divide-by number selectable from 1, 4, 16, and 64

PWC

• 1 channel (1 input)

• 16-bit up counter

• Simple LPF digital filter

Multifunction Timer

• Low-pass filter that removes noise that is below the frequency of the set clock

• Pulse width measurement that can be performed by precise settings using seven types ofclock signals

• Event count for signals from pin input

• Interval timer using seven types of clocks and external input clocks

4

1.1 Features

USB Host Function

• USB1.0

• 8 KB RAM for storing parameters

USB Function

• USB1.1 full-speed, double buffer

• CONTROL IN/OUT, BULK IN/OUT, and INTERRUPT IN

OSDC Function

• High-definition OSDC

• Analog RGB I/F (DAC)

• Digital RGB I/F

• PLL for dot clock generation

Other Interval Timers

• 16-bit timer: 3 channels (U-TIMER)

• Watchdog timer

I/O Ports

Maximum of 72 ports

Other Features

• Has a built-in oscillation circuit as a clock source.

• INIT is provided as a reset pin.

• Additionally, a watchdog timer reset and software resets are provided.

• Stop mode and sleep mode supported as low-power modes

• Gear function

• Built-in time-base timer

• Package: LQFP-144, 0.5 mm pitch, and 20 mm × 20 mm

• CMOS technology: 0.25 µm

• Supply voltage: two sources of 3.3 V (-0.3 V to +0.3 V) and 2.5 V (-0.2 V to +0.2 V)

5

CHAPTER 1 OVERVIEW

1.2 Block Diagram

Figure 1.2-1 is a block diagram of the MB91310.

Block Diagram

Figure 1.2-1 Block Diagram

OSDCFont ROMFLASH 512 KB*2

ROM 168 KB*2

32 to 16 adapter

USBfunction

USB host

Multifunction timer 4ch

Interruptcontroller

Clockcontrol

FR CPU Core

Flash 512KB

RAM 16KB

Bit search

Bus converter DMAC5ch

Reloadtimer 3ch

PWC1ch

PPG4ch

Port

I2C4ch

A/D10ch

UART5ch

U-TIMER5ch

32

32

Externalinterrupt

Externalmemory

I/F

DSU*1

*1 : DSU: MB91FV310A only*2 : Font ROM: MB91FV310A: FLASH 512 KB : MB91F312A : MASK ROM 168 KB

6



The MB91310 is available in one type of package.Figure 1.3-1 shows the dimensions of the MB91310.

Dimensions of the MB91310

Figure 1.3-1 External Dimensions of MB91310

Please confirm the latest Package dimension by following URL.

http://edevice.fujitsu.com/package/en-search/

144-pin plastic LQFP Lead pitch 0.50 mm

Package width ×package length

20.0 × 20.0 mm

Lead shape Gullwing

Sealing method Plastic mold

Mounting height 1.70 mm MAX

Weight 1.20g

Code(Reference)

P-LFQFP144-20×20-0.50

144-pin plastic LQFP(FPT-144P-M08)

(FPT-144P-M08)

C 2003 FUJITSU LIMITED F144019S-c-4-6

Details of "A" part

0.25(.010)

(Stand off)(.004±.004)0.10±0.10

(.024±.006)0.60±0.15

(.020±.008)0.50±0.20

1.50+0.20–0.10

+.008–.004.059

0˚~8˚

0.50(.020)

"A"

0.08(.003)

0.145±0.055(.006±.002)

LEAD No. 1 36

INDEX

37

72

73108

109

144

0.22±0.05(.009±.002)

M0.08(.003)

20.00±0.10(.787±.004)SQ

22.00±0.20(.866±.008)SQ

(Mounting height)

*

Dimensions in mm (inches).Note: The values in parentheses are reference values.©2003-2008 FUJITSU MICROELECTRONICS LIMITED F144019S-c-4-7

Note 1) *:Values do not include resin protrusion.Resin protrusion is +0.25(.010)Max(each side).

Note 2) Pins width and pins thickness include plating thickness.Note 3) Pins width do not include tie bar cutting remainder.

7

CHAPTER 1 OVERVIEW

1.4 Pin Layout

This section shows the pin layout of the MB91310.

Pin Layout of the MB91310

Figure 1.4-1 is a diagram of the pin layout of the MB91310.

Figure 1.4-1 Pin Layout of the MB91310

DC

KO

VO

B1

VO

B2

VD

DE

VD

DI

VS

SR

2R

1R

0G

2G

1G

0B

2B

1B

0U

HP

UH

MU

DP

UD

MV

DD

EV

DD

IX

1BV

SS

X0B

P74

P73

P72

P71

P70

ICD

3 *

ICD

2 *

ICD

1 *

ICD

0 *

ICS

2 *

ICS

1 *

ICS

0 *

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

DOCKIFH

VSYNCHSYNC

VGSCPOVSS

VDDI(PLL)VDDR(2.5V)VREF(1.1V)

ROUTVSSR

VDDG(2.5V)

GOUTVSSG

VDDB(2.5V)

BOUTVSSBAVCCAVRH

AVSS/AVRLAN0AN1AN2AN3AN4AN5AN6AN7AN8AN9

P00/SCL0

123456789101112131415161718192021222324252627282930313233343536

108107106105104103102101100999897969594939291908988878685848382818079787776757473

IBREAK *ICLK *TRST *VSSVDDIVDDENMIP65/INT3P64/INT2P63/INT1P62/INT0P61P60/ATRGP57/TRG3P56/TRG2P55/TRG1P54/TRG0P53/TMI3P52/TMI2P51/TMI1P50/TMI0MD3MD2MD1MD0P47/PPG3P46/PPG2P45/PPG1P44/PPG0X1AVSSX0AVDDIVDDEP43/TMO3P42/TMO2

37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72

P01/S

DA

0P

02/SC

L1P

03/SD

A1

VD

DE

VD

DI

X0

VS

SX

1IN

ITP

04/SC

L2P

05/SD

A2

P06/S

CL3

P07/S

CL4

P10/S

DA

3P

11/SD

A4

P12/S

I0P

13/SO

0P

14/SC

K0

P15/S

I1P

16/SO

1P

17/SC

K1

P20/S

I2P

21/SO

2P

22/SC

K2

P23/S

I3P

24/SO

3P

25/SC

K3

P30/S

I4/TIN

0P

31/SO

4/TIN

1P

32/SC

K4/T

IN2

P33/TO

0P

34/TO1

P35/TO

2P

36/RIN

P40/T

MO

0P

41/TM

O1

TOP VIEW

LQFP-144MB91FV310AMB91F312

*: Do not be connected anything to TRST, ICS2 to ICS0, ICD3 to ICD0, ICLK and IBREAK pins on MB91F312A.Because these pins are used as open pins on MB91FV310A.

8



This section describes the pin functions of the MB91310.

List of Pin Functions

Table 1.5-1 lists the pin functions.

Table 1.5-1 Pin Functions of the MB91310 (1 / 7)

Pin number

Pin nameI/O circuit

formFunction

1 DOCKI D Dot clock input

2 FH D Horizontal sync output

3 VSYNC D Vertical sync input

4 HSYNC D Horizontal sync input

5 VGS - Guard band ground

6 CPO K Charge pump output

7 VSS - Power supply for dot clock PLL

8 VDDI(PLL) - Dot clock PLL ground

9 VDDR(2.5V) - D/A power for R

10 VREF(1.1V) K Voltage reference input

11 VRO(2.7KΩ) K Resistor connection pin

12 RCOMP(0.1µF) K Capacitor connection pin

13 ROUT K R output (analog)

14 VSSR - D/A ground for R

15 VDDG(2.5V) - D/A power for G

16 GCOMP(0.1µF) K Capacitor connection pin

17 GOUT K G output (analog)

18 VSSG - D/A ground for G

19 VDDB(2.5V) - D/A power for B

20 BCOMP(0.1µF) K Capacitor connection pin

21 BOUT K B output (analog)

22 VSSB - D/A ground for B

23 AVCC - A/D power

24 AVRH - Reference power supply for A/D power

9

CHAPTER 1 OVERVIEW

25 AVSS - A/D ground

26 AN0 E Analog input










36 P00 C General-purpose port

SCL0 I2C clock pin


SDA0 I2C data pin


SCL1 I2C clock pin


SDA1 I2C data pin

40 VDDE - 3.3 V power supply

41 VDDI(PLL) - 2.5 V power supply

42 X0 A 10 MHz oscillator pin

43 VSS - Ground

44 X1 A 10 MHz oscillator pin

45 INIT B Initial (reset) pin


SCL2 I2C clock pin


SDA2 I2C data pin


Pin number

Pin nameI/O circuit

formFunction

10


48 P06 N General-purpose port

SCL3 I2C clock pin

49 P07 General-purpose port

SCL4 I2C clock pin

50 P10 N General-purpose port

SDA3 I2C data pin

51 P11 General-purpose port

SDA4 I2C data pin


SI0 UART0 serial input


SO0 UART0 serial output


SCK0 UART0 clock input-output


















Pin number

Pin nameI/O circuit

formFunction

11

CHAPTER 1 OVERVIEW





TIN0 Reload timer 0 trigger input








TO0 Reload timer 0 output






RIN PWC input


TMO0 Multifunction timer 0 output








76 VDDI - 2.5 V power supply

77 X0A A 32 kHz oscillator pin

78 VSS - Ground


Pin number

Pin nameI/O circuit

formFunction

12


79 X1A A 32 kHz oscillator pin


PPG0 PPG0 output


PPG1 PPG1 output


PPG2 PPG2 output


PPG3 PPG3 output

84 MD0 F Mode pin

85 MD1 F Mode pin

86 MD2 F Mode pin

87 MD3 F Mode pin (ground)


TMI0 Multifunction timer 0 input








TRG0 PPG0 trigger input








ATRG A/D conversion trigger input


Pin number

Pin nameI/O circuit

formFunction

13

CHAPTER 1 OVERVIEW


98 P62 J General-purpose port

INT0 External interrupt input 0







102 NMI G NMI input



105 VSS - Ground

106 TRST B DSU tool reset (Do not connect the open pin with other in MB91F312A)

107 ICLK C DSU clock (Do not connect the open pin with other in MB91F312A)

108 IBREAK L DSU break (Do not connect the open pin with other in MB91F312A)

109 ICS0 M DSU status (Do not connect the open pin with other in MB91F312A)



112 ICD0 H DSU data (Do not connect the open pin with other in MB91F312A)




116 P70 I General-purpose port





121 X0B A 48 MHz oscillator pin

122 VSS - Ground

123 X1B A 48 MHz oscillator pin


Pin number

Pin nameI/O circuit

formFunction

14




126 UDM USB USB-Function

127 UDP USB-Function

128 UHM USB USB-Host

129 UHP USB-Host

130 B0 D RGB digital output



133 G0 D RGB digital output



136 R0 D RGB digital output



139 VSS - Ground



142 VOB2 D Translucent color period output

143 VOB1 D OSD display period output

144 DCKO D Dot clock output


Pin number

Pin nameI/O circuit

formFunction

15

CHAPTER 1 OVERVIEW


This section describes the input-output circuit types of the MB91310.

Input-Output Circuit Types

Table 1.6-1 lists the input-output circuit types of the MB91310.

Table 1.6-1 Input-Output Circuit Types of the MB91310 (1 / 5)

Classification Circuit type Remarks

A

• Oscillation feedback

B

• CMOS hysteresis input with pull-up resistors

C

• CMOS level outputCMOS level hysteresis input with standby control

Clock input

Standby control

X0

X1

Digital input

Digital output

Digital output

Digital input

Standby control

16


D

• 2.5 V CMOS level outputCMOS level hysteresis input with standby control

E

• Analog input with switches

F

• CMOS level input without standby control

G

• CMOS level hysteresis input without standby control



Digital input

Digital output

Digital output

2.5V

Standby control

Control

Analog input

Digital input

Digital input

17

CHAPTER 1 OVERVIEW

H

• CMOS level outputHysteresis input with standby control and pull-down resistor

I

• CMOS level outputHysteresis input with standby control and pull-up resistor

J

• CMOS level outputCMOS level hysteresis input without standby control



Digital output

Digital output

Digital input

Standby control

Digital output

Digital output

Digital input

Standby control

Digital output

Digital input

Digital output

18


K

• Analog pin

L

• CMOS hysteresis input with pull-down resistor

M

• CMOS level output



Digital input

Open drain control

Digital output

19

CHAPTER 1 OVERVIEW

N

• Two I2C portsCMOS hysteresis inputCMOS output with stop control



Digital input

Digital output

Open drain control

Digital input

Digital output

Open drain control

Control

20


This chapter provides precautions on handling the MB91310 series.

2.1 Precautions on Handling the Device

21



This section contains information on preventing a latch up and on the handling of pins.

Preventing a Latch up

A latch up can occur if, on a CMOS IC, a voltage higher than VDD or a voltage lower than VSS isapplied to an input or output pin or a voltage higher than the rating is applied between VDD andVSS. A latch up, if it occurs, significantly increases the power supply current and may causethermal destruction of an element. When you use a CMOS IC, be very careful not to exceed themaximum rating.

Unused Input Pins

Do not leave an unused input pin open, since it may cause a malfunction. Handle by, forexample, using a pull-up or pull-down resistor.

Power Supply Pins

If more than one VDD or VSS pin exists, those that must be kept at the same potential aredesigned to be connected to one other inside the device to prevent malfunctions such as latchup. Be sure to connect the pins to a power supply and ground external to the device to minimizeundesired electromagnetic radiation, prevent strobe signal malfunctions due to an increase inground level, and conform to the total output current rating. Given consideration to connectingthe current supply source to VDD and VSS of the device at the lowest impedance possible.

It is also recommended that a ceramic capacitor of around 0.1 µF be connected between VDDand VSS at circuit points close to the device as a bypass capacitor.

Quartz Oscillation Circuit

Noise near the X0 or X1 pin may cause the device to malfunction. Design printed circuit boardsso that X0, X1, the quartz oscillator (or ceramic oscillator), and the bypass capacitor to groundare located as near to one another as possible.

It is strongly recommended that printed circuit board artwork that surrounds the X0 and X1 pinswith ground be used to increase the expectation of stable operation.

Mode Pins (MD0 to MD3)

These pins must be directly connected to VDD or VSS when they are used. Keep the patternlength between a mode pin on a printed circuit board and VDD or VSS as short as possible sothat they can be connected at a low impedance.

Tool Reset Pins (TRST)

Be sure to input the same signal as the INIT, when this pin is not used the tool. The sameprocessing is executed for the product.

22


Power-on

Immediately after power-on, be sure to apply a reset with the INIT pin to initialize the settings(INIT).

Also immediately after power-on, keep the INIT pin at the L level until the oscillator has reachedthe required frequency stability. (For initialization by INIT from the INIT pin, the oscillationstabilization wait time is set to the minimum value.)

Source Oscillation Input at Power-on

At power-on, be sure to input a source clock until the oscillation stabilization wait time isreached.

Precautions at Power-On/Power-Off

Precautions when turning on and off VDDI (internal 2.5 V power supply) and VDDE (external 3.3 V power supply)

To ensure the reliability of LSI devices, do not continuously apply only VDDE (external) whenVDDI (internal) is off.

When VDDE (external) is changed from off to on, the power noise may make it impossible toretain the internal state of the circuit.

• Power-on: VDDI (internal) --> VDDE (external) --> analog -->signal

• Power-off: Signal--> analog --> VDDE (external) --> VDDI (internal)

Synchronous Mode Software Reset

When using the synchronous wode software reset, the following two conditions must besatisfied before setting the SRST bit in the STCR (standby control register) to "0".

• Set interrupt enable flag (I-Flag) to interrupts clisabled (I-Flag=0)

• NMI not used

Limitations

Clock controller

INIT must be kept at the L level until the oscillation stabilization wait time is reached.

Bit search module

Only word access is permitted for registers BSD0, BSD1, and BDSC.

I/O port

Only byte access is permitted for ports.

23

Changed " Precautions at Power-On/Power-Off". Added " Synchronous Mode Software Reset".


Low-power Modes

To place the device in standby mode, use the synchronous standby mode (set with bit8: SYNCSbit of the time-base counter control register (TBCR)) and be sure to use the following sequence:

/* Writing STCR */

ldi #_STCR, R0 ; STCR register (0481H)

ldi #Val_of_Stby, rl ; Val_of_Stby is the write data to STCR.

stb rl,@r0 ; Writing to STCR

/* Writing CTBR */

ldi #_CTBR, r2 ; CTBR register (0483H)

ldi #0xA5, rl ; Clear command (1)

stb rl,@r2 ; Writing A5 to CTBR



/* Clearing the time-base counter in here */

ldub @r0, rl ; Reading STCR

/* Starting synchronous standby transition */

ldub @r0, rl ; Reading dummy STCR

nop ; NOP × 5 for timing adjustment

nop

nop

nop

nop

24

Added " Low-power Modes".


This chapter provides basic information required to understand the functions of the MB91310. It covers architecture, specifications, and instructions.

3.1 Memory Space

3.2 Internal Architecture

3.3 Programming Model

3.4 Data Configuration

3.5 Word Alignment

3.6 Memory Map

3.7 Branch Instructions

3.8 EIT (Exception, Interrupt, and Trap)

3.9 Operating Modes

3.10 Reset (Device Initialization)

3.11 Clock Generation Control

3.12 Device State Control

3.13 Watch Timer

3.14 Main Clock Oscillation Stabilization Wait Timer

25


3.1 Memory Space

The MB91310 has a logical address space of 4 GB (232 addresses), which the CPU accesses linearly.

Memory Space

The MB91310 has a logical address space of 4GB (232 addresses), while the CPU accesslineally.

Direct addressing area

The areas in the address space listed below are used for input-output.

These areas called the direct addressing area. The address of an operand can be directlyspecified in an instruction.

The size of the direct addressing area varies according to the size of data to be accessed:

• Byte data access : 0 to 0FFH

• Half word data access : 0 to 1FFH

• Word data access : 0 to 3FFH

Memory Map

Figure 3.1-1 shows the memory space of this product.

Figure 3.1-1 Memory Map

MB91FV310A

I/O

I/O

FlashROM1512KB

FlashROM2512KB

USB-HOST(RAM)USB-FUNC

USB-HOST(REG)

OSDC

Program

Font

Direct addressing

area

See the I/O map.

Accessprohibited

Built-in RAM

Externalarea

0000 0000H

0000 0400H

0001 0000H

0003 C000H

0004 0000H0005 0000H

0005 8000H

0006 0000H

0007 0000H0007 8000H

0008 0000H

0010 0000H

0018 0000H

0020 0000H

FFFF FFFFH

MB91F312A

I/O

I/O

FlashROM1512KB

MASKROM2168KB

USB-HOST(RAM)USB-FUNC

USB-HOST(REG)

OSDC

Accessprohibited

Built-in RAM

Externalarea

Access prohibited Access prohibited

26



The FR family CPU is a high-performance core that is designed based on a RISC architecture with high-level function instructions for embedded applications.

Features

RISC architecture used

Basic instruction: One instruction per cycle

32-bit architecture

General-purpose register: 32 bits × 16

4 GB linear memory space

Multiplier installed

• 32-bit by 32-bit multiplication: 5 cycles

• 16-bit by 16-bit multiplication: 3 cycles

Enhanced interrupt processing function

• Quick response speed: 6 cycles

• Support of multiple interrupts

• Level mask function: 16 levels

Enhanced instructions for I/O operations

• Memory-to-memory transfer instruction

• Bit-processing instructions

Efficient code

Basic instruction word length: 16 bits

Low-power consumption

Sleep and stop modes

Gear function

27


Internal Architecture

The FR CPU uses the Harvard architecture, in which the instruction bus and data buses areindependent of each other.

A 32-bit <----> 16-bit bus converter is connected to the 32-bit bus (F-bus) to provide an interfacebetween the CPU and peripheral resources. A Harvard <----> Princeton bus converter isconnected to the I-bus and D-bus to provide an interface between the CPU and the buscontroller.

Figure 3.2-1 shows connections in the internal architecture.

28


Figure 3.2-1 Internal Architecture

32

32

32

32

32

32

16

24

16

FR CPU

D BUS I BUS

32 bit

16 bit

Princeton bus

converter

Harvard

F-bus

Bus converter

Peripheral resources Bus controllersInternal I/O

R-bus

I address

Address

Data

I data

External address

External data

29


CPU

The CPU is a compact implementation of the 32-bit RISC FR architecture.

Five instruction pipe lines are used to execute one instruction per cycle. A pipeline consists ofthe following stages:

• Instruction fetch (IF): Outputs an instruction address to fetch an instruction.

• Instruction decode (ID): Decodes a fetched instruction. Also reads a register.

• Execution (EX): Executes an arithmetic operation.

• Memory access (MA): Performs a load or store access to memory.

• Write-back (WB): Writes an operation result (or loaded memory data) to a register.

Figure 3.2-2 Instruction Pipelines

Instructions are never executed randomly. If Instruction A enters a pipeline before Instruction B,it always reaches the write-back stage before Instruction B.

In general, one instruction is executed per cycle. However, multiple cycles are required toexecute a load/store instruction with a memory wait, a branch instruction without a delay slot, ora multiple-cycle instruction. The execution of instructions slows down if the instructions are notsupplied fast enough.

32-bit/16-bit bus converter

The 32-bit/16-bit bus converter provides an interface between the F-BUS accessed with 32-bitwidth and the R-BUS accessed with 16-bit width and enables data access from the CPU to built-in peripheral circuits.

If the CPU performs a 32-bit width access to the R bus, this bus converter converts the accessinto two 16-bit width accesses. Some of the built-in peripheral circuits have limitations on theaccess bus width.

Instruction 1

Instruction 2

Instruction 3

Instruction 4

Instruction 5

Instruction 6

CLK

WBIF ID EX MA

IF ID EX MA WB

ID EX MA WB

EX MA WB

MA WB

WB

30


Harvard/Princeton bus converter

The Harvard/Princeton bus converter coordinates instruction and data accesses of the CPU toprovide a smooth interface between it and external buses.

The CPU has a Harvard architecture with separate buses for instructions and data. On the otherhand, the bus controller that performs control of external buses has a Princeton architecturewith a single bus. The Harvard/Princeton bus converter assigns priorities to instruction and dataaccesses from the CPU to control accesses to the bus controller. This function allows the orderof external bus accesses to be permanently optimized.

Overview of Instructions

The FR supports the general RISC instruction set as well as logical operation, bit manipulation,and direct addressing instructions optimized for embedded applications. For the instruction set,see the "APPENDIX H INSTRUCTION LISTS". Each instruction is 16-bit length (except forsome instructions are 32- or 48-bit length), resulting in superior efficiency of memory use.

An instruction set is classified into the following function groups:

• Arithmetic operation

• Load and store

• Branch

• Logical operation and bit manipulation

• Direct addressing

• Other

Arithmetic operation

Arithmetic operation instructions include standard arithmetic operation instructions (addition,subtraction, and comparison) and shift instructions (logical shift and arithmetic shift). Theaddition and subtraction instructions include an operation with carries for use with multiple-word-length operations and an operation that does not change flag values, a convenience in addresscalculations.

Furthermore, 32-bit-by-32-bit and 16-bit-by-16-bit multiplication instructions and a 32-bit-by-32-bit step division instruction are provided.

Additionally, an immediate data transfer instruction that sets immediate data in a register and aregister-to-register transfer instruction are provided.

An arithmetic operation instruction is executed using the general-purpose registers and themultiplication and division registers in the CPU.

Load and store

Load and store instructions read and write to external memory. They are also used to read andwrite to a peripheral circuit (I/O) on the chip.

Load and store instructions have three access lengths: byte, halfword, and word. In addition toindirect memory addressing via general registers, indirect memory addressing via registers withdisplacements and via registers with register incrementing or decrementing are provided forsome instructions.

Branch

The branch group includes branch, call, interrupt, and return instructions. Some branchinstructions have delay slots while others do not. These may be optimized according to theapplication. The branch instructions are described in detail later.

31


Logical operation and bit manipulation

Logical operation instructions perform the AND, OR, and EOR logical operations betweengeneral-purpose registers or a general-purpose register and memory (and I/O). Bit manipulationinstructions directly manipulate the contents of memory (and I/O). They access memory usinggeneral register indirect addressing.

Direct addressing

Direct addressing instructions are used for access between an I/O and a general-purposeregister or between an I/O and the memory. High-speed and high-efficiency access can beachieved since an I/O address is directly specified in an instruction instead of using registerindirect addressing. Indirect memory addressing via registers with register incrementing ordecrementing are provided for some instructions.

Other types of instructions

Other types of instructions include instructions that provide flag setting, stack manipulation, sign/zero extension, and other functions in the PS register. Also, function entry and exit instructionsthat support high-level languages and register multi-load/store instructions are provided.

32



This section explains the programming model in detail.

Basic Programming Model

Figure 3.3-1 Basic Programming Model

32 bits

[Initial value]

R0

XXXX XXXX H

R1

General-purpose register

R12

R13 A C

R14 F P

XXXX XXXX H

R15 S P

0000 0000 H

Program counter PC

Program status PS ILM SCR CCR

Table base register TBR

Return pointer RP

System stack pointer SSP

User stack pointer USP

Multiply and divide registers MDH MDL

33


Registers

General-purpose registers

Figure 3.3-2 General-Purpose Registers

Registers R0 to R15 are general-purpose registers. They are used as the accumulator forvarious operations and pointers for memory access.

Of these 16 registers, the following registers are intended for special applications and thereforeenhanced instructions are provided for them:

R13: Virtual accumulator

R14: Frame pointer

R15: Stack pointer

The initial value after reset is not defined for R0 though R14 and is 00000000H (SSP value) forR15.

Program status (PS)

The program status (PS) register holds the program status and consists of three parts: ILM,SCR, and CCR.

In the figure, all the undefined bits are reserved. During reading, "0" is always read.

This register cannot be written.

[Initial value]

R0 XXXX XXXX H

R1

R12

R13 A C

R14 F P XXXX XXXX H

R15 S P 0000 0000 H

32 bits

bit 31 20 16 10 8 7 0

ILM SCR CCR

34


Condition code register (CCR)

[bit5] Stack flag

Specifies the stack pointer to be used as R15.

Reset clears this bit to "0".

Set this bit to "0" when executing a RETI instruction.

[bit4] Interrupt enable flag

Enable or disable a user interrupt request.


[bit3] Negative flag

Indicate the sign when the operation result is regarded as an integer represented by its 2'scomplement.

The initial value after reset is undefined.

[bit2] Zero flag

Indicate whether the operation result is "0".


bit 7 6 5 4 3 2 1 0

- - S I N Z V C --00XXXX B

[Initial value]

Value Description

0 The system stack pointer (SSP) is used as R15.When an EIT occurs, this bit is automatically set to "0".(Note that the value saved on the stack is the value before it is cleared.)

1 The user stack pointer (USP) is used as R15.

Value Description

0 User interrupt disabled.When the INT instruction is executed, this bit is cleared to "0".(Note that the value saved on the stack is the value before it is cleared.)

1 User interrupt enabled.The mask processing of a user interrupt request is controlled by the value held in ILM.

Value Description

0 Indicates that the operation result is a positive value.

1 Indicates that the operation result is a negative value.

Value Description

0 Indicates that the operation result is not "0".

1 Indicates that the operation result is "0".

35


[bit1] Overflow flag

Indicate whether an overflow has occurred as a result of the operation when the operand isregarded as an integer represented by its 2's complement.


[bit0] Carry flag

Indicate whether a carry or a borrow has occurred from the most significant bit in theoperation.


System condition code register (SCR)

[bit10, bit9] Step division flag

Hold the intermediate data when step division is executed.

Do not change these bits during step division.

To execute other processing during a step division, save and restore the value of the PSregister to ensure that the step division is restarted.


When the DIV0S instruction is executed, the multiplicand and divisor are accessed and thisflag is set.

When the DIV0U instruction is executed, this flag is cleared.

[bit8] Step trace trap flag

This bit specifies whether the step trace trap is to be enabled.


The step trace trap function is also used by emulators. When being used by an emulator, thisfunction cannot be used in a user program.

Value Description

0 Indicates that the operation did not cause an overflow.

1 Indicates that the operation caused an overflow.

Value Description

0 Indicates that no carry or borrow has occurred.

1 Indicates that a carry or borrow has occurred.

bit 10 9 8 [Initial value]

D1 D0 T XX0B

Value Description

0 The step trace trap is disabled.

1 The step trace trap is enabled.All user NMIs and user interrupts are prohibited.

36


ILM

The interrupt level mask (ILM) register holds an interrupt level mask value. The value held inILM is used as a level mask.

An interrupt request to the CPU is accepted only when its interrupt level is higher than the levelindicated in this ILM.

The highest level is 0 (00000B), and the lowest level is 31 (11111B).

The program setting range is limited.

• When the original value is between 16 and 31:A new value between 16 and 31 can be set. If an instruction that sets a value between 0 and15 is executed, the specified value plus 16 is transferred.

• When the original value is between 0 and 15:Any value between 0 and 31 can be set.

Reset initializes this bit to 15 (01111B).

Program counter (PC)

[bit31 to bit0]

These are the bits of the program counter that indicates the address of the instruction beingexecuted.

Bit0 is set to "0" when the PC is updated after an instruction is executed. Bit0 can become"1" only if the branch address is an odd number address.

However, even if the branch address is an odd number address, bit0 is invalid and thereforethe instruction should be placed at an even number address.


Table base register (TBR)

The table base register holds the first address of the vector table to be used during EITprocessing.

The initial value after reset is 000FFC00H.

bit 20 19 18 17 16 [Initial value]

ILM4 ILM3 ILM2 ILM1 ILM0 01111B

PC XXXXXXXXH

bit 31 0 [Initial value]

TBR 000FFC00H


37


Return pointer (RP)

The return pointer holds the address returned from a subroutine.

When a CALL instruction is executed, the PC value is transferred to this RP.

When a RET instruction is executed, the RP contents are transferred to PC.


System stack pointer (SSP)

SSP is the system stack pointer.

SSP functions as R15 when the S flag is "0".

SSP can also be specified explicitly.

This register is also used as a stack pointer that specifies the stack on which the PS and PCcontents are to be saved if an EIT occurs.

The initial value after reset is 00000000H.

User stack pointer (USP)

USP is the user stack pointer

USP functions as R15 when the S flag is "1".

USP can also be specified explicitly.


This register cannot be used by the RETI instruction.

Multiply and divide register

The multiply and divide registers are 32-bit length.


When multiplication is executed

For a 32-bit-by-32-bit multiplication, the 64-bit length operation result is stored in the multiplyand divide registers as follows:

MDH: High-order 32 bits

MDL: Low-order 32 bitsFor a 16-bit-by-16-bit multiplication, the result is stored as follows:

RP XXXXXXXXH


SSP 00000000H


USP XXXXXXXXH


MDHMDL

bit 31 0

38


MDH: Undefined

MDL: 32-bit result

When division is executed

At the start of calculation, the dividend is stored in MDL.

If a DIV0S/DIV0U, DIV1, DIV2, DIV3, or DIV4S instruction is executed for a division, theresult is stored in MDL and MDH as follows:

MDH: Remainder

MDL: Quotient

39


3.4 Data Configuration

The MB91310 uses the following two data ordering methods:• Bit ordering• Byte ordering

Bit Ordering

Use the little endian method for bit ordering.

Byte Ordering

Use the big endian method for byte ordering.

bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LSBMSB

MSB LSBMemory bit 31 23 15 7 0

bit7 0

10101010 11001100 11111111 00010001

10101010Address n

Address (n+1)

Address (n+2)

Address (n+3)

11001100

11111111

00010001

40

3.5 Word Alignment

3.5 Word Alignment

Since instructions and data are accessed in byte units, the addresses at which they are placed depend on the instruction length or the data width.

Program Access

A program must be placed at an address that is a multiple of 2.

Bit0 of the PC is set to "0" if the PC is updated when an instruction is executed.

Bit0 can be set to "1" only if an odd-number address is specified as the branch address.

If bit0 is set to "1", however, bit0 is invalid and an instruction must be placed at the address thatis a multiple of 2.

No odd-number address exception exists.

Data Access

If data is accessed, forced alignment is applied to the address based on the width.

Word access: An address must be a multiple of 4. (The lowest-order 2 bits are forcibly set to 00.)

Halfword access: An address must be a multiple of 2. (The lowest-order bit is forcibly set to 0.)

Byte access: -

During word or halfword data access, some of the bits in the result of calculating an effectiveaddress are forcibly set to 0. For example, in @(R13, Ri) addressing mode, the register beforeaddition is used without change in the calculation (even if the lowest-order bit is 1) and the low-order bits are masked. A register before calculation is not masked.

[Example] LD @(R13, R2), R0

R13 00002222H

R2 00000003H

Addition result 00002225H

Lower 2 bits forcibly masked

Address pin 00002224H

+)

41


3.6 Memory Map

This section shows the memory map for the MB91310.

Memory Map

The address space is 32 bits linear.

Figure 3.6-1 Memory Map

Direct addressing area

The following areas in the address space are the areas for I/O. When direct addressing is usedin these areas, an operand address can be directly specified in an instruction.

The size of an address area for which an address can be directly specified varies is determinedby the data length as follows:

• Byte data (8 bits): 0 to 0FFH

• Halfword data (16 bits): 0 to 1FFH

• Word data (32 bits): 0 to 3FFH

Vector table initial area

The area from 000FFC00H to 000FFFFFH is the initial EIT vector table area.

You can place the vector table that will be used during EIT processing at any address byrewriting the TBR. Initialization by a reset places the table at this address.

0000 0000H

0000 0100H

0000 0200H

0000 0400H

000F FC00H

000F FFFFH

Byte data

Direct addressing areaHalfword data

Word data

Vector table initial area

FFFF FFFFH

42



An operation with or without a delay slot can be specified for a branch instruction used in the MB91310.

Branch Instruction with Delay Slot

Instructions written as follows perform a branch operation with a delay slot:

Operation Explanation

In operation with a delay slot, the instruction located just after a branch instruction (placed in a“delay slot”) is executed before the instruction that branches is executed.

Since an instruction in the delay slot is executed before the branch operation, the apparentexecution speed is one cycle. However, a NOP instruction must be placed in the delay slot ifthere is no valid instruction put there.

[Example]

If a conditional branch instruction is used, an instruction placed in the delay slot is executedwhether or not the condition for branching is met.

If a delay branch instruction is used, the order of execution for some instructions seems to bereversed. However, this occurs only for updating the PC and the instructions are executed in thespecified order for other operations (register update and reference, etc.)

The following is a concrete example.

Ri referenced by the JMP:D @Ri / CALL:D @Ri instruction is not affected even though Ri isupdated by the instruction in the delay slot.

JMP:D @Ri CALL:D label12 CALL:D @Ri RET:D

BRA:D label9 BNO:D label9 BEQ:D label9 BNE:D label9

BC:D label9 BNC:D label9 BN:D label9 BP:D label9

BV:D label9 BNV:D label9 BLT:D label9 BGE:D label9

BLE:D label9 BGT:D label9 BLS:D label9 BHI:D label9

; List of instructions

ADD R1, R2 ;

BRA:D LABEL ; Branch instruction

MOV R2, R3 ; Delay slot ... Executed before branch

...

LABEL: ST R3, @R4 ; Branch destination

43


[Example]

RP referenced by the RET:D instruction is not affected even though RP is updated by theinstruction in the delay slot.

[Example]

The flag referenced by the Bcc:D rel instruction is not affected by the instruction in the delayslot.

[Example]

If RP is referenced by an instruction in the delay slot of the CALL:D instruction, the data that hasbeen updated by the CALL:D instruction is read.

[Example]

Instructions that can be placed in the delay slot

Only an instruction meeting the following conditions can be executed in the delay slot.

• One-cycle instruction

LDI:32 #Label, R0

JMP:D @R0 ; Branch to Label

LDI:8 #0, R0 ; No effect on the branch destination address

...

RET:D ; Branch to address defined beforehand in RP

MOV R8, RP ; No effect on the return operation

...

ADD #1, R0 ; Flag change

BC:D Overflow ; Branch to execution result of above instruction

ANDCCR #0 ; This flag update is not referenced by the above branch instruction.

...

CALL:D Label ; Updating RP and branching

MOV RP, R0 ; Transferring RP, execution result of above CALL:D

...

44


• Instruction other than a branch instruction

• Instruction whose operation is not affected even though the order is changed

A one-cycle instruction is an instruction denoted in the Number of Cycles column in the list ofinstructions as 1, a, b, c, and d.

Step trace trap

A step trace trap does not occur between the execution of a branch instruction with a delay slotand the delay slot.

Interrupt/NMI

An interrupt/NMI is not accepted between the execution of a branch instruction with a delay slotand the delay slot.

Undefined instruction exception

An undefined instruction exception does not occur if there is an undefined instruction in thedelay slot. If an undefined instruction is in the delay slot, it operates as a NOP instruction.

Branch Instruction without Delay Slot

Instructions written as follows perform a branch operation without a delay slot:

Operation Explanation

In operation without a delay slot, instructions are executed in the order in which they arespecified. An instruction immediately following a branch is never executed before it.

[Example]

A branch instruction without a delay slot is executed in two cycles if a branch occurs and in onecycle if no branch occurs.

Since no appropriate instruction can be placed in the delay slot, this instruction results in a moreefficient instruction code than a branch instruction with a delay slot and with NOP specified.

JMP @Ri CALL label12 CALL @Ri RET

BRA label9 BNO label9 BEQ label9 BNE label9

BC label9 BNC label9 BN label9 BP label9

BV label9 BNV label9 BLT label9 BGE label9

BLE label9 BGT label9 BLS label9 BHI label9

; List of instructions

ADD R1, R2 ;

BRA LABEL ; Branch instruction (without a delay slot)

MOV R2, R3 ; Not executed

...

LABEL: ST R3, @R4 ; Branch destination

45


For both optimal execution speed and code efficiency, select an operation with a delay slot if avalid instruction can be placed in the delay slot; otherwise, select an operation without a delayslot.

46



EIT, a generic term for exception, interrupt, and trap, refers to suspending program execution if an event occurs during execution and then executing another program.

EIT (Exception, Interrupt, and Trap)

An exception is an event that occurs related to the execution context. Execution restarts fromthe instruction that caused the exception.

An interrupt is an event that occurs independently of execution context. The event is caused byhardware.

A trap is an event that occurs related to the execution context. Some traps, such as systemcalls, are specified in a program. Execution restarts from the instruction following the one thatcaused the trap.

Features

EIT for the MB91310 has the following features:

• Multi-interrupt support

• Level masking function (15 levels available to the user)

• Trap instruction (INT)

• Emulator activation EIT (hardware/software)

EIT Causes

The following are causes of EIT:

• Reset

• User interrupt (internal resource, external interrupt)

• NMI

• Delayed interrupt

• Undefined instruction exception

• Trap instruction (INT)

• Trap instruction (INTE)

• Step trace trap

• No-coprocessor trap

• Coprocessor error trap

Return from EIT

• RETI instruction.

47


3.8.1 EIT Interrupt Levels

The interrupt levels are 0 to 31 and are managed with five bits.

Interrupt Levels

Table 3.8-1 shows the allocation of the levels.

Operation is possible for levels 16 to 31.

The interrupt level does not affect an undefined instruction exception, no-coprocessor trap,coprocessor error trap, or an INT instruction. It does not change the ILM, either.

I Flag

A flag that specifies whether an interrupt is permitted or prohibited. This flag is provided as bit4of the PS register.

Table 3.8-1 EIT Interrupt Levels

LevelInterrupt Factor Notes

Binary Decimal

00000......

00011

00100

00101......

01110

0......3

4

5......14

(Reserved for system)......(Reserved for system)

(Reserved for system)......(Reserved for system)

If the original ILM value is between 16 and 31, a program cannot set a value in this ILM range.

01111 15 NMI (for user)

1000010001

...

...1111011111

1617......3031

InterruptInterrupt......Interrupt-

User interrupts prohibited if ILM is set

Interrupts prohibited if ICR is set

INTE instructionStep trace trap

Value Description

0Interrupts prohibitedCleared to "0" if the INT instruction is executed.(Note that a value saved on the stack is the value before it is cleared.)

1Interrupts permittedThe mask processing of an interrupt request is controlled by the value in the ILM register.

48


Interrupt Level Mask (ILM) Register

A PS register (Bits 20 to 16) that holds an interrupt level mask value.

The CPU accepts only an interrupt request sent to it with an interrupt level higher than the levelindicated by the ILM.

The highest level is 0 (00000B) and the lowest level is 31 (11111B).

Values that can be set by a program have a limit. If the original value is between 16 and 31, thenew value must be between 16 and 31. If an instruction that sets a value between 0 and 15 isexecuted, the specified value plus 16 is transferred.

If the original value is between 0 and 15, any value between 0 and 31 may be set.

Note:

Use the STILM instruction to set this register.

Level Mask for Interrupt and NMI

If an NMI or interrupt request occurs, the interrupt level (Table 3.8-1 ) of the interrupt source iscompared with the level mask value held in the ILM. A request meeting the following condition ismasked and is not accepted:

Interrupt level of cause ≥ Level mask value

49


3.8.2 Interrupt Control Register (ICR)

The interrupt control register (ICR: Interrupt Control Register), located in the interrupt controller, sets the level of an interrupt request. An ICR is provided for each of the interrupt request inputs. The ICR is mapped on the I/O space and is accessed from the CPU through a bus.

Configuration of Interrupt Control Register (ICR)

[bit4] ICR4

ICR4 is always set to "1".

[bit3 to bit0] ICR3 to ICR0

These bits are the low-order 4 bits of the interrupt level of the corresponding interrupt source.They can be read and written to.

Together with bit4, a value between 16 and 31 can be set in the ICR.

Mapping of Interrupt Control Register (ICR)

bit 7 6 5 4 3 2 1 0

R R/W R/W R/W R/W

- - - ICR4 ICR3 ICR2 ICR1 ICR0 Initial value ---11111B

Table 3.8-2 Interrupt Sources, Interrupt Control Registers, and Interrupt Vectors

Interrupt source

Interrupt control register

Corresponding interrupt vector

NumberAddress

Hexadecimal Decimal

IRQ00 ICR00 00000440H 10H 16 TBR + 3BCH

IRQ01 ICR01 00000441H 11H 17 TBR + 3B8H

IRQ02 ICR02 00000442H 12H 18 TBR + 3B4H

...

.........

...

.........

...

.........

IRQ45 ICR45 0000046DH 3DH 61 TBR + 308H

IRQ46 ICR46 0000046EH 3EH 62 TBR + 304H

IRQ47 ICR47 0000046FH 3FH 63 TBR + 300H

TBR initial value : 000F FC00H

Note: See “CHAPTER 11 INTERRUPT CONTROLLERS”.

50


3.8.3 System Stack Pointer (SSP)

The system stack pointer (SSP) is used to point to the stack to save and restore data when EIT is accepted or a return operation occurs.

System Stack Pointer (SSP)

Eight is subtracted from the register value during EIT processing and eight is added to theregister value during the return operation from EIT that occurs when the RETI instruction isexecuted.

The system stack pointer (SSP) is initialized to 00000000H by a reset.

The SSP is also used as general-purpose register R15 if the S flag in the CCR is set to "0".

Interrupt Stack

The value in the PC or PS is saved to or restored from the area indicated by SSP. After aninterrupt occurs, the PC contents are stored at the address indicated by SSP and the PScontents are stored at the address indicated by SSP plus 4.

Figure 3.8-1 Interrupt Stack

SSP 00000000H


[Example] [Before interrupt] [After interrupt]

SSP 80000000H SSP 7FFFFFF8H

Memory

80000000H 80000000H

7FFFFFFCH 7FFFFFFCH PS7FFFFFF8H 7FFFFFF8H PC

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3.8.4 Table Base Register (TBR)

Indicate the beginning address of the vector table for EIT.

Table Base Register (TBR)

The table base register (TBR) consists of 32 bits as shown below:

Obtain a vector address by adding to the TBR the offset value predetermined for an EIT cause.

The table base register (TBR) is initialized to 000FFC00H by a reset.

EIT Vector Table

A 1 KB area from the address indicated in the table base register (TBR) is the vector area forEIT.

The size for each vector is 4 bytes. The relationship between a vector number and a vectoraddress can be expressed as follows:

vctadr = TBR + vctofs

= TBR + (3FCH - 4 × vct)

vctadr: Vector address

vctofs: Vector offset

vct: Vector number

The low-order two bits of the addition result are always handled as "00".

The area from 000FFC00H to 000FFFFFH is the initial area for the vector table upon reset.

Special functions are allocated to some of the vectors.

Table 3.8-3 shows the vector table on the architecture.

TBR 000FFC00H


52


Table 3.8-3 Vector Table (1 / 3)

Interrupt sourceInterrupt number

Interrupt level OffsetDefault

address of TBRDecimal Hexadecimal

Reset *1 0 00 - 3FCH 000FFFFCH

Mode vector *1 1 01 - 3F8H 000FFFF8H

Reserved for system 2 02 - 3F4H 000FFFF4H

Reserved for system 3 03 - 3F0H 000FFFF0H

Reserved for system 4 04 - 3ECH 000FFFECH

Reserved for system 5 05 - 3E8H 000FFFE8H

Reserved for system 6 06 - 3E4H 000FFFE4H

No-coprocessor trap 7 07 - 3E0H 000FFFE0H

Coprocessor error trap 8 08 - 3DCH 000FFFDCH

INTE instruction 9 09 - 3D8H 000FFFD8H

Instruction break exception 10 0A - 3D4H 000FFFD4H

Operand break trap 11 0B - 3D0H 000FFFD0H

Step trace trap 12 0C - 3CCH 000FFFCCH

NMI request (tool) 13 0D - 3C8H 000FFFC8H

Undefined instruction exception 14 0E - 3C4H 000FFFC4H

NMI request 15 0F Fixed to 15(FH) 3C0H 000FFFC0H

External Interrupt 0 16 10 ICR00 3BCH 000FFFBCH

External Interrupt 1 17 11 ICR01 3B8H 000FFFB8H



External Interrupt 4 20 14 ICR04 3ACH 000FFFACH

External Interrupt 5 21 15 ICR05 3A8H 000FFFA8H



Reload Timer 0 24 18 ICR08 39CH 000FFF9CH

Reload Timer 1 25 19 ICR09 398H 000FFF98H

Reload Timer 2 26 1A ICR10 394H 000FFF94H

Maskable interrupt source *2 27 1B ICR11 390H 000FFF90H

Maskable interrupt source *2 28 1C ICR12 38CH 000FFF8CH

Maskable interrupt source *2 29 1D ICR13 388H 000FFF88H

53


Maskable interrupt source *2 30 1E ICR14 384H 000FFF84H

Maskable interrupt source *2 31 1F ICR15 380H 000FFF80H

Maskable interrupt source *2 32 20 ICR16 37CH 000FFF7CH

Maskable interrupt source *2 33 21 ICR17 378H 000FFF78H









Maskable interrupt source *2 42 2A ICR26 354H 000FFF54H





Time-base timer overflow 47 2F ICR31 340H 000FFF40H











Maskable interrupt source *2 58 3A ICR42 314H 000FFF14H







54


*1: Even though the TBR value is changed, the reset vector and the mode vector are always fixed addresses.000FFFFCH and 000FFFF8H are used.

*2: The maskable interrupt source is defined for each model. For the vector table, see "APPENDIX B Interrupt Vector".



Delayed interrupt source bit 63 3F ICR47 300H 000FFF00H

Reserved for system (used in REALOS) 64 40 - 2FCH 000FFEFCH

Reserved for system (used in REALOS) 65 41 - 2F8H 000FFEF8H

Reserved for system 66 42 - 2F4H 000FFEF4H

Reserved for system 67 43 - 2F0H 000FFEF0H

Reserved for system 68 44 - 2ECH 000FFEECH

Reserved for system 69 45 - 2E8H 000FFEE8H



Reserved for system 72 48 - 2DCH 000FFEDCH

Reserved for system 73 49 - 2D8H 000FFED8H

Reserved for system 74 4A - 2D4H 000FFED4H

Reserved for system 75 4B - 2D0H 000FFED0H

Reserved for system 76 4C - 2CCH 000FFECCH

Reserved for system 77 4D - 2C8H 000FFEC8H

Reserved for system 78 4E - 2C4H 000FFEC4H

Reserved for system 79 4F - 2C0H 000FFEC0H

Used in INT instruction80|

255

50|

FF-

2BCH|

000H

000FFEBCH|

000FFC00H





55


3.8.5 Multiple EIT Processing

If multiple EIT causes occur at the same time, the CPU repeats the operation of selecting and accepting one of the EIT causes, executing the EIT sequence, and then detecting EIT causes again. If there are no more EIT causes be accepted while the CPU is detecting EIT causes, the CPU executes the handler instruction of the last accepted EIT cause. As a result, the order of executing handlers for multiple EIT causes that occur at the same time is determined according to the following two elements:• Priority of EIT causes to be accepted• How other causes can be masked when one cause is accepted

Priority of EIT Causes To Be Accepted

The priority of EIT causes to be accepted is the order of causes for which the EIT sequence isto be executed (that is, saving the PS and PC, updating the PC, and masking other causes, ifrequired). The handler of a cause accepted earlier is not necessarily executed earlier.

Table 3.8-4 lists the acceptance priority of EIT causes.

*: The priority is 6 only if the INTE instruction and the NMI for emulators occur at the same time. (The NMI for emulators is used for breaks due to data access).

Table 3.8-4 Priority of EIT Causes to Be Accepted and Masking of Other Causes

Priority of acceptance

Cause Masking of other causes

1 Reset Other causes are abandoned.

2 Undefined instruction exception Canceled

3 INT instruction I flag=0

4No-coprocessor trapCoprocessor error trap

-

5 User interrupt ILM=level of cause accepted

6 NMI (for users) ILM=15

7 (INTE instruction) ILM=4 *

8 NMI (for emulators) ILM=4

9 Step trace trap ILM=4

10 INTE instruction ILM=4

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In consideration of masking other causes after an EIT cause is accepted, the handlers of EITcauses that occur at the same time are executed in the order shown in Table 3.8-5 .

Figure 3.8-2 Multiple EIT Processing

Table 3.8-5 Order of Executing EIT Handlers

Order of executing handlers

Cause

1 Reset *1

2 Undefined instruction exception

3 Step trace trap *2

4 INTE instruction *2

5 NMI (for users)

6 INT instruction

7 User interrupt

8 No-coprocessor trap, coprocessor error trap

*1: Other causes are abandoned.*2: If the INTE instruction is executed in steps, only a step trace trap EIT occurs. An INTE

cause is ignored.

[Example]

(High) NMI occurring

Priority

(Low) INT instruction executed

(2) Executed next

(1) Executed first

INT instruction handler

NMI handler

Main routine

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3.8.6 EIT Operations

This section describes EIT operations.

EIT Operations

In the following, it is assumed that the destination source PC indicates the address of theinstruction that detected an EIT cause.

In addition, “address of the next instruction” means that the instruction that detected EIT is asfollows:

• If LDI is 32: PC + 6

• If LDI is 20 and COPOP, COPLD, COPST, and COPSV are used: PC + 4

• Other instructions: PC + 2

Operation of User Interrupt/NMI

If an interrupt request for a user interrupt or a user NMI occurs, whether the request can beaccepted is determined with the following procedure:

1. Compare the interrupt levels of requests that have occurred simultaneously and select therequest with the highest level (the smallest value). As levels to be compared, the value heldin the corresponding ICR is used for a maskable interrupt and a predetermined constant isused for an NMI.

2. If multiple interrupt requests with the same level occur, select the interrupt request with thesmallest interrupt number.

3. Mask and do no accept an interrupt request with an interrupt level greater than or equal tothe level mask value. Go to Step 4) if the interrupt level is less than the level mask value.

4. Mask and do not accept the selected interrupt request if it is maskable and the I flag is set to"0". Go to Step 5) if the I flag is "1". If the selected interrupt request is an NMI, go to Step 5)regardless of the I flag value.

5. If the above conditions are met, the interrupt request is accepted at a break in the instructionprocessing.

If a user interrupt or NMI request is accepted when EIT requests are detected, the CPUoperates as follows, using an interrupt number corresponding to the accepted interrupt request.

Note:

Parentheses in [Operation] show an address indicated by the register.

[Operation]

1. SSP-4 --> SSP

2. PS --> (SSP)

3. SSP-4 --> SSP

4. Address of next instruction --> (SSP)

5. Interrupt level of accepted request --> ILM

6. "0" --> S flag

7. (TBR + Vector offset of accepted interrupt request) --> PC

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If a user interrupt or NMI request is accepted when EIT requests are detected, the CPUoperates as follows, using an interrupt number corresponding to the accepted interrupt request.Parentheses show an address indicated by the register.

Operation of INT Instruction

INT #u8

A branch to the interrupt handler for the vector indicated by u8 generation.

[Operation]

1. SSP-4 --> SSP

2. PS --> (SSP)

3. SSP-4 --> SSP

4. PC + 2 --> (SSP)

5. "0" --> I flag

6. "0" --> S flag

7. (TBR + 3FCH-4 × u8) --> PC

Operation of INTE Instruction

INTE

A branch to the interrupt handler for the vector indicated by vector number #9 generation.

[Operation]

1. SSP-4 --> SSP

2. PS --> (SSP)

3. SSP-4 --> SSP

4. PC + 2 --> (SSP)

5. "00100" --> ILM

6. "0" --> S flag

7. (TBR+3D8H) --> PC

Do not use the INTE instruction in the processing routine of the INTE instruction or a step tracetrap.

During step execution, no EIT due to INTE generation.

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Operation of Step Trace Trap

Set the T flag in the SCR of the PS to enable the step trace function. A trap and a break thenoccur every time an instruction is executed.

[Step trace trap detection conditions]

· T flag =1

· There is no delayed branch instruction.

· A processing routine other than the INTE instruction or a step trace trap is in progress.

If the above conditions are met, a break occurs between instruction operations.

[Operation]

1. SSP-4 --> SSP

2. PS --> (SSP)

3. SSP-4 --> SSP


5. "00100" --> ILM

6. "0" --> S flag

7. (TBR+3CCH) --> PC

Set the T flag to enable the step trace trap to prohibit a user NMI and a user interrupt. No EIToccurs due to the INTE instruction.

A trap occurs in the instruction following the one in which the T flag has been set.

Operation of Undefined Instruction Exception

If, during instruction decode, an undefined instruction is detected, an undefined instructionexception occurs.

An undefined instruction exception is detected under the following conditions:

• An undefined instruction is detected during instruction decode.

• The instruction is not located in the delay slot (it does not immediately follow)

If the above conditions are met, an undefined instruction exception and a break occur.

[Operation]

1. SSP-4 --> SSP

2. PS --> (SSP)

3. SSP-4 --> SSP

4. PC --> (SSP)

5. "0" --> S flag

6. (TBR+3C4H) - -> PC

The PC value to be saved is the address of an instruction that detected an undefined instructionexception.

No-coprocessor Trap

If a coprocessor instruction using a coprocessor that is not installed is executed, a no-coprocessor trap occurs.

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[Operation]

1. SSP-4 --> SSP

2. PS --> (SSP)

3. SSP-4 --> SSP


5. "0" --> S flag

6. (TBR+3E0H) --> PC

Coprocessor Error Trap

If an error occurs while a coprocessor is being used and then a coprocessor instruction thatoperates on the coprocessor is executed, a coprocessor error trap occurs.

[Operation]

1. SSP-4 --> SSP

2. PS --> (SSP)

3. SSP-4 --> SSP


5. "0" --> S flag

6. (TBR+3DCH) --> PC

Operation of RETI Instruction

The RETI instruction specifies return from the EIT processing routine.

[Operation]

1. (R15) --> PC

2. R15+4 --> R15

3. (R15) --> PS

4. R15+4 --> R15

The RETI instruction must be executed while the S flag is set to "0".

Precaution on Delay Slot

A delay slot for a branch instruction has restrictions regarding EIT.

See Section "3.7 Branch Instructions".

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3.9 Operating Modes

Two operating modes are provided: bus mode and access mode. This section describes these modes.

Operating Modes

Bus mode

Bus mode refers to a mode in which the operations of internal ROM and the external accessfunction are controlled. A bus mode is specified using the setting pins (MD2, MD1, and MD0)and the ROMA bit in the mode data.

Access mode

An access mode is specified using the WTH1 and WTH0 bits in the mode register and theDBW1 and DBW0 bits in ACR0 to ACR7 (Area Configuration Register).

Bus Modes

The MB91310 has the following three bus modes.

Bus Mode 0 (single-chip mode)

In this mode, internal I/O, D-bus RAM, F-bus RAM, and F-bus ROM are valid. Access to otherareas is invalid.

External pins do not serve as bus pins, but serve as peripheral or general-purpose I/O ports.

Bus Mode 1 (internal-ROM/external-bus mode)

In this mode, internal I/O, D-bus RAM, and F-bus RAM, as well as F-bus ROM, are valid.Access to an area that enables external access is handled as access to an external space.Some external pins serve as bus pins.

Bus Mode 2 (external-ROM/external-bus mode)

In this mode, internal I/O, D-bus RAM, and F-bus RAM are valid, but access to F-bus ROM isinvalid. All accesses are handled as access to an external space. Some external pins serve asbus pins.

Single chipInternal ROM/external busExternal ROM/external bus

16-bit bus width

8-bit bus width

Access modeBus mode

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3.9 Operating Modes

Mode Settings

For the MB91310, set the operating mode using the mode pins (MD2, MD1, and MD0) and themode register (MODR).

Mode pins

Use the three mode pins (MD2, MD1, and MD0) to specify mode vector fetch.

Note:

Mode settings other than the above are prohibited.

Mode register (MODR)

Mode data is data written to the mode register by a mode vector fetch (see Section "3.10.3Reset Sequence").

Mode data is always set in the mode register when any reset source arises. A user programcannot write data to the mode register.

Note:

Nothing exists at the address (0000_07FFH) of the MB91310 mode register.

Data can be rewritten to the mode register in emulator mode. Use an 8-bit length data transferinstruction to rewrite data. A 16-bit or 32-bit length data transfer instruction cannot be used torewrite data to the mode register.

Figure 3.9-1 shows the bit configuration of the mode register (MODR).

Figure 3.9-1 Bit Configuration of the Mode Register (MODR)

[bit7 to bit3] Reserved bits

These bits are reserved.

Note:

Be sure to set bits 7 to 3 to "00000". If any other value is set for these bits, operation isunpredictable.

Mode pinMode name

Reset vector access area

RemarksMD2 MD1 MD0

0 0 0Internal ROM mode vector

Internal -

0 0 1External ROM mode vector

ExternalSet the bus width using the mode register.

WTH00 0 WTH1ROMA000

0123456bit 7 Initial value

xxxxxxxxB

MODR

000FFFF8H

Operating mode setting bits

63


[bit2] ROMA (Internal ROM enable bit)

This bit indicates whether to enable internal F-bus RAM and F-bus ROM areas.

[bit1, bit0] WTH1, WTH0 (Bus width specification bit)

These bits indicate the bus width specification to be used in external bus mode.

In external bus mode, this value is set in the DBW1 and DBW0 bits of ACR (CS0 area).

ROMA Function Remarks

0 External ROM modeThe internal F-bus RAM is enabled, and the internal ROM area (8 0000H to 10 0000H) becomes the external ROM area.

1 Internal ROM modeThe internal F-bus RAM and F-bus ROM are enabled.

WTH1 WTH0 Function Remarks

0 0 8-bit bus width External bus mode

0 1 16-bit bus width External bus mode

1 0 - Setting prohibited

1 1 Single-chip mode Single-chip mode

64



This section describes a reset (that is, initialization) of the MB91310.

Reset (Device Initialization)

If a reset source occurs, the device stops all the programs and hardware operations andcompletely initializes the state. This state is called the reset state.

When a reset source no longer exists, the device starts programs and hardware operations fromtheir initial state. The series of operations from the reset state to the start of operations is calledthe reset sequence.

65


3.10.1 Reset Levels

The reset operations of the MB91310 are classified into two levels, each of which has different causes and initialization operations. This section describes these reset levels.

Settings Initialization Reset (INIT)

The highest-level reset, which initializes all settings, is called a settings initialization reset (INIT).

A settings initialization reset (INIT) mainly performs the following initialization:

Items initialized in a settings initialization reset (INIT)

• Device operation mode (bus mode and external bus width settings)

• All internal clock settings (clock source selection, PLL control, and divide-by setting)

• All settings on external bus CS0 area

• All settings on pin statuses other than the above settings

• All sections initialized by an operation initialization reset (RST)

For more information, see the description of each of these functions.

Note:

After power-on, be sure to apply the settings initialization reset (INIT) at the INIT pin.

Operation Initialization Reset (RST)

A normal-level reset that initializes the operation of a program is called an operation initializationreset (RST).

If a settings initialization reset (INIT) occurs, an operation initialization reset (RST) also occurs.

An operation initialization reset (RST) mainly initializes the following items:

Items initialized by an operation initialization reset (RST)

• Program operation

• CPU and internal buses

• Register settings of peripheral circuits

• I/O port settings

• All CS0 area settings of external buses

For more information, see the description of each of these functions.

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3.10.2 Reset Sources

This section describes the reset sources and the reset levels in the MB91310.To determine reset sources that have occurred in the past, read the RSRR (reset source register). For more information about registers and flags described in this section, see Section "3.11.5 Block Diagram of Clock Generation Controller" and "3.11.6 Register of Clock Generation Controller".

INIT Pin Input (Settings Initialization Reset Pin)

The INIT pin, which is an external pin, is used as the settings initialization reset pin.

A settings initialization reset (INIT) request is generated while the "L" level is being input to thispin.

Input the "H" level to this pin to clear a settings initialization reset (INIT) request.

If a settings initialization reset (INIT) is generated in response to a request from this pin, bit15(INIT bit) of the RSRR (reset source register) is set.

Because a settings initialization reset (INIT) in response to a request from this pin has thehighest interrupt level among all reset sources, it has precedence over any other input,operation, or state.

Immediately after power-on, be sure to apply a settings initialization reset (INIT) at the INIT pin.To assure the oscillation stabilization wait time for the oscillation circuit immediately after power-on, input the "L" level to the INIT pin for the stabilization wait time required by the oscillationcircuit. INIT at the INIT pin initializes the oscillation stabilization wait time to the minimum value.

• Reset source: "L" level input to the external INIT pin

• Source of clearing: "H" level input to the external INIT pin

• Reset level: Settings initialization reset (INIT)

• Corresponding flag: bit15 (INIT)

Software Reset (STCR: SRST Bit Writing)

If "0" is written to bit4 (SRST bit) of the standby control register (STCR), a software resetrequest occurs. A software reset request is an operation initialization reset (RST) request.

When the request is accepted and a operation initialization reset (RST) is generated, thesoftware reset request is cleared.

If an operation initialization reset (RST) is generated due to a software reset request, a bit11(SRST bit) in the RSRR (reset source register) is set.

An operation initialization reset (RST) is generated due to a software reset request only after allbus access has stopped and if bit9 (SYNCR bit) of the time-base counter control register(TBCR) has been set (synchronization reset mode). Thus, depending on the bus usage status,a long time is required before an operation initialization reset (RST) occurs.

Note the restritions that apply to bit9:SYNCR in the TBCR (time-base counter control register)when using the synchronous mode software reset.

• Reset source: Writing "0" to bit4 (SRST) of the standby control register (STCR)

• Source of clearing: Generation of an operation initialization reset (RST)

67


• Reset level: Operation initialization reset (RST)

• Corresponding flag: bit11(SRST)

Watchdog Reset

Writing to the watchdog timer control register (RSRR) starts the watchdog timer. Unless A5H/5AH is written to the time-base counter clear register (CTBR) within the cycle specified in Bits 9and 8 (WT1 and WT0 bits) in the RSRR, a watchdog reset request occurs.

A watchdog reset request is a settings initialization reset (INIT) request. If, after the request isaccepted, a settings initialization reset (INIT) occurs or an operation initialization reset (RST)occurs, the watchdog reset request is cleared.

If a settings initialization reset (INIT) is generated due to a watchdog reset request, bit13(WDOG bit) in the reset source register (RSRR) is set.

Note that, if a settings initialization reset (INIT) is generated due to a watchdog reset request,the oscillation stabilization wait time is not initialized.

• Reset source: Setting cycle of the watchdog timer elapses

• Source of clearing: Generation of a settings initialization reset (INIT) or an operation initialization reset (RST)

• Reset level: Settings initialization reset (INIT)

• Corresponding flag: bit13 (WDOG)

68

Changed " Watchdog Reset". (watchdog reset postpone register(WPR) → Time Base Counter Clear register(CTBR))


3.10.3 Reset Sequence

When a reset source no longer exists, the device starts to execute the reset sequence.A reset sequence has different operations depending on the reset level.This section describes the operations of the reset sequence for different reset levels.

Setting Initialization Reset (INIT) Clear Sequence

If a settings initialization reset (INIT) request is cleared, the following operations are performedone step at a time for the device.

1. Clear the settings initialization reset (INIT) and enter the oscillation stabilization wait state.

2. For the oscillation stabilization wait time (set with Bits 3 and 2 [OS1 and OS0 bits] in theSTCR), maintain the operation initialization reset (RST) state and stop the internal clock.

3. In the operation initialization reset (RST) state, start internal clock operation.

4. Clear the operation initialization reset (RST) and enter the normal operating state.

5. Read the mode vector from address 000FFFF8H.

6. Write the mode vector to the MODR (mode register) at address 000007FDH.

7. Read the reset vector from address 000FFFFCH.

8. Write the reset vector to the program counter (PC).

9. The program starts execution from the address loaded in the program counter (PC).

Operation Initialization Reset (RST) Clear Sequence

If an operation initialization reset (RST) request is cleared, the following operations areperformed one step at a time for the device.

1. Clear the operation initialization reset (RST) and enter the normal operating state.

2. Read the mode vector from address 000FFFF8H.

3. Write the mode vector to the mode register (MODR) at address 000007FDH.

4. Read the reset vector from address 000FFFFCH.

5. Write the reset vector to the program counter (PC).

6. The program starts execution from the address loaded in the program counter (PC).

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3.10.4 Oscillation Stabilization Wait Time

If a device returns from the state in which the original oscillation was or may have been stopped, the device automatically enters the oscillation stabilization wait state. This function prevents the use of oscillator output after starting before oscillation has stabilized.For the oscillation stabilization wait time, neither an internal nor an external clock is supplied; only the built-in time-base counter runs until the stabilization wait time set in the standby control register (STCR) has elapsed.This section describes the oscillation stabilization wait operation.

Sources of an Oscillation Stabilization Wait

The following lists sources of an oscillation stabilization wait.

Clearing of a settings initialization reset (INIT)

The device enters the oscillation stabilization wait state if a settings initialization reset (INIT) iscleared for a variety of reasons.

When the oscillation stabilization wait time has elapsed, the device enters the operationinitialization reset (RST) state.

Returning from stop mode

The device enters the oscillation stabilization wait state immediately after stop mode is cleared.

However, if it is cleared by a settings initialization reset (INIT) request, the device enters thesettings initialization reset (INIT) state. Then, after the settings initialization reset (INIT) iscleared, the device enters the oscillation stabilization wait state.

When the oscillation stabilization wait time has elapsed, the device enters the statecorresponding to the source that cleared stop mode:

• Return due to input of a valid external interrupt request (including NMI): The device entersthe normal operating state.

• Return due to a settings initialization reset (INIT) request: The device enters the operationinitialization reset (RST) state.

• Return due to an operation initialization reset (RST) request: The device enters theoperation initialization reset (RST) state.

Returning from an abnormal state when PLL is selected

If, while the device is operating with PLL as the source clock, an abnormal condition*1 occurs inPLL control, the device automatically enters an oscillation stabilization wait to assure the PLLlock time.

When the oscillation stabilization wait time has elapsed, the device enters the normal operatingstate.

*1: The multiply-by rate is changed while PLL is working, or an incorrect bit such as a bitequivalent to PLL operation enable bit is generated.

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Selecting an Oscillation Stabilization Wait Time

The oscillation stabilization wait time is measured with the built-in time-base counter.

If a source for an oscillation stabilization wait occurs and the device enters the oscillationstabilization wait state, the built-in time-base counter is initialized and then it starts to measurethe oscillation stabilization wait time.

Using bits 3 and 2 (OS1 and OS0 bits) of the standby control register (STCR), select and setone of the four types of oscillation stabilization wait time.

Once selected, a setting is initialized only if a settings initialization reset (INIT) is generated dueto the external INIT pin. The oscillation stabilization wait time that has been set before a reset ismaintained if a settings initialization reset (INIT) is generated or an operation initialization reset(RST) is generated due to a watchdog reset condition.

The four types of oscillation stabilization wait time settings are designed for the following fourtypes of use:

• OS1, OS0=00: No oscillation stabilization wait time (if neither PLL nor the oscillator shouldstop in stop mode)

• OS1, OS0=01: PLL lock wait time (if an oscillator should not stop in stop mode)

• OS1, OS0=10: Oscillation stabilization wait time (intermediate) (if an oscillator that stabilizesquickly, such as a ceramic vibrator, is used)

• OS1, OS0=11: Oscillation stabilization wait time (long) (if an ordinary quartz oscillator will beused)

Immediately after power-on, be sure to apply the settings initialization reset (INIT) at the INITpin.

To assure the oscillation stabilization wait time of the oscillation circuit immediately after power-on, maintain "L" level input to the INIT pin for the stabilization wait time required by theoscillation circuit. (INIT generated due to the INIT pin initializes the oscillation stabilization waittime setting to the minimum value.)

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3.10.5 Reset Operation Modes

Two modes for an operation initialization reset (RST) are provided: normal (asynchronous) reset mode and synchronous reset mode. The operation initialization reset mode is selected with bit9 (SYNCR bit) of the time-base counter control register (TBCR). This mode setting is initialized only by a settings initialization reset (INIT). A settings initialization reset always results in an asynchronous reset.This section describes the operation of these modes.

Normal Reset Operation

Normal reset operation refers to a transition to the operation initialization rest (RST) stateimmediately after an operation initialization reset (RST) request.

If a rest (RST) request is accepted in this mode, the device immediately enters the reset (RST)state regardless of the status of internal bus access.

In this mode, the result of a bus access being performed prior to each state transition isunpredictable. However, these requests can certainly be accepted.

If bit9 (SYNCR bit) of the time-base counter control register (TBCR) is set to "0", normal resetmode is selected. The initial value after a settings initialization reset (INIT) is normal resetmode.

Synchronous Reset Operation

Synchronous reset operation refers to a transition to the operation initialization reset (RST) stateafter all bus access has stopped when an operation initialization reset (RST) request occurs.

Even if a reset (RST) request is accepted in this mode, the device does not enter the reset(RST) state while internal bus access is in progress.

If the above request is accepted, a sleep request is issued to the internal buses. If all the busesstop and enter the sleep state, the device enters the operation initialization reset (RST) state.

In this mode, the result of all bus accesses is guaranteed because all bus access is stoppedprior to each status transition.

If bus access does not stop for some reason, no requests can be accepted while the bus accessis in progress. Even in this case, the settings initialization reset (INIT) is immediately valid.

Bus access may not stop in the following cases:

• A bus release request (BRQ) continues to be input to the external extended bus interface,bus release acknowledge (BGRNT) is valid, and a new bus access request arrives from aninternal bus.

• A ready request (RDY) continues to be input to the external extended bus interface and buswait is valid. In the following cases, the device eventually enters another state but only aftera long time:

72


Notes:

• The DMA controller, which stops transfer when a request is accepted, does not delay transitionto another state.

• If bit9 (SYNCR bit) of the time-base counter control register (TBCR) is set to "1", synchronousreset mode is selected. The initial value after a settings initialization reset (INIT) is normal resetmode.

• Note the restritions that apply to bit9:SYNCR in the TBCR (time-base counter control register)when using the synchronous mode software reset.

73

Changed " Synchronous Reset Operation". (Reference: → Notes:)



This section describes clock generation and control.

Clock Generation Control

The internal operating clock of the MB91310 is generated as follows:

• Selection of a source clock: Select a clock supply source.

• Generation of a base clock: Divide the source clock by two or perform PLL oscillation togenerate a base clock.

• Generation of an internal clock: Divide the base clock and generate four types of operatingclocks, which are supplied to each section.

Each clock generation and its control is described. The decriptionof each register and thedetailed explanation of the flag refer to Section "3.11.5 Block Diagram of Clock GenerationController" and "3.11.6 Register of Clock Generation Controller".

Selection of Source Clock

A resonator is connected to external oscillator pins X0/X1 and X0A/X1A, and the clock pulsesgenerated by the built-in oscillator circuit is used as the source clock.

The MB91310 is the source of all clocks, including the external bus clock.

The external oscillator pins and built-in oscillator circuit can use the main clock or sub clock, andthese two clocks can be arbitrarily switched during operation.

• Main clockThe main clock, generated from the X0/X1 pins, is intended for use as a high-speed clock.

• Sub clockThe sub clock, generated from the X0A/X1A pins, is intended for use as a low-speed clock.

The main clock and sub clock are multiplied by the built-in main PLL and sub clock, each ofwhich can be independently controlled.

Generate an internal base clock by selecting one of the following source clocks:

• Main clock divided by two

• Main clock multiplied in the main PLL

• Sub clock as is

Select a source clock by setting the clock source control register (CLKR).

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3.11.1 PLL Controls

The operation (oscillation) enable and disable and multiply-by-rate setting can be independently controlled for each of the PLL oscillator circuits provided for each of main source clock and sub clock. Each control is set in the clock source control register (CLKR).This section describes each control.

PLL Operation Enable

To enable or disable the main PLL oscillator circuit operation, set bit10 (PLL1EN bit) of the clocksource control register (CLKR).

To enable or disable the sub clock oscillator circuit operation, set bit11 (PLL2EN bit) of the clocksource control register (CLKR).

After a setting initialization reset (INIT), bits PLL1EN and PLL2EN are initialized to "0", causingthe PLL oscillator circuit operation to stop. While it is stopped, PLL output cannot be selectedas the source clock.

When the program operation starts, set the multiply-by rate of the PLL to be used as the clocksource, enable it, and switch the source clock after the PLL lock wait time elapses. For the PLLlock wait time, use of a time-base timer interrupt is recommended.

While PLL output is selected as the source clock, the PLL cannot be stopped (writing to theregister is disabled). To stop a PLL upon transition to stop mode, reselect as the source clockthe main clock divided by two before stopping the PLL.

If bit0 (OSCD1 bit) or bit1 (OSCD2 bit) of the standby control register (STCR) is set to stoposcillation in stop mode, the corresponding PLL automatically stops when the device enters stopmode. As a result, you do not need to set operation stop. When the device returns from stopmode later, the PLL automatically restarts the oscillation operation. If oscillation is not set tostop in stop mode, the PLL does not automatically stop. In this case, set operation stop beforetransition to stop mode as required.

75


PLL Multiply-by Rate

Set the multiply-by rate of the main PLL in bits 14 to 12 (PLL1S2, PLL1S1, and PLL1S0 bits) ofthe clock source control register (CLKR).

After a setting initialization reset (INIT), all bits are initialized to "0".

PLL multiply-by rate setting

To change the PLL multiply-by rate setting from the initial value, do so before or as soon as thePLL is enabled after the program has started execution. After changing the multiply-by rate,switch the source clock after the lock wait time elapses. For the PLL lock wait time, use of atime-base timer interrupt is recommended.

To change the PLL multiply-by rate setting during operation, switch the source clock to a clockother than the PLL in question before making the change. After changing the multiply-by rate,switch the source clock after the lock wait time has elapsed, as described above.

You can also change the PLL multiply-by rate setting while using a PLL. In this case, however,the program stops running after the device automatically enters the oscillation stabilization waitstate after the multiply-by rate setting is rewritten and does not resume execution until thespecified oscillation stabilization wait time has elapsed.

The program does not stop running if the clock source is switched to a clock other than a PLL.

76


3.11.2 Oscillation Stabilization Wait Time and PLL Lock Wait Time

If a clock selected as the source clock is not already stabilized, an oscillation stabilization wait time is required (See Section "3.10.4 Oscillation Stabilization Wait Time").For a PLL, a lock wait time is required after operation starts until the output stabilizes to the specified frequency.This section describes the wait time used in various situations.

Wait Time after Power-On

After power-on, an oscillation stabilization wait time for the main clock oscillation circuit isrequired.

Since the oscillation stabilization wait time setting is initialized to the minimum value due to INITpin input (settings initialization reset pin), assure the oscillation stabilization wait time by usingthe time during which the "L" level is sent to the INIT pin input.

In this state, since no PLL is enabled, no lock wait time needs to be considered.

Wait Time after Setting Initialization

If a settings initialization reset (INIT) is cleared, the device enters the oscillation stabilization waitstate. In this case, the specified oscillation stabilization wait is internally generated. In the firstoscillation stabilization wait state after input from the INIT pin, the setting time is initialized to theminimum value, soon ending this state, and the device enters the operation initialization reset(RST) state.

If, after a program starts running, a settings initialization reset (INIT) is generated for a reasonother than INIT pin input and is then cleared, the oscillation stabilization wait time specified inthe program is internally generated.

In these states, since no PLL is enabled, no lock wait time needs to be considered.

Wait Time after Enabling a PLL

If you enable a stopped PLL after a program starts execution, use the PLL output only after thelock wait time elapses. If the PLL is not selected as the source clock, the program can run evenduring the lock wait time. For the PLL lock wait time, use of a time-base timer interrupt isrecommended.

Wait Time after Changing the PLL Multiply-by Rate

If you change the multiply-by rate setting of a running PLL after a program starts execution, usethe PLL output only after lock wait time elapses.

If the PLL is not selected as the source clock, the program can run even during the lock waittime.

For the PLL lock wait time, use of a time-base timer interrupt is recommended.

77


Wait Time after Returning from Stop Mode

If, after a program starts execution, the device enters stop mode and then stop mode is cleared,the oscillation stabilization wait time specified in the program is internally generated. If the clockoscillation circuit selected as the source clock is set to stop in stop mode, the oscillationstabilization wait time of the oscillation circuit or the lock wait time of the PLL in use, whicheveris longer, is required. Set the oscillation stabilization wait time before entering stop mode.

If the clock oscillation circuit selected as the source clock is not set to stop in stop mode, thePLL does not automatically stop. No oscillation stabilization wait time is required unless the PLLhas stopped. Setting the oscillation stabilization wait time to the minimum value before stopmode is entered is recommended.

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3.11.3 Clock Distribution

An operating clock for each function is generated based on the base clock generated from the source clock. A total of three internal operating clocks are provided. A divide-by rate can be set independently for each of them.This section describes these internal operating clocks.

CPU Clock (CLKB)

This clock is used for the CPU, internal memory, and internal buses.

It is used by the following circuits:

• CPU

• Instruction cache

• Built-in RAM and ROM

• Bit search module

• I-bus, D-bus, X-bus, and F-bus

• DMA controller

• DSU

Note:

Since 40 MHz is the upper-limit frequency for operation, do not set a combination of multiply-by rate and divide-by rate that results in a frequency exceeding this limit.

79


Peripheral Clock (CLKP)

This clock is used for peripheral circuits and peripheral buses.


• Peripheral bus

• Clock controller (only for the bus interface)

• Interrupt controller

• Peripheral I/O ports (port*, port*)

• I/O port bus

• External interrupt input

• UART

• 16-bit timer

• A/D converter

• Free-run timer

• Reload timer

• Up/down counter

• I2C interface

• PPG

Note:


External Bus Clock (CLKT)

This clock is used for external extended bus interfaces.


• External extended bus interface

• External CLK output

Note:


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3.11.4 Clock Division

A divide-by rate can be set independently for each of the internal operating clocks. With this function, an optimal operating frequency can be set for each circuit.

Clock Division

Set a divide-by rate in Basic Clock Division Setting Register 0 (DIVR0) and Basic Clock DivisionSetting Register 1 (DIVR1). Each of these registers has four setting bits and (Register settingvalue + 1) is the divide-by rate of the clock in relation to the base clock. Even if the divide-byrate setting is an odd number, the duty is always 50.

If the setting value is changed, the new divide-by rate becomes valid at the leading edge of thenext clock after the setting is made.

The divide-by rate setting is not initialized if an operation initialization reset (RST) occurs andthe setting made before the reset occurs is retained. The divide-by rate setting is initialized onlyif a settings initialization reset (INIT) occurs. In the initial state, all clocks other than theperipheral clock (CLKP) have a divide-by rate of 1. Thus, be sure to set the divide-by ratebefore changing the source clock to a faster clock.

An upper-limit frequency for the operation is set for each clock. If you set a combination ofsource clock, PLL multiply-by rate setting, and divide-by rate setting that results in a frequencyexceeding this upper-limit frequency, operation is not guaranteed. (Be extra careful of the orderin which you change settings to select the source clock and to configure the associated settingitems.)

81


3.11.5 Block Diagram of Clock Generation Controller

This section provides a block diagram of the clock generation controller.The detailed description of register in the figure refers to "3.11.6 Register of Clock Generation Controller".

Block Diagram

Figure 3.11-1 shows a block diagram of the clock generation controller.

Figure 3.11-1 Block Diagram of Clock Generation Controller

X1

X0

1/2

PLL

X1A

X0A

Selector

Selector

Selector

[Clock generator]

CPU clock division

Peripheral clock division

External bus clock division

Sto

p co

ntro

l

CPU clock

Peripheral clock

External bus clock

R-B

US

DIVR0,1 registers

Peripheral circuit operation stop control register

Perip

hera

l ci

rcui

t ope

ratio

n st

op c

ontro

l

Oscilla-tion circuit

Oscilla-tion circuit

Sele

ctor

CLKR register

Main clock oscillator stabilization wait timer (for sub clock selection)

Resetoccurrence F/F

Resetoccurrence F/F

Statustransition control circuit

STCR register

Internal reset

Internal interrupt

[Stop and sleep controller]

Stop status

Sleep status

Internal reset (RST)

Internal reset (INIT)

Counter clock

Interrupt enable

INIT pin

CTBR register

Time-base counter

Watchdog F/F

Overflow detection F/FTBCR register

RSRR register

Time-base timerinterrupt reques

[Watchdog controller]

Selector

[Reset source circuit]

Main clock

Sub clock

Watch timer

82

Changed " Block Diagram".


3.11.6 Register of Clock Generation Controller

This section describes the functions of registers to be used in the clock generation controller.

Reset Source Register/Watchdog Timer Control Register (RSRR)

Figure 3.11-2 shows the configuration of the reset source register/watchdog timer controlregister (RSRR).

Figure 3.11-2 Configuration of Reset Source Register/Watchdog Timer Control Register (RSRR) Bits

This register holds the source of the last reset that occurred as well as the interval setting andstartup control for the watchdog timer. If the timer is read, the reset source that has been heldis cleared after it is read. If more than one reset is generated before this register is read, resetsource flags are accumulated and the multiple flags are set.

Writing to this register starts the watchdog timer. Thereafter, the watchdog timer continuesrunning until a reset (RST) occurs.

[bit15] INIT (INITialize reset occurred)

This bit indicates whether a reset (INIT) occurred due to INIT pin input.

• This bit is initialized to "0" after it is read.

• This bit is readable; writing to the bit has no effect on the bit value.

[bit14] (Reserved bit)

[bit13] WDOG (WatchDOG reset occurred)

This bit indicates whether a reset (INIT) occurred due to the watchdog timer.

• This bit is initialized to "0" after a reset (INIT) due to INIT pin input or just after it is read.


bit 15 14 13 12 11 10 9 8

R R R R R R R R/W

Address:00000480H INIT - WDOG - SRST - WT1 WT0

Initial value (INIT) * * * x x * 0 0Initial value (RST) x x x * * x 0 0*: Varies according to the source.x: Not initialized

Initial value (INIT pin) 1 0 0 0 0 0 0 0

0 INIT occurred due to INIT pin input.

1 INIT occurred due to INIT pin input.

0 No INIT occurred due to the watchdog timer.

1 INIT occurred due to watchdog timer.

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This bit is reserved.

[bit11] SRST (Software ReSeT occurred)

This bit indicates whether a reset (RST) occurred due to writing to the SRST bit of the STCRregister (a software reset).

• This bit is initialized to "0" after a reset (INIT) due to INIT pin input or just after it is read.




[bit9, bit8] WT1, WT0 (Watchdog interval Time select)

This bit sets the interval of the watchdog timer.

The values written to these bits determine the interval of the watchdog timer, which can beselected from the four types shown in the following table.

• These bits are initialized to "00" after a reset (RST).

• These bits are readable, but are writable only once after a reset (RST). Any further writing isdisabled.

0 No RST occurred due to a software reset.

1 RST occurred due to a software reset.

WT1 WT0Minimum required interval for

writing to the CTBR to suppress a watchdog reset

Time from writing the last 5AH to the CTBR until a watchdog reset

occurs

0 0 φ × 216 (initial value) φ × 216 to φ × 217

0 1 φ × 218 φ × 218 to φ × 219

1 0 φ × 220 φ × 220 to φ × 221

1 1 φ × 222 φ × 222 to φ × 223

φ: Frequency of the system base clock

84

Changed the table of "[bit9,8]WT1,WT0(Watchdog interval Time select)". (WPR → CTBR)


Standby Control Register (STCR)

Figure 3.11-3 shows the configuration of the standby control register (STCR).

Figure 3.11-3 Configuration of Standby Control Register (STCR) Bits

The standby control register controls the operating mode of the device.

This register controls the transition to the two standby modes of stop and sleep, pins when instop mode, and the stopping of oscillation stop. It also sets the oscillation stabilization wait timeand issues software resets.

The following describes the functions of the standby control register (STCR) bits.

Note the restrictions that apply to bit9:SYNCR in the TBCR (time-base counter control register) when

using the synchronous mode software reset.

Note:

To place the device in standby mode, use the synchronous standby mode (set with bit8: SYNCS bitof the time-base counter control register (TBCR)) and be sure to use the following sequence:

/* Writing STCR */




/* Writing CTBR */











nop

nop

nop

nop

bit 7 6 5 4 3 2 1 0

R/W R/W R/W R/W R/W R/W R/W R/W

Address:00000481H STOP SLEEP HIZ SRST OS1 OS0 OSCD2 OSCD1

Initial value (INIT pin) 0 0 1 1 0 0 1 1

Initial value (RST) 0 0 x 1 x x x x Initial value (INIT) 0 0 1 1 x x 1 1

85

Added "Note:" in " Standby Control Register(STCR)".


[bit7] STOP (STOP mode)

This bit specifies entry into stop mode. If "1" is written to both bit6 (SLEEP bit) and this bit,this bit has precedence and the device enters stop mode

• This bit is initialized to "0" by a reset (RST) and by a stop return source.

• This bit is readable and writable.

[bit6] SLEEP (SLEEP mode)

This bit specifies entry into stop mode. If "1" is written to both bit7 (STOP bit) and this bit,this bit (STOP) has precedence and the device enters stop mode.

• This bit is initialized to "0" by a reset (RST) and by a sleep return source.


[bit5] HIZ (HIZ mode)

This bit controls the pin state in stop mode.

• This bit is initialized to "0" by a reset (INIT).


[bit4] SRST (Software ReSeT)

This bit specifies issuing of a software reset (RST).

• This bit is initialized to "1" by a reset (RST).

• This bit is readable and writable. The read value is always "1".

Note the restritions that apply to bit9:SYNCR in the TBCR (time-base counter control register)when using the synchronous mode software reset.

[bit3, bit2] OS1, OS0 (Oscillation Stabilization time select)

These bits set the oscillation stabilization wait time used after a reset (INIT), return from stopmode, etc.

The values written to these bits determine the interval of the watchdog timer, which can beselected from the four types shown in the following table.

0 Stop mode not entered (initial value)

1 Stop mode entered

0 Sleep mode not entered (initial value)

1 Sleep mode entered

0 The pin state before stop mode entered is maintained.

1 Pin output is set to high-impedance state in stop mode (initial value).

0 A software reset is issued.

1 A software reset is not issued (initial value).

86


• These bits are initialized to "00" by a reset (INIT) which INIT pin inputs. However, when thereset by INIT pin input and the reset by HSTX pin input are simultaneously valid, these bitsare initialized to "11".

• These bits are readable and writable.

[bit1] OSCD2 (OSCillation Disable mode for XIN2)

This bit controls stopping of the sub-oscillation input (XIN2) in stop mode.



[bit0] OSCD1 (OSCillation Disable mode for XIN1)

This bit controls stopping of main oscillation input (XIN1) in stop mode.



Time-Base Counter Control Register (TBCR)

Figure 3.11-4 shows the configuration of the time-base counter control register (TBCR) bits.

Figure 3.11-4 Configuration of Time-Base Counter Control Register (TBCR) Bits

The time-base counter control register controls time-base timer interrupts, among other things.

This register enables time-base timer interrupts, selects an interrupt interval time, and sets anoptional function for the reset operation.

OS1 OS0Oscillation stabilization

wait timeIf the source oscillation is

10 MHz

0 0 φ × 21 (initial value) 0.4 [µs]

0 1 φ × 211 410 [µs]

1 0 φ × 216 13.1 [ms]

1 1 φ × 222 839 [ms]

φ: Frequency of the system base clock; in this case, twice the cycle of the source oscillation input

0 Not stopping the sub-oscillation in stop mode

1 Stopping the sub-oscillation in stop mode (initial value)

0 Main oscillation does not stop in stop mode.

1 Main oscillation stops in stop mode (initial value).

bit 15 14 13 12 11 10 9 8


Address: 00000482H TBIF TBIE TBC2 TBC1 TBC0 - SYNCR SYNCS

Initial value (RST) 0 0 x x x x x xInitial value (INIT) 0 0 x x x x 0 0

87


[bit15] TBIF (Time-Base timer Interrupt Flag)

This bit is the time-base timer interrupt flag. It indicates that the interval time (TBC2 to TBC0bits, which are bit13 to bit11) specified by the time-base counter has elapsed.

A time-base timer interrupt request is generated if this bit is set to "1" when interrupts areenabled by bit14 (TBIE bit, TBIE=1).


• This bit is readable and writable, although only "0" can be written to it. Writing "1" does notchange the bit value. The value read by a read modify write instruction is always "1".

[bit14] TBIE (Time-Base timer Interrupt Enable)

This bit is the time-base timer interrupt request output enable bit.

It controls output of an interrupt request when the interval time of the time-base counter haselapsed. A time-base timer interrupt request is generated if bit15 (TBIF bit) is set to "1" whenthis bit is set to "1".



[bit13 to bit11] TBC2, TBC1, TBC0 (Time-Base timer Counting time select)

These bits set the interval time of the time-base counter that is used for the time-base timer.

The values written to these bits determine the interval time, which can be selected from theeight types shown in Table 3.11-1 .

Clear source An instruction writes "0".

Set sourceThe specified interval time elapses (the trailing edge of the time-base counter is detected).

0 Time-base timer interrupt request output disabled (initial value)

1 Time-base timer interrupt request output enabled

Table 3.11-1 Interval Settings

TBC2 TBC1 TBC0 Timer interval timeIf the source oscillation is 10 MHz

and PLL is multiplied by 4

0 0 0 φ × 211 51.2 [µs]

0 0 1 φ × 212 102 [µs]

0 1 0 φ × 213 205 [µs]

0 1 1 φ × 222 105 [ms]

1 0 0 φ × 223 210 [ms]

1 0 1 φ × 224 419 [ms]

1 1 0 φ × 225 839 [ms]

1 1 1 φ × 226 1678 [ms]


88


• The initial value is undefined. Be sure to set a value before enabling an interrupt.


[bit10] (reserved bit)

This bit is reserved. The read value is undefined. Writing to this bit has no effect onoperation.

[bit9] SYNCR (SYNChronous Reset enable)

This bit is the synchronous reset enable bit.

This bit specifies whether normal reset operation or synchronous reset operation is executedwhen an operation initialization reset (RST) request occurs. Normal reset operationperforms a reset (RST) immediately. Synchronous reset operation performs an operationinitialization reset (RST) after all bus access has stopped.



Note:

When using the synchronous mode software reset, the following two conditions must besatisfied be before setting the SRST bit in the STCR (standby control register) to "0".

• Set interrupt enable flag (I-Flag) to interrupts disabled (I-Flag)

• NMI not used

[bit8] SYNCS (SYNChronous Standby enable)

This bit is the synchronous standby enable bit.

It is used to select one of the following operations, which is to be used if an standby request(either sleep or stop mode request) occurs: (1) Performing a normal standby operation onlyby writing to the control bit in the STCR register or (2) performing a synchronous standbyoperation by reading the STCR register after writing to the control bit in the STCR register.



0 Normal reset operation (initial value)

1 Synchronous reset operation

0 Normal standby operation (initial value)

1 Synchronous standby operation

89

Changed " Time-Base Counter Control Register (TBCR)". (Added the Note in "[Bit 9] SYNCR (SYNChronous Reset enable)".)


Time-Base Counter Clear Register (CTBR)

Figure 3.11-5 shows the configuration of the time-base counter clear register (CTBR) bits.

Figure 3.11-5 Configuration of Time-Base Counter Clear Register (CTBR) Bits

The time-base counter clear register initializes the time-base counter.

If A5H and 5AH are written successively to this register, all the bits in the time-base counterare cleared to 0 as soon as 5AH is written. There is no time limit between writing of A5H and5AH. However, if data other than 5AH is written after A5H is written, A5H must be writtenagain before 5AH is written. Otherwise, a clear operation will not occur.

Clearing occurs automatically while the CPU is not running, such as in the stop, sleep, or DMAtransfer state. If one of these conditions occurs, a watchdog reset is automatically postponed.However, a watchdog reset is not postponed when an external bus hold request (BRQ) hasbeen accepted. To hold the external bus for a long time, enter sleep mode and then input a holdrequest (BRQ).

Note:

If the time-base counter is cleared using this register, the oscillation stabilization waitinterval, watchdog timer interval, and time-base timer interval temporarily vary.

Clock Source Control Register (CLKR)

Figure 3.11-6 shows the configuration of the clock source control register (CLKR) bits.

Figure 3.11-6 Configuration of Clock Source Control Register (CLKR) Bits

The clock source control register is used to select the clock source that will be used as the baseclock of the system and controls the PLL. Use this register to select one of three clock sources(the MB91310 supports only two of these). This register also enables the main PLL and each ofthe sub-PLLs and selects the multiply-by rate for them.

[bit15] PLL2S0 (PLL2 ratio Select 0)

This bit is the multiply-by rate selection bit for the sub clock.

Select one of the two multiply-by rates for the sub clock.

Always write "0" to this bit for the MB91310.

bit 7 6 5 4 3 2 1 0

W W W W W W W W

Address: 00000483H D7 D6 D5 D4 D3 D2 D1 D0

Initial value (RST) x x x x x x x x Initial value (INIT) x x x x x x x x

bit 15 14 13 12 11 10 9 8

Address: 00000484H PLL2S0 PLL1S2 PLL1S1 PLL1S0 PLL2EN PLL1EN CLKS1 CLKS0

Initial value (RST) x x x x x x x xInitial value (INIT) 0 0 0 0 0 0 0 0


0 Multiply-by rate setting 1 (initial value)

1 Multiply-by rate setting 1

90

Changed " Time-Base Counter Clear Register (CTBR)".




[bit14 to bit12] PLL1S2, PLL1S1, PLL1S0 (PLL1 ratio Select 2-0)

These bits are the multiply-by selection bits for the main PLL. Select one of the eightmultiply-by rates (the MB91310 supports only four of these) shown in Table 3.11-2 .

Note:

Rewriting of this bit is disabled while the main PLL is selected as the clock source. Theupper-limit frequency for operation is 40 MHz. Do not set a multiply-by rate that results in afrequency exceeding this limit.

• These bits are initialized to "000B" by a reset (INIT).


[bit11] PLL2EN (PLL2 ENable)

This is the operation enable bit for the sub clock.

Rewriting of this bit is disabled while the sub clock is selected as the clock source. Selectionof the sub clock as the clock source is disabled while this bit is set to "0" (because of thesettings of bits 9 and 8 [bits CLKS1 and CLKS0]).

The sub clock stops in stop mode even when this bit is set to "1" as long as STCR bit1(OSCD2) is set to "1". After the device returns from the stop mode, the sub clock is enabledagain.



Table 3.11-2 Main PLL Multiply-By Rate Settings

PLL1S2 PLL1S1 PLL1S0Main PLL multiply-

by rate

0 0 0 × 1 (equal) For source oscillator 10 (MHz), φ = 100[ns] (10 (MHz))

0 0 1 × 2 (multiplied by 2) For source oscillator 10 (MHz), φ = 50[ns] (20 (MHz))



1 0 0 × 5 (multiplied by 5) Not supported by the MB91310.





0 Sub clock stopped (initial value)

1 Sub clock enabled

91


[bit10] PLL1EN (PLL1 ENable)

This bit is the enable bit of the main PLL.

Rewriting of this bit is disabled while the main PLL is selected as the clock source. Selectionof the main PLL as the clock source is disabled while this bit is set to "0" (because of thesettings of bits 9 and 8 [bits CLKS1 and CLKS0]).

The main PLL stops in stop mode even when this bit is set to "1" as long as STCR bit1(OSCD2) is set to "1". After the device returns from the stop mode, the main PLL is enabledagain.



[bit9, bit8] CLKS1, CLKS0 (CLocK source Select)

These bits set the clock source that will be used by the FR core.

The values written to these bits determine the clock source, which can be selected from thethree types shown in Table 3.11-3 .

While bit9 (CLKS1) is set to "1", the value of bit8 (CLKS0) cannot be changed. Table 3.11-4 liststhe combinations of bits CLKS1 and CLKS0 that cannot be changed and those that can.

To select the sub clock in the post-INIT state, first write "01" and then write "11".

• These bits are initialized to "00" by a reset (INIT).


From sub clock source X0A/X1A, the source oscillation input with the frequency divided by 2cannot be selected.

0 Main PLL stopped (initial value)

1 Main PLL enabled

Table 3.11-3 Clock Source Settings

CLKS1 CLKS0 Clock source setting

0 0 Source oscillation input from X0/X1 divided by 2 (initial value)

0 1 Source oscillation input from X0/X1 divided by 2

1 0 Main PLL

1 1 Sub clock

Table 3.11-4 Combinations of CLKS1 and CLKS0 Bits that Can and Cannot Be Changed

Cannot be changed Can be changed

"00" --> "11" "00" --> "01" or "10"

"01" --> "10" "01" --> "11" or "00"

"10" --> "01" or "11" "10" --> "00"

"11" --> "00" or "10" "11" --> "01"

92


Base Clock Division Setting Register 0 (DIVR0)

Figure 3.11-8 shows the configuration of the Base Clock Division Setting Register 0 (DIVR0)bits.

Figure 3.11-7 Configuration of Base Clock Division Setting Register 0 (DIVR0) Bits

Base Clock Division Setting Register 0 (DIVR0) controls the divide-by rate of an internal clock inrelation to the base clock. This register sets the divide-by rates of the CPU clock, the clocks ofan internal bus (CLKB) and a peripheral circuit, and the peripheral bus clock (CLKP).

An upper-limit frequency for the operation is prescribed for each clock. If the combination ofsource clock selected, PLL multiply-by rate setting, and divide-by rate setting results in afrequency exceeding this upper-limit frequency, operation is unpredictable. Be extremelycareful of the order in which you change the settings when selecting the source clock.

If the setting in this register is changed, the new frequency-divide-by rate takes effect for theclock rate following the one during which the setting was made.

[bit15 to bit12] B3, B2, B1, B0 (clkB divide select 3-0)

These bits are the clock divide-by rate setting bits of the CPU clock (CLKB). Set the clockdivide-by rate of the CPU, internal memory, and internal bus clock (CLKB). The valueswritten to these bits determine the divide-by rate (clock frequency) of the CPU and internalbus clock in relation to the base clock, which can be selected from the 16 types shown inTable 3.11-5 .

The upper-limit frequency for operation is 40 MHz. Do not set a divide-by rate that results ina frequency exceeding this limit.

bit 15 14 13 12 11 10 9 8

Address: 00000486H B3 B2 B1 B0 P3 P2 P1 P0



Table 3.11-5 Clock Divide-By Rate (CPU Clock ) Settings

B3 B2 B1 B0 Clock divide-by rateClock frequency: if the source oscillation is

10 [MHz] and the PLL is multiplied by 4

0 0 0 0 φ 40 [MHz] (initial value)

0 0 0 1 φ × 2 (divided by 2) 20 [MHz]

0 0 1 0 φ × 3 (divided by 3) 13.3 [MHz]

0 0 1 1 φ × 4 (divided by 4) 10 [MHz]

0 1 0 0 φ × 5 (divided by 5) 8 [MHz]

0 1 0 1 φ × 6 (divided by 6) 6.67 [MHz]

0 1 1 0 φ × 7 (divided by 7) 5.71 [MHz]

0 1 1 1 φ × 8 (divided by 8) 5 [MHz]

... ... ... ... ... ...

1 1 1 1 φ × 16 (divided by 16) 2.5 [MHz]


93


• These bits are initialized to 0000 by a reset (INIT).


[bit11 to bit8] P3, P2, P1, P0 (clkP divide select 3-0)

These bits are the clock divide-by rate setting bits of the peripheral clock (CLKP). Set theclock divide-by rate of the peripheral circuit and the peripheral bus clock (CLKP). The valueswritten to these bits determine the divide-by rate (clock frequency) of the peripheral circuitand the peripheral bus clock in relation to the base clock, which can be selected from the 16types shown in Table 3.11-6 .

The upper-limit frequency for operation is 20 MHz. Do not set a divide-by rate that results ina frequency exceeding this limit.



Base Clock Division Setting Register 1 (DIVR1)

Figure 3.11-8 shows the configuration of the Base Clock Division Setting Register 1 (DIVR1)bits.

Figure 3.11-8 Configuration of Base Clock Division Setting Register 1 (DIVR1) Bits

Base clock division setting register 1 controls the divide-by rate of an internal clock in relation tothe base clock.

This register sets the divide-by rate for the external extended bus interface clock (CLKT).

An upper-limit frequency for the operation is set for each clock. If the combination of source

Table 3.11-6 Clock Divide-by Rate (Peripheral Clock ) Settings

P3 P2 P1 P0 Clock divide-by rateClock frequency: if the source oscillation is 10 [MHz] and the PLL is multiplied by 4

0 0 0 0 φ Setting prohibited

0 0 0 1 φ × 2 (divided by 2) 20 [MHz]

0 0 1 0 φ × 3 (divided by 3) 13.3 [MHz]

0 0 1 1 φ × 4 (divided by 4) 10 [MHz] (initial value)

0 1 0 0 φ × 5 (divided by 5) 8 [MHz]

0 1 0 1 φ × 6 (divided by 6) 6.67 [MHz]

0 1 1 0 φ × 7 (divided by 7) 5.71 [MHz]

0 1 1 1 φ × 8 (divided by 8) 5 [MHz]

... ... ... ... ... ...

1 1 1 1 φ × 16 (divided by 16) 2.5 [MHz]


bit 7 6 5 4 3 2 1 0

Address: 00000487H T3 T2 T1 T0 - - - -



94


clock selected, PLL multiply-by rate setting, and divide-by rate setting results in a frequencyexceeding this upper-limit frequency, operation is unpredictable. (Be extremely careful of theorder in which you change the settings when selecting the source clock.)

If the setting in this register is changed, the new divide-by rate takes effect for the clock ratefollowing the one during which the setting was made.

[bit7 to bit4] T3, T2, T1, T0 (clkT divide select 3-0)

These bits are the clock divide-by rate setting bits of the external bus clock (CLKT). Set theclock divide-by rate of the external extended bus interface clock (CLKT). The values writtento these bits determine the divide-by rate (clock frequency) of the external extended businterface clock in relation to the base clock, which can be selected from the 16 types shownin Table 3.11-7 .

The upper-limit frequency for operation 20 MHz. Do not set adivide-by rate that results in afrequency exceeding this limit.



[bit3 to bit0] (reserved bits)


Table 3.11-7 Clock Divide-By Rate (External Bus Clock) Settings

T3 T2 T1 T0 Clock divide-by rateClock frequency: if the source oscillation is

10 [MHz] and the PLL is multiplied by 4

0 0 0 0 φ Setting prohibited

0 0 0 1 φ × 2 (divided by 2) 20 [MHz]

0 0 1 0 φ × 3 (divided by 3) 13.3 [MHz]

0 0 1 1 φ × 4 (divided by 4) 10 [MHz]

0 1 0 0 φ × 5 (divided by 5) 8 [MHz]

0 1 0 1 φ × 6 (divided by 6) 6.67 [MHz]

0 1 1 0 φ × 7 (divided by 7) 5.71 [MHz]

0 1 1 1 φ × 8 (divided by 8) 5 [MHz]

... ... ... ... ... ...

1 1 1 1 φ × 16 (divided by 16) 2.5 [MHz]


95


Oscillation Control Register (OSCCR)

Figure 3.11-9 shows the bit configuration of the oscillation control register (OSCCR).

Figure 3.11-9 Bit Configuration of Oscillation Control Register (OSCCR)

The oscillation control register controls the main clock oscillation during operation of the subclock.

[bit8] OSCDS1 (OSCillation Disable on Sub clock for XIN1)

This bit is the stop bit for main clock oscillation while the sub clock is selected.

Writing "1" to this bit stops main clock oscillation while the sub clock is selected as the clocksource.

Writing "1" to this bit is disabled while the main clock is selected.

Selection of the main clock is disabled while this bit is set to "1". Set this bit to "0", and waitfor stabilization of the main clock oscillation. Then, switch to the main clock. Use the mainoscillation stabilization wait timer to secure the oscillation stabilization wait time.

If INIT switches the clock source to the main clock when this bit stops main clock oscillation,the main oscillation stabilization wait time is also required. If the settings of bits 3 and 2(OS1 and OS0) of the standby control register (STCR) do not satisfy the main oscillationstabilization wait time, the operation after return is unpredictable. In this case, set valuesthat satisfy both the sub clock oscillation stabilization wait time and the main clock oscillationstabilization wait time in the STCR (OS1 and OS0) bits. For INIT from the INIT pin, an "L"level signal must continue to be input to the INIT pin until main clock oscillation is stabilized.

For details about the oscillation stabilization wait, see Section "3.11.2 OscillationStabilization Wait Time and PLL Lock Wait Time".

• This bit is initialized to "0" after a reset (INIT).

• This bit can be read and written.

bit 15 14 13 12 11 10 9 8

Address: 0000048AH - - - - - - - OSCDS1

Initial value (RST) x x x x x x x xInitial value (INIT) x x x x x x x 0


0 Main clock oscillation is not stopped during execution of sub clock (default value).

1 Main clock oscillation is stopped during execution of sub clock.

96


3.11.7 Peripheral Circuits of Clock Controller

This section describes the peripheral circuit functions of the clock controller.

Time-Base Counter

The clock controller has a 26-bit time-base counter that runs on the system base clock.

The time-base counter is used to measure the oscillation stabilization wait time in addition tohaving the uses listed below (For more information about the oscillation stabilization wait time,see Section "3.10.4 Oscillation Stabilization Wait Time").

• Watchdog timer

The watchdog timer, which is used to detect a system runaway, measures time using the bitoutput of the time-base counter.

• Time-base timer

The time-base timer generates an interval interrupt using output from the time-base counter.

The following describes these functions.

Watchdog timer

The watchdog timer detects a runaway using output from the time-base counter. If a programrunaway results in a watchdog reset no longer being postponed for a specified interval, asettings initialization reset (INIT) request is generated as a watchdog reset.

[Startup and interval setting of the watchdog timer]

The watchdog timer is started when the reset source register and the watchdog timer controlregister (RSRR) are written to for the first time after a reset (RST). At this time, the intervaltime of the watchdog timer is set in bits 9 and 8 (WT1 and WT0 bits). Only the time definedin this first write is valid as the interval time setting. Any further writing is ignored.

[Postponing a watchdog reset]

Once the watchdog timer is started, the program must write A5H and 5AH in this order tothe time-base counter clear register (CTBR). This operation initializes the watchdog resetgeneration flag.

[Generation of a watchdog reset]

The watchdog reset generation flag is set at the trailing edge of the time-base counter outputof the specified interval. If the flag has already been set when a trailing edge is detected asecond time, a settings initialization reset (INIT) request is generated as a watchdog reset.

[Stopping the watchdog timer]

The watchdog timer, once started, cannot be stopped until an operation initialization reset(RST) occurs.

In the following states, when an operation initialization reset (RST) occurs, the watchdogtimer is stopped and remains inoperative until a program starts it.

• Operation initialization reset (RST) state

• Settings initialization reset (INIT) state

• Oscillation stabilization wait reset (RST) state

97

Changed "[Postponing a watchdog reset]". (watchdog reset postpone register(WPR) → Time Base Counter Clear register(CTBR))


[Suspending the watchdog timer (automatic postponement)]

If program operation stops on the CPU, the watchdog reset generation flag is initialized andgeneration of a watchdog reset is postponed. Stopping of program operation specificallyrefers to the following statuses:

• Sleep state

• Stop state

• Oscillation stabilization wait RUN state

• DMA transfer in progress on the data bus (D-bus)

• Emulation mode

If the time-base counter is cleared, the watchdog reset generation flag is initialized at the sametime, postponing generation of a watchdog reset.

Time-base timer

The time-base timer generates an interval using output from the time-base counter. This timeris appropriate for measurements that require a relatively long time (for example, a maximum

interval of base clock × 227 cycles such as for the PLL lock wait time or a sub block.

If the trailing edge of the time-base counter output for the specified interval is detected, a time-base timer interrupt request is generated.

[Startup and interval settings of the time-base timer]

For the time-base timer, the interval time is set in bits 13-11 (TBC2, TBC1, and TBC0 bits) ofthe time-base counter control register (TBCR). The trailing edge of the time-base counteroutput for the specified interval is always detected. Thus, after setting the interval time, clearbit15 (TBIF bit) and then set bit14 (TBIE bit) to "1" to enable output of an interrupt request.

Before changing the interval time, set bit14 (TBIE bit ) to "0" to disable interrupt requestoutput.

Since the time-base counter always counts regardless of these settings, before enablinginterrupts, clear the time-base counter to obtain an accurate interval interrupt time.Otherwise, an interrupt request may be generated immediately after an interrupt is enabled.

[Clearing of the time-base counter due to a program]

If A5H and 5AH are written in this order to the time-base counter clear register (CTBR), allbits of the time-base counter are cleared to "0" immediately after 5AH is written. There isno time limit between writing of A5H and 5AH. However, if data other than 5AH is writtenafter A5H is written, A5H must be written again before 5AH is written. Otherwise, noclear operation occurs.

If the time-base counter is cleared, the watchdog reset generation flag is initialized at thesame time, postponing generation of a watchdog reset.

98


[Clearing of the time-base counter due to the device state]

All bits of the time-base counter are cleared to 0 at the same time if the device enters one ofthe following states:

• Stop state

• Settings initialization reset (INIT) state

Especially in the stop state, an interval interrupt of the time-base timer may unintentionally begenerated because the time-base counter is used to measure the oscillation stabilization waittime. Before setting stop mode, therefore, disable time-base timer interrupts to prevent thetime- base timer from being used.

In any other state, time-base timer interrupts are automatically disabled because an operationinitialization reset (RST) occurs.

Watch Timer

The watch timer is a 15-bit free-run timer that performs incremental counting in synchronizationwith the 32 kHz sub clock. The operation of this timer is not affected by the clock sourceselection or the clock divide-by rate.

The watch timer is used to measure the sub clock stabilization wait time and perform processingat fixed intervals using the sub clock.

The watch timer performs incremental counting while the sub clock is operating and is stoppedwhen bit1 (OSCD2 bit) of the standby control register (STCR) is set to "1" so that the watchtimer enters stop mode. To prevent the watch timer from being stopped in stop mode, set theOSCD2 bit to "0" before the watch timer enters stop mode so that the sub clock is not stopped.

Follow the procedure below for switching the clock source from the main clock to sub clockusing the watch timer:

1. Set the watch timer for the oscillation stabilization wait time. If necessary, clear all bits of thewatch timer to "0".

2. Set bit11 (PLL2EN bit) of the clock source register(CLKR) to "1" to start sub clock oscillation.

3. Use the watch timer to wait until the sub clock is stabilized. At this time, use a watchinterrupt to secure the oscillation stabilization wait time.

4. After the sub clock has been stabilized, use bits 9 and 8 (CLKS1 and CLKS0 bits) of theclock source register (CLKR) to switch the clock source from the main clock to sub clock. Ifthe clock source is switched to the sub clock before the sub clock is stabilized, an unstableclock is supplied and subsequent operation is unpredictable. Be sure to switch to the subclock after the sub clock has been stabilized.

For more information on the watch timer, see Section "3.13 Watch Timer".

99


Main Clock Oscillation Stabilization Wait Timer (for the sub clock select)

The main clock oscillation stabilization wait timer is a 26-bit free-run timer that performsincremental counting in synchronization with the main clock. The operation of this timer is notaffected by the clock source selection or the clock divide-by rate.

The main clock oscillation stabilization wait timer is used to measure the main clock oscillationstabilization wait time.

Main clock oscillation can be controlled by bit8 (OSCDS1 bit) of the oscillation control register(OSCCR) while the device is operating on the sub clock. This timer is used to measure theoscillation stabilization wait time when main clock oscillation is restarted after it has beenstopped.

Follow the procedure below for switching the clock source to the main clock when the device isoperating on the sub clock with the main clock stopped.

1. Clear the main clock oscillation stabilization wait timer.

2. Set bit8 (OSCDS1 bit) of the oscillation control register (OSCCR) to "0" to start main clockoscillation.

3. Use the main clock oscillation stabilization wait timer to wait until the main clock oscillation isstabilized.

4. After the main clock has been stabilized, use bits 9 and 8 (CLKS1 and CLKS0 bits) of theclock source register (CLKR) to switch the clock source from the main clock to sub clock. Ifthe clock source is switched to the main clock before the main clock is stabilized, anunstable clock is supplied and subsequent operation is unpredictable. Be sure to switch tothe main clock after the main clock has been stabilized.

For more information on the main clock oscillation stabilization wait timer, see Section "3.14Main Clock Oscillation Stabilization Wait Timer".

100



This section describes the states of the MB91310 and their control.

Device State Control

3.12.1 Device States and State Transitions

3.12.2 Low-power Modes

101


3.12.1 Device States and State Transitions

This section describes device operating states and the transition between operating states.

Transition of Device States

Figure 3.12-1 shows the transition of device states.

Figure 3.12-1 Transition of Device States

Main clock oscillation stabilization wait reset

Power-on

Setting initialization reset (INIT)

Program reset (RST)

Main clock RUNMain clock sleep

Main clock stop

Sub clock RUNSub clock sleep

Sub clock stop (watch state[*2])

1

2

3

4

4

5

5

7

7

8

8

9

9

3

3

11

1

1

1

1

1

1

1

1

1

1

1

Main clock mode

Sub clock mode

12

12345678910

11

1213

INIT pin = 0 (INIT)INIT pin = 1 (clearance of INIT state)End of oscillation stabilization wait timeRelease from reset (RST) stateSoftware reset (RST)Entry to sleep state (writing of instruction)Entry to stop state (writing of instruction)InterruptExternal interrupt not requiring a clockSwitching from main clock to sub clock(writing of instruction)Switching from sub clock to main clock(writing of instruction)Watchdog timer reset (INT)Entry to sub clock sleep state (writing of instruction)

Highest

Lowest

Priority of state transition requestsSettings initialization reset (INIT) requestEnd of oscillation stabilization wait timeOperation initialization reset (RST) requestInterrupt requestStop mode requestSleep mode request

Oscillation stabilization wait RUN

Program reset (RST)

12

13

10

6

Oscillation stabilization wait RUN

102


Notes:

*1 To switch the clock source between the main clock and sub clock, change the status ofbits 1 and 0 (CLKS1 and CLKS0 bits) of the clock source register (CLKR) in the RUNstate after oscillation of the switch-destination clock has been stabilized.

*2 To stop a circuit other than the watch timer in the watch state, set bit1 (OSCD2 bit) of thestandby control register (STCR) to "0" in the sub clock RUN state then change to stopmode.

RUN State (Normal Operation)

In the RUN state, a program is being executed. All internal clocks are supplied and all circuitsare enabled.

For the 16-bit peripheral bus, however, only the bus clock is stopped, when it is not beingaccessed.

State transition request is accepted. If synchronous reset mode is selected, however, statetransition operations different from normal reset mode are used for some requests. For moreinformation, see "Synchronous Reset Operation" in Section "3.10.5 Reset Operation Modes".

Sleep State

In the sleep state, a program is stopped. Program operation causes a transition to this state.

Only execution of the program on the CPU is stopped; peripheral circuits are enabled. Theinstruction cache is stopped and the built-in memory modules and the internal and externalbuses are stopped unless the DMA controller issues a request.

If a valid interrupt request occurs, the state is cleared and the RUN state (normal operation)is entered.

If a settings initialization reset (INIT) request occurs, the settings initialization reset (INIT)state is entered.

If an operation initialization reset (RST) request occurs, the operation initialization reset(RST) state is entered.

Stop State

In the stop state, the device is stopped. Program operation causes a transition to this state.

All internal circuits are stopped. All internal clocks are stopped and the oscillation circuit andPLL can be stopped if set to do so.

In addition, the external pins (except some) can be set to high impedance via settings.

If a specific valid interrupt request (no clock required) occurs, the oscillation stabilizationwait RUN state is entered.


If an operation initialization reset (RST) request occurs, the oscillation stabilization waitreset (RST) state is entered.

103


Oscillation Stabilization Wait RUN State

In the oscillation stabilization wait RUN state, the device is stopped. This state occurs after areturn from the stop state.

All internal circuits except the clock generation controller (time-base counter and device statecontroller) are stopped. All internal clocks are stopped, but the oscillation circuit and the PLLthat has been enabled are running.

High impedance control of external pins in the stop or other state is cleared.

If the specified oscillation stabilization wait time elapses, the RUN state (normal operation) isentered.


If an operation initialization reset (RST) request occurs, the oscillation stabilization wait reset(RST) state is entered.

Oscillation Stabilization Wait Reset (RST) Status

In the oscillation stabilization wait reset (RST) state, the device is stopped. This state occursafter a return from the stop state or the settings initialization reset (INIT) state. All internalcircuits except the clock generation controller (time-base counter and device state controller)are stopped. All internal clocks are stopped, but the oscillation circuit and the PLL that hasbeen enabled are running.

• High impedance control of external pins in the stop state, etc., is cleared.

• An operation initialization reset (RST) is output to the internal circuits.

• If the specified oscillation stabilization wait time elapses, the oscillation stabilization waitreset (RST) state is entered.

• If a settings initialization reset (INIT) request occurs, the settings initialization reset (INIT)state is entered.

Operation Initialization Reset (RST) State

In the operation initialization reset (RST) state, a program is initialized. This state occurs if anoperation initialization reset (RST) request is accepted or the oscillation stabilization wait reset(RST) state is ended.

Execution of a program on the CPU is stopped and the program counter is initialized. Mostperipheral circuits are initialized. All internal clocks are stopped, but the oscillation circuit andthe PLL that has been enabled are running.

• An operation initialization reset (RST) is output to the internal circuits.

• If an operation initialization reset (RST) no longer exists, the RUN state (normal operation) isentered and the operation initialization reset sequence is executed. After a return from thesettings initialization reset (INIT), the settings initialization reset sequence is executed.

• If a settings initialization reset (INIT) request occurs, the settings initialization reset (INIT)state is entered.

104


Settings Initialization Reset (INIT) State

In the settings initialization reset (INIT) state, all settings are initialized. This state occurs if asettings initialization reset (INIT) is accepted or the hardware standby state is ended.

Execution of a program on the CPU is stopped and the program counter is initialized. Allperipheral circuits are initialized. The oscillation circuit runs, but the PLL stops running. Allinternal clocks are stopped while the "L" level is input to the external INIT pin; otherwise, theyrun.

• A settings initialization reset (INIT) and an operation initialization reset (RST) are output tothe internal circuits.

• If a settings initialization reset (INIT) no longer exists, the state is cleared and the oscillationstabilization wait reset (RST) state is entered. Then, the operation initialization reset (RST)state is entered and the settings initialization reset sequence is executed.

Priority of State Transition Requests

In any state, state transition requests conform to the priority listed below. However, somerequests that occur only in a specific state are valid only in that state.

[Highest] Settings initialization reset (INIT) request

Hardware standby request

End of oscillation stabilization wait time (occurs only in the oscillation stabilization wait reset state and the oscillation stabilization wait RUN state)

Operation initialization reset (RST) request

Valid interrupt request (occurs only in the RUN, sleep, and stop states)

[Lowest] Stop mode request (writing to a register) (occurs only in the RUN state)

105


3.12.2 Low-power Modes

This section describes the low-power modes, some MB91310 states, and how to use the low-power modes.

Low-power Modes

The MB91310 has the following two low-power modes:

• Sleep mode: The device enters the sleep state due to writing to a register.

• Stop mode: The device enters the stop state due to writing to a register.

These modes are described below.

Sleep mode

If "1" is set for bit6 (SLEEP bit) of the standby control register (STCR), sleep mode is initiatedand the device enters the sleep state. The sleep state is maintained until a source for returnfrom the sleep state is generated.

If "1" is set for both bit7 (STOP bit) and bit6 of the standby control register (STCR), bit7 (STOPbit) has precedence and the device enters the stop state.

For more information about the sleep state, see "Sleep State" in Section "3.12.1 Device Statesand State Transitions".

[Transition to Sleep Mode]

To enter the sleep mode, use the synchronous standby mode (set with the SYNCS bit as bit8 inthe TBCR, or time-base counter control register) and be sure to use the following sequence:

/* Writing STCR */




/* Writing CTBR */











nop

nop

nop

nop

106

Changed " Sleep mode" of " Low-power Modes". (Added the "[Transition to Sleep Mode]" and "[Transition to Stop Mode]".)


[Transition to Stop Mode]

To enter the stop mode, use the synchronous standby mode (set with the SYNCS bit as bit8 inthe TBCR, or time-base counter control register) and be sure to use the following sequence:

/* Writing STCR */




/* Writing CTBR */











nop

nop

nop

nop

[Circus that stop in the sleep state]

• Program execution on the CPU

• Data cache

• Bit search module (enabled if DMA transfer occurs)

• Various built-in memory (enabled if DMA transfer occurs)

• Internal types of and external buses (enabled if DMA transfer occurs)

[Circuits that do not stop in the sleep state]

• Oscillation circuit

• PLL that has been enabled

• Clock generation controller

• Interrupt controller

• Peripheral circuit

• DMA controller

• DSU

[Sources of return from the sleep state]

• Generation of a valid interrupt request

If an interrupt request with an interrupt level other than interrupt disabled (1FH) occurs, sleepmode is cleared and the RUN state (normal operation state) is entered.

107

Changed " Sleep mode" of " Low-power Modes". (Added the "[Transition to Sleep Mode]" and "[Transition to Stop Mode]".)


To prevent sleep mode from being cleared even when an interrupt request occurs, setinterrupt disabled (1FH) as the interrupt level in the corresponding ICR.

• Generation of a settings initialization reset (INIT) request

If a settings initialization reset (INIT) request occurs, the settings initialization reset (INIT)state is unconditionally entered.

• Generation of an operation initialization reset (RST)

If an operation initialization reset (RST) occurs, the operation initialization reset (RST) stateis unconditionally entered.

Note:

For information about the priority of sources, see "Priority of State Transition Requests" inSection "3.12.1 Device States and State Transitions".

[Normal and synchronous standby operations]

If "1" is set for bit8 (SYNCS bit) of the time-base counter control register (TBCR), synchronousstandby operation is enabled. In this case, simply writing to the SLEEP bit does not cause atransition to the sleep state. Instead, writing to the SLEEP bit and then reading the STCRregister causes a transition to the sleep state.

If "0" is set for the SYNCS bit, normal standby operation is selected. In this case, simply writingto the SLEEP bit causes a transition to the sleep state.

If, in normal standby operation, the value set for the divide-by rate of the peripheral clock(CLKP) is larger than the CPU clock (CLKB), many instructions are executed before writing tothe SLEEP bit actually occurs. Thus, after the write instruction to the SLEEP bit, the samenumber of NOP instructions as 5 + (CPU clock divide-by rate/peripheral clock divide-by rate)instructions or more must be inserted. Otherwise, subsequent instructions are executed beforethe transition to the sleep state.

In synchronous standby operation, the sleep state occurs only after writing to the SLEEP bitactually occurs and reading of the STCR register are completed. This is because the CPU usesthe bus until the value read from the STCR register is stored in the CPU. Thus, in any setting ofthe relationship between the divide-by rates of the CPU clock (CLKB) and the peripheral clock(CLKP), insert only two NOP instructions after the write instruction for the SLEEP bit and theread instruction for the STCR register to prevent any subsequent instructions from beingexecuted before transition to the sleep state.

Stop mode

If "1" is set for bit7 (STOP bit) of the standby control register (STCR), stop mode is initiated andthe device enters the stop state. The stop state is maintained until a source for return from thestop state occurs.

If "1" is set for both bit6 (SLEEP bit) and bit7 bit of the standby control register (STCR), bit7(STOP bit) has precedence and the device enters the stop state.

For more information about the stop state, see "Stop State" in Section "3.12.1 Device Statesand State Transitions".

108


[Circuits that stop in the stop state]

• Oscillation circuits set to stop

If "1" is set for bit1 (OSCD2 bit) of the standby control register (STCR), the sub clockoscillation circuit in the stop state is stopped. If "1" is set for bit0 (OSCD1 bit) of the standbycontrol register (STCR), the main clock oscillation circuit in the stop state is stopped.

• PLL connected to the oscillation circuit that is either disabled or set to stop

If "1" is set for bit1 (OSCD2 bit) of the standby control register (STCR) and "1" is set for bit11(PLL2EN bit) of the clock source control register (CLKR), the sub clock PLL in the stop stateis stopped. If "1" is set for bit0 (OSCD1 bit) of the standby control register (STCR) and "1" isset for bit10 (PLL1EN bit) of the clock source control register (CLKR), the main clock PLL inthe stop state is stopped.

• All internal circuits except those, described below, that do not stop in the stop state

[Circuits that do not stop in the stop state]

• Oscillation circuits that are set not to stop

• If "0" is set for bit1 (OSCD2 bit) of the standby control register (STCR), the sub clockoscillation circuit in the stop state is not stopped.

• If "0" is set for bit0 (OSCD1 bit) of the standby control register (STCR), the main clockoscillation circuit in the stop state is not stopped.

• PLL connected to the oscillation circuit that is enabled and is not set to stop

• If "0" is set for bit1 (OSCD2 bit) of the standby control register (STCR) and "1" is set forbit11 (PLL2EN bit) of the clock source control register (CLKR), the sub clock PLL in thestop state is not stopped.

• If "0" is set for bit0 (OSCD1 bit) of the standby control register (STCR) and "1" is set forbit10 (PLL1EN bit) of the clock source control register (CLKR), the main clock PLL in thestop state is not stopped.

[High impedance control of a pin in the stop state]

If "1" is set for bit5 (HIZ bit) of the standby control register (STCR), the output of a pin in the stopstate is set to the high impedance state.

See Appendix/ "Pin states of Each CPU State" for the pins subject this type of control.

If bit5 (HIZ bit) of the standby control register (STCR) is set to "0", the pin outputs in the stopstate maintain the values set before transition to the stop state.

For details see Appendix/ "Pin States of Each CPU State".

[Sources of return from the stop state]

• Generation of a specific valid interrupt request (not requiring a clock)

Only the external interrupt input pins (INTn pins), main clock oscillation stabilization waittimer interrupt during main clock oscillation, and watch interrupt during sub clock oscillationare enabled.

If an interrupt request with an interrupt level other than interrupt disabled (1FH) occurs, stopmode is cleared and the RUN state (normal operation state) is entered.

To prevent stop mode from being cleared even when an interrupt request occurs, setinterrupt disabled (1FH) as the interrupt level in the corresponding ICR.

• Generation of a settings initialization reset (INIT) request

If a settings initialization reset (INIT) request occurs, the settings initialization reset (INIT) isunconditionally entered.

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• Generation of an operation initialization reset (RST)

If an operation initialization reset (RST) occurs, the operation initialization reset (RST) isunconditionally entered.

Note:

For information about the priority of sources, see "Priority of State Transition Requests" inSection "3.12.1 Device States and State Transitions".

[Selecting a clock source in stop mode]

Select the main clock divided by 2 as the source clock before setting stop mode. For moreinformation, see Section "3.11 Clock Generation Control" especially Section "3.11.1 PLLControls".

The same limitations as in the normal operation apply to the setting of a divide-by rate.

[Normal and synchronous standby operations]

If "1" is set for bit8 (SYNCS bit) of the time-base counter control register (TBCR), synchronousstandby operation is enabled. In this case, simply writing to the STOP bit does not cause atransition to the stop state. Instead, writing to the STOP bit and then reading the STCR registercauses a transition to the stop state. If "0" is set for the SYNCS bit, normal standby operation isselected. In this case, simply writing to the STOP bit causes a transition to the stop state.

If, in normal standby operation, the value set for the divide-by rate of the peripheral clock(CLKP) is larger than the CPU clock (CLKB), many instructions are executed before writing tothe STOP bit actually occurs. Thus, after the write instruction to the STOP bit, the samenumber of NOP instructions as 5 + (CPU clock divide-by rate/peripheral clock divide-by rate)instructions or more must be inserted. Otherwise, subsequent instructions are executed beforethe transition to the stop state.

In synchronous standby operation, the stop state occurs only after writing to the STOP bitactually occurs and the reading of STCR register are completed. This is because the CPU usesthe bus until the value read from the STCR register is stored into the CPU. Thus, in any settingof relationship between divide-by rates of the CPU clock (CLKB) and the peripheral clock(CLKP), insert only two NOP instructions after the write instruction for the STOP bit and the readinstruction for the STCR register to prevent any subsequent instructions from being executedbefore transition to the stop state.

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3.13 Watch Timer

3.13 Watch Timer

The watch timer is a 15-bit free-run timer that performs incremental counting in synchronization with the sub clock. The watch timer has an interval timer function to generate interrupts repeatedly at fixed time intervals.The internal time can be selected from four types as follow.

Watch Timer

Table 3.13-1 Interval Timer of the Watch Timer

Sub clock cycle Interval time

1/FCL (about 30.5 µs)• FCL indicates the sub clock oscillation

frequency.

210/FCL (31.25ms)

213/FCL (0.25s)

214/FCL (0.50s)

215/FCL (1.00s)

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Block Diagram

Figure 3.13-1 shows the block diagram of the watch timer.

Figure 3.13-1 Block Diagram of the Watch Timer

Watch timer

The watch timer is a 15-bit incremental counter that uses the sub clock source oscillation as thecount clock.

Counter clear circuit

The counter clear circuit clears the counter not only when the WCL bit of the WPCR register isset to "0" but also when a reset (INIT) request is generated.

Interval timer selector

The interval timer selector selects one of the four frequency-divide outputs of the watch timercounter for the interval timer. The trailing edge of the selected frequency-divide output becomesan interrupt source.

Watch timer control register (WPCR)

The watch timer control register is used to select the interval time, clear the counter, controlinterrupts, and check the counter status.

215 214 213 212 211 210 29 28 27 26 25 24 23 22 21

14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


(31.25ms)

(0.25s)

(0.5s)

(1.0s)

WIF WIE WS1 WS0 WCL


FCL

Watch timer control register (WPCR)

Reset (INIT)

Watch timer counter

Watch timer interrupt

FCL: Sub clock source oscillationThe numbers in parentheses indicate the intervals when the sub clock source oscillation frequency is 32.768 kHz.

112

3.13 Watch Timer

Watch Timer Control Register

Figure 3.13-2 shows the bit configuration of the watch timer control register.

Figure 3.13-2 Bit Configuration of Watch Timer Control Register

[bit15] WIF (watch timer interrupt flag)

This bit is the watch timer interrupt flag.

This bit is set to "1" at the trailing edge of the selected frequency-divide output for the intervaltimer.

If this bit and the watch timer interrupt enable bit are "1", a watch timer interrupt request isoutput.

• This bit is cleared to "0" by a reset (INIT) request.

• Data can be written to and read from this bit. However, only "0" can be written. If an attemptis made to write "1" to this bit, its value is not changed.

• If a read modify write instruction is issued, "1" is always read from this bit.

[bit14] WIE (watch timer interrupt enable)

This bit enables or disables the interrupt request output to the CPU. If this bit and the watchtimer interrupt flag bit are "1", a watch timer interrupt request is output.


• Data can be written to and read from this bit.


These bits are reserved. When writing data to these bits, be sure to write "000B". (Writing of"111B" to these bits is prohibited.)

Data read from these bits is undefined.

[bit10, bit9] WS1, WS0 (watch timer interval select 1, 0)

These bits select the interval of the interval timer.

One of the following four intervals is selected according to the output bits of the watch timercounter:

Initial value WPCR bit 15 14 13 12 11 10 9 8 At INIT At RST Access 0000 048C H WIF WIE WS1 WS0 WCL 00 xx R/W

R/W R/W R/W R/W W H

H

0 Watch timer interrupt not requested (default value)

1 Watch timer interrupt requested

0 Output of watch timer interrupt request disabled (default value)

1 Output of watch timer interrupt request disabled

WS1 WS0 Interval timer interval (at FCL = 32.768 kHz)

0 0 210/FCL (31.25 ms) (default value)

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• These bits are cleared to "00" by a reset (INIT) request.

• Data can be written to and read from these bits.

[bit8] WCL (watch timer clear)

Writing "0" to this bit clears the watch timer to 0.

• Only "0" can be written to this bit. Writing "1" to this bit does not affect timer operation.

• The value read from this bit is always "1".

Watch Timer Interrupt

If the set interval time elapses while the watch timer counter is counting with the sub clock, thewatch timer interrupt flag (WIF) is set to "1". Then, if the watch timer interrupt enable bit (WIE)has been set to "1" (interrupt output enabled), an interrupt request is output to the CPU. Notethat watch interrupts do not occur when sub clock oscillation is stopped (see the next Item,"Operation of interval timer function") because counting is stopped when the sub clock isstopped.

To clear an interrupt request, write "0" to the WIF bit using the interrupt processing routine.Note that the WIF bit is set to "1" at the trailing edge of the selected frequency-divide outputregardless of the value of the WIE bit.

Note:

The WIF and WCL bits must be cleared to "0" (WIF=WCL=0) at the same time if watch timerinterrupt request output is to be enabled (WIE = 1) or the value of the WS1 and WS0 bits areto be changed after release from the reset state.

References:

• If the WIE bit is changed from "0" to "1" to enable interrupt output when the WIF bit is "1", aninterrupt request is output immediately.

• If a counter clear (WCL bit of WPCR is "1") and overflow of selected bits occur at the sametime, the WIF bit is not set to "1".

0 1 213/FCL (0.25s)

1 0 214/FCL (0.50s)

1 1 215/FCL (1.00s)

WS1 WS0 Interval timer interval (at FCL = 32.768 kHz)

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3.13 Watch Timer

Operation of Interval Timer Function

The watch timer counter continues incremental counting while the sub clock is running. Whensub clock oscillation stops, counting stops in the following cases:

• Counting stops when bit11 (PLL2EN) of the clock source register (CLKR) is "0".

On the MB91310, the PLL2EN is cleared to "0" at reset by an INIT request. To use thewatch timer, write "1" to the PLL2EN bit to start sub clock oscillation.

• Counting is stopped throughout stop mode if the MB91310 is put into stop mode by stoppingsub clock oscillation with bit1 [OSCD2 bit] of the standby control register [STCR] set to "1".To make the watch timer operate in stop mode, set the OSCD2 bit to "0" before entry to thestandby state, because the OSCD2 bit is initialized to "1" at reset by an INIT request.

If the counter is cleared (WCL bit is cleared to "0"), the counter starts counting from 0000H.When the count reaches 7FFFH, the counter restarts counting from 0000H. When the trailingedge of the frequency-divide output selected for the interval timer is detected, the watchtimer interrupt flag (WIF) bit is set to "1". In other words, a watch timer interrupt request isgenerated at the selected intervals on the basis of the selected interval time.

Operation of Clock Supply Function

The MB91310 uses a time-base counter to secure the oscillation stabilization wait time afterINIT or stop mode. On the other hand, the MB91310 uses the watch timer to secure the subclock oscillation stabilization wait time while the main clock is selected as the clock source. Thisis because the watch timer operates with the sub clock regardless of clock source selection.

Follow the procedure below to perform sub clock oscillation stabilization wait operation while theMB91310 is operating on the main clock:

1. Set the interval time for the watch timer to 1 second (when FCL = 32.768 kHz), and clear thecounter to 0 (by writing "11" to the WS1 and WS0 bits and "0" to the WCL bit).If it is necessary to perform processing after the end of the oscillation stabilization wait withan interrupt, initialize the interrupt flag (by writing "0" to the WIF bit and "1" to WIE bit).

2. Start sub clock oscillation (by writing "1" to bit11 [PLL2EN bit] of CLKR).

3. In the program, wait until the WIF bit is set to "1".

4. Make sure that the WIF bit has been set to "1", then perform the processing to be done afterthe end of the oscillation stabilization wait. If interrupts are enabled, an interrupt isgenerated when the WIF bit is set to "1". Then, perform the processing to be done after theend of the oscillation stabilization wait by an interrupt routine. If it is necessary to switch theclock source from the main clock to sub clock, switch the clock source after making sure thatthe WIF bit has been set to "1" as described above. (If the clock source is switched to thesub clock before sub clock oscillation is stabilized, unstable clock is supplied to the entiredevice and subsequent operation is unpredictable.)

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Operation of The Watch Timer

Figure 3.13-3 shows the counter states at start of watch timer, switching to the sub clock, andtransition to stop mode during operation with the sub clock.

Figure 3.13-3 Counter States at Transition to Stop Mode

Precautions for Using the Watch Timer

• Use the oscillation stabilization wait time as a reference value because the oscillation cycleis unstable immediately after oscillation is started.

• No timer interrupt is generated while sub clock oscillation is stopped because the watchtimer is stopped when sub clock oscillation is stopped. Do not stop sub clock oscillation if itis necessary to use the watch timer for processing.

• If a WIF setting request occurs at the same time as a zero-clearance request from the CPU,the WIF setting request has priority and the zero-clearance request is ignored.

Sub clock Sub clock

- Timer clearance (WCL bit = 1) (other than 0)- Timer interval selection (WS1 and WS0 bits = 11B)- Start of sub clock oscillation (PLL2EN bit of CLKR = 1)

Cleared by interrupt routine

Sub clock oscillation stabilization wait time

Interval time

7FFF H

4000 H

WIF

Clock source

Clock modeRUN RUN

Stop *1

- Change of interval time (WS1 and WS0 bits = 10B)- Switching from main clock to sub clock

*1 When the OSCD2 bit of STCR is set to “0” (oscillation is not stopped in stop mode)

Value of counter

Instruction to enter stop mode

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The main clock oscillation stabilization wait timer is a 23-bit free-run timer that performs incremental counting in synchronization with the main clock. The main clock oscillation stabilization wait timer has an interval timer function to generate interrupts repeatedly at fixed time intervals. This timer is used to secure main clock oscillation stabilization wait time when main clock oscillation is restarted after it has been stopped by setting bit8 (OSCDS1) of the oscillation control register (OSCCR) during operation with the sub clock.The interval time can be selected from three types as follow.

Main Clock Oscillation Stabilization Wait Timer

Table 3.14-1 Time Intervals for Main Clock Oscillation Stabilization Wait Timer

Main clock interval Interval time

1/FCL (about 100 ns)• FCL indicates the main clock oscillation frequency.

212/FCL (410 µs)

217/FCL (13.1 ms)

223/FCL (839 ms)

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Block Diagram

Figure 3.14-1 Block Diagram of the Main Clock Oscillation Stabilization Wait Timer

Main clock oscillation stabilization wait timer

The main clock oscillation stabilization wait timer is a 32-bit incremental counter that uses themain clock source oscillation as the count clock.


The counter clear circuit clears the counter not only when the WCL bit of the OSCR register isset to "0" but also when a reset (INIT) request is generated.


The interval timer selector selects one of the three frequency-divide outputs of the main clockoscillation stabilization wait timer counter for the interval timer. The trailing edge of the selectedfrequency-divide output becomes an interrupt source.

Main clock oscillation stabilization wait timer control register (OSCR)

The main clock oscillation stabilization wait timer control register is used to select the intervaltime, clear the counter, control interrupts, and check counter status.

223217 212 29 28 27 26 25 24 23 22 21

22 16 11 8 7 6 5 4 3 2 1 0


(13.1ms) (839ms)

WIF WIE WS1 WS0 WCL


FCL

Main clock oscillation stabilization wait timer interrupt request

Main clock oscillation stabilization wait timer control register (OSCR)

FCL: Main clock source oscillationThe numbers in parentheses indicate the intervalswhen the main clock source oscillation frequency is 10 MHz.

Reset (INIT)

Main clock oscillation stabilization wait timer counter

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Main Clock Oscillation Stabilization Wait Timer Control Register

Figure 3.14-2 shows the bit configuration of the main clock oscillation stabilization wait timercontrol register.

Figure 3.14-2 Bit Configuration of Main Clock Oscillation Stabilization Wait Timer Control Register

[bit15] WIF (watch timer interrupt flag)

This bit is the main clock oscillation stabilization wait timer interrupt flag.

This bit is set to "1" at the trailing edge of the selected divided output for the interval timer.

If this bit and the main clock oscillation stabilization wait timer interrupt enable bit are 1, amain clock oscillation stabilization wait timer interrupt request is output.


• Data can be written to and read from this bit. However, only "0" can be written. If an attemptis made to write "1" to this bit, its value is not changed.

• If a read modify write instruction is issued, "1" is always read from this bit.

[bit14] WIE (watch timer interrupt enable)

This bit enables or disables the interrupt request output to the CPU. If this bit and main clockoscillation stabilization wait timer interrupt flag bit are "1", a main clock oscillationstabilization wait timer interrupt request is output.


• Data can be written to and read from this bit.


These bits are reserved. When writing data to these bits, be sure to write "00B" to these bits.(Writing of "11B" to these bits is prohibited.)

Data read from these bits are undefined.

[bit10, bit9] WS1, WS0 (watch timer interval select 1, 0)

These bits select the interval of the interval timer.

One of the following three intervals is selected according to the output bits of the main clock

Initial value OSCR 15 14 13 12 11 10 9 8 At INIT At RST Access 0000 0490H WIF WIE WS1 WS0 WCL 00 xx R/W

R/W R/W R/W R/W W H H

bit

0 Main clock oscillation stabilization wait timer interrupt not requested (default value)

1 Main clock oscillation stabilization wait timer interrupt requested

0 Output of main clock oscillation stabilization wait timer interrupt request disabled (default value)

1 Output of main clock oscillation stabilization wait timer interrupt request disabled

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oscillation stabilization wait timer counter:

• These bits are cleared to "00B" by a reset (INIT) request.

• Data can be written to and read from these bits.

[bit8] WCL (watch timer clear)

Writing "0" to this bit clears the main clock oscillation stabilization wait timer to "0".

• Only "0" can be written to this bit. Writing "1" to this bit does not affect timer operation.

• The value read from this bit is always "1".

Main Clock Oscillation Stabilization Wait Timer Interrupt

If the set interval time elapses while the main clock oscillation stabilization wait timer counter iscounting with the main clock, the main clock oscillation stabilization wait timer interrupt flag(WIF) is set to "1". Then, if the main clock oscillation stabilization wait timer interrupt enable bit(WIE) is set to "1" (interrupt output is enabled), an interrupt request is output to the CPU. Notethat watch interrupts do not occur when main clock oscillation is stopped (see the next Item,"Operation of interval timer function") because counting is stopped when the main clock isstopped.

To clear an interrupt request, write "0" to the WIF bit by the interrupt processing routine. Notethat the WIF bit is set to "1" at the trailing edge of the selected frequency-divide outputregardless of the value of the WIE bit.

Note:

The WIF and WCL bits must be cleared to "0" (WIF=WCL=0) at the same time if main clockoscillation stabilization wait timer interrupt output is to be enabled (WIE = 1) or the value ofthe WS1 and WS0 bits are to be changed after release from the reset state.

References:

• If the WIE bit is changed from "0" to "1" to enable interrupt output when the WIF bit is "1", aninterrupt request is output immediately.

• If a counter clear (WCL bit of WPCR is "1") and overflow of selected bits occur at the sametime, the WIF bit is not set to "1".

WS1 WS0 Interval timer interval (at FCL = 10 MHz)

0 0 Setting prohibited

0 1 212/FCL (410 µs) (default value)

1 0 217/FCL (13.1 ms)

1 1 223/FCL (839 ms)

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Operation of Interval Timer Function

The main clock oscillation stabilization wait timer counter continues incremental counting whilethe main clock is oscillated. When main clock oscillation stops, counting stops in the followingcase:

• Counting is stopped throughout stop mode if the MB91310 is put into stop mode by stoppingsub clock oscillation with bit0 [OSCD1 bit] of the standby control register [STCR] set to "1".To make the main clock oscillation stabilization wait timer operate in stop mode, set theOSCD2 bit to "0" before entry into the standby state because the OSCD1 bit is initialized to"1" at reset by an INIT request.

If the counter is cleared (WCL bit is cleared to "0"), the counter starts counting from 0000H.When the count reaches 7FFFH, the counter restarts counting from 0000H. If the trailing edgeof the frequency-divide output selected for the interval timer is detected, the main clockoscillation stabilization wait timer interrupt flag (WIF) bit is set to "1". In other words, a mainclock oscillation stabilization wait timer interrupt request is generated at the selected intervals onthe basis of the selected interval time.

Operation of Clock Supply Function

The MB91310 uses a time-base counter to secure the oscillation stabilization wait time afterINIT or stop mode. On the other hand, the MB91310 uses the main clock oscillationstabilization wait timer to secure the main clock oscillation stabilization wait time while the subclock is selected as the clock source. This is because the main clock oscillation stabilizationwait timer operates on the main clock regardless of the clock source selection.

Follow the procedure below to perform main clock oscillation stabilization wait operation whilethe MB91310 is operating on the sub clock:

1. Set the time required for main clock oscillation stabilization with the WT1 and WT0 bits, andclear the counter to 0 (by writing the oscillation stabilization wait time to the WS1 and WS0bits and "0" to the WCL bit).If it is necessary to perform processing after the end of oscillation stabilization wait with aninterrupt, initialize the interrupt flag (by writing "0" to the WIF and WIE bits).

2. Start main clock oscillation (by writing "1" to bit8 [OCSDS1 bit] of OSCCR).

3. In the program, wait until the WIF bit is set to "1".

4. Make sure that the WIF bit has been set to "1", then perform the processing to be done afterthe end of oscillation stabilization wait. If interrupts are enabled, an interrupt is generatedwhen the WIF bit is set to "1". Then, perform the processing to be done after the end ofoscillation stabilization wait by an interrupt routine. If it is necessary to switch the clocksource from the sub clock to main clock, switch the clock source after making sure that the 4) WIF bit has been set to "1" as described above. (If the clock source is switched to themain clock before main clock oscillation is stabilized, an unstable clock is supplied to theentire device and subsequent operation is unpredictable.)

121


Operation of the Main Clock Oscillation Stabilization Wait Timer

Figure 3.14-3 shows the counter states at the start of the main clock oscillation stabilization waittime and switching to the main clock.

Figure 3.14-3 Counter States at Switching to the Main Clock

Precautions on Using the Main Clock Oscillation Stabilization Wait Timer

• Use the oscillation stabilization wait time as a reference value, because the oscillation cycleis unstable immediately after oscillation is started.

• No timer interrupt is generated while main clock oscillation is stopped, because the mainclock oscillation stabilization wait timer is stopped when main clock oscillation is stopped.Do not stop main clock oscillation if it is necessary to use the main clock oscillationstabilization wait timer for processing.

• If a WIF setting request occurs at the same time as a zero-clearance request from the CPU,the WIF setting request has priority and the zero-clearance request is ignored.

Sub clock Main clock

- Timer clearance (WCL bit = 1) (other than 0)- Timer interval selection (WS1 and WS0 bits = 11B)- Start of main clock oscillation

(OSCDS1 bit of OSCCR = 0)

Cleared by interrupt routine

Main clock oscillation stabilization wait time

H

WIF (interrupt request)

WIE (interrupt mask)

Clock mode

- Switching from sub clock to main clock

7 FFFFF

Value of counter

122


The external bus interface controller controls the interfaces with the internal bus for chips and with external memory and I/O devices.This chapter explains each function of the external bus interface and its operation.

4.1 Overview of the External Bus Interface

4.2 External Bus Interface Registers

4.3 Setting Example of the Chip Select Area

4.4 Endian and Bus Access

4.5 Operation of the Ordinary bus interface

4.6 Burst Access Operation

4.7 Address/data Multiplex Interface

4.8 Prefetch Operation

4.9 DMA Access Operation

4.10 Bus Arbitration

4.11 Procedure for Setting a Register

4.12 Notes on Using the External Bus Interface

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This section explains the features, block diagram, I/O pins, and registers of the external bus interface.The external bus interface is used to connect various function macros on the chip. The CS1, CS2, and CS3 areas are connected to the USB host, USB function and OSDC.CS0 and CS4 to CS7 cannot be used.For more information about setting each area, see "APPENDIX F External Bus Interface Setting".

Features

The external bus interface has the following features:

Addresses of up to 32 bits (4 GB space) can be output.

Various kinds of external memory (8-bit/16-bit/32-bit modules) can be directly connected and multiple access timings can be mixed and controlled.

• Asynchronous SRAM and asynchronous ROM/FLASH memory (multiple write strobe methodor byte enable method)

• Page mode ROM/FLASH memory (Page sizes 2, 4, and 8 can be used)

• Burst mode ROM/FLASH memory (such as MBM29BL160D/161D/162D)

• Address/data multiplex bus (8-bit/16-bit width only)

• Synchronous memory (such as ASIC built-in memory) (Synchronous SRAM cannot bedirectly connected)

Eight independent banks (chip select areas) can be set, and chip select corresponding to each bank can be output.

• The size of each area can be set in multiples of 64 KB (64 KB to 2 GB for each chip selectarea).

• An area can be set at any location in the logical address space (Boundaries may be limiteddepending on the size of the area.)

In each chip select area, the following functions can be set independently:

• Enabling and disabling of the chip select area (Disabled areas cannot be accessed)

• Setting of the access timing type to support various kinds of memory

• Detailed access timing setting (individual setting of the access type such as the wait cycle)

• Setting of the data bus width (8-bit/16-bit/32-bit)

• Setting of the order of bytes (big or little endian) (Only big endian can be set for the CS0area)

• Setting of write disable (read only area)

• Enabling and disabling of fetches from the built-in cache

124


• Enabling and disabling of the prefetch function

• Maximum burst length setting (1, 2, 4, 8)

A different detailed timing can be set for each access timing type.

• For the same type of access timing, a different setting can be made in each chip select area.

• Auto-wait can be set to up to 15 cycles (asynchronous SRAM, ROM, Flash, and I/O area).

• The bus cycle can be extended by external RDY input (asynchronous SRAM, ROM, Flash,and I/O area).

• The first access wait and page wait can be set (burst, page mode, and ROM/FLASH area).

• Various kinds of idle/recovery cycles and setting delays can be inserted.

Fly-by transfer by DMA can be performed.

• Transfer between memory and I/O can be performed in a single access operation.

• The memory wait cycle can be synchronized with the I/O wait cycle in fly-by.

• The hold time can be secured by only extending transfer source access.

• Idle/recovery cycles specific to fly-by transfer can be set.

External bus arbitration using BRQ and BGRNT can be performed.

Pins that are not used by the external interface can be used as general-purpose I/O ports through settings.

125


Block Diagram

Figure 4.1-1 shows the block diagram of the external bus interface.

Figure 4.1-1 Block Diagram of the External Bus Interface

32 32

Internal address bus

External address bus

Internal data bus

External data bus

write buffer switch

switchread buffer

ADDRESS BLOCKDATA BLOCK

+1 or +2

address buffer

ASZ

ASR

BRQBGRNTRDY

RDWR0,WR1,WR2,WR3AS,BAA

CS0 to CS7

MUX

External terminal controller

All-block control

resisters&

control

comparator

126


I/O Pins

These are external bus interface signal.

The following lists the I/O pins for each interface:

Ordinary bus interface

• A31-A00, D31-D00(AD15-AD00)

• CS0, CS1, CS2, CS3, CS4, CS5, CS6, CS7

• AS, SYSCLK, MCLK

• RD

• WR, WR0(UUB), WR1(ULB), WR2(LUB), WR3(LLB)

• RDY, BRQ, BGRNT

Memory interface

• MCLK, SYSCLK

• LBA(=AS), BAA (for burst ROM/FLASH)

DMA interface

• IOWR, IORD

• DACK0, DACK1, DACK2

• DREQ0, DREQ1, DREQ2

• DEOP0/DSTP0, DEOP1/DSTP1, DEOP2/DSTP2

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Register List

Figure 4.1-2 shows the registers used by the external bus interface:

Figure 4.1-2 List of External Bus Interface Registers

bit31 24 23 16 15 8 7 0

ASR0

ASR1

ASR2

ASR3

ASR4

ASR5

ASR6

ASR7

AWR0

AWR2

AWR4

AWR6

ACR0

ACR1

ASR2

ACR3

ACR4

ACR5

ACR6

ACR7

AWR1

AWR3

AWR5

AWR7

MCRA

Reserved

IOWR0

Reserved

CSER

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

IOWR2

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

TCR

Reserved

Reserved

Reserved

Reserved

Reserved

MCRB

Reserved

IOWR1

Reserved

CHER

Reserved

Reserved

Reserved

(MODR)

RCR

00000640H

00000644H

00000648H

0000064CH

00000650H

00000654H

00000658H

0000065CH

00000660H

00000664H

00000668H

0000066CH

00000670H

00000674H

00000678H

0000067CH

00000680H

00000684H

00000688H

0000068CH

000007F8H

000007FCH

Address

• Reserved indicates a reserved register. For a write, be sure to set "0".• MODR cannot be accessed from user programs.

Notes:

128



This section explains the registers used in the external bus interface.

Register Types

The following registers are used by the external bus interface:

• Area select registers (ASR0 to ASR7)

• Area configuration registers (ACR0 to ACR7)

• Area wait registers (AWR0 to AWR7)

• I/O wait registers for DMAC (IOWR0 to IOWR2)

• Chip select area enable register (CSER)

• Cache enable register (CHER)

• Pin/timing control register (TCR)

129


4.2.1 Area Select Registers 0 to 7(ASR0 to ASR7)

This section explains the configuration and functions of area select registers 0 to 7 (ASR0 to ASR7).

Configuration of Area Aelect Registers 0 to 7 (ASR0 to ASR7)

The area select registers (ASR0 to ASR7) specify the start address of each chip select area ofCS0 to CS7.

Table 4.2-1 shows the configuration of area select registers 0 to 7 (ASR0 to ASR7: Area SelectRegister).

Figure 4.2-1 Configuration of the Area Select Registers (ASR0 to ASR7)

Initial valueASR0 bit15 14 13 12 2 1 0 INIT RST Access

0000 0640H A31 A30 A29 A18 A17 A16 0000H 0000H R/W

ASR1 bit15 14 13 12 2 1 0

0000 0644H A31 A30 A29 A18 A17 A16 xxxxH xxxxH R/W

ASR2 bit15 14 13 12 2 1 0


ASR3 bit15 14 13 12 2 1 0

0000 064CH A31 A30 A29 A18 A17 A16 xxxxH xxxxH R/W

ASR4 bit15 14 13 12 2 1 0


ASR5 bit15 14 13 12 2 1 0


ASR6 bit15 14 13 12 2 1 0


ASR7 bit15 14 13 12 2 1 0

0000 065CH A31 A30 A29 A18 A17 A16 xxxxH xxxxH R/W

130


Functions of Bits in the Area Select Registers (ASR0 to ASR7)

The area select registers (ASR0 to ASR7) specify the start address of each chip select area ofCS0 to CS7.

The start address can be specified in the 16 high-order bits from A31 to A16. Each chip selectarea starts with the address set in this register and covers the range set by the four bits ASZ3 toASZ0 of registers ACR0 to ACR7.

The boundary of each chip select area obeys the setting of the four bits ASZ3 to ASZ0 ofregisters ACR0 to ACR7. For example, if an area of 1 MB is set by the four bits ASZ3 to ASZ0,the four low-order bits of registers ASR0 to ASR7 are ignored and only bits A31 to A20 arevalid.

The ASR0 register is initialized to 0000H by INIT and RST. ASR1 to ASR7 are not initialized byINIT and RST, and are therefore undefined. After starting chip operation, be sure to set thecorresponding ASR register before enabling each chip select area with the CSER register.

131


4.2.2 Area Configuration Registers 0 to 7 (ACR0 to ACR7)

This section explains the configuration and functions of area configuration registers 0 to 7 (ACR0 to ACR7).

Configuration of Area Configuration Registers 0 to 7 (ACR0 to ACR7)

The area configuration registers 0 to 7 (ACR0 to ACR7) set the function of each chip selectarea.

Figure 4.2-2 shows the configuration of area configuration registers 0 to 7 (ACR0 to ACR7).

Figure 4.2-2 Configuration of Area Configuration Registers 0 to 7 (ACR0 to ACR7)

ACR0H

0000 0642H ASZ3 ASZ2 ASZ1 ASZ0 DBW1 DBW0 BST1 BST0 1111**00B 1111**00B

00000000B 00000000B

xxxxxxxxB xxxxxxxxB

R/W

ACR0L bit7 6 5 4 3 2 1 0

bit7 6 5 4 3 2 1 0

bit7 6 5 4 3 2 1 0

bit7 6 5 4 3 2 1 0

0000 0643H SREN PFEN WREN 0 TYP3 TYP2 TYP1 TYP0 R/W

ACR1H

0000 0646H ASZ3 ASZ2 ASZ1 ASZ0 DBW1 DBW0 BST1 BST0 R/W

ACR1L

0000 0647H SREN PFEN WREN LEND TYP3 TYP2 TYP1 TYP0 xxxxxxxxB xxxxxxxxB

xxxxxxxxB xxxxxxxxB

xxxxxxxxB xxxxxxxxB

xxxxxxxxB xxxxxxxxB

xxxxxxxxB xxxxxxxxB

R/W

ACR2H

0000 064AH ASZ3 ASZ2 ASZ1 ASZ0 DBW1 DBW0 BST1 BST0 R/W

ACR2L

0000 064BH SREN PFEN WREN LEND TYP3 TYP2 TYP1 TYP0 R/W

ACR3H

0000 064EH ASZ3 ASZ2 ASZ1 ASZ0 DBW1 DBW0 BST1 BST0 R/W

ACR3L

0000 064FH SREN PFEN WREN LEND TYP3 TYP2 TYP1 TYP0 R/W

bit15 14 13 12 11 10 9 8

bit15 14 13 12 11 10 9 8

bit15 14 13 12 11 10 9 8

bit15 14 13 12 11 10 9 8

Initial value

INIT RST Access

(Continued)

132


ACR4H bit15 14 13 12 11 10 9 8

bit15 14 13 12 11 10 9 8

bit15 14 13 12 11 10 9 8

bit15 14 13 12 11 10 9 8

0000 0652H ASZ3 ASZ2 ASZ1 ASZ0 DBW1 DBW0 BST1 BST0

ACR4L

ACR5H

ACR5L

ACR6H

ACR6L

ACR7H

ACR7L

bit7 6 5 4 3 2 1 0

0000 0653H SREN PFEN WREN LEND TYP3 TYP2 TYP1 TYP0

0000 0656H ASZ3 ASZ2 ASZ1 ASZ0 DBW1DBW0 BST1 BST0

bit7 6 5 4 3 2 1 0

0000 0657H SREN PFEN WREN LEND TYP3 TYP2 TYP1 TYP0

0000 065AH ASZ3 ASZ2 ASZ1 ASZ0 DBW1DBW0 BST1 BST0

bit7 6 5 4 3 2 1 0

0000 065BH SREN PFEN WREN LEND TYP3 TYP2 TYP1 TYP0

SREN PFEN WREN LEND TYP3 TYP2 TYP1 TYP0

0000 065EH ASZ3 ASZ2 ASZ1 ASZ0 DBW1DBW0 BST1 BST0

bit7 6 5 4 3 2 1 0

0000 065FH

xxxxxxxxB xxxxxxxxB R/W

xxxxxxxxB xxxxxxxxB

xxxxxxxxB xxxxxxxxB

xxxxxxxxB xxxxxxxxB

xxxxxxxxB xxxxxxxxB

xxxxxxxxB xxxxxxxxB

R/W

R/W

R/W

R/W

R/W

xxxxxxxxB xxxxxxxxB

xxxxxxxxB xxxxxxxxB

R/W

R/W

Initial value INIT RST Access

(Continued)

133


Functions of Bits in the Area Configuration Registers (ACR0 to ACR7)

The following explains the functions of the bits in area configuration registers 0 to 7 (ACR0 toACR7):

[bit15 to bit12] ASZ3 to ASZ0 (Area Size Bits 3-0)

These bits set the size of each chip select area as indicated in Table 4.2-1 .

ASZ3 to ASZ0 are used to set the size of each area by modifying the number of bits for addresscomparison to a value different from ASR. Thus, an ASR contains bits that are not compared.Bits ASZ3 to ASZ0 of ACR0 are initialized to 1111B (0FH) by RST. Despite this setting,however, the CS0 area just after RST is executed is specially set from 00000000H toFFFFFFFFH (setting of entire area). The entire-area setting is reset after the first write to ACR0and an appropriate size is set as indicated in Table 4.2-1 .

[bit11, bit10] DBW1, DBW0 (Data Bus Width 1, 0)

These bits set the data bus width of each chip select area as indicated in Table 4.2-2 .

Table 4.2-1 Area Size Settings

ASZ3 ASZ2 ASZ1 ASZ0 Size of each chip select area

0 0 0 0 64 KB (00010000H byte, ASR A[31:16] bits are valid)




0 1 0 0 1 MB (00100000H byte, ASR A[31:20] bits are valid)











1 1 1 1 2048 MB (80000000H byte, ASR A[31] bit is valid)

134


The same values as those of the WTH bits of the mode vector are written automatically to bitsDBW1, DBW0 of ACR0 during the reset sequence.

[bit9, bit8] BST1, BST0 (BurST size 1, 0)

These bits set the maximum burst length of each chip select area as indicated in Table 4.2-3 .

In areas for which a burst length other than the single access is set, continuous burst access isperformed within the address boundary determined by the burst length only when prefetchaccess is performed or data having a size exceeding the bus width is read.

The maximum burst length of the bus width 32-bit area must be set to four bursts or less.Setting of two bursts or less is recommended.

The maximum burst length of the bus width 16-bit area must be set to four bursts or less.Setting of two bursts or less is recommended.

RDY input is ignored in areas for which any burst length other than the single access is set.

[bit7] SREN (ShaRed ENable)

This bit sets enabling or disabling of sharing of each chip select area by BRQ/BGRNT asindicated in Table 4.2-1 .

In areas where sharing is enabled, chip select output (CSnX) is set to high impedance while thebus is open (during BGRNT=Low output). In areas where sharing is disabled, chip select output(CSnX) is not set to high impedance even though the bus is open (during BGRNT=Low output).

Access strobe output (AS, BAA, RD, WR0, WR1, WR2, WR3, WR, etc.) is set to highimpedance only if sharing of all areas enabled by CSER is enabled.

Table 4.2-2 Setting of the Data Bus Width of Each Chip Select Area

DBW1 DBW0 Data bus width

0 0 8 bits (byte access)

0 1 16 bits (halfword access)

1 0 32 bits (word access)

1 1 Reserved Setting disabled

Table 4.2-3 Setting of the Maximum Burst Length of Chip Select

BST1 BST0 Maximum burst length

0 0 1 (single access)

0 1 2 bursts (address boundary: 1 bit)

1 0 4 bursts (address boundary: 2 bits)

1 1 8 bursts (address boundary: 3 bits)

Table 4.2-4 Enabling and Disabling Sharing of Each Chip Select Area by BRQ/BGRNT

SREN Sharing enable/disable

0 Disable sharing by BRQ/BGRNT(CSX cannot be high impedance)

1 Enable sharing by BRQ/BGRNT(CSX can be high impedance)

135


[bit6] PFEN (PreFetch ENable)

This bit sets enabling and disabling of prefetching of each chip select area as indicated inTable 4.2-5 .

When reading from an area for which prefetching is enabled, the subsequent address is read inadvance and stored in the built-in prefetch buffer. When the stored address is accessed fromthe internal bus, the lookahead data in the prefetch buffer is returned without performingexternal access.

For more information, see Section "4.8 Prefetch Operation".

[bit5] WREN(WRite ENable)

This bit sets enabling or disabling of writing to each chip select area as indicated in Table4.2-6 .

If an area for which write operations are disabled is accessed for a write operation from theinternal bus, the access is ignored and no external access at all is performed. Set the WRENbit of areas for which write operations are not required, such as data areas, to "1".

[bit4] LEND (Little ENDian select)

This bit sets the order of bytes of each chip select area as indicated in Table 4.2-7 .

Be sure to set the LEND bit of ACR0 to "0". CS0 supports only the big endian method.

[bit3 to bit0] TYP3 to TYP0 (TYPe select)

These bits set the access type of each chip select area as indicated in Table 4.2-8 .

Table 4.2-5 Enabling and Disabling Prefetching of Each Chip Select Area

PFEN Prefetch enable/disable

0 Disable prefetch

1 Enable prefetch

Table 4.2-6 Enabling and Disabling Writing to Each Chip Select Area

WREN Write enable/disable

0 Disable write

1 Enable write

Table 4.2-7 Order of Bytes of Each Chip Select Area

LEND Order of bytes

0 Big endian

1 Little endian

136


Set the access type as the combination of all bits.

For details of the operations of each access type, see the explanation of operation of eachtype.

CS area mask setting function

If you want to set an area some of whose operation settings are changed for a certain CS area(referred to as the base setting area), you can set TYP3 to TYP0 of ACR in another CS area to1111 so that the area can function as a mask setting area.

If you do not use the mask setting function, disable any overlapping area settings for multipleCS areas.

Access operations to the mask setting area are as follows:

• CSX corresponding to a mask setting area is not asserted.

• CSX corresponding to a base setting area is not asserted.

• For the following ACR settings, the settings on the mask setting area side are valid:

• bit11, bit10 (DBW1, DBW0): Bus width setting

Table 4.2-8 Access Type Settings for Chip Select Area

TYP3 TYP2 TYP1 TYP0 Access type

0

0 x xNormal access (asynchronous SRAM, I/O, and single/page/burst-ROM/FLASH)

1 x xAddress data multiplex access (8/16-bit bus width only)

x

x 0 Disable WAIT insertion by the RDY pin.

x 1Enable WAIT insertion by the RDY pin (disabled during bursts).

0 xUse the WR0 to WR3 pins as write strobes (WR is always "H").

1 x Use the WR pin as the write strobe. *1

1

0 00 Setting disabled

1 Setting disabled

0 1 0 Setting disabled





1 1 1Mask area setting (The access type is the same as that of the overlapping area) *2

*1: If this setting is made, WR0 to WR3 can be used as the enable of each bit.*2: CS area mask setting function.

137


• bit9, bit8 (BST1, BST0): Burst length setting

• bit7 (SREN): Sharing-enable setting

• bit6 (PFEN): Prefetch-enable setting

• bit5 (WREN): Write-enable setting (For this setting only, only a setting that is the same asthat of the base setting area is allowed)

• bit4 (LEND): Little endian setting

• For the following ACR setting, the setting on the base setting area side is valid:

• bit3 to bit0 (TYP3 to TYP0): Access type setting

• For the AWR settings, the settings on the mask setting area side are valid.

• For the CHER settings, the settings on the mask setting area side are valid.

A mask setting area can be set for only part of another CS area (base setting area). You cannotset a mask setting area for an area without a base setting area. Use care when setting ASRand bits ASZ3 to ASZ0 of ACR.

The following restrictions apply when using these bits:

• A write-enable setting cannot be implemented by a mask.

• Write-enable settings in the base CS area and the mask setting area must be identical.

• If write operations to a mask setting area are disabled, the area is not masked and operatesas a base CS area.

• If write operations to the base CS area are disabled but are enabled to the mask settingarea, the area has no base, resulting in malfunctions.

138


4.2.3 Area Wait Register (AWR0 toAWR7)

This section explains the configuration and functions of the area wait registers (AWR0 to AWR7).

Configuration of the Area Wait Registers (AWR0 to AWR7)

The area wait registers (AWR0 to AWR7) specify various kinds of waits for each chip selectarea.

Figure 4.2-3 shows the configuration of the area wait registers (AWR0 to AWR7).

Figure 4.2-3 Configuration of the Area Wait Registers (AWR0 to AWR7)

AWR0H bit31 30 29 28 27 26 25 24

bit31 30 29 28 27 26 25 24

bit31 30 29 28 27 26 25 24

0000 0660H W15 W14 W13 W12 W11 W10 W09 W08 01111111B 01111111B

11111111B 11111111B

R/W

AWR0L

AWR1L

bit23 22 21 20 19 18 17 16

bit23 22 21 20 19 18 17 16

bit23 22 21 20 19 18 17 16

0000 0661H W07 W06 W05 W04 W03 W02 W01 W00 R/W

AWR1H

0000 0662H W15 W14 W13 W12 W11 W10 W09 W08 xxxxxxxxB xxxxxxxxB

xxxxxxxxB xxxxxxxxB

xxxxxxxxB xxxxxxxxB

xxxxxxxxB xxxxxxxxB

xxxxxxxxB xxxxxxxxB

xxxxxxxxB xxxxxxxxB

xxxxxxxxB xxxxxxxxB

xxxxxxxxB xxxxxxxxB

R/W

bit7 6 5 4 3 2 1 0

0000 0663H W07 W06 W05 W04 W03 W02 W01 W00 R/W

AWR2H

AWR2L

AWR3H

AWR3L

AWR4L

AWR4H

0000 0664H W15 W14 W13 W12 W11 W10 W09 W08 R/W

0000 0665H W07 W06 W05 W04 W03 W02 W01 W00 R/W

0000 0666H W15 W14 W13 W12 W11 W10 W09 W08 R/W

bit7 6 5 4 3 2 1 0

0000 0667H W07 W06 W05 W04 W03 W02 W01 W00 R/W

0000 0668H W15 W14 W13 W12 W11 W10 W09 W08 R/W

0000 0669H W07 W06 W05 W04 W03 W02 W01 W00 R/W

bit15 14 13 12 11 10 9 8

bit15 14 13 12 11 10 9 8


(Continued)

139


Registers AWR0 to AWR7 specify various kinds of waits for each chip select area.

The function of each bit depends on the setting of the access type (bits TYP3 to TYP0) ofregisters ACR0 to ACR7.

0000 066AH W15 W14 W13 W12 W11 W10 W09 W08

AWR5L bit7 6 5 4 3 2 1 0

0000 066BH W07 W06 W05 W04 W03 W02 W01 W00

bit31 30 29 28 27 26 25 24

0000 066CH W15 W14 W13 W12 W11 W10 W09 W08

0000 066DH W07 W06 W05 W04 W03 W02 W01 W00

0000 066EH W15 W14 W13 W12 W11 W10 W09 W08

bit7 6 5 4 3 2 1 0

0000 066FH W07 W06 W05 W04 W03 W02 W01 W00

bit23 22 21 20 19 18 17 16

bit15 14 13 12 11 10 9 8

bit15 14 13 12 11 10 9 8AWR5H

AWR6L

AWR6H

AWR7L

AWR7H

xxxxxxxxB xxxxxxxxB

xxxxxxxxB xxxxxxxxB

xxxxxxxxB xxxxxxxxB

xxxxxxxxB xxxxxxxxB

xxxxxxxxB xxxxxxxxB

R/W

R/W

R/W

R/W

R/W

xxxxxxxxB xxxxxxxxB R/W


(Continued)

140


Normal Access or Address/Data Multiplex Access

A chip select area specified using the following settings for the access type (bits TYP3 to TYP0)of registers ACR0 to ACR7 operates as an area for normal access or address/data multiplexaccess.

Table 4.2-9 shows the areas that operate with normal access and address/data multiplexaccess.

The following lists the functions of each AWR0 to AWR7 bit for a normal access or address/datamultiplex access area. Since the initial values of registers other than AWR0 are undefined, setthem to their initial values before enabling each area with the CSER register.

Table 4.2-9 Areas for Normal Access and Address/Data Multiplex Access Operation

TYP3 TYP2 TYP1 TYP0 Access type

0 0 x xNormal access (asynchronous SRAM, I/O, and single/page/burst-ROM/FLASH)

0 1 x xAddress data multiplex access (8/16-bit bus width only)

141


Functions of Bits in the Area Wait Registers (AWR0 to AWR7)

The following explains the functions of the bits in the area wait registers (AWR0 to AWR7).

[bit15 to bit12] W15 to W12 (First Wait Cycle)

These bits set the number of auto-wait cycles to be inserted into the first access cycle ofeach cycle. Except for the burst access cycles, only this wait setting is used.

The initial value of the CS0 area is set to 7 (wait). The initial values of the other areas areundefined.

Table 4.2-10 lists the settings for the number of auto-wait cycles during first access.

[bit11 to bit8] W11 to W08 (Inpage Access Wait Cycle)

These bits set the number of auto-wait cycles to be inserted into the inpage access cycleduring burst access. They are valid only for burst cycles.

Table 4.2-11 lists the settings for the number of auto-wait cycles during burst access.

If the same value is set for the first access wait cycle and inpage access wait cycle, the accesstime for the address in each access cycle is not the same. This is because the inpage accesscycle contains an address output delay.

Table 4.2-10 Settings for the Number of Auto-Wait Cycles (During First Access)

W15 W14 W13 W12 First access wait cycle

0 0 0 0 Auto-wait cycle 0


... ...


Table 4.2-11 Settings for the Number of Auto-Wait Cycles (During Burst Access)

W11 W10 W09 W08 Inpage access wait cycle



... ...


142


[bit7, bit6] W07, W06 (Read -> Write Idle Cycle)

The read -> write idle cycle is set to prevent collision of read data and write data on the databus when a write cycle follows a read cycle. During an idle cycle, all chip select signals arenegated and the data terminals maintain the high impedance state. If a write cycle follows aread cycle or an access operation to another chip select area occurs after a read cycle, thespecified idle cycle is inserted.Table 4.2-12 lists the settings for idle cycles.

[bit5, bit4] W05, W04 (Write Recovery Cycle)

The write recovery cycle is set if a device that limits the access period after write access is tobe controlled. During a write recovery cycle, all chip select signals are negated and the datapins maintain the high impedance state. If the write recovery cycle is set to 1 or more, awrite recovery cycle is always inserted after write access.

Table 4.2-13 lists the settings for the number of write recovery cycles.

Table 4.2-12 Settings of the Idle Cycle

W07 W06 Read -> write idle cycles

0 0 0 cycle

0 1 1 cycle

1 0 2 cycles

1 1 3 cycles

Table 4.2-13 Settings for the Number of Write Recovery Cycles

W05 W04 Write recovery cycles

0 0 0 cycle

0 1 1 cycle

1 0 2 cycles

1 1 3 cycles

143


[bit3] W03 (WR0 to WR3, WR Output Timing Selection)

The WR0 to WR3, WR output timing setting selects whether to use write strobe output as anasynchronous strobe or synchronous write enable. The asynchronous strobe settingcorresponds to normal memory/IO. The synchronous enable setting corresponds to clock-synchronized memory/IO (such as the memory in an ASIC).

Table 4.2-14 shows the settings for the WR output timing selection.

If synchronous write enable (W03 bit of AWR is "0") is used, operations are as follows:

• The timing of synchronous write enable output assumes that the output is captured by therising edge of MCLK output of an external memory access clock. This timing is differentfrom the asynchronous strobe output timing.

• The WR0 to WR3 and WR terminal output asserts synchronous write enable output at thetiming at which AS pin output is asserted. For a write to an external bus, the synchronouswrite enable output is L. For a read from an external bus, the synchronous write enableoutput is H.

• Write data is output from the external data output pin in the clock cycle following the cycle inwhich synchronous write enable output is asserted. If write data cannot be output becausethe internal bus is temporarily unavailable, assertion of synchronous write enable output maybe extended until write data can be output.

• Read strobe output (RD) functions as an asynchronous read strobe regardless of the settingof the WR0 to WR3 and WR output timing. Use it as is for controlling the data I/O direction.

If synchronous write enable output is used, the following restrictions apply:

• Do not make the following additional wait settings:

• CSX -> RD/WR setup (Always set "0" for the W01 bit of AWR)

• First wait cycle setting (Always set "0000B" for the W15 to W12 bits of AWR)

• Do not make the following access type settings (TYP3 to TYP0 bits in the ACR register (bits3-0))

• Address/data multiplex bus setting (Always set "0" for the TYP2 bit in the ACR register)

• Setting to use WR0 to WR3 as a strobe (Always set "0" for the TYP1 bit of ACR)

• RDY input enable setting (Always set "0" for the TYP0 bit of ACR)

• For synchronous write enable output, always set 1(00B for bits BST1,BST0 bits of ACR) asthe burst length.

Table 4.2-14 Settings for the WR Output Timing Selection

W03 WR0 to WR3, WR output timing selection

0 MCLK synchronous write enable output (valid from AS=L)

1 Asynchronous write strobe output (normal operation)

144


[bit2] W02 (Address -> CSX Delay: Address -> CSX Delay)

The address -> CSX delay setting is made when a certain type of setup is required for theaddress when CSX falls or CSX edges are needed for successive accesses to the samechip select area.

Set the address and set the delay from AS output to CS0 to CS7 output.

Table 4.2-15 shows the settings for the CS0 to CS7 output delay.

If no delay is selected by setting "0", assertion of CS0 to CS7 starts at the same timing that ASis asserted. If, at this point, successive accesses are made to the same chip select area,assertion of CS0 to CS7 without change between two access operations may continue.

If delay is specified by selecting "1", assertion of CS0 to CS7 starts when the external clockmemory MCLK output rises. If, at this point, successive accesses are made to the same chipselect area, CS0 to CS7 are negated at a timing between two access operations. If CSX delayis selected, one setup cycle is inserted before asserting the read/write strobe after assertion ofthe delayed CSX (operation is the same as the CSX ->RD/WR setup setting of W01).

The address -> CSX delay setting works for DACKX signal (basic mode) output to the samearea in the same way. DACKX output in basic mode has the same waveforms as those of CSXoutput to the same area.

[bit1] W01 (CSX -> RD/WR Setup Extension Cycle: CSX -> RD/WR setup)

The CSX -> RD/WR setup extension cycle is set to extend the period before the read/writestrobe is asserted after CSX is asserted. At least one setup extension cycle is insertedbefore the read/write strobe is asserted after CSX is asserted.

Table 4.2-16 shows the settings for the CSX -> RD/WR setup extension cycle.

If 0 cycle is selected by setting "0", RD/WR0 to WR3/WR are output at the earliest whenexternal clock MCLK output rises just after CSX is asserted. WR0 to WR3/WR may be delayedone cycle or more depending on the internal bus state.

If 1 cycle is selected by setting "1", RD/WR0 to WR3/WR are always output 1 cycle or morelater.

When successive accesses are made within the same chip select area without negating CSX, asetup extension cycle is not inserted. If a setup extension cycle for determining the address isrequired, set the W02 bit and insert the address -> CSX delay. Since CSX is negated for eachaccess operation, the setup extension cycle is enabled.

If the CSX delay set by W02 is inserted, this setup cycle is always enabled regardless of thesetting of the W01 bit.

Table 4.2-15 Settings for the CS0 to CS7 Output Delay

W02 Address -> CSX delay

0 Delay

1 No delay

Table 4.2-16 Settings for the CSX -> RD/WR Setup Extension Cycle

W01 CSX -> RD/WR setup delay cycle

0 0 cycle

1 1 cycle

145


[bit0] W00 (RD/WR -> CSX Hold Extension Cycle: RD/WR -> CSX Hold Cycle)

The RD/WR -> CSX hold extension cycle is set to extend the period before negating CSXafter the read/write strobe is negated. One hold extension cycle is inserted before CSX isnegated after the read/write strobe is negated.

Table 4.2-17 shows the settings for the RD/WR -> CSX hold extension cycle.

If 0 cycle is selected by setting "0", CS0 to CS7 are negated after the hold delay after it starts onthe rising edge of external memory clock MCLK output after RD/WR0 to WR3/WR are negated.

If 1 cycle is selected by setting "1", CS0 to CS7 are negated one cycle later.

When making successive accesses within the same chip select area without negating CSX, thehold extension cycle is not inserted. If a hold extension cycle for determining the address isrequired, set the W02 bit and insert the address -> CSX delay. Since CSX is negated for eachaccess operation, this hold extension cycle is enabled.

Table 4.2-17 Settings for the RD/WR -> CSX Hold Extension Cycle

W00 RD/WR -> CSX hold extension cycle

0 0 cycle

1 1 cycle

146


4.2.4 I/O Wait Registers for DMAC (IOWR0 to IOWR2)

This section explains the configuration and functions of the I/O wait registers for DMAC (IOWR0 to IOWR2).

Configuration of the I/O Wait Registers for DMAC (IOWR0 to IOWR2)

The I/O wait registers for DMAC (IOWR0 to IOWR2) set various kinds of waits during DMA fly-by access.

Figure 4.2-4 shows the configuration of the I/O wait registers for DMAC (IOWR0 to IOWR2).

Figure 4.2-4 Configuration of the I/O Wait Registers for DMAC (IOWR0 to IOWR2)

Functions of Bits in the I/O Wait Registers for DMAC (IOWR0 to IOWR2)

The following explains the functions of the bits in the I/O wait registers for DMAC (IOWR0 toIOWR2).

[bit31, bit23, bit15] RYE0 to RYE2 (RDY function setting: ReadY Enable 0,1,2)

These bits set the wait control using RDY for channels 0 to 2 at DMA fly-by access.

Table 4.2-18 shows the settings for wait control using RDY.

When "1" is set, wait insertion by the RDY pin can be performed during fly-by transfer on therelevant channel. IOWR and IORD are extended until the RDY pin is enabled. Also, RD/WR0to WR3/WR on the memory side are extended synchronously. If the chip select area of the fly-by transfer destination is set to RDY-enabled in the ACR register, wait insertion by the RDY pincan be performed regardless of the RYEn bit of IOWR. When the chip select area of the fly-bytransfer destination is set to RDY-disabled in the ACR register, wait insertion by the RDY pincan only be performed during fly-by access if the area is set to RDY-enabled by the RYEn bit onthe IOWR side.

IOWR0

IOWR1

IOWR2

bit31 30 29 28 27 26 25 24

0000 0688H RYE0 HLD0 WR01 WR00 IW03 IW02 IW01 IW00

0000 0689H RYE1 HLD1 WR11 WR10 IW13 IW12 IW11 IW10

0000 068AH RYE2 HLD2 WR21 WR20 IW23 IW22 IW21 IW20

bit23 22 21 20 19 18 17 16

bit15 14 13 12 11 10 9 8

xxxxxxxxB xxxxxxxxB

xxxxxxxxB xxxxxxxxB

xxxxxxxxB xxxxxxxxB

R/W

R/W

R/W


Table 4.2-18 Settings for Wait Control Using RDY

RYEn RDY function setting

0 Disable RDY input for I/O access.

1 Enable RDY input for I/O access.

147


[bit30, bit22, bit14] HLD0 to HLD2 (Hold Wait Setting: HoLD wait control)

These bits control the hold cycle of the read strobe signal on the transfer source access sideduring DMA fly-by access.

Table 4.2-19 shows the settings for hold wait.

If "0" is set, the read strobe signal (RD for memory -> I/O and IORD for I/O -> memory) and thewrite strobe signal (IOWR for memory -> I/O and WR0 to WR3 and WR for I/O -> memory) onthe transfer source access side are output at the same timing.

If "1" is set, the read strobe signal is output one cycle longer than the write strobe signal tosecure a hold time for data at the transfer source access side when sending it to the transferdestination.

[bit29, bit28, bit21, bit20, bit13, bit12] WR0,1,2 (I/O Idle Cycle setting: I/O Idle Wait)

These bits set the idle cycle for continuous access during DMA fly-by access.Table 4.2-20lists the settings for the number of I/O idle cycles.

If one or more cycles is set as the number of idle cycles, cycles equal to the number specifiedare inserted after I/O access during DMA fly-by access. During the idle cycles, all CSX andstrobe output is negated and the data pin is set to the high impedance state.

Table 4.2-19 Settings for Hold Wait

HLDn Hold wait setting

0 Do not insert a hold extension cycle.

1 Insert a hold extension cycle to extend the read cycle by one cycle.

Table 4.2-20 Settings for the I/O Idle Cycle

WRn1 WRn0 Setting of the I/O idle cycle

0 0 0 cycle

0 1 1 cycle

1 0 2 cycles

1 1 3 cycles

148


[bit27 to bit24, bit19 to bit16, bit11 to bit8] IW03-00,IW13-10,IW23-20 (I/O Wait Cycle: I/Oaccess Wait)

These bits set the auto-wait cycle for I/O access during DMA fly-by access.

Because data is synchronized between the transfer source and transfer destination, the I/O sidesetting of the IWnn bits and the wait setting for the fly-by transfer destination (such as memory),whichever is larger, is used as the number of wait cycles to be inserted. Consequently, morewait cycles than specified by the IWnn bits may be inserted.

IWn3 IWn2 IWn1 IWn0 I/O wait cycle

0 0 0 0 0 cycle

0 0 0 1 1 cycle

... ...

1 1 1 1 15 cycles

149


4.2.5 Chip Select Enable Register (CSER)

This section describes the configuration and functions of the chip select enable register (CSER).

Configuration of the Chip Select Enable Register (CSER)

The chip select enable register (CSER) enables and disables each chip select area.

Figure 4.2-5 shows the configuration of the chip select enable register (CSER).

Figure 4.2-5 Configuration of the Chip Select Enable Register (CSER)

Functions of Bits in the Chip Select Enable Register (CSER)

The following explains the functions of the bits in the chip select enable register (CSER).

[bit31 to bit24] CSE7 to CSE0 (Chip Select Enable: Chip select enable 0-7)

These bits are the chip select enable bits for CS0 to CS7.

The initial value is 00000001B, which enables only the CS0 area.

When "1" is written, a chip select area operates according to the settings of ASR0 to ASR7,ACR0 to ACR7, and AWR0 to AWR7.

Before setting this register, be sure to make all settings required for the corresponding chipselect areas.

bit31 30 29 28 27 26 25 24

0000 0680H CSE7 CSE6 CSE5 CSE4 CSE3 CSE2 CSE1 CSE0 00000001B 00000001B R/W


CSE7-0 Area control

0 Disable

1 Enable

150


Table 4.2-21 lists the corresponding CS_X for the chip select enable bits.

Table 4.2-21 CSnX Corresponding to the Chip Select Enable Bits

CSE bit Corresponding CSnX

bit24: CSE0 CS0

bit25: CSE1 CS1

bit26: CSE2 CS2

bit27: CSE3 CS3

bit28: CSE4 CS4

bit29: CSE5 CS5

bit30: CSE6 CS6

bit31: CSE7 CS7

151


4.2.6 Cache Enable Register (CHER)

This section explains the configuration and functions of the cache enable register (CHER).

Configuration of the Cache Enable Register (CHER)

The cache enable register (CHER) controls the transfer of data read from each chip select area.

Figure 4.2-6 shows the configuration of the cache enable register (CHER).

Figure 4.2-6 Configuration of the Cache Enable Register (CHER)

Functions of Bits in the Cache Enable Register (CHER)

The following explains the functions of the bits in the cache enable register (CHER).

[bit23 to bit16] CHE7 to CHE0 (Cache area setting: Cache Enable 7 to 0)

These bits enable and disable each chip select area for transfers to the built-in cache.

Table 4.2-22 shows the settings for enabling and disabling transfers to the built-in cache.

bit23 22 21 20 19 18 17 16

0000 0681H CHE7 CHE6 CHE5 CHE4 CHE3 CHE2 CHE1 CHE0 11111111B 111111111B R/W


Table 4.2-22 Enabling and Disabling Transfers to the Built-in Cache

CHEn Cache area setting

0 Not a cache area (data read from the applicable area is not saved in the cache)

1 Cache area (data read from the applicable area is saved in the cache)

152


4.2.7 Pin/Timing Control Register (TCR)

This section explains the configuration and functions of the pin/timing control register and its function.

Configuration of the Pin/Timing Control Register (TCR)

The pin/timing control register (TCR) controls the functions related to the general external businterface controller, such as the setting of common pin functions and timing control.

Figure 4.2-7 shows the configuration of the pin/timing control register (TCR).

Figure 4.2-7 Configuration of the Pin/Timing Control Register (TCR)

Functions of Bits in the Pin/Timing Control Register (TCR)

The following explains the functions of the bits in the pin/timing control register (TCR).

[bit7] BREN (BRQ input enable: BRQ enable)

This bit enables BRQ pin input and external bus sharing.

Table 4.2-23 shows the settings for enabling BRQ pin input.

In the initial state ("0"), BRQ input is ignored. When "1" is set, the bus is made open (controlwith high impedance) and BGRNT is activated ("L" level is output) when the bus is ready to bemade open after the BRQ input becomes "H" level.

[bit6] PSUS (Prefetch suspend: Prefetch SUSpend)

This bit controls temporary stopping of prefetch to all areas.

Table 4.2-24 shows the settings for temporarily stopping prefetch to all areas.

bit7 6 5 4 3 2 1 0

0000 0683H BREN PSUS PCLR Reserved OHT1 OHT0 RDW1 RDW0 00000000B 0000xxxxB W


Table 4.2-23 Enabling BRQ Pin Input

BREN BRQ input enable setting

0No bus sharing by BRQ/BGRNT.BRQ input is disabled.

1Bus sharing by BRQ/BGRNT.BRQ input is enabled.

Table 4.2-24 Temporarily Stopping Prefetch to All Areas

PSUS Prefetch control

0 Enable prefetch

1 Suspend prefetch.

153


If "1" is set, no new prefetch operation is performed before "0" is written. Since during this timethe contents of the prefetch buffer are not deleted unless a prefetch buffer occurs, clear theprefetch buffer using the PCLR bit function (bit5) before restarting prefetch.

[bit5] PCLR (Prefetch buffer all clear: Prefetch buffer CleaR)

This bit completely clears the prefetch buffer.

Table 4.2-25 shows the settings for prefetch buffer control.

If "1" is written, the prefetch buffer is cleared completely. When clearing is completed, the bitvalue automatically returns to "0". Interrupt (set to "1") the prefetch by the PSUS bit and thenclear the buffer (It is also possible to write "10B" to both the PSUS and PCLR bits).

[bit4] Reserved (Reserved bit)

This bit is reserved. Be sure to set it to "0".

[bit3, bit2] OHT1, OHT0 (Output hold delay selection: Output Hold Throttle)

These bits adjust the delay value for holding external control signal output to external clockMCLK output. Table 4.2-26 shows the settings for output hold delay selection.

The delay value is the target value under typical conditions.

Asynchronous reading, write strobes (RD/WR0/WR1/WR2/WR3/WR/IOWR/IORD), and the falltiming of delayed CSX are not subject to this delay value adjustment.

Although OHT1, OHT0 do not malfunction if they are rewritten during operation, external busoperation stops temporarily when the timing is switched.

Table 4.2-25 Settings for Prefetch Buffer Control

PCLR Prefetch buffer control

0 Normal state

1 Clear the prefetch buffer.

Table 4.2-26 Settings for Output Hold Delay Selection

OHT1 OHT0 Output hold delay selection

0 0 Output on fall of SYSCLK/MCLK.

0 1 Output (3 ns) after SYSCLK/MCLK rises.

1 0 Output (4 ns) after SYSCLK/MCLK rises.

1 1 Output (5 ns) SYSCLK/MCLK rises.

154


[bit1, bit0] RDW1,RDW0 (Wait cycle reduction: ReDuce Wait cycle)

These bits instruct all chip select areas and fly-by I/O channels to reduce only the number ofauto-wait cycles in the auto-access cycle wait settings uniformly while the AWR registersettings are retained unchanged. The settings for idle cycles, recovery cycles, setup, andhold cycles are not affected. Table 4.2-27 shows the settings for wait cycle reduction.

The purpose of this function is to prevent an excessive access cycle wait during operation on alow-speed clock (for example, when the base clock is switched to low speed or the frequencydivision ratio setting of the external bus clock is large).

To reset the wait cycle in these cases, each of the AWRs must usually be rewritten one at atime. However, when the RDW1/RDW0 bit function is used, the access cycle wait is reducedfor all of the AWRs in a single operation while all of the other high-speed clock settings in eachregister are retained.

Before returning the clock to high speed, be sure to reset the RDW1/RDW0 bits to "00B".

Note:

The TCR register is a write only register (cannot be read). The TCR register can only be writtento. The TCR register value cannot be read.

Table 4.2-27 Settings for Wait Cycle Reduction

RDW1 RDW0 Wait cycle reduction

0 0 Normal wait (AWR0 to AWR7 settings)

0 1 1/2 (1-bit shift to the right) of the AWR0 to AWR7 settings



155


4.3 Setting Example of the Chip Select Area

In the external bus interface, a total of eight chip select areas can be set.This section presents an example of setting the chip select area.

Example of Setting the Chip Select Area

The address space of each area can be placed, in units of a minimum of 64 KB, anywhere inthe 4 GB space using ASR0 to ASR7 (Area Select Registers) and ACR0 to ACR7 (AreaConfiguration Registers). When bus access is made to an area specified by these registers, thecorresponding chip select signals (CS0 to CS7) are activated ("L" output) during the accesscycle.

Example of setting ASRs and ASZ3-0

• ASR1=0003H ACR1 ASZ[3:0]=0000B: Chip select area 1 is assigned to 00030000H to0003FFFFH.

• ASR2=0FFCH ACR2 ASZ[3:0]=0010B: Chip select area 2 is assigned to 0FFC0000H to10000000H.

• ASR3=0011H ACR3 ASZ[3:0]=0100B: Chip select area 3 is assigned to 00100000H to00200000H.

Since at this point 1 MB is set for bits ASZ3-0 from the ACR, the unit for boundaries 1 MB and19-16 of ASR3 are ignored. Before there is any writing to ACR0 after a reset, 00000000H toFFFFFFFFH is assigned to chip select area 0.

Note:

Set the chip select areas so that there is no overlap.

Figure 4.3-1 shows an example of setting the chip select area.

Figure 4.3-1 Example of Setting the Chip Select Area

(Initial value) (Example)

00000000H 00000000H

00030000H Area 1 64 KB

00040000H

Area 0 00100000H

Area 3 1 MB

00200000H

0FFC0000H

0FFFFFFFH

Area 2 256 KB

FFFFFFFFH FFFFFFFFH

156



There is a one-to-one correspondence between the WR3 to WR0 control signals and the location of the bytes on the data bus regardless of the data bus width.This section summarizes the location of the bytes on the data bus used for the specified data bus width and the corresponding control signal for each bus mode.

Relationship between Data Bus Width and Control Signal

Ordinary bus interface

Figure 4.4-1 Data Bus Width and Control Signal on the Ordinary Bus Interface

Time division I/O interface

Figure 4.4-2 Data Bus Width and Control Signal in the Time Division I/O Interface

D31

D0

a) 32-bit bus width

data bus Control signal

WR0(UUB)

WR1(ULB)

WR2(LUB)

WR3

data bus Control signal data bus Control signal

WR0(UUB)

WR1(ULB)

WR0(UUB)

-

-

-

-

-

b) 16-bit bus width c) 8-bit bus width

(D15-0 are not used) (D23-0 are not used)

-

-

-

-

-(LLB)

D31

D0

a) 32-bit bus width

data bus Control signal

WR0(UUB)

WR1(ULB)

WR2(LUB)

WR3

data bus Control signal data bus Control signal

WR0(UUB)

WR1(ULB)

WR0(UUB)

-

-

-

-

-

b) 16-bit bus width c) 8-bit bus width

(D15-0 are not used) (D23-0 are not used)

-

-

-

-

-(LLB)

157


4.4.1 Big Endian Bus Access

Except for the CS0 area, the FR Family can switch between the big endian method and little endian method for each chip select area. When the LEND bit of the ACR register is set to "0", the chip select area is treated as big endian.Normally, the FR Family executes external bus access using big endian.

Data Format

The relationship between the internal register and the external data bus is as follows:

Figure 4.4-3 Word Access (when LD/ST instruction executed)

Figure 4.4-4 Halfword access (when LDUH/STH instruction executed)

D31

D15

D23

D7

D0

AA

BB

CC

DD

Internal register

D31

D15

D23

D7

D0

AA

BB

CC

DD

External register

D31

D15

D23

D7

D0

AA

BB

D31

D15

D23

D7

D0

AA

BB

D31

D15

D23

D7

D0

AA

BB

D31

D15

D23

D7

D0

AA

BB

a) Output address low-order b) Output address low-order digits "00" digits "10"

Internal register External bus Internal register External bus

158


Figure 4.4-5 Byte access (when LDUB/STB instruction executed)

Data Bus Width

Figure 4.4-6 32-Bit Bus Width


Figure 4.4-8 8-Bit bus Width

D31

D15

D23

D7

D0AA

D31

D15

D23

D7

D0

AAD31

D15

D23

D7

D0AA

D31

D15

D23

D7

D0

AA

D31

D15

D23

D7

D0AA

D31

D15

D23

D7

D0

AA

D31

D15

D23

D7

D0AA

D31

D15

D23

D7

D0

AA

a) Output address b) Output address c) Output address d) Output address low-order digits "00" low-order digits "01" low-order digits "10" low-order digits "11"

Internal External Internal External Internal External Internal External register bus register bus register bus register bus

read/write

D07

D15

D23

D31

D07

D15

D23

D31

External busInternal register

AA

BB

CC

DD

AA

BB

CC

DD

read/write

D07

D15

D23

D31

D23

D31"00"

External bus

Output address low-order digits

Internal register

"10"

AA

BB

CC

DD

AA

BB

CC

DD

D07

D15

D23

D31 D31AA

BB

CC

DD

AA BB CC DDread/write

"00"

External bus

Output address low-order digits

Internal register

"01" "10" "11"

159


External Bus Access

For external bus access, the following items are arranged as illustrated later for bus widths of32-bit, 16-bit and 8-bit and for word, halfword, and byte access.

• Access byte location

• Program address and output address

• Bus access count

PA1/PA0: Two low-order bits of the address specified by the program

Output A1/A0: Two low-order bits of the output address

: Location of initial byte of the output address

+ : Data byte location to be accessed

(1) to (4) : Bus access count

FR family does not detect misalignment errors.

Therefore, for word access, the lower two bits of the output address are always 00 regardless ofwhether 00, 01, 10, or 11 is specified as the lower two bits by the program. For halfwordaccess, the lower two bits of the output address are 00 if the lower two bits specified by theprogram are 00 or 01, and are 10 if 10 or 11.

160



(a) PA1/PA0=00→(1) Output A1/A0=00

(b) PA1/PA0=01→(1) Output A1/A0=00

(c)PA1/PA0=10→(1) Output A1/A0=00

(d)PA1/PA0=11→(1) Output A1/A0=00

(a) PA1/PA0=00→(1) Output A1/A0=00

(b) PA1/PA0=01→(1) Output A1/A0=00

(c)PA1/PA0=10→(1) Output A1/A0=10

(d)PA1/PA0=11→(1) Output A1/A0=10

(a) PA1/PA0=00→(1) Output A1/A0=00

(b) PA1/PA0=01→(1) Output A1/A0=01

(c)PA1/PA0=10→(1) Output A1/A0=10

(d)PA1/PA0=11→(1) Output A1/A0=11

111001

(1)

LSBMSB

32bit

00 111001

(1)

00 111001

(1)

00 111001

(1)

00

(A) Word access

(B) Halfword access

(C) Byte access

111001

(1)

00

(1)

111001

(1)

00 111001

(1)

0011100100

111001

(1)

00 111001

(1)

00 111001

(1)

00 111001

(1)

00

161



1110

01

LSBMSB

00(1)

(2)

(1)

(2)

(1)

(2)

(1)

(2)1110

0100

1110

0100

1110

0100

(a) PA1/PA0=00 (1) Output A1/A0=00 (2) Output A1/A0=10

(b) PA1/PA0=01 (1) Output A1/A0=00 (2) Output A1/A0=10

(c) PA1/PA0=10 (1) Output A1/A0=00 (2) Output A1/A0=10

(d) PA1/PA0=11 (1) Output A1/A0=00 (2) Output A1/A0=10

1110

0100

1110

0100

1110

0100

1110

0100

(a) PA1/PA0=00 (1) Output A1/A0=00

(b) PA1/PA0=01 (1) Output A1/A0=01

(c) PA1/PA0=10 (1) Output A1/A0=10

(d) PA1/PA0=11 (1) Output A1/A0=11

(1) (1)

(1) (1)

1110

0100

1110

0100

1110

0100

1110

0100

(a) PA1/PA0=00 (1) Output A1/A0=00

(b) PA1/PA0=01 (1) Output A1/A0=00

(c) PA1/PA0=10 (1) Output A1/A0=10

(d) PA1/PA0=11 (1) Output A1/A0=10

(1) (1)

(1) (1)

(A) Word access

(B) Halfword access

(C) Byte access

162



11

10

01

00

11

10

01

00

11

10

01

00

11

10

01

00

(a) PA1/PA0=00 (1) Output A1/A0=00

(b) PA1/PA0=01 (1) Output A1/A0=00

(c) PA1/PA0=10 (1) Output A1/A0=10

(d) PA1/PA0=11 (1) Output A1/A0=10

(1)

(1)

(1)

(1)

LSBMSB

11

10

01

(1)

(2)

(3)

(4)

(1)

(2)

(3)

(4)

(1)

(2)

(3)

(4)

(1)

(2)

(3)

(4)

8bit

00

11

10

01

00

11

10

01

00

11

10

01

00

(a) PA1/PA0=00 (1) Output A1/A0=00 (2) Output A1/A0=01 (3) Output A1/A0=10 (4) Output A1/A0=11

(b) PA1/PA0=01 (1) Output A1/A0=00 (2) Output A1/A0=01 (3) Output A1/A0=10 (4) Output A1/A0=11

(c) PA1/PA0=10 (1) Output A1/A0=00 (2) Output A1/A0=01 (3) Output A1/A0=10 (4) Output A1/A0=11

(d) PA1/PA0=11 (1) Output A1/A0=00 (2) Output A1/A0=01 (3) Output A1/A0=10 (4) Output A1/A0=11

(A) Word access

(B) Halfword access

(C) Byte access

11

10

01

00

11

10

01

00

11

10

01

00

11

10

01

00

(a) PA1/PA0=00 (1) Output A1/A0=00 (2) Output A1/A0=01

(b) PA1/PA0=01 (1) Output A1/A0=00 (2) Output A1/A0=01

(c) PA1/PA0=10 (1) Output A1/A0=10 (2) Output A1/A0=11

(d) PA1/PA0=11 (1) Output A1/A0=10 (2) Output A1/A0=11

(1)

(2)

(1)

(2)

(1)

(2)

(1)

(2)

163


Example of Connection with External Devices

Figure 4.4-12 shows an example of connection the MB91310 to external devices.

Figure 4.4-12 Example of Connecting the MB91310 to External Devices

D31 D07 D00D00D15D00D16 D15 D08 D07D08 D07D24 D23

D31 W | RD24 0 X

D23 W | RD16 1 X

D15 W | RD08 2 X

D07 W | RD00 3 X

00 01 10 11 0 1 0

*) For 16/8-bit devices, use the data bus on the MSB side of this LSI.

32-bit device (low-order 2 bits of the address 00-11)

*) 16-bit device (low-order 1 bit of the address 0/1)

*) 8-bit device

164


4.4.2 Little Endian Bus Access

Except for the CS0 area, the FR Family can switch between the big endian method and little endian method for each chip select area. When the LEND bit of the ACR register is set to "1", the chip select area is treated as little endian.Little endian bus access of the FR Family is implemented by using the bus access operation used for the big endian method. Basically, the order of output addresses and control signal output are the same as those for the big endian method and the locations of the bytes on the data bus are swapped in accordance with the bus width.Note that, when a connection is made, the big endian area and the little endian area must be kept physically separate.

Differences between Little Endian and Big Endian

The following explains the differences between little endian and big endian.

The order of addresses that are output is the same for little endian and big endian.

Word access

The byte data on the MSB side for big endian address A1, A0=00 becomes byte data on theLSB side when the little endian method is used.

For a word address, the locations of all four bytes in the word are reversed:

Halfword access

The byte data on the MSB side for the big endian address A0 becomes byte data on the LSBside when the little endian method is used.

For halfword access, the byte locations of two bytes are reversed.

Byte access

There is no difference between little endian and big endian.

There is no difference between little endian and big endian for the data bus and control signalused for 32-bit, 16-bit, and 8-bit bus widths.

Restrictions on the Little Endian Area

• If prefetch is enabled for a little endian area, always use word access to access the area. Ifdata written to the prefetch buffer is accessed with any length other than word length, thecorrect endian conversion is not performed and the wrong data will be read. The reason ishardware restrictions related to the endian conversion mechanism.

• Do not place any instruction code in a little endian area.

• Access to the 32-bit little endian area is restricted to word access. For an area set to theexternal bus 32-bit width and for the little endian area, access (write and read) the area usingonly word access. Access (write and read) using halfword or byte access will not beexecuted correctly.

165


Data Format

The relationship between the internal register and external data bus is as follows:

Figure 4.4-13 Relationship between the Internal Register and External Data Bus for Word Access

Figure 4.4-14 Relationship between Internal Register and External Data Bus for Halfword Access

Figure 4.4-15 Relationship between Internal Register and External Data Bus for Byte Access

D31

D15

D23

D7

D0

AA

BB

CC

DD

Internal registerD31

D15

D23

D7

D0AA

BB

CC

DD

External bus

(1) Word access (when executing the LD/ST instructions)

D31

D15

D23

D7

D0

AA

BB

D31

D15

D23

D7

D0

AA

BBD31

D15

D23

D7

D0

AA

BB

D31

D15

D23

D7

D0AA

BB

(2) Halfword access (when executing the LDUH/STH instructions)

a) Output address low-order digits b) Output address low-order digits

Internal register External bus Internal register External bus

D31

D15

D23

D7

D0AA

D31

D15

D23

D7

D0

AAD31

D15

D23

D7

D0AA

D31

D15

D23

D7

D0

AA

D31

D15

D23

D7

D0AA

D31

D15

D23

D7

D0

AA

D31

D15

D23

D7

D0AA

D31

D15

D23

D7

D0AA

(3) Byte access (when executing the LDUB/STB instructions)a) Output address b) Output address c) Output address d) Output address low-order digits low-order digits low-order digits low-order digits Internal External Internal External Internal External Internal External register bus register bus register bus register bus

166


Data Bus Width




read/write

D07

D15

D23

D31

D07

D15

D23

D31

External busInternal register

AA

BB

CC

DD

DD

CC

BB

AA

D07

D15

D23

D31

D23

D31"00" "10"

External busInternal registerOutput address low-order digits

AA

BB

CC

DD

BB

AA

DD

CC

read/write

D07

D15

D23

D31 D31"00" "01"

AA

BB

CC

DD

CCDD

"10" "11"

AABBread/write

External busInternal registerOutput address low-order digits

167


Examples of Connection with External Devices

The following shows examples of connecting the MB91310 to external devices for each buswidth.



10 0011

D31 D08D07 D00D16D15D31D00D16D15 D24D23D08D07D24D23

D07 W | RD00 3

X

D15 W | RD08 2

X

D23 W | RD16 1

X

D31 W | RD24 0

X

00 01 1110 01

Little endian areaBig endian area

big endian area

D31 W | RD24 0 X

D23 W | RD16 1 X

D00D15 D08 D07

0 1

little endian area

D00D15 D08 D07

1 0

168



D00D07 D00D07

big endian area

D31 W | RD24 0 X

little endian area

169


4.4.3 Comparison of Big Endian and Little Endian External Access

This section shows a comparison of big endian and little endian external access in word access, halfword access, and byte access for each bus width.

Word Access

Big endian mode Little endian mode

32-bit bus width

16-bit bus width

Control pin

Internal Reg

External pin

Address 2 low-order bits: "0"

(1)D00D00

D31D31AA

CC

BB

DD

WR0

WR1

WR2

WR3

AA

CC

BB

DD

Control pin

Internal Reg

External pin

Address: "0"

(1)D00D00

D31D31AA

CC

BB

DD

WR0

WR1

WR2

WR3

DD

BB

CC

AA

address: "0" "2"

D00

D31D31AA

CC

BB

DD

WR0

WR1

AA CC

BB DD

Internal External Control Reg pin pin

(1) (2)

D16

AA

CC

BB

DD

WR0

WR1

DD BB

CC AAD16

address: "0" "2"


D00

D31D31

D16

(1) (2)

170


8-bit bus width


"0" "1" "2" "3"

AA AA BB CC DD

CC

BB

DD

WR0

(1) (2) (3) (4)

address:


D00

D31D31

D24AA AADD CC BB

CC

BB

DD

WR0

"0" "1" "2" "3"address:


D00

D31D31

D24

(1) (2) (3) (4)

171


Halfword Access


32-bit bus width

Control pin

Internal Reg

External pin

address: "0"

(1)D00D00

D31D31

AA

BB

WR0

WR1

AA

BB

Control pin

Internal Reg

External pin

address: "0"

WR0

WR1

D00D00

D31D31

AA

BB

(1)

AA

BB

Control pin

Internal Reg

External pin

address: "2"

WR2

WR3D00D00

D31D31

CCCC

DDDD

(1)

Control pin

Internal Reg

External pin

address: "2"

WR2

WR3D00D00

D31D31

CC

CC DD

DD

(1)

172


16-bit bus width

8-bit bus width


AA

BB

WR0

WR1BB

AA

address: "0"

D00

D31D31


(1)

D16AA

BB

WR0

WR1

B

A

address: "0"

D00

D31D31


(1)

D16

CC

DD

WR0

WR1DD

CC

address: "2"

D00

D31D31


(1)

D16CC

DD

WR0

WR1DD

CC

address: "2"

D00

D31D31


(1)

D16

AA

BB

WR0BBAA

address: "0" "1"

D00 D00

D31D31


(1) (2)

D24

AA

BB

WR0AABB

address: "0" "1"

D00 D00

D31D31


(1) (2)

D24

CC

DD

WR0DDCC

address: "2" "3"

D00 D00

D31D31


(1) (2)

D24

CC

DD

WR0CCDD

address: "2" "3"

D00 D00

D31D31


(1) (2)

D24

173


Byte Access


32-bit bus width

Control pin

Internal Reg

External pin

address: "0"

WR0

D00D00

D31D31

AA

(1)

AA WR0

D00D00

D31D31

AA

(1)

AA

Control pin

Internal Reg

External pin

address: "0"

WR1

D00D00

D31D31

BB

(1)

BB

Control pin

Internal Reg

External pin

address: "1"

WR1

D00D00

D31D31

BB

(1)

BB

Control pin

Internal Reg

External pin

address: "1"

WR2

D00D00

D31D31

CC

(1)

CC

Control pin

Internal Reg

External pin

address: "2"

WR2

D31D31

D00D00CC

(1)

CC

Control pin

Internal Reg

External pin

address: "2"

174


32-bit bus width


WR3D00D00

D31D31

DD

(1)

DD

Control pin

Internal Reg

External pin

address: "3"

WR3D00D00

D31D31

DD

(1)

DD

Control pin

Internal Reg

External pin

address: "3"

175


16-bit bus width


AA

AA WR0

address: "0"

D00

D31D31


(1)

D16

AA

AA WR0

address: "0"

D00

D31D31


(1)

D16

BB

BB WR1

address: "1"

D00

D31D31


(1)

D16

BB

BB WR1

address: "1"

D00

D31D31


(1)

D16

CC

CC WR0

address: "2"

D00

D31D31


(1)

D16

CC

CC WR0

address: "2"

D00

D31D31


(1)

D16

DD

DD WR1

address: "3"

D00

D31D31


(1)

D16

DD

DD WR1

address: "3"

D00

D31D31


(1)

D16

176


8-bit bus width


AA

AA WR0

address: "0"

D00

D31D31


(1)

D24

AA

AA WR0

address: "0"

D00

D31D31


(1)

D24

BB

BB WR0

address: "1"

D00

D31D31


(1)

D24

BB

BB WR0

address: "1"

D00

D31D31


(1)

D24

CC

CC WR0

address: "2"

D00

D31D31


(1)

D24

CC

CC WR0

address: "2"

D00

D31D31


(1)

D24

DD

DD WR0

address: "3"

D00

D31D31


(1)

D24

DD

DD WR0

address: "3"

D00

D31D31


(1)

D24

177



This section explains operation of the ordinary bus interface.

Ordinary Bus Interface

For the ordinary bus interface, two clock cycles are the basic bus cycles for both read accessand write access.

The following operational phases of the ordinary bus interface are explained below with the useof a timing chart.

• Basic timing (for successive accesses)

• WR + byte control type

• Read -> write

• Write -> write

• Auto-wait cycle

• External wait cycle

• Synchronous write enable output

• CSX delay setting

• CSX -> RD/WR setup, RD/WR -> CSX hold setting

• DMA fly-by transfer (I/O -> memory)

• DMA fly-by transfer (memory -> I/O)

178


4.5.1 Basic Timing

This section shows the basic timing for successive accesses.

Basic Timing (For Successive Accesses)

Figure 4.5-1 shows the operation timing for (TYP[3:0] = 0000B, AWR = 0008H )

Figure 4.5-1 Basic Timing (For Successive Accesses)

• AS is asserted for one cycle in the bus access start cycle.

• A[31:0] continues to output the address of the location of the start byte in word/halfword/byteaccess from the bus access start cycle to the bus access end cycle.

• If the W02 bit of the AWR0 to AWR7 registers is "0", CS0 to CS7 are asserted at the sametiming as AS. For successive accesses, CS0 to CS7 are not negated. If the W00 bit of theAWR register is "0", CS0 to CS7 are negated after the bus cycle ends. If the W00 bit is "1",CS0 to CS7 are negated one cycle after bus access ends.

• RD and WR0 to WR3 are asserted from the 2nd cycle of the bus access. Negation occursafter the wait cycle of bits W15 to W12 of the AWR register is inserted. The timing ofasserting RD and WR0 to WR3 can be delayed by one cycle by setting the W01 bit of theAWR register to "1". However, depending on the internal state, the assertion of WR0 toWR3 may not start in the 2nd cycle and may even be delayed if the W01 bit is set to "0".

• If a setting is made so that WR0 to WR3 is used like TYP[3:0]=0x0xB, WR is always "H".

• For read access, D[31:0] is read when MCLK rises in the cycle in which the wait cycle endedafter RD was asserted.

• For write access, data output to D[31:0] starts at the timing at which WR0 to WR3 areasserted.

MCLK

A[31:0]

AS

CSnX

RD

D[31:0]

WRnX

D[31:0]

READ

WRITE

#1 #2

#1 #2

#1 #2

179


4.5.2 Operation of WR + Byte Control Type

This section shows the operation timing for the WR + byte control type.

Operation Timing of the WR + Byte Control Type

Figure 4.5-2 shows the operation timing for (TYP[3:0] = 0010B, AWR = 0008H).

Figure 4.5-2 Timing Chart for the WR + Byte Control Type

• Operation of AS, CSnX, RD, A[31:0], and D[31:0] is the same as that described in "4.5.1Basic Timing".

• WR is asserted from the 2nd cycle of the bus access. Negation occurs after the wait cycle ofbits W15 to W12 of the AWR register is inserted. The timing of asserting RD and WR0 toWR3 can be delayed by one cycle by setting the W01 bit of the AWR register to "1".However, depending on the internal state, assertion of WR0 to WR3 may not start in the 2ndcycle and may even be delayed if the W01 bit is set to "0". (Operation is the same as that forWR0 to WR3 described in "4.5.1 Basic Timing" .)

MCLK

AS

CSnX *

RD

READ

WR

WR0, WR1

WR2, WR3WRITE

A[31:0]

D[31:0]

D[31:0]

WR2, WR3

WR0, WR1

180


• WR0 to WR3 indicate the byte location expressed with negative logic when they are used foraccess as the byte enable signal (UUB, ULB, LUB, LLB). Assertion continues from the busaccess start cycle to the bus access end cycle and changes at the same timing as theaddress timing. The byte location for access is indicated for both read access and writeaccess.

• For write access, data output to D[31:0] starts at the timing at which WR is asserted.

• If the areas defined by TYP[3:0]=0x0xB (WR0 to WR3 used) and TYP[3:0]=0x1xB (WR +byte control) are mixed, be sure to make the following setting for all areas that will be used.(For details, see the notes).

• Set at least one read -> write idle cycle.

• Set at least one write recovery cycle.

181


4.5.3 Read -> Write Operation

This section shows the operating timing for read -> write.

Operation Timing of Read -> Write

Figure 4.5-3 shows the operation timing for (TYP[3:0]=0000B, AWR=0048H).

Figure 4.5-3 Timing Chart for Read -> Write

• Setting of the W07/W06 bits of the AWR register enables 0-3 idle cycles to be inserted.

• Settings in the CS area on the read side are enabled.

• This idle cycle is inserted if the next access after a read access is write access or access toanother area.

MCLK

AS

CSnX

RD

WRnX

D[31:0]

A[31:0]

Read WriteIdle*

182


4.5.4 Write -> Write Operation

This section shows the operation timing for write -> write.

Write -> Write Operation


Figure 4.5-4 Timing Chart for the Write -> Write Operation

• Setting of the W05/W04 bits of the AWR register enables 0-3 write cycles to be inserted.

• After all of the write cycles, recovery cycles are generated.

• Write recovery cycles are also generated if write access is divided into phases for accesswith a bus width wider than that specified.

Read WriteWrite recovery *

MCLK

AS

CSnX

WRnX

D[31:0]

A[31:0]

183


4.5.5 Auto-Wait Cycle

This section shows the operation timing for the auto-wait cycle.

Auto-Wait Cycle Timing


Figure 4.5-5 Timing Chart for the Auto-Wait Cycle

Setting of the W15 to W12 bits (first wait cycles) of the AWR register enables 0-15 auto-waitcycles to be set.

In Figure 4.5-5 , two auto-wait cycles are inserted, making a total of four cycles for access. Ifauto-wait is set, the minimum number of bus cycles is 2 cycles + (first wait cycles). For a writeoperation, the minimum number of bus cycles may be still longer depending on the internalstate.

Basic cycle Wait cycle *

MCLK

A[31:0]

AS

CSnX

RD

D[31:0]

WRnX

D[31:0]

184


4.5.6 External Wait Cycle

This section shows the operation timing for the external wait cycle.

External Wait Cycle Timing


Figure 4.5-6 Timing Chart for the External Wait Cycle

Setting "1" for the TYP0 bit of the ACR register and enabling the external RDY input pin enablesexternal wait cycles to be inserted.

Basic cycle 2 auto-wait cycles Wait cycle by RDY

Wait

Release

MCLK

AS

CSnX

RD

A[31:0]

D[31:0]

D[31:0]

WRnX

RDY

185


4.5.7 Synchronous Write Enable Output

This section shows the operation timing for synchronous write enable output.

Operation Timing for Synchronous Write Enable Output


Figure 4.5-7 Timing Chart for Synchronous Write Enable Output

• If synchronous write enable output is enabled (If the W03 bit of the AWR is "0"), operation isas follows.

• WR0 to WR3 and WR pin output asserts synchronous write enable output at the timing atwhich AS pin output is asserted. For a write to an external bus, the synchronous writeenable output is "L". For a read from an external bus, the synchronous write enable output is"H".

• Write data is output from the external data output pin in the clock cycle following the cycle inwhich synchronous write enable output is asserted. If write data cannot be output becausethe internal bus is temporarily unavailable, assertion of synchronous write enable output maybe extended until write data can be output.

• Read strobe output (RD) functions as an asynchronous read strobe regardless of the settingof WR0 to WR3 and WR output timing. Use it as is for controlling the data I/O.

Read

Write

#1 #2

#1 #2

#1 #2

MCLK

AS

CSnX *

RD

D[31:0]

WRnX

D[31:0]

A[31:0]

186


• If synchronous write enable output is used, the following restrictions apply:

Do not set the following additional wait because the timing for synchronous write enableoutput becomes meaningless:

- CSX -> RD/WR setup

(Always write "0" to the W01 bit of AWR)

- First wait cycle setting

(Always write "0000B" to bits W15 to W12 of AWR)

Do not set the following access types (TYP[3:0] bits (Bits 3-0) in the ACR register) becausethe timing for synchronous write enable output becomes meaningless:

- Multiplex bus setting

(Always write "0" to the TYP2 bit of ACR)

- RDY input enable setting

(Always write "0" to the TYP0 bit of ACR)

• For synchronous write enable output, always set the burst length to 1

(set bits BST1 and BST0 to "00B").

187


4.5.8 CSX Delay Setting

This section shows the operation timing for the CSX delay setting.

Operation Timing for the CSX Delay Setting

Figure 4.5-8 shows the operation timing for (TYP[3:0]=0000B, AWR=000CH).

Figure 4.5-8 Operation Timing Chart for the CSX Delay Setting

If the W02 bit is "1", assertion starts in the cycle following the cycle in which AS is asserted. Forsuccessive accesses, a negation period is inserted.

READ

WRITE

MCLK

AS

CSnX

RD

D[31:0]

WRnX

D[31:0]

A[31:0]

188


4.5.9 CSX -> RD/WR Setup and RD/WR -> CSX Hold Setting

This section shows the operation timing for the CSX -> RD/WR setup and RD/WR -> CSX hold settings.

Operation Timing for the CSX -> RD/WR Setup and RD/WR -> CSX Hold Settings

Figure 4.5-9 shows the operation timing for (TYP[3:0]=0000B AWR=000BH).

Figure 4.5-9 Timing Chart for the CSX -> RD/WR Setup and RD/WR -> CSX Hold Settings

• Setting "1" for the W01 bit of the AWR register enables the CSX -> RD/WR setup delay to beset. Set this bit to extend the period between chip select assertion and read/write strobe.

• Setting "1" for the W00 bit of the AWR register enables the RD/WR -> CSX hold delay to beset. Set this bit to extend the period between read/write strobe negation and chip selectnegation.

• The CSX -> RD/WR setup delay (W01 bit) and RD/WR -> CSX hold delay (W00 bit) can beset independently.

• When making successive accesses within the same chip select area without negating thechip select, neither a CSX -> RD/WR setup delay nor an RD/WR -> CSX hold delay isinserted.

• If a setup cycle for determining the address or a hold cycle for determining the address isneeded, set "1" for the address -> CSX delay setting (W02 bit of the AWR register).

READ

WRITE

MCLK

AS

CSnX

RD

D[31:0]

WRnX

D[31:0]

A[31:0]

CS->RD/WRDelay

RD/WR->CSDelay

189


4.5.10 DMA Fly-By Transfer (I/O -> Memory)

This section shows the operation timing for DMA fly-by transfer (I/O -> memory).

Operation Timing for DMA Fly-By Transfer (I/O -> Memory)

Figure 4.5-10 shows the operation timing for (TYP[3:0]=0000B, AWR=0008H, IOWR=51H). Thistiming chart shows a case in which a wait is not set on the memory side.

Figure 4.5-10 Timing Chart for DMA Fly-By Transfer (I/O -> Memory)

• Setting "1" for the HLD bit of the IOWR0 to IOWR2 registers enables the I/O read cycle to beextended by one cycle.

• Setting bits IW3 to IW0 of the IOWR0 to IOWR2 registers enables 0-15 wait cycles to beinserted.

• If wait is also set on the memory side (AWR:W15 toW12 is not "0"), the larger value is usedas the wait cycle after comparison with the I/O wait (IW3 to IW0 bits).

DACKnX(IORD)

Basic cycle Basic cycle

MCLK

AS

CSnX

WRnX

D[31:0]

A[31:0]

I/O wait cycle *1

I/O hold wait *2

I/O wait cycle *1

I/O hold wait *2

I/O idle cycle

190


4.5.11 DMA Fly-By Transfer (Memory -> I/O)

This section shows the operation timing for DMA fly-by transfer (memory -> I/O).

Operation Timing for DMA Fly-By Transfer (Memory -> I/O)

Figure 4.5-11 shows the operation timing chart for (TYP[3:0]=0000B, AWR=0008H, IOWR=51H).This timing chart shows a case in which a wait is not set on the memory side.

Figure 4.5-11 Timing Chart for DMA Fly-By Transfer (Memory -> I/O)

• Setting "1" for the HLD bit of the IOWR0 to IOWR2 registers enables the I/O read cycle to beextended by one cycle.

• Setting the WR1, WR0 bits of the IOWR0 to IOWR2 registers enables 0-3 write recoverycycles to be inserted.

• If the write recovery cycle is set to "1" or more, a write recovery cycle is always inserted afterwrite access.

• Setting bits IW3 to IW0 of the IOWR0 to IOWR2 registers enables 0-15 wait cycles to beinserted.

• If wait is also set on the memory side (AWR:W15 to W12 is not "0"), the larger value is usedas the wait cycle after comparison with the I/O wait (IW3 to IW0 bits).

RD

DACKnX(IOWR)

MCLK

AS

CSnX

D[31:0]

A[31:0]

Basic cycle Basic cycleI/O wait cycle *1

I/O hold wait *2

I/O wait cycle *1

I/O hold wait *2

I/O idle cycle

191



In the external bus interface, the operation that transfers successive data items in one access sequence is called burst access. The normal access cycle (that is, not burst access) is called single access. One access sequence starts with an assertion of AS and CSX and ends with negation of CSX. Multiple data items two or more units of data of the unit set for the area.This section explains burst access operation.

Burst Access Operation

Figure 4.6-1 shows the operation timing chart for (first wait cycle: 1, page wait cycle: 1,TYP[3:0]=0000B, AWR=3208H).

Figure 4.6-1 Timing Chart for Burst Access

• In the external bus interface, the operation that transfers successive data items in oneaccess sequence is called burst access. The normal access cycle (that is, not burst access)is called single access. One access sequence starts with an assertion of AS and CSX andends with negation of CSX. Multiple data items means two or more units of data having thebus width set for the area.

• In addition to more efficient use of access cycles when a sizable amount of data ofasynchronous memory such as page mode ROM and burst flash memory is read, burstcycles can also be used for reading from normal asynchronous memory.

• The access sequence when burst cycles are used can be divided into the following twotypes:

- First access cycle

MCLK

AS(LBA)

CSnX

RD

WRnX

D[31:0]

A[31:0]

WRnXWR

BAA

First cycle wait *1

Inpage access wait *2

Inpage access

wait

Inpage access

wait

192


The first access cycle is the start cycle for the burst access and operates in the same way asthe normal single access cycle.

- Page access cycle

The page access cycle is a cycle following the first access cycle in which both CSX and RD(read strobe) are asserted. Wait cycles that are different from those set for a single cyclecan be set. The page access cycle is repeated while access remains in the addressboundary determined by the burst length setting. When access within the address boundaryends, burst access terminates and CSX is negated.

• Setting of the W15 to W12 bits of the AWR register enable the first 0-15 wait cycles to beinserted. At this point, the minimum number of the first access cycles is the wait cycles + 2cycles (three cycles in Figure 4.6-1 ).

• Setting of the W11 to W08 bits of the AWR register enables 0-15 page wait cycles to beinserted. At this point, the page access cycles can be obtained from the page wait cycles +1 cycle (Two cycles in Figure 4.6-1 ).

• Setting of the BST bits of the ACR register enables the burst length to be set as 1, 2, 4, or 8.If the burst length is set to "1", single access mode is set and only the first cycle is repeated.However, if the data bus width is set to 32 bits (the BST bits of the ACR register are 10B). setthe burst length to 4 or less (A malfunction occurs if the burst length is set to 8).

• If burst access is enabled, burst access is used when prefetch access or transfer with alarger size than the specified data bus width is performed. For example, if word access to anarea whose data bus width is set to 8 bits and burst length to 4 is performed, access of 4bursts is performed once instead of repeating byte access four times.

• Since RDY input is ignored in areas for which burst access is set, do not setTYP[3:0]=0xx1B.

• The LBA and BAA signals are designed for burst FLASH memory. LBA indicates the start ofaccess and BAA indicates the address increment.

• A[31:0] is updated after the wait cycles that were set during burst access.

193



This section explains the following three cases of operation of the address/data multiplex interface:• Without external wait• With external wait• CSX -> RD/WR setup

Without External Wait

Figure 4.7-1 shows the operation timing chart for (TYP[3:0]=0100B, AWR=0008H).

Figure 4.7-1 Timing Chart for the Address/Data Multiplex Interface (without External Wait)

• Making a setting such as TYP[3:0]=01xxB in the ACR register enables the address/datamultiplex interface to be set.

• If the address/data multiplex interface is set, set 8 bits or 16 bits for the data bus width(DBW1, DBW0 bits). The 32-bit bus width is not supported.

• In the address/data multiplex interface, the total of 3 cycles of 2 address output cycles + 1data cycle becomes the basic number of access cycles.

• In the address output cycles, AS is asserted as the output address latch signal.

• As with a normal interface, the address indicating the start of access is output to A[31:0]during the time division bus cycle. Use this address if you want to use an address more than8/16 bits in the address/data multiplex interface.

data[15:0]

MCLK

AS

CSnX

RD

A[31:0]

D[31:16]

D[31:16]

WRWRITE

READ

address[15:0]

address[15:0] data[15:0]

address[31:0]

194


• As with the normal interface, auto-wait (AWR:W15 to W12), read -> write idle cycle(AWR:W07, W06), write recovery (AWR:W05, W04), address -> CSX delay (AWR:W02),CSX -> RD/WR setup delay (AWR:W01), and RD/WR -> CSX hold delay (AWR:W00) can beset.

• In areas for which the address/data multiplex interface is set, set 1(DBW1,DBW0=00B) asthe burst length.

With External Wait

Figure 4.7-2 shows the operation timing chart for (TYP[3:0]=0101B, AWR=1008H).

Figure 4.7-2 Timing Chart for the Address/Data Multiplex Interface (with External Wait)

• Making a setting such as TYP[3:0]=01x1B in the ACR register enables RDY input in theaddress/data multiplex interface.

data[15:0]

External wait

Release

MCLK

AS

CSnX

RD

A[31:0]

D[31:16]

D[31:16]

WR

RDY

WRITE

READ

address[31:0]


address[15:0]

195


CSX -> RD/WR Setup

Figure 4.7-3 shows the operation timing chart for (TYP[3:0]=0101B, AWR=100BH).

Figure 4.7-3 Timing Chart for the Address/Data Multiplex Interface (CSX -> RD/WR Setup)

• Setting "1" for the CSX -> RD/WR setup delay (AWR:W01) enables the multiplex addressoutput cycle to be extended by one cycle as shown in Figure 4.7-3 , allowing the address tobe latched directly to the rising edge of AS. Use this setting if you want to use AS as an ALE(Address Latch Enable) strobe without using MCLK.

data[15:0]

MCLK

AS

CSnX

RD

A[31:0]

D[31:16]

D[31:16]

WRWRITE

READ

address[31:0]


address[15:0]

196



This section explains the prefetch operation.

Prefetch Operation

The external bus interface controller contains a prefetch buffer consisting of 16 X 8 bits.

If the PSUS bit of the TCR register is "0" and read access to an area to which the PFEN bit ofthe ACR register is set to "1" occurs, the subsequent address is prefetched and then stored inthe prefetch buffer.

If the stored address is accessed from the internal bus, the lookahead data in the prefetch bufferis returned without external access being performed. This can reduce the wait time forsuccessive accesses to the external bus areas.

Basic conditions for starting external access using prefetch

External bus access using prefetch occurs when the following conditions are met:

• The PSUS bit of the TCR register is "0".

• Neither sleep mode nor stop mode is set.

• Read access by the external bus to a chip select area for which prefetch is enabled hasbeen performed. DMA access and read access by a read modified write system instruction,however, are excluded.

• No external bus access request (external bus area access to an area for which prefetch isnot enabled or DMA transfer with an external bus area) other than the prefetch access hasoccurred.

• The part of the prefetch buffer for the next operation of capturing the prefetch access iscompletely empty.

While the above conditions are met, the prefetch access will continue. If external bus areaaccess to an area for which prefetch is not enabled occurs after prefetch access, prefetchaccess to the area for which prefetch is enabled will continue as long as the prefetch bufferclear conditions are not met.

For an access that mixes multiple prefetch-enabled areas and multiple prefetch-disabled areas,the prefetch buffer always holds data of the prefetch-enabled area accessed last. Since, in thiscase, access to prefetch-disabled areas does not affect the prefetch buffer state at all, data inthe prefetch buffer is not wasted even if prefetch-disabled data access and prefetch-enabledinstruction fetch are mixed.

Optional clear for temporary stopping of a prefetch access

Setting "1" for the PSUS bit of the TCR register temporarily stops a prefetch. The prefetch canbe restarted by setting the PSUS bit to "0". At this point, the contents of the buffer are retainedif no error occurs or a buffer clear such as occurs when the PCLR bit is set does not occur.

Setting "1" for the PCLR bit of the TCR register completely clears the prefetch buffer. Clear thebuffer by setting the PSUS bit when prefetch is interrupted.

Prefetch is temporarily stopped for the minimum unit (64 KB) of the boundary=chip select areawhere the high-order 16 bits of an address change. If the boundary is crossed, first a bufferread error occurs and then prefetch starts in a new area.

197


Unit for one prefetch access operation

The unit for one prefetch access operation is determined by the DBW bits (bus width) and BSTbits (burst length).

Prefetch access always occurs with the full size of the bus width specified by the DBW bits andaccess for the count of the burst length set by the BST bits in one access operation isperformed. That is, if any value other than 00B is set for the BST bits, the prefetch alwaysoccurs in page mode/burst mode. Keep in mind whether ROM/RAM is conformable and enoughaccess time is applicable. (Set an appropriate value bits W15 to W08 bits of the AWR register).

During burst access, successive accesses occur only within the address boundary that that isdetermined by the burst length. Thus, if the boundary is crossed, for example, 4 bytes of freespace are available in the buffer, these 4 bytes cannot be accessed in one operation (If theprefetch buffer starts at xxxxxx0EH, 4 bytes of free space are available in the buffer, and twobursts are set even though the bus width is 16 bits, only 2 bytes, xxxxxx0EH and xxxxxx0FH,can be captured in the next prefetch access).

The following provides two examples:

• Area whose bus width is set to 16 bits and whose burst length is set to 2

The amount of data read into the buffer in one prefetch operation is 4 bytes. In this case,prefetch access is delayed until 4 bytes of free space are available in the prefetch buffer.

• Area whose bus width is set to 8 bits and whose burst length is set to 8

The amount of data read into the buffer in one prefetch operation is 8 bytes. In this case,prefetch access is delayed until 8 bytes of free space are available in the prefetch buffer.

Burst length setting and prefetch efficiency

If requests for external bus access, other than prefetch access, to or errors in the prefetch bufferoccur during one operation of prefetch access as explained in the previous bullet, "Unit of oneprefetch access operation", these access requests must wait until access to the prefetch bufferthat is being executed is completed.

Thus, if the burst length is too long, the efficiency and reaction of bus access other than prefetchmay be degraded. If, on the other hand, the burst length is set to 1, many read cycles may bewasted even if burst/page access memory is connected because single access is alwaysperformed.

If settings are made so that the amount of data read in one prefetch access operation is large,prefetch access can be started only after free space in the prefetch buffer for this amount isavailable. Thus, access to the prefetch buffer is infrequent, and the external bus tends to beidle. For example, if the bus width is set to 16 bits and the burst length is set to 8, the amount ofdata read into the buffer in one prefetch operation is 16 bytes. Thus, a new prefetch access canbe started only after the prefetch buffer is completely empty.

Adjust the optimum burst length to suit use and the environment after taking the above intoconsideration. Generally, when connecting asynchronous memory to which burst/page accesscannot be applied, it is best to set the burst length to 1 (single access). Conversely, whenmemory whose burst/page access cycle is short is connected, it is better to set the burst lengthto any value other than 1 (single access). In this case, it is best to make the setting so that 8bytes (half of the buffer) are read in one read operation according to the bus width. However,the optimum condition varies with the frequency of external access and varies with thefrequency divide-by rate setting of the external access clock.

198


Reading from the prefetch buffer

Data stored in the prefetch buffer is read in response to access from the internal bus if anaddress matches, and no external access is performed. In reading from the buffer, addressescan be hit (up to 16 bits) if they are in the forward direction but not continuous, so that a secondread from the external bus is avoided, if possible, even for a short forward branch.

If the address currently being accessed for prefetch matches during access from the internalbus, a wait signal is returned internally before data is captured after prefetch access iscompleted. In this case, no buffer error occurs.

If an address in the prefetch buffer matches when a read is performed for DMA transfer, data inthe prefetch buffer is not used, and instead, external data is read by the external bus. In thiscase, a buffer error occurs. The prefetch is not continued and no prefetch access is performeduntil a new external access operation to a prefetch-enabled area occurs.

Clearing/updating the prefetch buffer

If either of the following conditions is met, the prefetch buffer is completely cleared:

• If "1" is written to the PCLR bit of the TCR register

• If a buffer read error occurs. A buffer read error is if any of the following events occurs:

• When no address is found in the buffer that matches in an to read from a prefetch-enabled area. In this case, the external bus is accessed again. Data read in this case isnot stored in the buffer, but the prefetch access is started from the subsequent address tostore addresses in the buffer.

• In an access to read from a prefetch-enabled area with a read modified systeminstruction. In this case, the external bus is accessed again. Data read in this case is notstored in the buffer. Also, no prefetch access is performed (This is because data iswritten to the next address).

• In an access to read from a prefetch-enabled area for DMA transfer. In this case, theexternal bus is accessed again. Data read in this case is not stored in the buffer. Also,no prefetch access is performed.

• If a buffer write hit occurs. A buffer write hit is as follows:

• When the address of just one byte that matches is found in the buffer in an access towrite to a prefetch-enabled area. In this case, the external bus is accessed again, but noprefetch access is performed before a new read access occurs.

Only part of the prefetch buffer is cleared when the following condition is met:

• If a buffer read hit occurs

In this case, only the part of the buffer before the hit address is cleared.

Restrictions on prefetch-enabled areas

If prefetch to a little endian area is enabled, be sure to access the area using word access. Ifdata read into the prefetch buffer is accessed with any length other than word length, the correctendian conversion is not performed and thus the wrong data will be read. This is due tohardware restrictions related to the endian conversion mechanism.

199



This section explains DMA access operation.

DMA Access Operation

This section explains the following five DMA operations:

• DMA fly-by transfer (I/O -> memory)

• DMA fly-by transfer (memory -> I/O)

• 2-cycle transfer (internal RAM -> I/O, RAM)

• 2-cycle transfer (external -> I/O)

• 2-cycle transfer (I/O -> external)

200


4.9.1 DMA Fly-By Transfer (I/O -> Memory)

This section explains DMA fly-by transfer (I/O -> memory).

DMA Fly-By Transfer (I/O -> Memory)

Figure 4.9-1 shows the operation timing chart for (TYP[3:0]=0000B, AWR=0008H, IOWR=41H).

Figure 4.9-1 shows when case when a wait is not set on the memory side.

Figure 4.9-1 Timing Chart for DMA Fly-By Transfer (I/O -> Memory)

• Setting "1" for the W01 bit of the AWR register enables the CSX -> RD/WR setup delay to beset. Set this bit to extend the period between assertion of chip select and the read/writestrobe.

• Setting "1" for the W00 bit of the AWR register enables the RD/WR -> CSX hold delay to beset. Set this bit to extend the period between negation of the read/write strobe and negationof chip select.

DACKnX

EOPnX

DACKnX

EOPnX

IORD

DREQn

FR30 compatible mode

Basic mode

MCLK

AS

CSnX

A[31:0]

D[31:0]

WRnX

Sense timing in demand mode

I/O wait I/O holdBasic cycle cycle *1 wait *2

memory address

201


• The CSX -> RD/WR setup delay (W01 bit) and RD/WR -> CSX hold delay (W00 bit) can beset independently.

• When successive accesses are made within the same chip select area without negating thechip select, neither CSX -> RD/WR setup delay nor RD/WR -> CSX hold delay is inserted.

• If a setup cycle for determining the address or a hold cycle for determining the address isneeded, set "1" for the address -> CSX delay setting (W02 bit of the AWR register).

Reference:

For I/O on the data output side, a read strobe of three bus cycles extended by the I/O waitcycle and I/O hold wait cycle is generated. For memory on the receiving side, a write strobeof two bus cycles extended by the I/O wait cycle is generated. The I/O hold wait cycle doesnot affect the write strobe. However, the address and CS signal are retained until the fly-bybus access cycles end.

202


4.9.2 DMA Fly-By Transfer (Memory -> I/O)

This section explains DMA fly-by transfer (memory -> I/O).

DMA Fly-By Transfer (Memory -> I/O)


Figure 4.9-2 shows a case in which a wait is not set on the memory side.

Figure 4.9-2 DMA Fly-By Transfer (Memory -> I/O)

• Setting "1" for the HLD bit of the IOWR0 to IOWR2 registers extends the I/O read cycle byone cycle.

• Setting bits WR1,WR0 bits of the IOWR0 to IOWR2 registers enables 0-3 write recoverycycles to be inserted.

• If the write recovery cycle is set to "1" or more, a write recovery cycle is always inserted afterwrite access.

• Setting bits IW3 to IW0 of the IOWR0 to IOWR2 registers enables 0-15 wait cycles to be

DACKnX

EOPnX

DACKnX

EOPnX

IOWR

DREQn

MCLK

AS

CSnX

A[31:0]

D[31:0]

RD


Basic mode

Sense timing in demand mode

I/O wait I/O holdBasic cycle cycle *1 wait *2

memory address

203


inserted.

• If wait is also set on the memory side (AWR:W15 to W12 is not "0"), the larger value is usedas the wait cycle after comparison with the I/O wait (IW3 to IW0 bits).

Reference:

For memory on the data output side, a read strobe of three bus cycles extended by the I/Owait cycle and I/O hold wait cycle is generated. For I/O on the receiving side, a write strobeof two bus cycles extended by the I/O wait cycle is generated. The I/O hold wait cycle doesnot affect the write strobe. However, the address and CS signal are retained until the fly-bybus access cycles end.

204


4.9.3 2-Cycle Transfer (Internal RAM -> External I/O, RAM)

This section explains 2-cycle transfer (internal RAM -> external I/O, RAM) operation.The timing is the same as for external I/O, RAM -> internal RAM.

2-Cycle Transfer (Internal RAM -> External I/O, RAM)


Figure 4.9-3 shows a case in which a wait is not set on the I/O side.

Figure 4.9-3 Timing Chart for 2-cycle Transfer (Internal RAM -> External I/O, RAM)

• The bus is accessed in the same way as an interface when DMAC transfer is not performed.

• DACKnX/EOPnX is not output in the internal RAM access cycles.

DACKnX

EOPnX

DACKnX

EOPnX

DREQn Sense timing in demand mode

MCLK

AS

CSnX(I/O side)

A[31:0]

D[31:0]

WRnX


Basic mode

I/O address

205


4.9.4 2-Cycle Transfer (External -> I/O)

This section explains 2-cycle transfer (external -> I/O) operation.

2-Cycle Transfer (External -> I/O)


Figure 4.9-4 shows a case in which a wait is not set for memory and I/O.

Figure 4.9-4 Timing Chart for 2-Cycle Transfer (External -> I/O)

• The bus is accessed in the same way as an interface when the DMAC transfer is notperformed.

• In basic mode, DACKnX/EOPnX is output in both transfer source bus access and transferdestination bus access.

idle

DACKnX

EOPnX

DACKnX

EOPnX

DREQn

MCLK

AS

CSnX

CSnX

A[31:0]

D[31:0]

WRnX

RD


Basic mode

memory address I/O address

206


4.9.5 2-Cycle Transfer (I/O -> External)

This section explains 2-cycle transfer (I/O -> external) operation.

2-Cycle Transfer (I/O -> External)


Figure 4.9-5 shows a case in which a wait is not set for memory and I/O.

Figure 4.9-5 Timing Chart for 2-Cycle Transfer (I/O -> External)

• The bus is accessed in the same way as an interface when the DMAC transfer is notperformed.

• In basic mode, DACKnX/EOPnX is output both in the transfer source bus access andtransfer destination bus access.

idle

DACKnX

EOPnX

DACKnX

EOPnX

DREQn

MCLK

AS

CSnX

CSnX

A[31:0]

D[31:0]

WRnx

RD


Basic mode

I/O address memory address

207



This section shows timing charts for releasing the bus right and for acquiring the bus right.

Releasing the Bus Right

Figure 4.10-1 shows the timing chart for releasing the bus right.

Figure 4.10-1 Timing Chart for Releasing the Bus Right

MCLK

A23-A0

AS

CSnX *

D31-D16

Read

BRQ

BGRNT

1 cycle

RD

208


Acquiring the Bus Right

Figure 4.10-2 shows the timing chart for acquiring the bus right.

Figure 4.10-2 Timing Chart for Acquiring the Bus Right

• Setting "1" for the BREN bit of the TRC register enables bus arbitration by BRQ/BGRNT tobe performed.

• When the bus right is released, the pin is set to high impedance and then BGRNT isasserted one cycle later.

• When the bus right is acquired, BGRNT is negated and then each pin is activated one cyclelater.

• CSnX is set to high impedance only if the SREN bit in the ACR0 to ACR7 registers is set.

• If all areas enabled by the CSER register are shared (the SREN bit of the ACR register is"1"), AS, BAA, RD, WR, and WR0 to WR3 are set to high impedance.

MCLK

A23-A0

AS

CSnX *

D31-D16

BRQ

BGRNT

WR

1 cycle

209


4.11 Procedure for Setting a Register

This section explains the procedure for setting a register.

Procedure for Setting a Register

Using the following procedures to make external bus interface settings:

• Before rewriting the contents of a register, be sure to set the CSER register so that thecorresponding area is not used ("0"). If you change the settings while "1" is set, accessbefore and after the change cannot be guaranteed.

• Use the following procedure to change a register:

1. Set "0" for the CSER bit corresponding to the applicable area.

2. Set both ASR and ACR at the same time using word access.

3. Set AWR.

4. Set the CHER bit corresponding to the applicable area.

5. Set the CSER bit corresponding to the applicable area.

• The CS0 area is enabled after a reset is released. If the area is used as a program area,the register contents need to be rewritten while the CSER bit is "1". In this case, makethe settings described in 2) to 4) above in the initial state with a low-speed internal clock.Then, switch the clock to a high-speed clock.

• Use the following procedure to change the register value in an area for which prefetch:

1. Set "0" for the CSER bit corresponding to the applicable area.

2. Set "1" for both the PSUS bit and PCLR bit of the TCR register.

3. Set both ASR and ACR at the same time using word access.

4. Set AWR.

5. Set the CHER bit corresponding to the applicable area.

6. Set "0" for both the PSUS bit and PCLR bit of the TCR register.

7. Set "1" for the bit of CSER corresponding to the applicable area.

210



This section explains some notes when using the external bus interface.

Notes for Use

If settings are made so that the area (TYP[3:0]=0x0xB) where WR0 to WR3 are used as a writestrobe and the area (TYP[3:0]=0x1xB) where WR is used as a write strobe are mixed, be sure tomake the following setting in all areas that will be used:

• Set at least one read -> write idle cycle (other than AWR:W07, W06=00B).

• Set at least one write recovery cycle (other than AWR:W05, W04=00B).

However, if WR0 to WR3 are disabled (ROM only is connected) in the area (TYP[3:0]=0x0xB)where WR0 to WR3 are used as a write strobe, the above restriction does not apply. Also, theabove restriction does not apply if both the address -> RD/WR setup cycle (W01=1) and RD/WR-> address hold cycle (W00=1) are set in the area (TYP[3:0]=0x1xB) where WR is used as awrite strobe.

The reason for the restriction is explained below.

In the area where WR is used as a write strobe by setting TYP[3:0]=0x1xB, the WR0/WR1 pin isset to byte enable (UBX/LBX) output. In this case, the byte enable output pin outputs theenable signal of each byte location at the same timing as that of the address and CSX output.

Thus, if an area where the WR0/WR1 pin is used as an asynchronous write strobe is accessedjust before or after the current access, the AC standard between CSX and WR0/WR1 cannot besatisfied in the area, possibly causing data to be written incorrectly.

If the read -> write idle cycle and write recovery cycle are set, the above AC standard can besatisfied because CSX is not asserted ("H" level is maintained) in these cycles.

This restriction is not needed if there is allowance for the AC standard (setup and hold) betweenCSX and WR0/WR1 in the area where the WR0/WR1 pin is used as an asynchronous writestrobe.

211


212

CHAPTER 5 I/O PORT

This chapter describes the I/O ports and the configuration and functions of registers.

5.1 Overview of the I/O Port

5.2 I/O Port Registers

213

CHAPTER 5 I/O PORT


This section provides an overview of the I/O port.

Basic Block Diagram of the I/O Port

The pins of this LSI device can be used as I/O ports if settings are made so that thecorresponding pins are not used for the inputs and outputs of the peripheral circuits.

Figure 5.1-1 shows the basic configuration of the port.

Figure 5.1-1 Basic Block Diagram of the I/O Port

The I/O port consists of PDRs (Port Data Registers), DDRs (Data Direction Registers), andPFRs (Port Function Registers).

0

1

1

0

PDR: Port Data RegisterDDR: Data Drection RegisterPFR: Port Function Register

Pin

PDR

Peripheral output

Peripheral output

PFR

DDR

Port Bus

214


I/O Port Modes

The I/O port has the following four modes:

Port input mode (PFR=0 & DDR=0)

• PDR read: Reads the level of the corresponding external pin.

• PDR write: Writes a setting value to the PDR.

Port output mode (PFR= 0 & DDR=1)

• PDR read: Reads the value of the PDR.

• PDR write: Outputs the value of the PDR to the corresponding external pin.

Peripheral output mode (PFR=1 & DDR=1)



Peripheral input mode (PFR=1 & DDR=0)



Note:

Port-related registers must be accessed in units of bytes.

The value of DDR becomes valid when the value of PFR is changed to switch the pin to ageneral-purpose pin.

215

CHAPTER 5 I/O PORT


This section describes the configuration and functions of the I/O port registers.

Configuration of the Port Data Registers (PDR)

Figure 5.2-1 shows the configuration of the port data registers (PDRs).

Figure 5.2-1 Configuration of the Port Data Registers (PDR)

• PDR0 to PDR7 are the input/output data registers for the I/O port.

• Input/output is controlled by the corresponding DDR0 to DDR7 and PFR0 to PFR3.

PDR0 7 6 5 4 3 2 1 0 Initial value

Initial value

Initial value

Initial value

Initial value

Initial value

Initial value

Initial value

Address: 00000010H P07 P06 P05 P04 P03 P02 P01 P00 XXXXXXXXB

PDR1 7 6 5 4 3 2 1 0Address: 00000011H P17 P16 P15 P14 P13 P12 P11 P10 XXXXXXXXB

PDR2 7 6 5 4 3 2 1 0Address: 00000012H - - P25 P24 P23 P21 P21 P20 --XXXXXXB

PDR3 7 6 5 4 3 2 1 0Address: 00000013H - P36 P35 P34 P33 P32 P31 P30 -XXXXXXXB



PDR6 7 6 5 4 3 2 1 0Address: 00000016H - - P65 P64 P63 P62 P61 P60 --XXXXXXB

PDR7 7 6 5 4 3 2 1 0Address: 00000017H - - - P74 P73 P72 P71 P70 ---XXXXXB

AccessR/W

AccessR/W

AccessR/W

AccessR/W

AccessR/W

AccessR/W

AccessR/W

AccessR/W

bit

bit

bit

bit

bit

bit

bit

bit

216


Configuration of the Data Direction Registers (DDR)

Figure 5.2-2 shows the configuration of the data direction registers (DDRs).

Figure 5.2-2 Configuration of the Data Direction Registers (DDR)

DDR0 to DDR7 control the input/output direction of the corresponding I/O port at the bit level.

• If PFR=0

• DDR=0: Port input

• DDR=1: Port output

• If PFR=1

• DDR=0: Peripheral input

• DDR=1: Peripheral output

DDR0 7 6 5 4 3 2 1 0 Initial value AccessAddress: 00000400H P07 P06 P05 P04 P03 P02 P01 P00 00000000B R/W


DDR2 7 6 5 4 3 2 1 0 Initial value AccessAddress: 00000402H - - P25 P24 P23 P22 P21 P20 --000000B R/W

DDR3 7 6 5 4 3 2 1 0 Initial value AccessAddress: 00000403H - P36 P35 P34 P33 P32 P31 P30 -0000000B R/W



DDR6 7 6 5 4 3 2 1 0 Initial value AccessAddress: 00000406H - - P65 P64 P63 P62 P61 P60 --000000B R/W

DDR7 7 6 5 4 3 2 1 0 Initial value AccessAddress: 00000407H - - - P74 P73 P72 P71 P70 ---00000B R/W

bit

bit

bit

bit

bit

bit

bit

bit

217

CHAPTER 5 I/O PORT

Configuration of the Port Function Registers (PFR)

Figure 5.2-3 shows the configuration of the port function registers (PFRs).

Figure 5.2-3 Configuration of the Data Direction Registers (PFR)

When the registers are reset, port functions are used.

PFR0 to PFR3 control the output of the corresponding peripherals in units of functions.

A pin to be used as a peripheral input pin must be set for input by DDR.

Note:

Be sure to set bit7 (I2CTST bit) of PFR0 to "0".

If the I2CE3 and I2CE4 bits are both "1", bridges are set between the SCL3/SCK3 and SCL4/SCK4.

PFR1 7 6 5 4 3 2 1 0Address: 00000411H UART3 SCKE3 UART2 SCKE2 UART1 SCKE1 UART0 SCKE0 00000000B R/W

PFR2 7 6 5 4 3 2 1 0Address: 00000412H TOE2 TOE1 TOE0 - - - UART4 SCKE4 000---00B R/W

PFR3 7 6 5 4 3 2 1 0Address: 00000413H TME3 TME2 TME1 TME0 PPGE3 PPGE2 PPGE1 PPGE0 00000000B R/W

- -

Initial value Access

PFR0 7 6 5 4 3 2 1 0Address: 00000410H I2CTST I2CE4 I2CE0I2CE1I2CE2I2CE3 0--00000B R/W




bit

bit

bit

bit

218


Initial Values and Functions of the Port Function Registers (PFRs)

Table 5.2-1 lists the initial values and functions of the port function registers (PFRs).

Table 5.2-1 Initial Values and Functions of the Port Function Registers (PFRs)(1/2)

Register name Bit name Bit value Function

PFR0I2CTST

0 I2C test bit

1 Setting prohibited

I2CE40 General-purpose port

1 SCL4 or SDA4 port (connected to I2C channel 4)









PFR1UART3

0 General-purpose port

1 SO3 output

SCKE30 General-purpose port

1 SCK3 output

UART2 0 General-purpose port

1 SO2 output

SCKE2 0 General-purpose port

1 SCK2 output


1 SO1 output


1 SCK1 output


1 SO0 output


1 SCK0 output

219

CHAPTER 5 I/O PORT

PFR2 UART4 0 General-purpose port

1 SO4 output


1 SCK4 output

TOE2 0 General-purpose port

1 TO2 output


1 TO1 output


1 TO0 output

PFR3 TME3 0 General-purpose port

1 TMO3 output

TME2 0 General-purpose port

1 TMO2 output


1 TMO1 output


1 TMO0 output

PPGE3 0 General-purpose port

1 PPG3 output


1 PPG2 output


1 PPG1 output


1 PPG0 output

Table 5.2-1 Initial Values and Functions of the Port Function Registers (PFRs)(2/2)

Register name Bit name Bit value Function

220

CHAPTER 6 U-TIMER

This chapter describes the U-TIMER, the configuration and functions of registers, and U-TIMER operation.

6.1 Overview

6.2 U-TIMER Registers

6.3 U-TIMER Operation

221

CHAPTER 6 U-TIMER

6.1 Overview

This section provides an overview and a block diagram of the U-TIMER (16 bit timer for UART baud rate generation).

Overview of the U-TIMER

The U-TIMER is a 16-bit timer used to generate the baud rate for the UART. Use a combinationof a chip operating frequency and a reload value of the U-TIMER to specify a baud rate.

The MB91310 has five built-in channels for this timer.

Block Diagram

Figure 6.1-1 shows the block diagram of the U-TIMER.

Figure 6.1-1 Block Diagram of the U-TIMER

0

0

bit 15

bit 15

UTIMR (reload register)

load

UTIM (timer)

clockunderflow

control

to UARTf.f.

(Peripheral Clock)

222



This section describes the configuration and functions of the registers used by the U-TIMER.

U-TIMER Registers

Figure 6.2-1 shows the registers used by the U-TIMER.

Figure 6.2-1 U-TIMER Registers

U-TIMER (UTIM)

Figure 6.2-2 shows the bit configuration of the U-TIMER (UTIM).

Figure 6.2-2 Bit Configuration of the U-TIMER (UTIM)

UTIM is a register that indicates the timer value. Use a 16-bit transfer instruction to access thisregister.

Reload Register (UTIMR)

Figure 6.2-3 shows the bit configuration of the reload register (UTIMR).

Figure 6.2-3 Bit Configuration of the Reload Register (UTIMR)

UTIMR is a register that stores the value to be reloaded into UTIM if UTIM underflows.

Be sure to use a 16-bit transfer instruction to access this register.

bit 15 8 7 0UTIM (R)

UTIMR (W)UTIMC (R/W)

15 14 12 0

ch.0ch.1ch.2

Address: 000064H b15 b14 b2 b1 b0Address: 00006CH

Address: 000074H

ch.3 Address: 00007CH

ch.4 Address: 000084H

R Access 0 Initial value

UTIM

R 0

bit

bit 15 14 12 0

ch.0ch.1ch.2

Address: 000064H b15 b14 b2 b1 b0Address: 00006CH

Address: 000074H

ch.3ch.4

Address: 00007CH

Address: 000084H

W Access 0 Initial value

UTIMR

W 0

223

CHAPTER 6 U-TIMER

U-TIMER Control Register (UTIMC)

Figure 6.2-4 shows the bit configuration of the U-TIMER control register (UTIMC).

Figure 6.2-4 Bit Configuration of the U-TIMER Control Register (UTIMC)

UTIMC controls the operation of the U-TIMER.

Be sure to use a byte transfer instruction to access this register.

[bit7] UCC1 (U-timer Count Control 1)

This bit controls the U-TIMER counting method.

The U-TIMER can set a normal cycle, 2(n+1) as well as an odd-numbered division for theUART.

Set UCC1 to "1" to generate a cycle of 2n+3.

Examples:

1. UTIMR=5, UCC1=0 --> Generation cycle =2n+2= 12 cycles

2. UTIMR=25, UCC1=1 --> Generation cycle =2n+3= 53 cycles

3. UTIMR=60, UCC1=0 --> Generation cycle =2n+2=122 cycles

Set UCC1 to "0" to use the U-TIMER as the interval timer.

[bit6, bit5] (reserved)


[bit4] UTIE (U-TIMER Interrupt Enable)

This bit is the interrupt enable bit for a U-TIMER underflow.

0: Interrupt disabled [initial value]

1: Interrupt enabled

Note:

Always write "0" to this bit because the MB91310 has no U-Timer interrupt.

[bit3] UNDR (UNDeR flow flag)

This bit is a flag indicating that an underflow has occurred. The UNDR bit is cleared at resetand when "0" is written to it. For a read by a read modify write instruction, "1" is always read.

Writing "1" to the UNDR has no effect.

bit 7 6 5 4 3 2 1 0 UCC1 UNDR CLKS UTST UTCR

R/W R/W R/W R/W R/W R/W 0 0 0 0 0 1

UTIEch.0ch.1ch.2

Address: 000067H

Address: 00006FH

Address: 000077Hch.3ch.4

Address: 00007FH

Address: 000087H

AccessInitial value

UTIMC

UCC1 Operation

0 Normal operation α=2n+2 [initial value]

1 +1 mode α=2n+3

n is the setting value of UTIMR.α is the cycle of the output clock for UART.

224


[bit2] CLKS (clock select)

In the MB91310, always write "0" to this bit.

[bit1] UTST (U-TIMER STart)

This bit is the U-TIMER operation enable bit.

0: Stopped. Writing "0" during operation stops running of the U-TIMER. [initial value]

1: Writing "1" during operation does not stop the U-TIMER.

[bit0] UTCR (U-TIMER CleaR)

Writing "0" to UTCR clears the U-TIMER to "0000H" (also clears the f.f. to "0").

The read value is always "1".

Notes:

• In the stop state, assert the start bit UTST (started) to automatically reload data.

• In the stop state, assert both the clear bit UTCR and the start bit UTST at the same time toclear the counter to 0 and generate an underflow in the count-down immediately after thecounter is cleared.

• During operation, the clear bit UTCR is asserted to clear the counter to 0. As a result, ashort, whisker-like pulse may be output in the output waveform, possibly causing the UARTto malfunction. While the output clock is being used, do not clear it using the clear bit.

• In the timer stop state, assert both bit1 (U-TIMER start bit: UTST) and bit0 (U-TIMER clearbit: UTCR) of the U-TIMER control register at the same time to set bit3 (underflow flag:UNDR) of this register when the counter is loaded after it has been cleared. At this timing,the internal baud rate clock is set to level.

• If the device attempts to set and clear the underflow flag at the same time, the flag is setand the clear operation becomes ineffective.

• Always write "0" to bit4 (UTIE) and bit0 (CLKS) of the U-TIMER control register (UTIMC).

• If the device attempts to write to and reload the data into the U-TIMER reload register atthe same time, old data is loaded into the counter. New data is loaded into the counter onlyin the next reload timing.

• If the device attempts to clear and load T-TIMER at the same time, the timer clearoperation takes precedence.

225

CHAPTER 6 U-TIMER

6.3 U-TIMER Operation

This section describes calculation of a baud rate for the U-TIMER.

Calculation of Baud Rate

The UART uses the underflow flip-flop (f.f. in the block diagram shown in Figure 6.1-1 of thecorresponding U-TIMER (from U-TIMER0 to UART0, from U-TIMER1 to UART1, from U-TIMER2 to UART2, from U-TIMER3 to UART3, or from U-TIMER4 to UART4) as the clocksource for baud rates.

Asynchronous (start-stop synchronization) mode

The UART uses the U-TIMER output divided by 16.

CLK synchronous mode

bps = (2n+2) 16

UCC1=0(Varies depending on the gear)

bps = (2n+3) 16

UCC1=1

Maximum bps Peripheral machine clock (CLKP): 20.275 MHz, 633,438 bps

bps = (2n+2)

UCC1=0(Varies depending on the gear)

bps = (2n+3)

Maximum bps Peripheral machine clock (CLKP): 20.27 MHz, 10,135,000 bps

UCC1=1

226


This chapter describes the 16-bit reload timer, the configuration and functions of registers, and 16-bit reload timer operation.

7.1 Overview of the 16-bit Reload Timer

7.2 16-bit Reload Timer Registers

7.3 16-bit Reload Timer Operation

227


7.1 Overview of the 16-bit Reload Timer

The 16-bit reload timer consists of a 16-bit down counter, a 16-bit reload register, a prescaler for internal count clock generation, and a control register.

Overview of the 16-bit Reload Timer

The MB91310 has three built-in channels for the 16-bit reload timer.

The count clock source can be selected from three internal clocks (peripheral machine clockdivided by 2, 8, and 32) and external events.

DMA transfers resulting from interrupts can be activated.

Block Diagram

Figure 7.1-1 is a block diagram of the 16-bit reload timer.

Figure 7.1-1 Block Diagram of the 16-bit Reload Timer

CSL1

CSL0

OUT CTL.

RELD

INTE

UF

CNTE

TRG

IRQ

External timer output (TO0 toTO2)

7

2

16

16

Peripheral machine clock input

IN CTL.

EXCK

2 1 2 3 2 5

TOE0 to TOE2 Bits in PFR2

R-

BU

S

16-bit down counter (TMR) UF

16-bit reload register (TMRLR)

Reload

Clock selector

Count enable

Re-trigger

MOD1

MOD0

MOD2

3

Externaltrigger

selectionExternal trriger input(TI)

228



This section describes the configuration and functions of the registers used by the 16-bit reload timer.

Registers

Figure 7.2-1 shows the registers of the 16-bit reload timer.

Figure 7.2-1 16-bit Reload Timer Registers

bit 15 14 13 12 11 10 9 8

Control status register

15 0 16-bit timer register

7 6 5 4 3 2 1 0

(TMR)

15 0 16-bit reload register(TMRLR)

CSL1 CSL0

RELD INTE UF CNTE TRG

(TMCSR)

MOD2 MOD1

MOD0

bit

bit

bit

229


7.2.1 Control Status Register (TMCSR)

The control status register (TMCSR) controls the operating modes and interrupts of the 16-bit timer.

Bit Configuration of the Control Status Register (TMCSR)

Figure 7.2-2 shows the bit configuration of the control status register (TMCSR)

Figure 7.2-2 Bit Configuration of the Control Status Register (TMCSR)

This register controls the 16-bit timer operation modes and interrupts.

Rewrite bits other than UF, CNTE, and TRG only when CNTE = 0.

Concurrent write to this register is allowed.

Be sure to write "0" when write to bit13, bit12, and bit5.

[bit13] (Reserved)

Be sure to write "0" at writing.

[bit12] (Reserved)

Be sure to write "0" at writing.

[bit11, bit10] CSL1, CSL0 (Count source Select)

These bits are the count source select bits. Count sources can be selected from internalclocks and external events. Table 7.2-1 shows the count sources that can be selected.

The count effective edges are set using the MOD1 and MOD0 bits when external events arespecified for count sources.

15 14 13 12 11 10 9 8

CSL1 CSL0

(R/W) (R/W) R/W R/W R/W R/W --XX0000 00000000

7 6 5 4 3 2 1 0

RELD INTE UF CNTE TRG

R/W R R/W R/W R/W R/W R/W R/W

ch.0 00004Ech.1 000056ch.2 00005E

H

H

H

B

Initial value

MOD1MOD2

MOD0

TMCSR

Address:

bit

bit

230


The minimum pulse width which is required the external clock is 2•T (T: peripheral machineclock).

[bit9 to bit7] MOD2, MOD1, MOD0 (MODe)

These bits are select the operation mode. The function is changed when the count sourcesare "internal clock" and "external clock".

When internal clock:reload trigger setting

When external clock:count effective edge setting

Be sure to set MOD2 bit to "0".

[Reload trigger setting at internal clock selection]

When the internal clock (CSL1, CSL0 = 00, 01, 10) selects as the count source, theeffective edge is inputted by setting of MOD2 to MOD0 bit is loaded the content of reloadregisters, and continued the count operation. The setting of MOD2 to MOD0 at theinternal clock selection is shown in Table 7.2-2 .

Note: X indicates an arbitration value.

[Effective edge setting at external event selection]

When the external clock event (CSL1, CSL0 = 11) selects ad the count source, theeffective edge is inputted by setting of MOD2 to MOD0 and the event is counted. Thesetting of MOD2 to MOD0 at the external event selection is shown in Table 7.2-3 .

Note: X indicates an arbitration value.The reload at the external event generates in the underflow and the softwaretrigger.

Table 7.2-1 Count Sources Set Using the CSL Bits

CSL1 CSL0 Count source (φ: Machine clock)

0 0 Internal clock φ/21 (channel 0 to channel 2)



1 1 External event (channel 0 to channel 2)

Table 7.2-2 Setting of MOD2 to MOD0

MOD2 MOD1 MOD0 Effective edge

0 0 0 Software trigger

0 0 1 External trigger (rising edge)

0 1 0 External trigger (falling edge)

0 1 1 External trigger (both edge)

1 X X Setting prohibited

Table 7.2-3 Setting of MOD2 to MOD0

MOD2 MOD1 MOD0 Effective edge

X 0 0 -

X 0 1 External event (rising edge)

X 1 0 External event (falling edge)

X 1 1 External event (both edge)

231


[bit6] (Reserved)

This bit is unused. The read value is always "0".

[bit5] (Reserved)

Be sure to write "0", at writing.

[bit4] RELD

This bit is the reload enable bit. If it is set to "1", reload mode is entered. As soon as thecounter value underflows from 0000H to FFFFH, the contents of the reload register areloaded into the counter and the count operation is continued.

If this bit is set to "0", one-shot mode is entered and the count operation is stopped when thecounter underflows from 0000H to FFFFH.

[bit3] INTE

This bit is the interrupt request enable bit. If the INTE bit is set to "1", an interrupt request isgenerated when the UF bit is set to "1". If it is set to "0", no interrupt request is generated.

[bit2] UF

This bit is the timer interrupt request flag. This bit is set to "1" when the counter valueunderflows from 0000H to FFFFH. Write "0" to this bit to clear it.

Writing "1" to this bit is meaningless. When this bit is read by a read modify write instruction,"1" is always read.

[bit1] CNTE

This bit is the count enable bit of the timer. Write "1" to this bit to enter the start trigger waitstate. Write "0" to this bit to stop the count operation.

[bit0] TRG

This bit is the software trigger bit. Write "1" to this bit to generate a software trigger, load thecontents of the reload register into the counter, and start the count operation.

Writing "0" to this bit is meaningless. The read value is always "0".

The trigger input to this register is valid only if CNTE=1. No operation occurs if CNTE=0.

232


7.2.2 16-bit Timer Register (TMR)

The 16-bit timer register (TMR) is a register to which the count value of the 16-bit timer can be read. The initial value is undefined.Be sure to read this register using a 16-bit data transfer instruction.

Bit Configuration of the 16-bit Timer Register (TMR)

Figure 7.2-3 shows the bit configuration of the 16-bit timer register (TMR).

Figure 7.2-3 Bit Configuration of the 16-bit Timer Register (TMR)

bit15 0TMR

R R R R R R R R

Address: ch.0 00004AH Initial value

xxxxH

ch.1 000052H

ch.2 00005AH

233


7.2.3 16-bit Reload Register (TMRLR)

The 16-bit reload register (TMRLR) holds the initial value of a counter. The initial value is undefined.Be sure to write this register using a 16-bit data transfer instruction.

Bit Configuration of the 16-bit Reload Register (TMRLR)

Figure 7.2-4 shows the bit configuration of the 16-bit reload register (TMRLR).

Figure 7.2-4 Bit Configuration of the 16-bit Reload Register (TMRLR)

bit15 0

TMRLR

W W W W W W W W

Address: ch.0 000048H

Initial value

xxxxHch.1 000050H

ch.2 000058H

234



This section describes the following operations of the 16-bit reload timer:• Internal clock operation• Underflow operation

Internal Clock Operation

If the timer operates with a divide-by clock of the internal clock, one of the clocks generated bydividing the peripheral machine clock by 2, 8, or 32 can be selected as the count source.

To start the count operation as soon as counting is enabled, write "1" to the CNTE and TRG bitsof the control status register. Trigger input occurring due to the TRG bit is always validregardless of the operating mode while the timer is running (CNTE=1).

Figure 7.3-1 shows the startup and operations of the counter.

After the counter start trigger is input, Time T (T: peripheral machine clock cycle) is requireduntil the data of the reload register is loaded into the counter.

Figure 7.3-1 Startup and Operations of the Counter

Count clock

Counter Reload data -1 -1 -1

Data load

CNTE (register)

TRG (register)

T

235


Underflow Operation

An underflow is an event in which the counter value changes from 0000H to FFFFH. Thus, anunderflow occurs at the count of [Reload register setting value + 1].

If the RELD bit of the control register is set to "1" when an underflow occurs, the contents of thereload register are loaded into the counter and the count operation is continued. If the RELD bitis set to "0", the counter stops at FFFFH.

An underflow sets the UF bit of the control status register and, if the INTE bit is set to "1",generates an interrupt request.

Figure 7.3-2 shows the timing chart of the underflow operation.

Figure 7.3-2 Timing Chart of the Underflow Operation

Operating States of the Counter

The CNTE bit of the control register and the internal signal WAIT determine the counter status.The states that can be set include the stop state, when CNTE=0 and WAIT=1 (STOP state); thestartup trigger wait state, when CNTE=1 and WAIT=1 (WAIT status); and the operation state,when CNTE=1 and WAIT=0 (RUN state).

Figure 7.3-3 shows the state transitions.

Reload data0000H -1 -1-1

Count clock

Counter

Data load

Underflow set

0000H FFFFH

Count clock

Counter

Underflow set

[RELD=1]

[RELD=0]

236


Figure 7.3-3 Status Transitions of Counter

Notes

• The internal prescaler is enabled if a trigger is applied when bit1 (timer enable: CNTE) of thecontrol status register is set to "1".

• If the device attempts to set and clear the interrupt request flag at the same time, the flag isset and the clear operation becomes ineffective.

• If the device attempts to write to the 16-bit reload timer register and reload the data into the16-bit reload timer register at the same time, old data is loaded into the counter. New data isloaded into the counter at the next reload timing.

• If the device attempts to load and count the 16-bit timer register at the same time, the load(reload) operation takes precedence.

State transition due to hardware

State transition due to register access

CNTE=1, WAIT=0

Counter: Running

Load completed

RELD UF TRG=1 TRG=1

CNTE=1, WAIT=0 Loads contents of reload register into counter.

RELD UF Counter: Holds the value when it stops; undefined just after reset and until data is loaded

CNTE=1, WAIT=1

CNTE=1 TRG=0

CNTE=1 TRG=1

Counter: Holds the value when it stops; undefined just after reset

CNTE=0, WAIT=1 Reset

RUN

LOAD

WAIT

STOP

237


238


This chapter gives an outline of the PPG (Programmable Pulse Generator) timer and explains the register configuration and functions and the timer operations.

8.1 Outline

8.2 Block Diagram of the PPG Timer

8.3 Registers of the PPG Timer

8.4 PWM Mode

8.5 One-shot Mode

8.6 Interrupts

8.7 PPG Output of ALL-L and ALL-H

8.8 Precautions on Using the PPG Timer

239


8.1 Outline

The PPG timer can efficiently output highly accurate PWM waveforms.The MB91310 has four channels of the PPG timer.

Outline

• Each channel consists of a 16-bit down counter, 16-bit data register with a cycle settingbuffer, 16-bit compare register with a duty setting buffer, and pin control block.

• One of the four count clocks can be selected for the 16-bit down counter:

• Internal clocks: φ, φ/4, φ/16, and φ/64

• A reset or counter borrow can initialize the counter value to "FFFFH".

• Each channel has PPG output (PPG0 to PPG3).

• Registers

• Cycle setting register: Data register for reload with bufferData is transferred from the buffer when an activation trigger signal is detected and acounter borrow occurs.The PPG output is inverted when a counter borrow occurs.

• Duty setting register: Compare register with bufferPPG output is inverted when the value of this register and the counter value match.

• Pin control

• Set to "1" when the duty matches (priority)

• Reset to "0" when a counter borrow occurs.

• Output-value fixed mode is available to facilitate output of all-L (or H).

• The polarity can be specified.

• An interrupt request can be generated as one of the following combinations:

• Activation of PPG timer (software trigger or trigger input)

• Generation of counter borrow (cycle match)

• Generation of duty match

• Generation of counter borrow (cycle match) or duty match

• Multiple channels can be activated at one time by using software or other interval timers.

Restart during operation can also be set.

240



Figure 8.2-1 shows an overall block diagram of the PPG timer. Figure 8.2-2 shows the block diagram for one channel of the PPG timer.

Overall Block Diagram of PPG Timer

Figure 8.2-1 Overall Block Diagram of PPG Timer

PPG0

TRG inputPPG timer ch.3




PPG1

PPG2

PPG3

External TRG1

External TRG0

External TRG3

External TRG2

241


Block Diagram for One Channel of PPG Timer

Figure 8.2-2 Block Diagram for One Channel of PPG Timer

cmp

Peripheral clock

Prescaler

PCRS

IRQ

PPG output

Enable

Software trigger

TRG input Edge detection

Reverse bit

PPG mask

S Q R

1/1

1/4

1/16

1/64

CK Load 16-bitdown counter

Start Borrow

PDUT

Mountingselect

242



This section explains the registers of the PPG timer.

Registers of the PPG Timer

Figure 8.3-1 shows the registers of the PPG timer.

Figure 8.3-1 Registers of the PPG Timer

Address Access bit 15 0

00000120 H PTMR0 R ch.0 Timer regiser

00000122 H PCSR0 W ch.0 Cycle Setting Register

00000124 H PDUT0 W ch.0 Duty Setting Register

00000126 H PCNH0 PCNL0 R/W ch.0 Control/Status Register

00000128 H PTMR1 R ch.1 Timer register

0000012A H PCSR1 W ch.1 Cycle Setting Register

0000012C H PDUT1 W ch.1 Duty Setting Register

0000012E H PCNH1 PCNL1 R/W ch.1 Control/Status Register

00000130 H PTMR2 R ch.2 Time register

00000132 H PCSR2 W ch.2 Cycle Setting Register

00000134 H PDUT2 W ch.2 Duty Setting Register

00000136 H PCNH2 PCNL2 R/W ch.2 Control/Status Register

00000138 H PTMR3 R ch.3 Timer register

0000013A H PCSR3 W ch.3 Cycle Setting Register

0000013C H PDUT3 W ch.3 Duty Setting Register

0000013E H PCNH3 PCNL3 R/W ch.3 Control/Status Register

243


8.3.1 Control Status Register (PCNH, PCNL)

The control status registers (PCNH and PCNL) are used to control and display the status of the PPG timer.

Register Configurations of Control Status Registers (PCNH and PCNL)

Figure 8.3-2 shows the register configuration of the control status registers (PCNH and PCNL).

Figure 8.3-2 Register Configurations of PCNH and PCNL

[bit15] CNTE (Timer Enable)

This bit enables operation of the 16-bit down counter.

[bit14] STGR (Software Trigger)

Writing "1" into this bit applies software trigger.

The read value is always "0".

[bit13] MDSE (Mode Select)

This bit is used to select either the PWM mode in which continuous pulses are output or theone-shot mode in which a single pulse is output.

PCNH bit 15 14 13 12 11 10 9 8 ch.0 000126

ch.1 00012Ech.2 000136ch.3 00013E

CNTE STGR MDSE RTRG CKS1 CKS0 PGMS R/W R/W R/W R/W R/W R/W R/W

0 0 0 0 0 0 0

PCNL bit 7 6 5 4 3 2 1 0 ch.0 000127

ch.1 00012Fch.2 000137ch.3 00013F

Address

Address

R/W R/W R/W R/W R/W R/W R/W

0 0 0 0 0 0 0

H

H

H

H

H

H

H

H

EGS1 EGS0 IREN IRQF IRS1 IRS0 OSEL

AttributeInitial valueRewrite during operation

AttributeInitial valueRewrite during operation

-

-

-

-

--

-

0 Disabled (initial value)

1 Enabled

0 PWM mode (initial value)

1 One-shot mode

244


[bit12] RTRG (Retrigger Select)

This bit enables a restart resulting from a software trigger or trigger input.

[bit11, bit10] CKS1 and CKS0 (Counter Clock Select)

These bits are used to select the count clock of the 16-bit down counter.

[bit9] PGMS (PPG Output Mask Select)

Writing "1" into this bit allows PPG output to be masked to "0" or "1", regardless of mode,cycle, and duty settings.

For all-H output in ordinary polarity mode and all-L output in reverse polarity mode, specifythe same value in the cycle setting register and duty setting register in order to output theabove mask value with the polarity reversed.

[bit8] (reserved)


[bit7, bit6] EGS1 and EGS0 (Trigger Input Edge Select Bit)

These bits are used to select an effective edge for the activation cause selected in generalcontrol register 1.

Regardless of the mode that is selected, writing "1" to the bit of a software trigger enablesthe software trigger.

0 Restart disabled (initial value)

1 Restart enabled

CKS1 CKS0 Cycle

0 0 φ (initial value)

0 1 φ/4

1 0 φ/16

1 1 φ/64

φ: Peripheral machine clock

Table 8.3-1 PPG output when write "1" to PGMS

Polarity PPG output

Ordinary polarity L output

Reverse polarity H output

EGS1 EGS0 Edge selection

0 0 Not effective (initial value)

0 1 Rising edge

1 0 Falling edge

1 1 Both edges

245

Changed the table in "Bits11 and 10 : CKS1 and CKS0 (Counter Clock Select)". (φ/2 (initial value) → φ (initial value))


[bit5] IREN (PPG Interrupt Request Enable)

This bit enables an interrupt request.

[bit4] IRQF (PPG Interrupt Request Flag)

If bit5, IREN, is enabled and an interrupt source selected in bits 3 and 2, the IRS1 and IRS0,occurs then this bit is set and an interrupt request is generated and issued to the CPU.

This bit is cleared if "0" is written to it.

This bit remains unchanged if "1" is written to it.

The read value by a read-modify-write instruction is always "1", regardless of the bit value.

[bit3, bit2]: IRS1, IRS0 (Interrupt Resource Select)

These bits are used to select a source that sets bit4, the IRQF.

[bit1] (reserved)

This bit is unused.

[bit0] OSEL: PPG Output Polarity Specification Bit

This bit sets the polarity of the PPG output.

Table 8.3-2 and Table 8.3-3 show the combination results for this bit and bit9 (PGMS).

0 Disabled (initial value)

1 Enabled

IRS1 IRS0 Interrupt resource

0 0 Software trigger or trigger input (initial value)

0 1 Occurrence of a counter borrow (cycle match)

1 0 Occurrence of a duty match

1 1 Occurrence of a counter borrow (cycle match) or duty match

Table 8.3-2 Combination of PPG Output Polarity Specifications

PGMS OSEL PPG output

0 0 Ordinary polarity (initial value)

0 1 Reverse polarity

1 0 Output fixed to L

1 1 Output fixed to H

246


Table 8.3-3 PPG Output Polarity Specification

Polarity After reset Duty match Counter borrow

Ordinary polarity "L" output Rising edge Falling edge

Reverse polarity "H" output Falling edge Rising edge

247


8.3.2 PPG Cycle Setting Register (PCSR)

The PPG cycle setting register (PCSR) is a register with a buffer for setting a cycle.Transfers from the buffer are performed with counter borrow.

Bit Configuration of PPG Cycle Setting Register (PCSR)

Figure 8.3-3 shows the bit configuration of the PPG cycle setting register (PCSR).

Figure 8.3-3 Bit Configuration of PPG Cycle Setting Register (PCSR)

When initializing or rewriting the cycle setting register, be sure to write to the duty settingregister after the writing of the cycle setting register.

This register must be accessed using 16-bit data.

PCSR bit 15 14 13 12 11 10 9 8 Address: ch.0 000122H

ch.1 00012AH

ch.2 000132H

ch.3 00013AH

7 6 5 4 3 2 1 0

Attribute Initial value

Write onlyUndefined

248


8.3.3 PPG Duty Setting Register (PDUT)

The PPG duty setting register (PDUT) is a register with buffer for setting a duty.Transfers from the buffer are performed with counter borrow.

Bit Configuration of PPG Duty Setting Register (PDUT)

Figure 8.3-4 shows the bit configuration of the PPG duty setting register (PDUT).

Figure 8.3-4 Bit Configuration of PPG Duty Setting Register (PDUT)

When the same value is set in the cycle setting register and the duty setting register, all-H isoutput in ordinary polarity mode and all-L is output in reverse polarity mode.

Do not specify a smaller value in PCSR than that in PDUT. Otherwise, PPG output becomesundefined.


PDUT bit 15 14 13 12 11 10 9 8 Address: ch.0 000124H

ch.1 00012CH

ch.2 000134H

ch.3 00013CH

7 6 5 4 3 2 1 0


Write onlyUndefined

249


8.3.4 PPG Timer Register (PTMR)

The PPG timer register (PTMR) is a register used to read the value of the 16-bit down counter.

Bit Configuration of PPG Timer Register (PTMR)

Figure 8.3-5 shows the bit configuration of the PPG timer register (PTMR).

Figure 8.3-5 Bit Configuration of PPG Timer Register (PTMR)


PDMR bit 15 14 13 12 11 10 9 8 Address: ch.0 000120H

ch.1 000128H

ch.2 000130H

ch.3 000138H

7 6 5 4 3 2 1 0


Read onlyFFFFH

250

8.4 PWM Mode

8.4 PWM Mode

In PWM mode, pulses are continuously output after an activation trigger is detected.

PWM Mode

In PWM mode, the PPG timer can output pulses continuously after an activation trigger signal isdetected.

The output pulse cycle can be controlled with the PCSR value, and the duty ratio can becontrolled with the PDUT value.

Note:

After data is written to PSCR, be sure to write data to PDUT.

PWM Mode Timing Chart

Figure 8.4-1 shows the PWM mode timing chart when trigger reactivation is disabled, andFigure 8.4-2 shows the PWM mode timing chart when trigger reactivation is enabled.

When reactivation is disabled

Figure 8.4-1 PWM Mode Timing Chart (Trigger Reactivation Disabled)

Rising edge detection Trigger ignored

Trigger

m

n

0

PPG (1)

(2)

(1) = T (n+1) ms(2) = T (m+1) ms

T: Count clock cyclem : PCSR valuen : PDUT value

251


When reactivation is enabled

Figure 8.4-2 PWM Mode Timing Chart (Retrigger enabled)

m

n

0

PPG

Rising edge detection Trigger restarted

Trigger

(1)

(2)

252

8.5 One-shot Mode

8.5 One-shot Mode

In one-shot mode, a single pulse of an arbitrary width is output by a trigger.

One-shot Mode

In one-shot mode, the PPG timer can output a single pulse of an arbitrary width when triggered.When reactivation is enabled, the PPG timer reloads the counter value after an edge is detectedduring operation.

One-shot Mode Timing Charts

Figure 8.5-1 show the one-shot mode timing chart when trigger reactivation is disabled. Figure8.5-2 shows the one-shot mode timing chart when trigger reactivation is enabled.

When reactivation is disabled

Figure 8.5-1 One-shot Mode Timing Chart (Trigger Reactivation Disabled)

m

n

0

PPG


Trigger

(1)

(2)

253


When reactivation is enabled

Figure 8.5-2 One-shot Mode Timing Chart (Trigger Restarted)

m

n

0

PPG


Trigger

(1)

(2)

254

8.6 Interrupts

8.6 Interrupts

Figure 8.6-1 shows the interrupt resources and timing chart.

Interrupt Resources and Timing Chart

Figure 8.6-1 Interrupt Resources and Timing Chart (PPG Output: Ordinary Polarity)

The maximum 2.5T (T: count clock cycle) is needed from hanging of the start trigger to loadingthe count value.

Trigger started

Load

Clock

Count value 0003 0002 0001 0000 0003

PPG

Interrupt

Effective edge compare match Borrow

2.5Tmaximum

X

255


8.7 PPG Output of ALL-L and ALL-H

This section describes PPG output of all-L and all-H.

PPG Output All-L and All-H

Figure 8.7-1 shows an example of the output method that sets the PPG output to all-L, andFigure 8.7-2 shows an example of the output method that sets the PPG output to all-H.

Figure 8.7-1 Example of the Output Method that Sets PPG Output to All-L

Figure 8.7-2 Example of the Output Method that Sets PPG Output to All-H

PPG

Reduce the duty.

Using an interrupt by borrow, set the PGMS (mask bit)to "1". If the PGMS (mask bit) is set to "0" during useof an interrupt by borrow, the PWM waveform can beoutput without generating glitches.

PPG

Increase the duty.

Using an interrupt by compare match, write to theduty setting register the same values as that in the cycle setting register.

256



This section gives notes on using the PPG timer.

Precautions on Using the PPG Timer

• If the device attempts to set and clear the interrupt request flag at the same time, the flag isset and the clear operation becomes ineffective.

• The settings of bit11 and bit10 (count clock select bits CKS1 and CKS0) of the PPG controlregister are reflected immediately after data is written to the bits. Change the settings of thebits when counting stops.

• If the device attempts to load and count the PPG down counter (PPGC: 16-bit down counter)at the same time, the load operation takes precedence.

257


258


This chapter gives an overview of the multifunction timer and explains the register configuration and functions and the timer operation.

9.1 Overview of the Multifunction Timer

9.2 Registers of the Multifunction Timer

9.3 Multifunction Timer Operation

259


9.1 Overview of the Multifunction Timer

The multifunction timer consists of four channels for a 16-bit up counter. This section gives an overview of the multifunction timer.

Features of the Multifunction Timer

The multifunction timer has the following features:

• A low-pass filter reduces noise that is below the amplitude of the set clock.

• The pulse width can be measured according to settings using seven types of clock signals.

• An event count from pin input is available.

• An interval timer that uses seven types of clocks and external input clocks is available.

Block Diagram

Figure 9.1-1 shows the block diagram of the multifunction timer.

Figure 9.1-1 Block Diagram of the Multifunction Timer

16 bit Counter

CK

CNT

CCLKP CKITO

Divider

Event counter

Interrupt

Interval register

CPIB

CLR

Edg

e de

tect

ion

EN

CPIA

Division

Synchronization

CLKP

LPF

OUT

Synchronization

Capture register

260



This section explains the configuration and functions of the registers used by the multifunction timer.

Registers of the Multifunction Timer

Figure 9.1-1 shows the registers of the multifunction timer.

Figure 9.2-1 Registers of the Multifunction Timer

bit150000F0H T0LPCR T0CCR (R/W)0000F2H T0TCR T0R (R/W)0000F4H (R/W)0000F6H (R/W)0000F8H T1LPCR T1CCR (R/W)0000FAH T1TRR T1R (R/W)0000FCH (R/W)0000FEH (R/W)000100H T2LPCR T2CCR (R/W)000102H T2TRR T2R (R/W)000104H (R/W)000106H (R/W)000108H T3LPCR T3CCR (R/W)00010AH T3TRR T3R (R/W)00010CH (R/W)00010EH (R/W)

T2DRRT2CRR

T3DRRT3CRR

T0DRRT0CRR

T1DRRT1CRR

8 7 0

000110H Access ProhibitedTTEST

261


9.2.1 Low-Pass Filter Control Register (TxLPCR)

The low-pass filter control register (TxLPCR) sets the low-pass filter for input pins.

Low-Pass Filter Control Register (TxLPCR)

The low-pass filter control register (TxLPCR) can be 8-bit accessed. Because this filter reducesnoise logically, the delay between the output waveform and the input waveform is the noisereduction width plus two cycles.

Figure 9.2-2 shows the bit configuration of the low-pass filter control register (TxLPCR).

Figure 9.2-2 Bit Configuration of the Low-Pass Filter Control Register (TxLPCR)

[bit15 to bit11] (reserved)

These bits are unused.

Writing to these bits is ignored, and the read value is always "0".

[bit10, bit9] FCx1, FCx0 (filter clock select flag)

These bits are used to select the operating clock for the LPF.

Table 9.2-1 shows the operating clock selection.

[bit8] FxEN (filter enable flag)

This bit specifies whether the filter is used.

bit15 14 13 12 11 10 9 8TxLPCR address

0000F0H

0000F8H

000100H

000108H

FCx1 FCx0 FxEN 00000000B

R/W R/W R/W

Initial value

Table 9.2-1 Operating Clock Selection

FCx1 FCx0 Noise reduction width (@20.27 MHz)

0 0 0.2 µs [initial value]

0 1 0.4 µs

1 0 0.8 µs

1 1 1.6 µs

0 The filter is not used [initial value].

1 The filter is used.

262


9.2.2 Capture Control Register (TxCCR)

The capture control register (TxCCR) sets the count, edge, and interrupt in capture mode.

Capture Control Register (TxCCR)

The capture control register can be 8-bit accessed. If this register is written to during operation(entire register ST = 1), the timer operation is unpredictable. Be sure to rewrite this registerwhen it is stopped (ST = 0).

Figure 9.2-3 shows the bit configuration of the capture control register (TxCCR).

Figure 9.2-3 Bit Configuration of the Capture Control Register (TxCCR)

[bit7] CPF (capture edge detection flag)

This bit indicates that the capture end edge has been detected.

Writing "1" to this bit has no effect.

Note:

If data is written to this flag from the hardware and the CPU at the same time, writing fromthe hardware has priority.

[bit6] (reserved)

This bit is unused.

Writing to this bit is ignored, and the read value is always "0".

[bit5] CPST (capture start edge select flag)

This bit sets the polarity of the capture start edge.

[bit4] CPED (capture end edge select flag)

This bit sets the polarity of the capture end edge.

bit7 6 5 4 3 2 1 0TxCCR address

0000F1H

0000F9H

000101H

000109H

CPOVCPF CPST CPED CPIE CPMD CPIS 00000000B

R/0 R/0 R/W R/W R/W R/W R/W

Initial value

0 No capture edge [initial value]

1 Capture edge

0 Rising edge [initial value]

1 Falling edge


1 Falling edge

263


[bit3] CPIE (capture interrupt enable flag)

This bit enables capture interrupt at capture end.

When this bit and CPF are both set to "1", an interrupt is sent to the CPU.

[bit2] CPOV (capture overflow detection flag)

This bit indicates that the counter has detected an overflow from FFFFH to 0000H in the free-run mode of capture mode.

Notes:

• Writing "1" to this bit has no effect.

• If data is written to this bit from the hardware and the CPU at the same time, writing fromthe hardware has priority.

[bit1] CPMD (capture count mode flag)

This bit sets the count mode of the capture counter.

[bit0] CPIS (capture input select flag)

This bit is used to select the input signal for capture.

0 Capture interrupts are disabled [initial value].

1 Capture interrupts are enabled

0 No capture overflow [initial value]

1 Capture overflow

0 Free-run mode [initial value]

1 Upper-limit compare mode

0 CPIA input is used [initial value].

1 CPIB input is used.

264


9.2.3 Timer Setting Register (TxTCR)

The timer setting register (TxTCR) controls the timer operation.

Timer Setting Register (TxTCR)

The timer setting register (TxTCR) can be 8-bit accessed. If this register is rewritten duringoperation (entire register ST = 1), the timer operation is unpredictable. Be sure to rewrite thisregister when it is stopped (ST = 0).

Figure 9.2-4 shows the bit configuration of the timer setting register (TxTCR).

Figure 9.2-4 Bit Configuration of the Timer Setting Register (TxTCR)

[bit15] TCF (timer compare match detection flag)

This bit indicates that a timer compare match has been detected.

Notes:

• Writing "1" to this bit has no effect.

• If data is written to this bit from the hardware and the CPU at the same time, writing datafrom the hardware has priority.

[bit14] TSES (timer start edge select flag)

This bit sets the start edge of the timer.

[bit13] TCC (timer count clear setting flag)

This bit specifies that the counter is cleared when a timer compare match is detected.

bit15 14 13 12 11 10 9 8TxTCR address

0000F2H

0000FAH

000102H

00010AH

TCS2TCF TSES TCC TIE CINV TCS1 TCS0 00000000B

R/W R/0 R/W R/W R/W R/W R/W R/W

Initial value

0 No compare match [initial value]

1 Compare match


1 Falling edge

0 Count clear [initial value]

1 No count clear

265


[bit12] TIE (timer interrupt enable flag)

This bit enables timer interrupts.

When this bit and TCF are both set to "1", an interrupt is sent to the CPU.

[bit11] CINV (timer clock invert flag)

This bit inverts the timer input clock signal from the external pin.

[bit10 to bit8] TCS2 to TCS0 (timer clock select flag)

These bits are used to select the timer clock.

Note:

To use the event count mode, set these bits to "111".

Table 9.2-2 shows the clocks to be selected.

0 Timer interrupts are disabled [initial value].

1 Timer interrupts are enabled.

0 The count increments at the rising edge of the clock [initial value].

1 The count increments at the falling edge of the clock.

Table 9.2-2 Clocks to be Selected

TCS bit Clock and source to be selected

TCS2 TCS1 TCS0 Division ratio Cycle (@20.27 MHz)

0 0 0 φ × 23 0.4 µs

0 0 1 φ × 25 1.6 µs

0 1 0 φ × 27 6.3 µs

0 1 1 φ × 29 25.3 µs

1 0 0 φ × 210 50.5 µs

1 0 1 φ × 212 202.1 µs

1 1 0 φ × 214 808.3 µs

1 1 1 External clock

266


9.2.4 Entire Timer Control Register (TxR)

The entire timer control register (TxR) controls the entire timer operation.

Enter Timer Control Register (TxR)

The entire timer control register (TxR) can be 8-bit accessed.

Figure 9.2-5 shows the bit configuration of the entire timer control register (TxR).

Figure 9.2-5 Bit Configuration of the Entire Timer Control Register (TxR)

[bit7 to bit5] (reserved)


Writing to these bits is ignored, and the read value is always "000B".

[bit4, bit3] TST2, TST1 (test bits)

These bits are test bits.

Always write "00B" to these bits.

[bit2, bit1] MD1, MD0 (timer select flag)

These bits are used to select the timer operation.

[bit0] ST (timer operation start flag)

This bit is the timer operation start flag.

Set CPIE or TIE to "0" before ST=0.

When ST=0 and the interrupt factor occurs at the same time, even though ST=0, the interruptoccurs.

bit7 6 5 4 3 2 1 0TxR address

0000F3H

0000FBH

000103H

00010BH

MD1TST2 TST1 MD0 ST 00000000B

R/W R/W R/W R/W R/W

Initial value

MD1 MD0 Selection mode

0 0 Interval timer [initial value]

0 1 Event count

1 0 Capture


0 Timer operation is disabled [initial value].

1 Timer operation is enabled.

267


9.2.5 Timer Compare Data Register (TxDRR)

The timer compare data register (TxDRR) stores timer compare data.

Timer Compare Data Register (TxDRR)

Figure 9.2-6 shows the bit configuration of the timer compare data register (TxDRR).

Figure 9.2-6 Bit Configuration of the Timer Compare Data Register (TxDRR)

The timer compare data register (TxDRR) compares data in this register and the value of thetimer counter and then indicates whether there is a compare match. To use this register, set theinterval time in the timer mode and the event count in the external event mode. Enter the uppercount limit in capture mode. This register cannot be 8-bit accessed. Setting 0 in this register

results in 216 counts.

bit15 14 13 12 11 10 9 8TxDRR address

0000F4H

0000FCH

000104H

00010CH

D11D12 D11D13D15 D14 D9 D8 Undefined

R/W R/W R/W R/W R/W

Initial value

bit7 6 5 4 3 2 1 0


R/W R/W R/W R/W

R/W R/W R/W

R/W R/W R/W R/W

Initial value

268


9.2.6 Capture Data Register (TxCRR)

The capture data register (TxCRR) is used to read the captured value.

Capture Data Register (TxCRR)

Figure 9.2-7 shows the bit configuration of the capture data register (TxCRR).

Figure 9.2-7 Bit Configuration of the Capture Data Register (TxCRR)

Data can also be written to the capture data register (TxCRR) to enter an initial value.

This register cannot be 8-bit accessed.

bit15 14 13 12 11 10 9 8TxCRR address

0000F6H

0000FEH

000106H

00010EH


R/W R/W R/W R/W R/W

Initial value

bit7 6 5 4 3 2 1 0


R/W R/W R/W R/W

R/W R/W R/W

R/W R/W R/W R/W

Initial value

269


9.2.7 Test Data Register (TTEST)

The test data register (TTEST) is used to test. Do not access the TTEST.

Test Data Register (TTEST)

Figure 9.2-8 Bit Configuration of the Test Data Register (TTEST)

bit15 14 13 12 11 10 9 8TTEST address

000110H


R/W R/W R/W R/W R/W

Initial value

bit7 6 5 4 3 2 1 0


R/W R/W R/W R/W

R/W R/W R/W

R/W R/W R/W R/W

Initial value

270



The multifunction timer has the following operating modes:• Interval timer• Event count• Capture modeThis section gives an overview of operation in each mode.The initial value of the toggle output of this module is "0" in all modes.

Interval Timer Mode

In the interval timer mode, the multifunction timer has functions that use the clock selected fromthe seven types of clock sources for the timer count and toggle output and generate an interruptif the counter value and the compare register value match.

Figure 9.3-1 shows the multifunction timer operating state in interval timer mode.

Figure 9.3-1 Multifunction Timer Operating State in Interval Timer Mode

Compare register value

0xFFFF

Counter value

Interrupt

Pin output

0x0000

An interrupt is generated at the pin output edge.

271


Event Count Mode

In the event count mode, the multifunction timer detects the pin input edge and counts theedges the specified number of times.

When the counter value and the compare register value match, TCF is set to "1". If TIE is set to"1" at this time, an interrupt is generated. When a compare match is detected, the counter canbe cleared.

Figure 9.3-2 shows the multifunction timer operating state in event count mode.

Figure 9.3-2 Multifunction Timer Operating State in Event Count Mode

Clock

Pin input

Edge detection

Counter

Toggle output

Compare register

This signal enables an interrupt to be generated and the counter to be cleared.

An output signal is output when a compare match is detected.

0 1 32 4

34

272


Capture Mode

In the capture mode, the width between the rising or falling edges of an external pin input canbe measured. The clock for measurement can be selected from the seven types of clocksources. The start and end edges can be selected from either the rising or falling edge. In free-run mode, the count value is captured when the end edge is reached. In the upper-limitcompare mode, an upper limit is input if the count value and the upper-limit compare valuematch before the end edge is reached. Otherwise, the captured value at the end edge is input.

Figure 9.3-3 shows an example of starting the count at the rising edge and ending it at thefalling edge in free-run mode.

Figure 9.3-3 Example of Rising and Falling Edges in Capture Mode

0xFFFF

Counter value

0x0000

External input

The value at this point is captured.

Capture register 7777xxxx

273


Low-Pass Filter

This module contains a low-pass filter for each external pin input.

This filter enables logical reduction of noise in four types of widths.

Figure 9.3-4 shows noise reduction using the low-pass filter.

Figure 9.3-4 Noise Reduction using the Low-Pass Filter

Filter clock

Input signal

Capture signal

State 0 1 0 0 01 1 1 1 1222

Output signal

2

This noise is reduced.

Filter clock

Input signal

Capture signal

State

Output signal

This noise is reduced.

All noise except signals that continue for at least two cycles of the filter clock is reduced.

000 1

274


This chapter gives an overview of the 16-bit pulse width counter and explains the register configuration and functions and the counter operation.

10.1 Overview of the 16-Bit Pulse Width Counter

10.2 Registers of the 16-Bit Pulse Width Counter

10.3 Operation of the 16-Bit Pulse Width Counter

275


10.1 Overview of the 16-Bit Pulse Width Counter

The 16-bit pulse width counter uses a 16-bit up counter to measure the pulse width of externally input signals.

16-Bit Pulse Width Counter

The 16-bit pulse width counter consists of a 16-bit up counter, three 8-bit control registers, aPWC data register, PWC upper data register, and a low-pass filter (LPF). This counter has thefollowing function:

• Interrupt request generation during data register transfer

Block Diagram

Figure 10.1-1 shows the block diagram of the 16-bit pulse width counter.

Figure 10.1-1 16-bit Pulse Width Counter

Capture Register

PWCCL

16 bit CounterPMI

Internal bus

PWCCH

Control circuit

LPF

Control bit

Flag setSampling interval selectionCount clock selection

5

4Sampling interval

Count clockCount clear

IRQ

Overflow

Count clock

PWCD

Upper value register

Upper value

276



This section explains the configuration and functions of the registers of the 16-bit pulse width counter.

Registers of the 16-Bit Pulse Width Counter

Figure 10.2-1 shows the register configuration of the 16-bit pulse width counter.

Figure 10.2-1 Register Configuration of the 16-bit Pulse Width Counter

Address000090H

000094H

000098H

00009CH

15 8 7 0PWC control registerPWC data registerPWC control registerPWC upper data register

PWCCL PWCCHPWCD

PWCUDReservePWCC2

277


10.2.1 PWC Control Register (PWCCL)

This section explains the configuration and functions of the PWC control register (PWCCL).

PWC Control Register (PWCCL)

Figure 10.2-2 shows the bit configuration of the PWC control register (PWCCL).

Figure 10.2-2 Bit Configuration of the PWC Control Register (PWCCL)

[bit7]: INT

This bit is a flag that indicates that capture data has been transferred to the PWC dataregister. When a capture data transfer interrupt request is enabled (bit6: INTE = 1) and thisbit is set, an interrupt request is generated.

The read modify write instruction is read "1".

[bit6]: INTE

This bit is the capture data transfer request interrupt enable bit.

[bit5]: OVFL

This bit is a flag that indicates that the 16-bit up counter has overflowed from FFFFH to0000H. When an overflow interrupt request is enabled (bit4: OVFLE = 1) and this bit is set,an interrupt request is generated.


7 6 5 4 3 2 1 0 Initial value PWCCL INT INTE OVFL OVFLE ST 0000--00B

( R/W ) ( R/W ) ( R/W ) ( R/W ) (R/W)

bit

0 Interrupt source is cleared.

1 Capture data is available.

0 Interrupt request is disabled.

1 Interrupt request is enabled.

0 Interrupt source is cleared.

1 An overflow occurs.

278


[bit4]: OVFLE

This bit is the overflow interrupt request enable bit.

[bit3, bit2]: Unused bits


[bit1]: Reserved

This bit is a reserved bit. Be sure to write "0" at writing.

[bit0]: ST

This bit is the PWC start bit.

Note:

Do not access this register using the read modify write (RMW) instruction.

0 Interrupt request is disabled.


0 PWC stops.

1 PWC operates.

279


10.2.2 PWC Control Register (PWCCH)

This section explains the configuration and functions of the PWC control register (PWCCH).

PWC Control Register (PWCCH)

Figure 10.2-3 shows the bit configuration of the PWC control register (PWCCH).

Figure 10.2-3 Bit Configuration of the PWC Control Register (PWCCH)

[bit7, bit6]: TEST1, TEST0

These bits are test bits.

[bit5]: Unused bit

This bit is unused.

[bit4, bit3]: CSLF1, CSFL0

These bits are used to select the LPF sampling interval from the ones listed in Table 10.2-1 .

7 6 5 4 3 2 1 0 Initial value PWCCH TEST1 TEST0 CSLF1 CS1 CS0 00-00000B

CSLF0

(R/W)CS2

(R/W)(R/W)(R/W)(R/W) ( )(R/W) (R/W)

bit

Writing a value of "1" is prohibited.

Table 10.2-1 LPF Sampling Interval

CSLF1 CSLF0 Sampling interval

0 0 φ × 26

0 1 φ × 28

1 0 φ × 210

1 1 φ × 212

(φ is the cycle of the system base clock.)

280


[bit2 to bit0]: CS2, CS1, CS0

These bits are used to select the internal count clock as shown in Table 10.2-2 .

Note:


Table 10.2-2 Internal Count Clock

CS2 CS1 CS0 Count clock selection

0 0 0 φ

0 0 1 φ divided by 26





281


10.2.3 PWC Data Register (PWCD)

The PWC data register (PWCD) stores the measured value of the pulse width.

PWC Data Register (PWCD)

Only the edge of input signal is captured the capture value. When the overflow is performed andthe upper value is exceeded, this register does not capture.

Figure 10.2-4 shows the bit configuration of the PWC data register (PWCD).

Figure 10.2-4 Bit Configuration of the PWC Data Register (PWCD)

Note:


( R )

15 14 13 12 11 10 9 8 PWCD

XXXX XXXXB

bit

7 6 5 4 3 2 1 0 Initial valuePWCD

bit

( R ) ( R ) ( R ) ( R ) ( R ) ( R ) ( R )

( R ) ( R ) ( R ) ( R ) ( R ) ( R ) ( R ) ( R )

XXXX XXXXB

Initial value

282


10.2.4 PWC Control Register (PWCC2)

This section explains the configuration and functions of the PWC Control Register (PWCC2).

PWC Control Register (PWCC2)

Figure 10.2-5 Bit Configuration of the PWC Control Register (PWCC2)

[bit7]: UPINT

This bit is a flag that indicates that the setting value of upper register has counted. When theupper value interrupt request is enabled (bit6: UPINTE=1) and this bit is set, an interruptrequest is generated.


[bit6]: UPINTE

This bit is a upper value interrupt request enable bit. Set to this bit to "1" and compare thecounter value and the upper setting register.

[bit5]: LOW

The bit represents that the capture value in the data register is indicated LOW width.

Note:


7 6 5 4 3 2 1 0 Initial value PWCC2 UPINT UPINTE LOW 000-----B

( R/W ) ( R/W ) ( R/W )

bit

0 Interrupt source is cleared. (Initial value)

1 Upper value over count is available.

0 Interrupt request is disabled. (Initial value)


0 HIGH width measurement is completed (Initial value)

1 LOW width measurement is completed.

283


10.2.5 Upper Value Setting Register (PWCUD)

This register stores the upper value of a pulse width measurement.

Upper Value Setting Register (PWCUD)

Figure 10.2-6 Bit Configuration of the Upper Value Setting Register (PWCUD)

This register is corresponding to each width regardless of H and L width, the pulse whichexceeds the upper value is measured and the UPINT bit of PWCC2 register is set. When thisregister exceeds the counter value, the count is continued and is not stopped. Therefore theinitial value of this register is undefined, writing "1" to the UPINTE bit of PWCC2 register, andwrite the upper value before compare it.

Note:


15 14 13 12 11 10 9 8 Initial valuePWCUD XXXX XXXXB

( R/W )

7 6 5 4 3 2 1 0 Initial valuePWCUD XXXX XXXXB

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

bit

bit

284



The 16-bit pulse width counter consists of a 16-bit up counter, three 8-bit control registers, a PWC data register, PWC upper data register, and an LPF. This counter measures the pulse width. One of five count clocks can be selected.

Basic Operation of the 16-Bit Width Pulse Counter

Pulse width count operation

The PWC captures the counter value and clears the counter at the rising and falling edge of thePMI signal. The cleared counter continues counting unchanged. When the count value iscaptured, the PWC generates an interrupt.

When the counter value changes from FFFFH to 0000H, the PWC generates an overflowinterrupt.

Figure 10.3-1 shows the basic operation of the 16-bit pulse width counter.

Figure 10.3-1 Basic Operation of the 16-bit Pulse Width Counter

Note:

The first edge (ST=1) is not captured after the operation enables.

PMI input

FFFFH

Upper value mmmH

0000H

PWCD

INT

OVFL

Rising edge

ST (operation enable)

xxxxH aaaaH bbbbH ccccH ddddH eeeeH

Falling edge

Count value

UPINT

LOW

The upper value interrupt is set, but not captured.

285


Count Clock Selection

One of five count clocks can be selected.

Selectable count clock is shown as follow.

LPF Sampling Intervals

The LPF sampling intervals can be selected as follow.

*: Caution of setting

The PWC operation clock is CLKP. The count clock and the LPF sampling clock operatesusing φ.

Therefore, it does not operate correctly when the PWC operation clock is not faster thanthe count clock and the LPF sampling clock.

Cycle: PWC operation clock × 4 < count clock

PWC opeariont clock × 4 < keep the LPF sampling clock condition.

Example: at CLKP : 20 MHz => 50 ns × 4 < count clock (φ × 26 : 1.6 µs)

at CLKP : 10 MHz => 100 ns × 4 < count clock (φ × 26 : 1.6 µs)

at CLKP : 5 MHz => 200 ns × 4 < count clock (φ × 26 : 1.6 µs)

at CLKP : 0.3 MHz => 3300 ns × 4 < count clock (φ × 26 : 1.6 µs) setting prohibited

Table 10.3-1 Count Clock Selection

CS2 CS1 CS0 Count clock selection

PLL frequency multiply by 4

(40 MHz)

PLL off (Source oscillation

10 MHz)

0 0 0 CLKP 50 ns 200 ns

0 0 1 φ × 26 * 1.6 µs 6.3 µs

0 1 0 φ × 28 * 6.3 µs 25.3 µs

0 1 1 φ × 210 * 25.3 µs 101.0 µs

1 0 0 φ × 212 * 101.0 µs 404.1 µs

(CLKP is the peripheral clock. φ is the cycle of the system base clock.)

CSLF1 CSLF0 Sampling interval PLL frequency multiply by 4

(40 MHz)

PLL off (Source oscillation 10 MHz)

0 0 φ × 26 * 1.6 µs 6.3 µs

0 1 φ × 28 * 6.3µs 25.3 µs

1 0 φ × 210 * 25.3 µs 101.0 µs

1 1 φ × 212 * 101.0 µs 404.1 µs


286


Figure 10.3-2 LPF Operation

Interrupt Request Generation

The 16-bit pulse width counter can generate the following three interrupt requests:

• Capture data transfer interrupt request

When capture data is transferred to the PWC data register, the interrupt flag is set. Wheninterrupt requests are enabled, an interrupt request is generated.

• Counter overflow interrupt request

When the counter value overflows from FFFFH to 0000H during measurement, the overflowflag is set. When interrupt requests are enabled, an interrupt request is generated.

Capture is not performed in overflow.

• Interrupt request which counts exceeding the value of upper register during counting

When the counter value is larger than the upper setting register during measurement, theflag is set. When interrupt requests are enabled, an interrupt request is generated.

Sampling clock

LPF output

Input signal

L is eliminated.

H is eliminated. L is eliminated.

H is eliminated.

Sampling clock

LPF output

Input signal

287


288


This chapter describes the interrupt controller, the configuration and functions of registers, and interrupt controller operation. It also presents an example of using the hold request cancellation request function.

11.1 Overview of the Interrupt Controller

11.2 Interrupt Controller Registers

11.3 Interrupt Controller Operation

11.4 Example of Using the Hold Request Cancellation Request Function (HRCR)

289



The interrupt controller controls interrupt acceptance and arbitration processing.

Hardware Configuration of the Interrupt Controller

The interrupt controller consists of the following components:

• ICR register

• Interrupt priority decision circuit

• Interrupt level and interrupt number (vector) generator

• HOLD request cancellation request generator

Major Functions

The interrupt controller has the following major functions:

• Detecting NMI requests and interrupt requests

• Deciding priority (using a level or number)

• Passing to the CPU an interrupt level based on the decision result to provide informationabout the interrupt source

• Passing to the CPU an interrupt number based on the decision result to provide informationabout the interrupt source

• Instruction for return from stop mode due to the occurrence of an interrupt with an NMI/interrupt level other than "11111B" (to CPU)

• Generating a HOLD request cancellation request for the bus master

290


Block Diagram

Figure 11.1-1 is a block diagram of the interrupt controller.

Figure 11.1-1 Block Diagram of the Interrupt Controller

6

5

WAKEUP (LEVEL 11111: "1")

LEVEL4-0

MHALTIHLDREQcancellation

requestLEVELand

VECTORgeneration

VECTORdecision

NMIprocessing

R-BUS

UNMI

Priority decision

VCT5-0

LEVEL decision

ICR00 . . .ICR47

RI00...

RI47(DLYIRQ)

291



This section describes the configuration and functions of the registers used by the interrupt controller.

Interrupt Controller Registers

Figure 11.2-1 shows the registers used by the interrupt controller.

Figure 11.2-1 Interrupt Controller Registers (Continued on next page)bit 7 6 5 4 3 2 1 0

Address: 00000440H -- -- -- ICR4 ICR3 ICR2 ICR1 ICR0 ICR00










Address: 0000044AH -- -- -- ICR4 ICR3 ICR2 ICR1 ICR0 ICR10

Address: 0000044BH -- -- -- ICR4 ICR3 ICR2 ICR1 ICR0 ICR11

Address: 0000044CH -- -- -- ICR4 ICR3 ICR2 ICR1 ICR0 ICR12

Address: 0000044DH -- -- -- ICR4 ICR3 ICR2 ICR1 ICR0 ICR13

Address: 0000044EH -- -- -- ICR4 ICR3 ICR2 ICR1 ICR0 ICR14

Address: 0000044FH -- -- -- ICR4 ICR3 ICR2 ICR1 ICR0 ICR15

















R R/W R/W R/W R/W

292


bit 7 6 5 4 3 2 1 0

















R R/W R/W R/W R/W

Address: 0000045H MHALTI -- -- LVL4 LVL3 LVL2 LVL1 LVL0 HRCL

R/W R R/W R/W R/W R/W

293


11.2.1 Interrupt Control Register (ICR)

An interrupt control register (ICR) is provided for each of the interrupt input and sets the interrupt level of the corresponding interrupt request.

Bit Configuration of the Interrupt Control Register (ICR)

Figure 11.2-2 shows the bit configuration of the interrupt control register (ICR).

Figure 11.2-2 Bit Configuration of the Interrupt Control Register (ICR)

[bit4 to bit0] ICR4 to ICR0

These bits, which are the interrupt level setting bits, specify the interrupt level of thecorresponding interrupt request.

If an interrupt request has an interrupt level defined in this register that exceeds the levelmask value defined in the ILM register of the CPU, it is masked by the CPU.

These bits are initialized to "11111B" by a reset.

Table 11.2-1 shows the correspondence between possible interrupt level setting bits andinterrupt levels.

bit 7 6 5 4 3 2 1 0 Initial value

-- -- -- ICR4 ICR3 ICR2 ICR1 ICR0 ---11111B

R R/W R/W R/W R/W

294


Table 11.2-1 Correspondence Between Possible Interrupt Level Setting Bits and Interrupt Levels

ICR4* ICR3 ICR2 ICR1 ICR0 Interrupt level

0 0 0 0 0 0

0 1 1 1 0 14

0 1 1 1 1 15 NMI

1 0 0 0 0 16 Maximum level that can be set

1 0 0 0 1 17

1 0 0 1 0 18

1 0 0 1 1 19

1 0 1 0 0 20

1 0 1 0 1 21

1 0 1 1 0 22

1 0 1 1 1 23

1 1 0 0 0 24

1 1 0 0 1 25

1 1 0 1 0 26

1 1 0 1 1 27

1 1 1 0 0 28

1 1 1 0 1 29

1 1 1 1 0 30

1 1 1 1 1 31 Interrupt disabled

*: ICR4 is always "1"; "0" cannot be written to this bit.

Reserved for system

(High)

(Low)

295


11.2.2 Hold Request Cancellation Request Level Setting Register (HRCL)

The hold request cancellation request level setting register (HRCL) is a level setting register used to generate a hold request cancellation request.

Hold Request Cancellation Request Level Setting Register (HRCL)

Figure 11.2-3 shows the bit configuration of the hold request cancellation request level settingregister (HRCL).

Figure 11.2-3 Bit Configuration of the Hold Request Cancellation Request Level Setting Register (HRCL)

[bit7] MHALTI

This bit is the DMA transfer disable bit controlled by an NMI request. An NMI request setsthis bit to "1". Write "0" to this bit to clear it. At the end of an NMI routine, clear this bit thesame way it would be cleared in a normal interrupt routine.

[bit4 to bit0] LVL4 to LVL0

This bit sets the interrupt level used to issue a hold request cancellation request to the busmaster.

If an interrupt request with a higher level than the level defined in the HRCL register occurs,a hold request cancellation request is issued to the bus master.

The LVL4 bit is always "1"; "0" cannot be written to this bit.

7 6 5 4 3 2 1 0 Initial value

MHALTI -- -- LVL4 LVL3 LVL2 LVL1 LVL0

R/W R R/W R/W R/W R/W

0--11111BAddress: 00000045H

bit

296



This section describes the following items regarding operation of the interrupt controller:• Priority decision• NMI• Hold request cancellation request• Return from standby mode (stop/sleep)

Priority Decision

The interrupt controller selects the interrupt source with the highest priority from among thosethat exist simultaneously and outputs the interrupt level and the interrupt number of this sourceto the CPU.

The following shows the priority decision criteria for interrupt sources:

• NMI

• Source that meets the following conditions:

• Source with a value other than 31 as the interrupt level (31 means interrupts disabled)

• Source with the smallest value for the interrupt level

• Source with the smallest interrupt number that satisfies the both conditions above

If no interrupt source is selected according to the above decision criteria, 31 (11111B) is outputas the interrupt level. The interrupt number at this time is undefined.

Table 11.3-1 shows the relationship between interrupt sources, interrupt numbers

Table 11.3-1 Relationship Between Interrupt Sources, Interrupt Numbers, and Interrupt Levels (1/4)


Interrupt level

OffsetDefault

address of TBR

RNDecimal Hexadecimal

Reset 0 00 − 3FCH 000FFFFCH −

Mode vector 1 01 − 3F8H 000FFFF8H −

Reserved for system 2 02 − 3F4H 000FFFF4H −


Reserved for system 4 04 − 3ECH 000FFFECH −

Reserved for system 5 05 − 3E8H 000FFFE8H −


No-coprocessor trap 7 07 − 3E0H 000FFFE0H −

Coprocessor error trap 8 08 − 3DCH 000FFFDCH −

INTE instruction 9 09 − 3D8H 000FFFD8H −

297


Instruction break exception 10 0A − 3D4H 000FFFD4H −

Operand break trap 11 0B − 3D0H 000FFFD0H −

Step trace trap 12 0C − 3CCH 000FFFCCH −

NMI request (tool) 13 0D − 3C8H 000FFFC8H −

Undefined instruction exception 14 0E − 3C4H 000FFFC4H −

NMI request 15 0FAlways 15 (FH)

3C0H 000FFFC0H −

External Interrupt 0 16 10 ICR00 3BCH 000FFFBCH 6

External Interrupt 1 17 11 ICR01 3B8H 000FFFB8H 7



External interrupt 4 (USB-function)

20 14 ICR04 3ACH 000FFFACH −

External interrupt 5 (USB-Host) 21 15 ICR05 3A8H 000FFFA8H −

External interrupt 6 (OSDC) 22 16 ICR06 3A4H 000FFFA4H -

External interrupt 7 (MS-IF) 23 17 ICR07 3A0H 000FFFA0H -

Reload Timer 0 24 18 ICR08 39CH 000FFF9CH 8

Reload Timer 1 25 19 ICR09 398H 000FFF98H 9

Reload Timer 2 26 1A ICR10 394H 000FFF94H 10

UART0 (reception completed) 27 1B ICR11 390H 000FFF90H 0

UART1 (reception completed) 28 1C ICR12 38CH 000FFF8CH 1

UART2 (reception completed) 29 1D ICR13 388H 000FFF88H 2

UART0 (transmission completed) 30 1E ICR14 384H 000FFF84H 3

UART1 (transmission completed) 31 1F ICR15 380H 000FFF80H 4

UART2 (transmission completed) 32 20 ICR16 37CH 000FFF7CH 5

DMAC0 (end, error) 33 21 ICR17 378H 000FFF78H −



DMAC3 (end, error) 36 24 ICR20 36CH 000FFF6CH −


A/D 38 26 ICR22 364H 000FFF64H −



Interrupt level

OffsetDefault

address of TBR


298


PPG0 39 27 ICR23 360H 000FFF60H 13

PPG1 40 28 ICR24 35CH 000FFF5CH 14

PPG2 41 29 ICR25 358H 000FFF58H 15

PPG3 42 2A ICR26 354H 000FFF54H −

PWC 43 2B ICR27 350H 000FFF50H −

Reserved for system 44 2C ICR28 34CH 000FFF4CH −

Reserved for system 45 2D ICR29 348H 000FFF48H −

Main clock oscillation wait 46 2E ICR30 344H 000FFF44H −

Time-base timer overflow 47 2F ICR31 340H 000FFF40H −

Reserved for system 48 30 ICR32 33CH 000FFF3CH −

Watch timer 49 31 ICR33 338H 000FFF38H −

I2C ch.0 50 32 ICR34 334H 000FFF34H −

I2C ch.1 51 33 ICR35 330H 000FFF30H −

I2C ch.2 52 34 ICR36 32CH 000FFF2CH −

I2C ch.3 53 35 ICR37 328H 000FFF28H −

UART3 (reception completed) 54 36 ICR38 324H 000FFF24H −


UART3 (transmission completed) 56 38 ICR40 31CH 000FFF1CH −

UART4 (transmission completed) 57 39 ICR41 318H 000FFF18H −

Multifunction timer 0 58 3A ICR42 314H 000FFF14H −

Multifunction timer 1 59 3B ICR43 310H 000FFF10H −

Multifunction timer 2 60 3C ICR44 30CH 000FFF0CH −

Multifunction timer 3 61 3D ICR45 308H 000FFF08H −

Reserved for system 62 3E ICR46 304H 000FFF04H −

Delayed interrupt source bit 63 3F ICR47 300H 000FFF00H −

Reserved for system (used in REALOS *1)

64 40 − 2FCH 000FFEFCH −

Reserved for system (used in REALOS *1)

65 41 − 2F8H 000FFEF8H −

Reserved for system 66 42 − 2F4H 000FFEF4H −




Interrupt level

OffsetDefault

address of TBR


299


NMI

An NMI (Non Maskable Interrupt) has the highest priority among the interrupt sources handledby this module. Thus, an NMI is always selected if it occurs at the same time as other interruptsources.

• If an NMI occurs, the following information is reported to the CPU:

• Interrupt level: 15 (01111B)

• Interrupt number: 15 (0001111B)

• Detecting an NMI

The external interrupt and NMI module sets and detects an NMI. This module only generatesan interrupt level, interrupt number, and MHALTI in response to an NMI request.

• Preventing a DMA transfer occurring due to an NMI

If an NMI request occurs, the MHALTI bit of the HRCL register is set to "1" to prevent DMAtransfer. To clear the state preventing DMA transfer, clear the MHALTI bit to "0" at the end ofthe NMI routine.

Reserved for system 68 44 − 2ECH 000FFEECH −

Reserved for system 69 45 − 2E8H 000FFEE8H −



Reserved for system 72 48 − 2DCH 000FFEDCH −

Reserved for system 73 49 − 2D8H 000FFED8H −

Reserved for system 74 4A − 2D4H 000FFED4H −

Reserved for system 75 4B − 2D0H 000FFED0H −

Reserved for system 76 4C − 2CCH 000FFECCH −

Reserved for system 77 4D − 2C8H 000FFEC8H −

Reserved for system 78 4E − 2C4H 000FFEC4H −

Reserved for system 79 4F − 2C0H 000FFEC0H −

Used in INT instruction80|

255

50|

FF−

2BCH|

000H

000FFEBCH|

000FFC00H

−



Interrupt level

OffsetDefault

address of TBR


300


Hold Request Cancellation Request (HRLC: Hold Request Cancel Request)

For an interrupt with a higher priority to be processed during CPU hold, the device that hasgenerated the hold request must cancel the request. Set in the HRCL register the interrupt levelto be used as the criterion of generating a cancellation request.

Generation criteria

If an interrupt source with a higher interrupt level than the level defined in the HRCL registeroccurs, a hold request cancellation request is generated.

• If the interrupt level of the HRCL register is greater than the interrupt level after a prioritydecision, a cancellation request occurs.

• If the interrupt level of the HRCL register is equal to or less than the interrupt level after apriority decision, no cancellation request occurs.

Because the cancellation request remains valid, no DMA transfer occurs unless the interruptsource that has caused the cancellation request is cleared. Be sure to clear the correspondinginterrupt source.

If an NMI is used, the cancellation request is valid because the MHALTI bit of the HRCL registeris set to "1".

Possible levels

Values that can be set in the HRCL register range from 10000B to 11111B, which is the samerange as for the ICR.

If this register is set to 11111B, an interrupt request is issued for all the interrupt levels. If thisregister is set to 10000B, an interrupt request is issued only for an NMI.

Table 11.3-2 shows the settings of interrupt levels at which a hold request cancellation requestoccurs.

After a reset, since DMA transfer is not allowed at any interrupt level, no DMA transfer isperformed if an interrupt has occurred. Be sure to set the HRCL register to the necessary value.

Table 11.3-2 Settings of Interrupt Levels at which Hold Request Cancellation Request Occurs

HRCL register Interrupt levels at which a cancellation request occurs

16 NMI only

17 NMI, Interrupt level 16

18 NMI, Interrupt levels 16 and 17

− −

31 NMI, Interrupt levels 16 to 30 [initial value]

301


Return from Standby Mode (Sleep/Stop)

This module implements a function that causes a return from stop mode if an interrupt requestoccurs. If at least one interrupt request that includes Nmi occurs (with an interrupt level otherthan 11111), a return request from stop mode is generated for the clock controller.

Since the priority decision unit restarts operation when a clock is supplied after returning fromstop, the CPU executes instructions until the result of the priority decision unit is obtained.

The same operation occurs after a return from the sleep state.

Registers in this module can be accessed even in the sleep state.

Notes:

• The device returns from stop mode if an NMI request is issued. However, set an NMI so thatvalid input can be detected in the stop state.

• Provide an interrupt level of 11111 in the corresponding peripheral control register for aninterrupt source that you do not want to cause return from stop or sleep.

302



To allow the CPU to perform high-priority processing during DMA transfer, cancel a hold request for DMA and clear the hold state. In this example, an interrupt is used to cancel a hold request to the DMA, allowing the CPU to perform priority operations.

Control Registers

Hold request cancellation level setting register (HRCL): This module

If an interrupt with a higher interrupt level than the level defined in this register occurs, a holdrequest cancellation request is issued to DMA. This register sets the level to be used as thecriterion for this purpose.

ICR: This module

This register sets a higher level than the level in the HRCL register for the ICR corresponding tothe interrupt source that will be used.

Hardware Configuration

Figure 11.4-1 shows the flow of signals.

Figure 11.4-1 Flow of Signals

IRQ MHALTI DHREQ I-UNIT DMA B-UNIT CPU

(ICR)

(HRCL) DHACK

DHREQ: D bus hold requestDHACK: D bus hold acknowledgeIRQ: Interrupt request

MHALTI: Hold request cancellation request

This module Bus access request

303


Hold Request Cancellation Request Sequence

Figure 11.4-2 Interrupt level HRCL < ICR (LEVEL)

If an interrupt request occurs, the interrupt level changes. If the interrupt level is higher than thelevel defined in the HRCL register, MHALTI becomes active for DMA. This causes DMA tocancel an access request and the CPU to return from the hold state to perform the interruptprocessing.

Figure 11.4-3 shows an example of the timing chart for multiple interrupts.

Figure 11.4-3 Example of Interrupt Level HRCL < ICR (Interrupt I) < ICR (Interrupt II)

Example of Interrupt Routine

(1), (3) Interrupt source clear

-

(2), (4) RETI

In the above example, while Interrupt Routine I is being executed, an interrupt with a higherpriority occurs. While the interrupt with a higher level than the level in the HRCL registerremains, DHREQ is low.

Note:

Be especially careful about the relationship between interrupt levels defined in the HRCLregister and ICR.

CPU Bus access request

DHREQ

DHACK

IRQ

LEVEL

MHALTI

RUN Bus hold Interrupt processingBus hold

(DMA transfer)Example of interrupt routine(1) Interrupt source clear

(2) RETI|

(1) (2)

CPU

Bus access request

DHREQ

DHACK

IRQ1

IRQ2

LEVEL

MHALTI

RUN Bus hold

(4) (2)(1)(3)

Interrupt IInterrupt

processing IInterrupt

processing IIBus hold

(DMA transfer)

304


This chapter describes the external interrupt and NMI controller, the configuration and functions of registers, and operation of the external interrupt and NMI controller.

12.1 Overview of the External Interrupt and NMI Controller

12.2 External Interrupt and NMI Controller Registers

12.3 Operation of the External Interrupt and NMI Controller

305


12.1 Overview of the External Interrupt and NMI Controller

The external interrupt controller is a block that controls external interrupt requests input to NMI and INT0 to INT7.H level, L level, rising edge, or falling edge can be selected as the level of a request to be detected (except for NMI).INT4 to INT7 are connected to the USB host, USB function, OSDC, and memory stick interrupt requests inside the LSI chip.

Block Diagram of the External Interrupt and NMI Controller

Figure 12.1-1 is a block diagram of the external interrupt and NMI controller.

Figure 12.1-1 Block Diagram of the External Interrupt and NMI Controller

8

16

8

5 5

Interrupt enable register

GateInterrupt request

INT0 to INT3NMI

Edge detection circuitSource F/F

Interrupt source register

Request level setting register

R BUS

306



This section describes the configuration and functions of the registers used by the external interrupt and NMI controller.

External Interrupt and NMI Controller Registers

Figure 12.2-1 shows the registers used by the external interrupt and NMI controller.

Figure 12.2-1 External Interrupt and NMI Controller Registers

bit 7 6 5 4 3 2 1 0

EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 (ENIR)

External interrupt enable register

bit 15 14 13 12 11 10 9 8

ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 (EIRR)

External interrupt request register

bit 15 14 13 12 11 10 9 8

LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 (ELVR)

bit 7 6 5 4 3 2 1 0

LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0

Request level setting register

307


12.2.1 Interrupt Enable Register (ENIR)

The enable interrupt request register (ENIR) controls the masking of external interrupt request output.

Interrupt Enable Register (ENIR)

Figure 12.2-2 shows the bit configuration of the interrupt enable register (ENIR)

Figure 12.2-2 Bit Configuration of the Interrupt Enable Register (ENIR)

Output for an interrupt request is enabled based on the bit in this register to which "1" has beenwritten (INT0 enable is controlled by EN0), after which the interrupt request is output to theinterrupt controller. The pin corresponding to the bit to which "0" is written holds the interruptsource but does not generate a request to the interrupt controller.

Note:

No mask bit exists for NMI.


ENIR Address: 000041H EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 00000000B

[R/W]

308


12.2.2 External Interrupt Request Register (EIRR)

The external interrupt request register (EIRR) indicates the presence or absence of a corresponding external interrupt request when reading from this register and the contents of the flip-flop (NMI flag) that indicates this interrupt request are cleared when writing to this register.

External Interrupt Request Register (EIRR)

Figure 12.2-3 shows the bit configuration of the external interrupt request register (EIRR).

Figure 12.2-3 Bit Configuration of the External Interrupt Request Register (EIRR)

If the read value of this EIRR register is "1", there is an external interrupt request at the pincorresponding to this bit.

Write "0" to this register to clear the request flip-flop of the corresponding bit.

Writing "1" to this has no effect.

For a read by a read modify write instruction, "1" is read.

Note:

The NMI flag cannot be read or written to by a user.

For details about the NMI flag, see Figure 12.3-4 .


EIRR Address: 000040H ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 00000000B

[R/W]

309


12.2.3 External Interrupt Request Level Setting Register (ELVR)

The external level register (ELVR) specifies how a request is detected.

External Interrupt Request Level Setting Register (ELVR)

Figure 12.2-4 shows the bit configuration of the external interrupt request level setting register(ELVR).

Figure 12.2-4 Bit Configuration of the External Interrupt Request Level Setting Register (ELVR)

In ELVR, two bits each are assigned to INT0 to INT15, which results in the settings shown inTable 12.2-1 . Even though the bits of the EIRR are cleared while the request input is level-baseoperation, the pertinent bits are set again as long as the input is at the level that is active.

A falling edge is always detected at NMI (except in the stop state).

In the stop state, the “L” level is detected.

Note:

As changing the external interrupt request level may cause an interrupt source internally, alwaysclear the external interrupt request register (EIRR) after changing the external interrupt requestlevel. To clear the external interrupt request register, first read the external interrupt request level settingregister and then write to the EIRR register to clear it.



ELVR Address: 000042H LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 00000000B

ELVR Address: 000043H LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0 00000000B

[R/W]

Table 12.2-1 Assignment of ELVR

LBx LAx Operation

0 0 L level indicates the existence of a request.

0 1 H level indicates the existence of a request.

1 0 A rising edge indicates the existence of a request.

1 1 A falling edge indicates the existence of a request.

310

Added "Note:" in " External Interrupt Request Level Setting Register (ELVR)".



If, after a request level and an enable register are defined, a request defined in the ELVR register is input to the corresponding pin, this module generates an interrupt request signal to the interrupt controller.

Operation of an External Interrupt

For simultaneous interrupt requests from resources, the interrupt controller determines theinterrupt request with the highest priority and generates an interrupt for it.

Figure 12.3-1 shows external interrupt operation.

Figure 12.3-1 External Interrupt Operation

Return from Standby

To use an external interrupt to return from the standby state in the clock stop mode, use an H-level request as the input request.

If you use an edge request, the device does not return from the stop state in clock stop mode.

Operating Procedure for an External Interrupt

Set up a register located inside the external interrupt controller as follows:

1. Set the general-purpose I/O port to be shared with pin for the external interrupt input toinput port.

2. Disable the target bit in the interrupt enable register (ENIR).

3. Set the target bit in the external interrupt request level setting register (ELVR).

4. Read the external interrupt request level setting register (ELVR).

5. Clear the target bit in the external interrupt request register (EIRR).

6. Enable the target bit in the interrupt enable register (ENIR).

(Simultaneous writing of 16-bit data is supported for steps 5) and 6)).

Before setting a register in this module, you must disable the enable register. In addition, beforeenabling the enable register, you must clear the interrupt source register. This procedure isrequired to prevent an interrupt source from occurring by mistake while a register is being set oran interrupt is enabled.

External interrupt

ELVR

EIRR

ENIR

Source

Resource request

ICR y y

ICR x x

CMP CMP

IL

ILM

Interrupt controller CPU

311

Changed " Operating Procedure for an External Interrupt".


External Interrupt Request Level

• If the request level is an edge request, a pulse width of at least three machine cycles(peripheral clock machine cycles) is required to detect an edge.

• If the request level is a level setting and request input arrives from outside and is thencancelled, the request to the interrupt controller remains active because a source holdingcircuit exists internally.

The interrupt source register must be cleared to cancel a request to the interrupt controller.

Figure 12.3-2 shows clearing of the source holding circuit when a level is set. Figure 12.3-3shows an interrupt source and an interrupt request to the interrupt controller when interrupts areenabled.

Figure 12.3-2 Clearing the Source Holding Circuit when a Level is Set

Figure 12.3-3 Interrupt Source and Interrupt Request to Interrupt Controller when Interrupts are Enabled

NMI

An NMI has the highest level among the user interrupts and cannot be masked. However, as anexception, an NMI can be masked from the moment a reset occurs until ILM is set.

An NMI is accepted under the following conditions:

• Normal: Rising edge

• STOP mode: L level

An NMI can be used to clear stop mode. Inputting the L level in the stop state clears the stopstate and causes the oscillation stabilization wait time to start. Returning the NMI pin to the Hlevel during the oscillation stabilization wait time eliminates the NMI source and performs noNMI processing after operation is restarted. To perform NMI processing after clearing the stopstate, maintain the NMI pin at the L level and return it to the H level in the NMI processingroutine.

The NMI request detector has an NMI flag that is set for an NMI request and is cleared only if aninterrupt for the NMI itself is accepted or a reset occurs. Note that this bit is not readable orwritable.

Figure 12.3-4 shows the NMI request detector.

Holds a source while it is not cleared

Interrupt input Level detection Source F/F(Source holding circuit) Enable gate Interrupt controller

Interrupt input"H" level

Interrupt request to interrupt controller Becomes inactive when source F/F is cleared

312


Figure 12.3-4 NMI Request Detector

(NMI flag)

NMI request(Stop clearing)

NMIQ SX

R

STOP

Falling edgedetection

clear (RST, interrupt acknowledge)

1

0

313


314


This chapter explains the delayed interrupt module and bit search module that are REALOS-related hardware.REALOS-related hardware is used by the real-time OS. When REALOS is used, the hardware cannot be used with the user program.

13.1 Delayed Interrupt Module

13.2 Delayed Interrupt Module Registers

13.3 Operation of the Delayed Interrupt Module

13.4 Bit Search Module

13.5 Bit Search Module Registers

13.6 Bit Search Module Operation

315


13.1 Delayed Interrupt Module

The delayed interrupt module generates an interrupt for switching tasks. Use this module to allow a software program to generate or an interrupt request for the CPU or to clear an interrupt request.

Block Diagram of the Delayed Interrupt Module

Figure 13.1-1 is a block diagram of the delayed interrupt module.

Figure 13.1-1 Block Diagram of the Delayed Interrupt Module

Interrupt requestDLYI

R-bus

316



This section describes the configuration and functions of the registers used by the delayed interrupt module.

Delayed Interrupt Module Registers

Figure 13.2-1 shows the registers of the delayed interrupt module.

Figure 13.2-1 Registers of the Delayed Interrupt Module

Delayed Interrupt Control Register (DICR: Delayed Interrupt Control Register)

The delayed interrupt control register (DICR) controls delayed interrupts.

Figure 13.2-2 shows the bit configuration of the delayed interrupt control register (DICR).

Figure 13.2-2 Bit Configuration of the Delayed Interrupt Control Register (DICR)

[bit0] DLYI

7 6 5 4 3 2 1 0

Address: 00000044H DICR

[R/W]

DLYI

bit

7 6 5 4 3 2 1 0

[R/W]

DLYI -------0B (Initial value)

bit

DLYI Description

0 A delayed interrupt source is cleared or no request exists. [initial value]

1 A delayed interrupt source is generated.

317


13.3 Operation of the Delayed Interrupt Module

A delayed interrupt refers to an interrupt generated for switching tasks. Use this function to allow a software program to generate an interrupt request for the CPU or to clear an interrupt request.

Interrupt Number

A delayed interrupt is assigned to the interrupt source corresponding to the largest interruptnumber.

On the MB91310, a delayed interrupt is assigned to interrupt number 63 (3FH).

DLYI Bit of DICR

Write "1" to this bit to generate a delayed interrupt source. Write "0" to it to clear a delayedinterrupt source.

This bit is the same as the interrupt source flag for a normal interrupt. Therefore, clear this bitand switch tasks in the interrupt routine.

318



The bit search module searches for 0, 1, or any points of change for data written to the input register and then returns the detected bit locations.

Block Diagram of the Bit Search Module

Figure 13.4-1 is a block diagram of the bit search module.

Figure 13.4-1 Block Diagram of the Bit Search Module

Input latch

Addressdecoder

Detection mode

1 detection data coding

Bit search circuit

Detection result

D-BUS

319



This section explains the configuration and functions of the registers used by the bit search module.

Bit Search Module Registers

Figure 13.5-1 Bit search module registers.

Figure 13.5-1 Bit Search Module Register

0 Detection Data Register (BSD0)

Figure 13.5-2 shows the bit configuration of the 0 detection data register (BSD0).

Figure 13.5-2 Bit Configuration of the 0 Detection Data Register (BSD0)

• 0 detection is performed for the written data.

• The initial value after a reset is undefined.

• The read value is undefined.

• Use a 32-bit length data transfer instruction for data transfer. Do not use 8-bit or 16-bit lengthdata transfer instructions.

1 Detection Data Register (BSD1)

Figure 13.5-3 shows the bit configuration of the 1 detection data register (BSD1).

Figure 13.5-3 Bit Configuration of the 1 Detection Data Register (BSD1)

Use a 32-bit length data transfer instruction for data transfer.

Do not use 8-bit or 16-bit length data transfer instructions.

31 0

Address: 000003F0H BSD0

Address: 000003F4H BSD1

Address: 000003F8H BSDC

Address: 000003FCH BSRR

0 detection data register

1 detection data register

Change point detection data register

Detection result register

bit

31 0000003F0H

Read/writeInitial value

Write onlyUndefined

bit

31 0000003F4H


R/WUndefined

bit

320


Writing

1 detection is performed for the written data.

Reading

Save data of the internal state of the bit search module is read. This register is used to save andrestore the original state when the bit search module is used by, for example, an interrupthandler.

Even though data is written to the 0 detection or change point detection data register, data canbe saved and restored only by using the 1 detection data register.

The initial value after a reset is undefined.

Change Point Detection Data Register (BSDC)

Figure 13.5-4 shows the bit configuration of the change point detection data register (BSDC).

Figure 13.5-4 Bit Configuration of the Change Point Detection Data Register (BSDC)

Point of change are detected in the written value.

The initial value after a reset is undefined.

The read value is undefined.

Use a 32-bit length data transfer instruction for data transfer. Do not use 8-bit or 16-bit lengthdata transfer instructions.

Detection Result Register (BSRR)

Figure 13.5-5 shows the bit configuration of the detection result register (BSRR).

Figure 13.5-5 Bit Configuration of the Detection Result Register (BSRR)

The 0, 1, or change point detection result is read from this register.

The detection result to be read is determined by the last written data register.

31 0000003F8H


Write onlyUndefined

bit

31 0000003FCH


Read onlyUndefined

bit

321



The bit search module performs the following three operations:• 0 detection• 1 detection• Change point detection

0 Detection

The bit search module scans data written to the 0 detection data register from the MSB to LSBand returns the location where the first "0" is detected. The detection result can be obtained byreading the detection result register. The relationship between the detected location and thereturn value is given in Table 13.6-1 .

If a "0" is not found (that is, the value is FFFFFFFFH), 32 is returned as the search result.

[Execution example]

1 Detection

The bit search module scans data written to the 1 detection data register from the MSB to LSBand returns the location where the first "1" is detected. The detection result can be obtained byreading the detection result register. The relationship between the detected location and thereturn value is given in Table 13.6-1 .

If a "1" is not found (that is, the value is 00000000H), 32 is returned as the search result.

[Execution example]

Write data Read value (decimal)

11111111111111111111000000000000B11111000010010011110000010101010B10000000000000101010101010101010B11111111111111111111111111111111B

(FFFFF000H) (F849E0AAH) (8002AAAAH) (FFFFFFFFH

--> 20--> 5--> 1--> 32


00100000000000000000000000000000B00000001001000110100010101100111B00000000000000111111111111111111B00000000000000000000000000000001B00000000000000000000000000000000B

(20000000H)(01234567H)(0003FFFFH)(00000001H)(00000000H)

--> 2--> 7--> 14--> 31--> 32

322


Change Point Detection

The bit search module scans data written to the change point detection data register from bit30to the LSB for comparison with the MSB value. The first location where a value that is differentfrom that of the MSB is detected is returned. The detection result can be obtained by readingthe detection result register.

The relationship between the detected location and the return value is given in Table 13.6-1 . Ifa change point is not detected, 32 is returned. In change point detection, 0 is never returned asa result.

[Execution example]


00100000000000000000000000000000B00000001001000110100010101100111B00000000000000111111111111111111B00000000000000000000000000000001B00000000000000000000000000000000B11111111111111111111000000000000B11111000010010011110000010101010B10000000000000101010101010101010B11111111111111111111111111111111B

(20000000H)(01234567H)(0003FFFFH)(00000001H)00000000H)FFFFF000H)F849E0AAH)8002AAAAH)(FFFFFFFFH)

--> 2--> 7--> 14--> 31--> 32--> 20--> 5--> 1--> 32

Table 13.6-1 Bit Locations and Return Values (decimal)

Detected bit

location

Return value

Detected bit

location

Return value

Detected bit

location

Return value

Detected bit

location

Return value

31 0 23 8 15 16 7 24

30 1 22 9 14 17 6 25

29 2 21 10 13 18 5 26

28 3 20 11 12 19 4 27

27 4 19 12 11 20 3 28

26 5 18 13 10 21 2 29

25 6 17 14 9 22 1 30

24 7 16 15 8 23 0 31

Not found 32

323


Save/Restore Processing

If it is necessary to save and restore the internal state of the bit search module, such as whenthe bit search module is used in an interrupt handler, use the following procedure:

1. Read the 1 detection data register and save its contents (save).

2. Use the bit search module.

3. Write the data saved in 1) to the 1 detection data register (restore).

With the above operation, the value obtained when the detection result register is read the nexttime corresponds to the value written to the bit search module before 1).

If the data register written to last is the 0 detection or change point detection register, the valueis restored correctly with the above procedure.

324


This chapter gives an overview of the 10-bit A/D converter, register configuration and functions, and 10-bit A/D converter operation.

14.1 Overview of the 10-Bit A/D Converter

14.2 Registers of the 10-Bit A/D Converter

14.3 Operation of the 10-Bit A/D Converter

325



The 10-bit successive approximation A/D converter has two operation modes: conversion start by software and conversion start by external trigger.

Features of the 10-Bit A/D Converter

• Conversion time: 10 µs (sampling: 7.8 µs, conversion: 2.2 µs) when fch is @20 MHz

• A/D conversion result register available for each channel

• Channel scan function

Block Diagram

Figure 14.1-1 shows the configuration diagram of the 10-bit A/D converter, and Figure 14.1-2shows its block diagram.

Figure 14.1-1 Configuration Diagram of the 10-Bit A/D Converter

A/DAN0 to AN9

External pin (ATRG) ATRG

IRQ

326


Figure 14.1-2 Block Diagram of the 10-Bit A/D Converter

Control Logic

A/D

Channel & StatusControl Logic

BUFFER 10

D/A Converter

Comparator

S/H

AN9AN8AN7AN6AN5AN4AN3AN2AN1AN0

IRQExternal pin ATRG

Inte

rnal

dat

a bu

s

MP

X

×

327



This section explains the configuration and functions of the registers of the 10-bit A/D converter.

Registers of the 10-Bit A/D Converter

Figure 14.2-1 shows the register configuration of the 10-bit A/D converter.

Figure 14.2-1 Register Configuration of the 10-Bit A/D Converter

Address 15 000020H

00022H

00024H

00026H

00028H

0002AH

0002CH

0002EH

00030H

00032H

00034H

00036H

00038H

ADCTH ADCTL A/D status control registerADCH A/analog input select registerADAT0 A/D conversion data channel 0ADAT1 A/D conversion data channel 1ADAT2 A/D conversion data channel 2ADAT3 A/D conversion data channel 3ADAT4 A/D conversion data channel 4ADAT5 A/D conversion data channel 5ADAT6 A/D conversion data channel 6ADAT7 A/D conversion data channel 7ADAT8 A/D conversion data channel 8ADAT9 A/D conversion data channel 9TEST A/D converter test register (access prohibited)

bit

328


14.2.1 A/DC Control Register (ADCTH, ADCTL)

This section explains the configuration and functions of the A/DC control register (ADCTH, ADCTL).

A/DC Control Register (ADCTH, ADCTL)

Figure 14.2-2 shows the bit configuration of the A/DC control register (ADCTH, ADCTL).

Figure 14.2-2 Bit Configuration of the A/DC Control Register (ADCTH, ADCTL)

[bit15 to bit10]: Don't Care

The read value of these bits are always "000000B".

[bit9]: TRG

When this bit is set to "1", A/D conversion is started when a rising edge is detected atexternal pin ATRG.

This bit is ignored if an edge is detected during A/D conversion.

[bit8]: STR

This bit is the A/D conversion start bit.

The read value of this bit is always "0".

[bit7 to bit4]: ASS3 to ASS0

These bits enable reading of the selected analog channel.

This bit enables reading of effective data when BUSY = 1.

ADCTH

ADCTL

15 14 13 12 11 10 9 8 Initial value 0000 0000B

(R) (R) (R) (R) (R) (R) (R/W) (R/W)

(R) (R) (R) (R) (R) (R) (R/W) (R/W)

"0" "0" "0" "0" "0" "0" TRG STR

ASS3 ASS2 ASS1 ASS0 BUSY "0" INT INTE

7 6 5 4 3 2 1 0 Initial value 0000 0000B

bit

bit

0 Start by external pin trigger is prohibited.

1 Start by external pin trigger

0 No effect

1 Software start/stop (write during conversion)

0 to 9 Selected channel

329


[bit3]: BUSY

This bit is a flag that indicates A/D conversion is in progress.

[bit2]: Don' Care


[bit1]: INT

This bit is the A/D conversion end flag.

[bit0]: INTE

This bit is the A/D conversion interrupt enable bit.

When INT and INTE are both set to "1", an interrupt request is generated.

Note:


0 A/D conversion is not in progress.

1 A/D conversion is in progress.

0 No conversion, or conversion is in progress.

1 Conversion is completed.

0 Interrupt is disabled.

1 Interrupt is enabled.

330


14.2.2 Software Conversion Analog Input Select Register

This section explains the configuration and functions of the software conversion analog input select register.

Software Conversion Analog Input Select Register

Figure 14.2-3 shows the bit configuration of the software conversion analog input select register.

Figure 14.2-3 Bit Configuration of the Software Conversion Analog Input Select Register



[bit9 to bit0]: i9 to i0

These bits are the software conversion analog input select bits.

If multiple inputs are selected, data is sequentially converted for all selected inputs.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value

ADCH "0" "0" "0" "0" "0" "0" i9 i8 i7 i6 i5 i4 i3 i2 i1 i0 00 00H

(R/W)

bit

0 Input is not selected.

1 Input is selected.

331


14.2.3 A/D Conversion Result Register (ch.0 to ch.9)

This section explains the configuration and functions of the A/D conversion result register (ch.0 to ch.9).

A/D Conversion Result Register (ch.0 to ch.9)

Figure 14.2-4 shows the bit configuration of the A/D conversion result register (ch.0 to ch.9).

Figure 14.2-4 Bit Configuration of the A/D Conversion Result Register (ch.0 to ch.9)



[bit9 to bit0]: d9 to d0

These bits indicate the A/D conversion result for the channels.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value ADAT0 to ADAT9

d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 00 00H

(R) "0" "0" "0" "0" "0" "0"

bit

332


14.2.4 A/D Converter Test Register

This section explains the configuration and functions of the A/D converter test register.

A/D Converter Test Register

Figure 14.2-5 shows the bit configuration of the A/D converter test register.

Figure 14.2-5 Bit Configuration of the A/D Converter Test Register

[bit15 to bit0]: TEST

These are the A/D converter test register bits.

Note:

Do not access this register.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value

TEST TEST 00 00H

(R/W)

bit

333


14.3 Operation of the 10-Bit A/D Converter

This section explains A/D conversion started by software and an external trigger.

A/D Conversion Started by Software

To perform A/D conversion started by software, select the required channel from analog inputpins AN0 to AN9. Write "1" to the corresponding bit of the ADCH register to enable A/Dconversion.

Single channel

If only one channel is selected as the analog input pin for conversion, writing "1" to the STR bitof the ADCTH register starts software-started conversion and sets the BUSY bit of the ADCTLregister to "1".

Writing "1" to the STR bit again during conversion initializes the converter and restartsconversion.

After A/D conversion ends, the BUSY bit of the ADCTL register is reset to "0" and the INT bit ofthe ADCTL register is set to "1". These status bits can be read to determine whether conversionhas ended. To generate an interrupt to complete conversion, set the INTE bit of the ADCTLregister to "1" beforehand.

Multiple channels (scan conversion)

If multiple channels are selected as the analog input pins for conversion, the converter performsA/D conversion for the first selected channel and then stores the conversion result in theregister corresponding to the channel. The converter then repeats this process for the remainingselected channels.

Writing "1" to the corresponding bit of the ADCTH register to select the channel for conversionand writing "1" to the STR bit of the ADCTH register starts conversion and sets the BUSY bit ofthe ADCTL register to "1". The channels are converted sequentially from 0 to 9. If a channel isnot selected in the ADCTH register, the converter skips that channel and starts conversion forthe next selected channel.

Writing "1" to the STR bit again during conversion initializes the converter and restartsconversion for the selected channels in the order of 0 to 9.

When A/D conversion for all selected channels ends, the BUSY bit of the ADCTL register isreset to "0" and the INT bit of the ADCTL register is set to "1". To generate an interrupt tocomplete conversion, set the INTE bit of the ADCTL register to "1" beforehand.

The results of A/D conversion are stored in the registers of individual channels.

A/D Conversion Started by External Trigger

If external trigger start is enabled (ADCTH: TRG = 1), detection of a rising edge at external pinATRG starts A/D conversion. If the signal for A/D conversion by software is received when theexternal trigger is enabled, conversion is also started. If a rising edge is detected again atexternal pin ATRG during A/D conversion, the converter is initialized and conversion is restartedfrom the beginning.

334

CHAPTER 15 UART

This chapter describes the UART, the configuration and functions of registers, and UART operation.

15.1 Overview of the UART

15.2 UART Registers

15.5 Example of Using the UART

15.6 Example of Setting U-TIMER Baud Rates and Reload Values

335

CHAPTER 15 UART


The UART is a serial I/O port used to perform asynchronous (start-stop synchronization) communication or CLK synchronous communication. The UART has the features shown below. The MB91310 has five UART channels.

Features

The UART has the following features:

• Full-duplex double buffer

• Either asynchronous (start-stop synchronization) or CLK synchronous communication can beselected.

• Multiprocessor mode is supported.

• Fully programmable baud rate: An arbitrary baud rate can be set using a built-in timer. (See"CHAPTER 6 U-TIMER".)

• An external clock can be used to set a baud rate.

• Error detection functions (parity, framing, overrun)

• The transfer signal is an NRZ code.

• UARTs Ch.0 to Ch.2 can use an interrupt to start DMA transfer (UARTs Ch.3 and Ch.4cannot start DMA transfer).

• The DMAC interrupt source is cleared if the DRCL register is written to.

336


Block Diagram

Figure 15.1-1 is a block diagram of the UART.

Figure 15.1-1 Block Diagram of the UART

Receive clock

Receive interrupt(to CPU)

SCK (clock)

Send interrupt(to CPU)

Send clock

SO (send data)

Send shifter

Sendingstarts

SODR

Control signal

Clockselection

circuit

From U-TIMER

External clock SCK

SI (receive data)

Receive controlcircuit

Start bit detectioncircuit

Receive bitcounter

Receive paritycounter

Send controlcircuit

Send controlcircuit

Send bitcounter

Send paritycounter

Receive shifter

Receivingcompleted

SIDR

Receive status decision circuit

DMA receive error occurrence signal

(To DMC)

R-BUS

SMRregister

SCR register

SSR register

Control signal

MD1 MD0

CS0

PEN P SBL CL A/D REC RXE TXE

PE ORE FRE RDRF TDRE BDSRIE TIE

337

CHAPTER 15 UART

15.1.1 Pairing of Send and Receive Transfers in UART Macro

This section explains how send and receive transfers in a UART macro can be paired.

Table 15.1-1 shows parings of send and receive transfers in a UART macro.

"Mixed transfer" is a transfer that alternates between program transfer and DMA transfer.

× indicates the pair in which transfer using DMA is unavailable. If the DRCL register in this pair iscleared to perform the DMAC error processing or to switch between DMA transfer and programtransfer, the DMA request state machine in one of the pair will be cleared. Therefore, forexample, one unnecessary data is output for the UART/SIO send, and one unnecessary read isperformed in the serial input data register (SIDR) for the UART receive.

*: There are some restrictions. Please refer to " Notes on UART communication using DMA".

Notes on UART Communication Using DMA

If a UART receive error is caused under the following conditions, follow the procedures in Figure15.1-2 .

• When DMA transfer is used for UART receive and program transfer is used for UART send.

• When DMA transfer is used for UART receive and UART send is not used.

Table 15.1-1 Pairings of UART/SIO Send and Receive

UART/SIO send

DMA transfer

Program transfer

Mixed transfer

Not used

UART/SIO receive

DMA transfer × ×

Program transfer ×

Mixed transfer × × × ×

Not used ×

338



Figure 15.1-2 Example of UART Receive Error Processing Flow (when DMA Transfer is Used for UART Receive)

If the DSS register is other than X11B (DMAC receive is end with an error), write to the DRCLregister and perform dummy reading to the SIDR register. Dummy reading of SIDR register isnecessary to initialize the state machine of UART address decoder.

Dummy read from

STCR register

DMAC

DSS bit

=X11B ?

DMAC interrupt source clear

(Write to DRCL register)

END

Set UART

Set DMAC

(Receive set up)

UART receive error

processing flow

YES(DMA Normal End)

NO

339


CHAPTER 15 UART

15.2 UART Registers

This section describes the configuration and functions of the registers used by the UART.

Registers

Figure 15.2-1 shows the registers used by the UART.

Figure 15.2-1 UART Registers

15 8 7 0

SCR SMR (R/W)

SSR SIDR(R)/SODR(W) (R/W)

DRCL (W)

8bi t 8bi t

7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 0

D7 D6 D5 D4 D3 D2 D1 D0(SIDR /SODR)

PE ORE FRE RDRF TDRE BDS RIE TIE (SSR)

MD1 MD0 - - CS0 - - - (SMR)

PEN P SBL CL A/D REC RXE TXE (SCR)

- - - - - - - - (DRCL)

Serial status register

Serial mode register

Serial control register

Serial input registerSerial output register

bit

bit

bit

bit

bit

bit

340

15.2 UART Registers

15.2.1 Serial Mode Register (SMR)

The serial mode register (SMR) specifies the UART operating mode.Set an operating mode while operation is stopped. Do not write to this register while operation is in progress.

Serial Mode Register (SMR)

Figure 15.2-2 shows the bit configuration of the serial mode register (SMR).

Figure 15.2-2 Bit Configuration of the Serial Mode Register (SMR)

The SMR specifies the UART operating mode. Set the operating mode while operation isstopped. Do not write to this register during operation.

[bit7, bit6] MD1, MD0 (MoDe select)

These bits select a UART operating mode.

Table 15.2-1 shows the settings for the UART operating modes.

Note:

In Mode 1, which is CLK asynchronous mode (multiprocessor), more than one slave CPU canbe connected to one host CPU. Since this resource cannot identify the data format of receiveddata, however, only the master in multiprocessor mode is supported. Because the parity checkfunction cannot be used, set PEN of the SCR register to "0".


These bits are reserved. Always write "11B" to these bits.

[bit3] CS0 (Clock Select)

This bit selects the UART operating clock.

7 6 5 4 3 2 1 0 Initial value SMR

Address ch.0 000063H MD1 MD0 CS0 00--0---B

ch.1 00006BH ch.2 000073H

ch.3 00007BH

ch.4 000083H

R/W R/W W

bit

Table 15.2-1 Settings for UART Operating Modes

Mode MD1 MD0 Operating mode

0 0 0Asynchronous (start-stop synchronization) normal mode [initial value]

1 0 1Asynchronous (start-stop synchronization) multiprocessor mode

2 1 0 Clock synchronous mode

− 1 1 Setting disabled

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CHAPTER 15 UART

Table 15.2-2 shows the UART operating clocks.


These bits are reserved. Always write "00B" to these bits.

[bit0] (reserved)


Table 15.2-2 UART Operating Clocks

CS0 Operating clock

0 Built-in timer (U-TIMER) [initial value]

1 External clock

342

15.2 UART Registers

15.2.2 Serial Control Register (SCR)

The serial control register (SCR) controls the transfer protocol that is used for serial communication.This section describes the configuration and functions of the serial control register (SCR)

Serial Control Register (SCR)

The SCR controls the transfer protocol that is used for serial communication.

Figure 15.2-3 shows the bit configuration of the serial control register (SCR).

Figure 15.2-3 Bit Configuration of the Serial Control Register (SCR)

[bit7] PEN (Parity Enable)

This bit specifies whether to add parity in serial communication when data communication isperformed.

Table 15.2-3 shows the parity.

Note:

Parity can be added only in normal mode (Mode 0) of asynchronous (start-stopsynchronization) communication mode. No parity can be added in multiprocessor mode(Mode 1) or CLK synchronous communication mode (Mode 2).

Address: ch.0 000062H PEN P SBL CL A/D REC RXE TXE 00000100B


R/W R/W R/W R/W R/W W R/W R/W

SCR

ch.1 00006AHch.2 000072H

ch.3 00007AH

ch.4 000082H

bit

Table 15.2-3 Parity

PEN Function

0 No parity [initial value]

1 Parity

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CHAPTER 15 UART

[bit6] P (Parity)

This bit specifies that even or odd parity be added to perform data communication.

Table 15.2-4 shows whether the parity is even or odd.

[bit5] SBL (Stop Bit Length)

This bit specifies the number of stop bits, which marks the end of a frame in asynchronous(start-stop synchronization) communication.

Table 15.2-5 shows the stop bit length.

[bit4] CL (Character Length)

This bit specifies the data length of one frame that is sent or received.

Table 15.2-6 shows the data length of one frame.

Note:

7-bit data can be handled only in normal mode (Mode 0) of asynchronous (start-stopsynchronization) communication mode. Use 8-bit data in multiprocessor mode (Mode 1) orCLK synchronous communication mode (Mode 2).

[bit3] A/D (Address/Data)

This bit specifies the data format of a frame that is sent or received in multiprocessor mode(Mode 1) of asynchronous (start-stop synchronization) communication mode.

Table 15.2-7 shows the data format of a frame.

Table 15.2-4 Even or Odd Parity

P Parity

0 Even parity [initial value]

1 Odd parity

Table 15.2-5 Stop Bit Length

SBL Stop bit length

0 1 stop bit [initial value]

1 2 stop bits

Table 15.2-6 Data Length of One Frame

CL Data length of one frame

0 7 bits [initial value]

1 8 bits

Table 15.2-7 Data Format of Frame

A/D Data format of frame

0 Data frame [initial value]

1 Address frame

344

15.2 UART Registers

[bit2] REC (Receiver Error Clear)

Write "0" to this bit to clear the error flags (PE, ORE, and FRE) in the SSR register.

Writing "1" to this bit has no effect. "1" is always read from this bit.

[bit1] RXE (Receiver Enable)

This bit controls the UART receive operation.

Table 15.2-8 shows the UART receive operation.

Note:

If a receive operation is disabled while it is in progress (while data is being input to thereceive shift register), reception of the frame is completed. The receive operation is stoppedwhen the received data is stored in the receive data buffer register (SIDR).

[bit0] TXE (Transmitter Enable)

This bit controls the UART send operation.

Table 15.2-9 shows the UART send operation.

Note:

If a send operation is disabled while it is in progress (while data is being output from thetransmission register), sending is stopped when no more send data is stored in the senddata buffer register (SODR).

Table 15.2-8 UART Receive Operation

RXE Enabling or disabling the receive operation

0 Disables receive operation. [initial value]

1 Enables receive operation.

Table 15.2-9 UART Send Operation

TXE Enabling or disabling send operation

0 Disables send operation. [initial value]

1 Enables send operation.

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CHAPTER 15 UART

15.2.3 Serial Input Data Register (SIDR)/Serial Output Data Register (SODR)

These registers are data buffer registers for receiving and sending.

Serial Input Data Register (SIDR)/Serial Output Data Register (SODR)

Figure 15.2-4 shows the bit configurations of the serial input data register (SIDR) and the serialoutput data register (SODR).

Figure 15.2-4 Bit Configurations of the Serial Input Data Register (SIDR) and the Serial Output Data Register (SODR)

These registers are data buffer registers for sending and receiving.

If the data length is seven bits, bit7 (D7) of SIDR and SODR contains invalid data. AccessingSIDR and SODR when BDS = 1 switches the high-order and low-order data on the bus. As aresult, it appears that bit0 (D0) is ignored.

Write to the SODR register only while the TDRE bit of the SSR register is "1".

Note:

Writing to the register with this address means writing to the SODR register. Reading fromthe register with this address means reading from the SIDR register.

Address: ch.0 000061H D7 D6 D5 D4 D3 D2 D1 D0 Undefined


R R R R R R R R ch.1 000069Hch.2 000071Hch.3 000079Hch.4 000081H

Address: Same as above D7 D6 D5 D4 D3 D2 D1 D0 Undefined

7 6 5 4 3 2 1 0

W W W W W W W W

SIDR

SODR

bit

bit

346

15.2 UART Registers

15.2.4 Serial Status Register (SSR)

The serial status register (SSR) consists of flags that indicate the operation state of the UART.This section describes the configuration and functions of the serial status register (SSR).

Serial Status Register (SSR)

Figure 15.2-5 shows the bit configuration of the serial status register (SSR)

Figure 15.2-5 Bit Configuration of the Serial Status Register (SSR)

The SSR is configured from flags that indicate the operating status of the UART.

Address: ch.0 000060H PE ORE FRE RDRF TDRE BDS RIE TIE 00001000B


R R R R R R/W R/W R/Wch.1 000068Hch.2 000070Hch.3 000078Hch.4 000080H

SSR bit

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CHAPTER 15 UART

Functions of Bits in the Serial Status Register (SSR)

The following describes the functions of the serial status register (SSR) bits.

[bit7] PE (Parity Error)

This bit, which is an interrupt request flag, is set when a parity error occurs during reception.

To clear the flag when it has been set, write "0" to the REC bit (bit10) of the SCR register.

If the PE bit is set, the SIDR data becomes invalid.

Table 15.2-10 shows the parity error interrupt request flag.

[bit6] ORE (Over Run Error)

This bit, which is an interrupt request flag, is set when an overrun error occurs duringreception.

To clear the flag when it has been set, write "0" to the REC bit of the SCR register.

If the ORE bit is set, the SIDR data becomes invalid.

Table 15.2-11 shows the overrun error interrupt request flag.

[bit5] FRE (FRaming Error)

This bit, which is an interrupt request flag, is set when a framing error occurs duringreception.

To clear the flag when it has been set, write "0" to the REC bit of the SCR register.

If the FRE bit is set, the SIDR data becomes invalid.

Table 15.2-12 shows the framing error interrupt request flag.

Table 15.2-10 Parity Error Interrupt Request Flag

PE Occurrence of parity error

0 No parity error has occurred. [initial value]

1 A parity error has occurred.

Table 15.2-11 Overrun Error Interrupt Request Flag

ORE Occurrence of overrun error

0 No overrun error has occurred. [initial value]

1 An overrun error has occurred.

Table 15.2-12 Framing Error Interrupt Request Flag

FRE Occurrence of framing error

0 No framing error has occurred. [initial value]

1 A framing error has occurred.

348

15.2 UART Registers

Note:

Switch the internal and external baud rate clocks using bit3 of the serial mode register onlywhile the UART is stopped, since the switching takes effect immediately after writing.

Bit3 of the serial mode register is write only.

[bit4] RDRF (Receiver Data Register Full)

This bit, which is an interrupt request flag, indicates that the SIDR register has receive data.

This bit is set when receive data is loaded into the SIDR register. It is automatically clearedwhen the data is read from the SIDR register.

Table 15.2-13 shows the receive data interrupt request flag.

[bit3] TDRE (Transmitter Data Register Empty)

This bit, which is an interrupt request flag, indicates whether send data can be written toSODR.

This bit is cleared when send data is written to the SODR register. It is set again when thewritten data is loaded into the send shiftier and begins to be transferred, indicating that thenext send data can be written.

Table 15.2-14 shows the send data interrupt request flag.

[bit2] BDS (Bit Direction Select)

This bit selects the transfer direction.

Table 15.2-15 shows the transfer direction selection bit.

Note:

Because the high-order and low-order data are switched when the serial data register iswritten to or read, the data will become invalid if the bit is rewritten after data is written to theSODR register. If the SODR register and BDS are rewritten at the same time using halfwords(16 bits), data will be written to the SODR register based on the BDS value before rewriting.

Table 15.2-13 Receive Data Interrupt Request Flag

RDRF Presence of receive data

0 No receive data exists. [initial value]

1 Receive data exists.

Table 15.2-14 Send Data Interrupt Request Flag

TDRE Disabling or enabling writing of send data

0 Disables writing of send data.

1 Enables writing of send data. [initial value]

Table 15.2-15 Transfer Direction Selection Bit

BDS Transfer direction

0 Sends starting from the least significant bit (LSB). [initial value]

1 Sends starting from the most significant bit (MSB).

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CHAPTER 15 UART

[bit1] RIE (Receiver Interrupt Enable)

This bit controls a reception interrupt.

Table 15.2-16 shows the receive interrupt.

Note:

Receive interrupt sources include errors due to PE, ORE, and FRE as well as normal receivedue to RDRF.

[bit0] TIE (Transmitter Interrupt Enable)

This bit controls send interrupt.

Table 15.2-17 shows the send interrupt.

Note:

Send interrupt sources include send requests due to TDRE.

Table 15.2-16 Receive Interrupt

RIE Disabling or enabling receive interrupts

0 Disables receive interrupt. [initial value]

1 Enables receive interrupt.

Table 15.2-17 Send Interrupt

TIE Disabling or enabling send interrupts

0 Disables send interrupt. [initial value]

1 Enables send interrupt.

350

15.2 UART Registers

15.2.5 DRCL Register

The DRCL register clears a DMAC interrupt source.

DRCL Register

Figure 15.2-6 shows the configuration of the DRCL register.

Figure 15.2-6 Configuration of the DRCL Register

The DRCL register clears a DMAC interrupt source. Write an arbitrary value to the DRCLregister to clear a DMAC interrupt source. Always use byte access to access the DRCL register.

When an interrupt occurs, DMAC transfer terminates and the DMAC retains the DMAC sourceuntil the DMAC interrupt source is cleared.

Even if the various interrupt request flags are cleared by interrupt processing when the DMAC isnot activated, the DMAC interrupt source is retained as is.

If the DMAC interrupt source remains as is and DMAC activation is enabled with a UARTspecified for the DMAC activation source, the DMAC will be activated and unintended operationexecuted even if the interrupt request flags are not set.

Therefore, when the DMAC is activated for the first time and when the UART has already beenused using interrupts that do not activate the DMAC, use this register to clear the DMACinterrupt source. (This register is write-only.)


W

-- -- -- -- -- -- -- --

W W W W W W W

Address: ch.0 000066H ch.1 00006EH ch.2 000076H ch.1 00007EH ch.2 000086H

DRCL--------B

bit

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CHAPTER 15 UART

15.3 UART Operation

The UART has two operating modes: asynchronous (start-stop synchronization) mode and clock mode.Asynchronous (start-stop synchronization) mode consists of normal and multiprocessor mode.This section describes the operation of these operating modes.

Operating Modes

The UART has the operating modes shown in Table 15.3-1 . Set a value in the SMR and SCRregisters to switch mode.

Note:

The stop bit length in asynchronous (start-stop synchronization) mode can be specified onlyfor a send operation. The stop bit length is always one bit for a receive operation. Sinceoperation is possible only in the above modes, do not make any other setting.

Table 15.3-1 UART Operating Modes

Mode Parity Data length Operating mode Stop bit length

0Yes/No 7 Asynchronous (start-stop

synchronization)normal mode 1 bit

or2 bits

Yes/No 8

1 No 8+1Asynchronous (start-stop

synchronization)multiprocessor mode

2 No 8 Clock mode No

352

15.3 UART Operation

Selecting a Clock for the UART

Internal timer

If you select the U-TIMER by setting CS0 to "0", the baud rate is determined according to thereload value set for the U-TIMER. At this time, you can calculate the baud rate as follows:

Asynchronous (start-stop synchronization): φ/(8 x β)

CLK synchronous: φ/β

φ: Peripheral machine clock frequency

β: Cycle defined for the U-TIMER (2n+2 or 2n+3; n is the reload value.)

In asynchronous (start-stop synchronization) mode, data can be transferred in the range from-1% to +1% of the specified baud rate.

External clock

If you select an external clock by setting CS0 to "1", the baud rate is as follows (the frequency ofthe external clock is assumed to be f):

Asynchronous (start-stop synchronization): f/8

CLK synchronous: f

Note:

However, that the maximum value for f is 3.125 MHz.

Asynchronous (Start-stop Synchronization) Mode

When the UART is used in Operating Mode 0 (normal mode) or Operating Mode 1 (multiprocessormode), the asynchronous transfer method is used.

Transfer Data Format

UART handles only data in the NRZ (Non Return to Zero) format.

Figure 15.3-1 shows the data format.

Figure 15.3-1 Transfer Data Format (Modes 0 and 1)

As shown in Figure 15.3-1 , the transfer of data always starts with the start bit (L level data),continues as long as the data bit length specified in LSB First, and ends with a stop bit (H leveldata). If an external clock is selected, you always must input a clock.

The data length can be set to 7 bits or 8 bits in normal mode (Mode 0), but must be set to 8 bitsin multiprocessor mode (Mode 1). In multiprocessor mode, no parity can be added; instead, theA/D bit is always added.

SI,SO

0 1 0 1 1 0 0 1 0 1 1Start LSB MSB Stop (Mode 0)

A/D Stop (Mode 1)

Data that has been transferred is 01001101B.

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CHAPTER 15 UART

Receive Operation

If the RXE bit (bit1) of the SCR register is set to "1", a receive operation is always in progress.

If a start bit appears on the receive line, one-frame data is received according to the data formatspecified in the SCR register. If an error occurs before reception of one frame is completed, theerror flag is set and then the RDRF flag (bit4 of the SSR register) is set. If, at this time, the RIEbit (bit1) of the same SSR register is set to "1", a receive interrupt is generated for the CPU.Check the flags of the SSR register and read the SIDR register if normal reception has occurredor perform the necessary processing if an error has occurred.

The RDRF flag is cleared when the SIDR register is read.

Send Operation

If the TDRE flag (bit3) of the SSR register is set to "1", send data is written to the SODRregister. If, at this time, the TXE bit (bit0) of the SCR register is set to "1", transmission occurs.

The TDRE flag is set again when the data set in the SODR register is loaded into the send shiftregister and begins to be transferred, indicating that the next send data can be set. If, at thistime, the TIE bit (bit0) of the same SSR register is set to "1", a send interrupt requesting that thesend data be set in the SODR register is generated for the CPU.

The TDRE flag is cleared if data is set in the SODR register.

Clock Synchronous Mode

If the UART is used in Operating Mode 2, the clock synchronous transfer method is used.

Transfer Data Format

The UART handles only data in the NRZ (Non Return to Zero) format.

Figure 15.3-2 shows the relationship between send and receive clocks and data.

Figure 15.3-2 Transfer Data Format (Mode 2)

When the internal clock (U-TIMER) has been selected, a data receive synchronous clock isautomatically generated as soon as data is received. While an external clock has been selected,you must check that data exists in the send data buffer SODR register of the send side UART(TDRE flag is "0") and then supply an accurate clock for one byte. Before sending starts andafter it ends, be sure to set the mark level.

The data length is 8 bits only, and no parity can be added. Only overrun errors are detectedbecause there is no start or stop bit.

Writing to SODR

SCK

RXE, TXE

SI, SO

1 0 1 1 0 0 1 0

Data that has been transferred is 01001101B.

Mark

LSB MSB (Mode 2)

354

15.3 UART Operation

Initialization

The following shows the setting values of the control registers required to use CLK synchronousmode.

• SMR register

• MD1, MD0: 10

• CS0: Specifies the clock input.

• PFR (port function) register

• SCKE: Set to "1" for an internal timer and to "0" for an external clock.

• UART: Set to "1" for send and to "0" for receive only.

• SCR register

• PEN: 0

• P,SBL,A/D: These bits are meaningless.

• CL: 1

• REC: 0 (to initialize the register)

• RXE, TXE: At least one of the bits must be set to "1".

• SSR register

• RIE: Set to "1" to enable interrupts and to "0" to disables interrupts.

• TIE: 0

Start of Communication

Write to the SODR register to start communication.

If only reception is performed, dummy send data must be written to the SODR register.

End of Communication

Check for the end of communication by making sure that the RDRF flag of the SSR register haschanged to "1". Use the ORE bit of the SSR register to check that communication has beenperformed correctly.

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CHAPTER 15 UART

15.4 Occurrence of Interrupts and Timing for Setting Flags

The UART has five flags and two interrupt sources.The five flags are PE, ORE, FRE, RDRF, and TDRE. PE means parity error, ORE means overrun error, and FRE means framing error. These flags are set when an error occurs during reception and are then cleared when 0 is written to REC of the SCR register. RDRF is set when receive data is loaded into the SIDR register and then cleared when data is read from the SIDR register. Mode 1 does not provide a parity detection function. Mode 2 does not provide a parity detection function or a framing error function. TDRE is set when the SODR register is empty, and writing to it is enabled and then cleared when data is written to the SODR register.

Occurrence of Interrupts and Timing for Setting Flags

There are two interrupt sources, one for receiving and one for sending. During receiving, aninterrupt is requested due to PE, ORE, FRE, or RDRF. During sending, an interrupt is requesteddue to TDRE. The following shows the timing for setting the interrupt flags in each of thesemodes.

Receive operation in Mode 0

The PE, ORE, FRE, and RDRF flags are set when the last stop bit is detected after a receivetransfer is completed, causing an interrupt request to be generated for the CPU. The SIDR datais invalid while PE, ORE, and FRE are active.

Figure 15.4-1 shows the timing for setting ORE, FRE, and RDRF in Mode 0.

Figure 15.4-1 Timing for Setting ORE, FRE, and RDRF (Mode 0)

Receive operation in Mode 1

The ORE, FRE, and RDRF flags are set when the last stop bit is detected after a receivetransfer is completed, causing an interrupt request to be generated for the CPU. The dataindicating an address or the data in bit9 is invalid because the length of data that can bereceived is 8 bits. The SIDR data is invalid while ORE and FRE are active.

Figure 15.4-2 shows the timing for setting ORE, FRE, and RDRF in Mode 1.

Data

PE,ORE,FRE

RDRF

Receive interrupt

D6 D7 Stop

356

15.4 Occurrence of Interrupts and Timing for Setting Flags

Figure 15.4-2 Timing for Setting ORE, FRE, and RDRF (Mode 1)

Reception operation in Mode 2

The ORE and RDRF flags are set when the last data (D7) is set after the reception transfer iscompleted, generating an interrupt request to the CPU. The SIDR data is invalid while ORE isactive.

Figure 15.4-3 shows the timing of setting ORE and RDRF in Mode 2.

Figure 15.4-3 Timing of Setting ORE and RDRF (Mode 2)

Send operation in modes 0, 1, and 2

TDRE is cleared when data is written to the SODR register. This bit is set when data istransferred to the internal shift register and the next data can be written, causing an interruptrequest to be generated for the CPU. If 0 is written to TXE of the SCR register (as well as RXEin mode 2) during a send operation, TDRE of the SSR register is set to 1, disabling the UARTsend operation after the transmission shiftier stops. The device sends data written to the SODRregister before transmission stops after 0 is written to the TXE of the SCR register (as well asRXE in mode 2) during the send operation.

Figure 15.4-4 shows the timing for setting TDRE in Modes 0 and 1. Figure 15.4-5 shows thetiming for setting TDRE in Mode 2.

Data

ORE,FRE

RDRF

Receive interrupt

D6 Address/Data Stop

Data

ORE

RDRF

Receive interrupt

D5 D6 D7

357

CHAPTER 15 UART

Figure 15.4-4 Timing for Setting TDRE (Modes 0 and 1)

Figure 15.4-5 Timing for Setting TDRE (Mode 2)

Precautions on Usage

Writing to the SODR register starts communication. Even for receive only, dummy send datamust be written to the SODR register.

Set the operating mode while operation is stopped. Data send and received while the operatingmode is being set is unpredictable.

Write to the DRCL register before starting DMA transfer due to an interrupt for the first time.

Writing to SODR

TDRE

SO interrupt

SO output

Interrupt request to CPU

ST: Start bit, D0 to D7: Data bitsSP: Stop bit, A/D: Address/data multiplexer

ST D0 D1 D2 D3 D4 D5 D6 D7 SP SP ST D0 D1 D2 D3A/D

Writing to SODR

TDRE

SO interrupt

SO output

Interrupt request to CPU

D0 to D7: Data bits

D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7

358



This section provides an example of using the UART. Mode 1 is used if more than one slave CPU is connected to a single host CPU.

Example of Using the UART

Figure 15.5-1 shows an example of constructing a system using mode 1. This resourcesupports only a communications interface on the host.

Figure 15.5-1 Example of Constructing a System Using Mode 1

Communication starts when the host CPU transfers address data. Address data is data usedwhen A/D bit of the SCR register is set to "1". This data is used to select a destination slaveCPU, enabling communication with the host CPU. Normal data is data used when A/D bit of theSCR register is set to "0". Figure 15.5-2 shows the flowchart.

In this mode, set the PEN bit of the SCR register to "0", since the parity check function cannotbe used.

SO

SI

Host CPU

SO SI SO SI

Slave CPU #0 Slave CPU #1

359

CHAPTER 15 UART

Figure 15.5-2 Communication Flowchart in Mode 1

(Host CPU)

START

Set transfer mode to 1.

Set “0” in A/D.

Enable receive operation.

Communicate with a slave CPU.

NO

NO

YES

YES

END

Set data used to select slave CPUs in D0 to

D7, set “1” in A/D, and transfer one byte.

Communicationcompleted?

Communicate withother slave

CPUs?

Disable the receive operation.

360



This section provides an example of setting U-TIMER baud rates and reload values.

Example of Setting U-TIMER Baud Rates and Reload Values

Table 15.6-1 shows setting values to be used in asynchronous (start-stop synchronization)mode. Table 15.6-2 shows setting values to be used in CLK synchronous mode.

A frequency in the tables represents a peripheral machine clock frequency. UCC1 is a value tobe set in the UCC1 bit of the UTIMC register of the U-TIMER.

The U-Timer reload value is displayed as a decimal value.

Table 15.6-1 Setting Values in Asynchronous (Start-Stop Synchronization) Mode

Baud rate (bps) ms φ=20.27MHz φ=10.135MHz

1200 833.33 527 (UCC1=0) 263 (UCC1=0)

2400 416.67 263 (UCC1=0) 131 (UCC1=0)

4800 208.33 131 (UCC1=0) 65 (UCC1=0)

9600 104.17 65 (UCC1=0) 32 (UCC1=0)

19200 52.08 32 (UCC1=0) 15 (UCC1=1)

38400 26.04 15 (UCC1=1) 7 (UCC1=1) *

57600 17.36 10 (UCC1=0) 4 (UCC1=1)

115200 8.681 4 (UCC1=1) 2 (UCC1=0) *

- - - -

10400 96.15 60 (UCC1=0) 29 (UCC1=1)

31250 32.00 19 (UCC1=0) * 9 (UCC1=0) *

62500 16.00 9 (UCC1=0) * 4 (UCC1=0) *

φ : Peripheral machine clock frequency* : An error exceeding plus minus 1% occurs.

Table 15.6-2 Setting Values in CLK Synchronous Mode

Baud rate (bps) ms φ=20.27MHz φ=10.135MHz

250K 4.00 39 (UCC1=1) 19 (UCC1=1) *

500K 2.00 19 (UCC1=1) * 9 (UCC1=0) *

1M 1.00 9 (UCC1=0) * 4 (UCC1=0) *

* : An error exceeding plus minus 1% occurs.

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CHAPTER 15 UART

362


This chapter describes the I2C interface, the configuration and functions of registers,

and I2C interface operation.

16.1 Overview of the I2C Interface

16.2 I2C Interface Registers

16.3 I2C Interface Operation

16.4 Operation Flowcharts

363



The I2C interface is a serial I/O port that supports Inter IC BUS.

Features

The I2C interface serves as a master or slave device on the I2C bus and has the followingfeatures:

• Master or slave sending and receiving

• Arbitration function

• Clock synchronization function

• Slave address and general call address detection function

• Transfer direction detection function

• Function that generates and detects a repeated START condition

• Bus error detection function

• 10-bit and 7-bit slave addresses

• Slave address reception acknowledge control in master mode

• Compound slave addresses available

• Interrupt enabled for a transmission or bus error

• Standard mode (maximum of 100 Kbps) and high-speed mode (maximum of 400 Kbps at themaximum) available

364


Block Diagram

Figure 16.1-1 is a block diagram of the I2C interface.

Figure 16.1-1 Block Diagram of the I2C Interface

ICCR CS4 CS3 CS2 CS1 CS0

I BSR BB

RSC

LRB

TRX

ADT

AL

IBCR

SCC

IBCR

INT INTE

BEIE

BER

GCAA

ACK

MSS

2 3 4 5 32

Sync

IRQ

IBSR

AAS

GCA

ITBA

IDAR

SCL0toSCL3

SDA0toSDA3

ITMK ISBA ISMK

ENTB RAL

FNSB

DBL IDBL

ICCR EN

CLKP

ISMK

ITMK

SCL4

SDA4

SD

A3

SC

L3

Register

Clock enable

Clock selection 2 (1/12)

Clock division 2

Shift clock generation

Shift clock edge change timing

I2C operation enable

I2C input/output

I2C input/output

R b

us

Bus busy

Repeat start

Last Bit

Send/receive

First Byte

Error

Start-stop condition detection

Arbitration lost detection

Interrupt request

End

GC-ACK enable

ACK enable

Master

Start

Start-stop conditiongeneration

Slave addresscomparisonGlobal call

Slave

365



This section describes the configuration and functions of registers used by the I2C interface.

I2C Interface Registers

Figure 16.2-1 shows the registers used by the I2C interface.

Bus control register (IBCR)

Figure 16.2-1 I2C Interface Registers (Continued on Next Page)

Bus status register (IBSR)

10-bit slave address register (ITBA)

15 14 13 12 11 10 9 8Address: BER BEIE SCC MSS ACK GCAA INTE INT

R/W R/W W R/W R/W R/W R/W R/W

0 0 0 0 0 0 0 0Initial value

ch.0 0000B4H

ch.1 0000C4H

ch.2 0000D4H

ch.3 0000E4H

bit

7 6 5 4 3 2 1 0

BB RSC AL LRB TRX AAS GCA ADT

R R R R R R R R

0 0 0 0 0 0 0 0

Address:

Initial value

ch.0 0000B5H

ch.1 0000C5H

ch.2 0000D5H

ch.3 0000E5H

bit

15 14 13 12 11 10 9 8TA9 TA8

R/W R/W

0 0

7 6 5 4 3 2 1 0TA7 TA6 TA5 TA4 TA3 TA2 TA1 TA0

R/W R/W R/W R/W R/W R/W

R R R R R R

R/W R/W

0 0 0 0 0 0

0 0 0 0 0 0

0 0

Address:

Initial value

Initial value

ch.0 0000B6H

ch.1 0000C6H

ch.2 0000D6H

ch.3 0000E6H

bit

bit

366


10-bit slave address mask register (ITMK)

7-bit slave address register (ISBA)

7-bit slave address mask register (ISMK)

Data register (IDAR)

15 14 13 12 11 10 9 8ENTB RAL TM9 TM8

R/W R R/W R/W

0 0

R

1

R

1

R

1

R

1 1 1

7 6 5 4 3 2 1 0TM7 TM6 TM5 TM4 TM3 TM2 TM1 TM0R/W R/W R/W R/W R/W R/W R/W R/W

1 1 1 1 1 1 1 1

Address:

Initial value

Initial value

ch.0 0000B8H

ch.1 0000C8H

ch.2 0000D8H

ch.3 0000E8H

bit

bit

7 6 5 4 3 2 1 0SA6 SA5 SA4 SA3 SA2 SA1 SA0R/WR R/W R/W R/W R/W R/W R/W00 0 0 0 0 0 0

Address:

Initial value

ch.0 0000BBH

ch.1 0000CBH

ch.2 0000DBH

ch.3 0000EBH

bit

15 14 13 12 11 10 9 8ENSB SM6 SM5 SM4 SM3 SM2 SM1 SM0R/W R/W R/W R/W R/W R/W R/W R/W0 1 1 1 1 1 1 1

Address:

Initial value

ch.0 0000BAH

ch.1 0000CAH

ch.2 0000DAH

ch.3 0000EAH

bit

7 6 5 4 3 2 1 0D7 D6 D5 D4 D3 D2 D1 D0R/W R/W R/W R/W R/W R/W R/W R/W0 0 0 0 0 0 0 0

Address:

Initial value

ch.0 0000BDH

ch.1 0000CDH

ch.2 0000DDH

ch.3 0000EDH

bit

367


Clock control register (ICCR)

Clock disable register (IDBL)

15 14 13 12 11 10 9 8TEST EN CS4 CS3 CS2 CS1 CS0

W R/W R/W R/W R/W R/W R/W0

R0 0 1 1 1 1 1

Address:

Initial value

ch.0 0000BEH

ch.1 0000CEH

ch.2 0000DEH

ch.3 0000EEH

bit

7 6 5 4 3 2 1 0

DBLR/W

0R0

R0

R0

R0

R0

R0

R0

Address:

Initial value

ch.0 0000BFH

ch.1 0000CFH

ch.2 0000DFH

ch.3 0000EFH

bit

368


16.2.1 Bus Status Register (IBSR)

The bus status register (IBSR) indicates the status of the I2C interface.This register is read-only.

Bus Status Register (IBSR)

Figure 16.2-2 shows the bit configuration of the bus status register (IBSR).

Figure 16.2-2 Bit Configuration of the Bus Status Register (IBSR)

This register is read-only for all bits. All bits are cleared when I2C interface operation is stopped(ICCR:EN = 0).

[bit7] BB (Bus Busy)

This bit indicates the status of the I2C bus.

[bit6] RSC (Repeated Start Condition)

This bit is the repeated START detection bit.

This bit is cleared when the address data transfer ends (ADT=0) or when the STOP condition isdetected.

[bit5] AL (Arbitration Lost)

This bit is the arbitration lost detection bit.

Write "0" to the INT bit or "1" to the MSS bit of the IBCR register to clear this bit.

Arbitration loss is detected if:

• The transmission data does not match the data on the SDA line at the rising edge of SCL.

• A repeated START condition is generated in the first bit of the data by another master.

• The I2C interface cannot generate a START or STOP condition because the SCL line is

7 6 5 4 3 2 1 0BB RSC AL LRB TRX AAS GCA ADTR R R R R R R R0 0 0 0 0 0 0 0

Address:

Initial value

ch.0 0000B5H

ch.1 0000C5H

ch.2 0000D5H

ch.3 0000E5H

bit

0 STOP condition detected

1 START condition detected (bus used)

0 Repeated START condition not detected

1 Repeated START condition detected while bus is being used

0 Arbitration lost not detected

1 Arbitration lost detected during master transmission

369


driven to "L" by another slave device.

[bit4] LRB (Last Received Bit)

This bit is an acknowledge storage bit that stores an acknowledge from the receiving device.

This bit is ten if an acknowledge is detected (reception 9 bits). This bit is cleared if a START orSTOP condition is detected.

[bit3] TRX (Transferring Data)

This bit indicates the transmission status during a data transfer.

This bit is set to "1" if:

• A START condition occurs in master mode.

• Transfer of the first byte ends during read access (transmission) in slave mode.

• Data is being sent in master mode.


• The bus is idle (IBCR:BB=0).

• An arbitration loss occurs.

• "1" is written to the SCC bit in the mask interrupt status (MSS=1, INT=1).

• The MSS bit is cleared in the mask interrupt status (MSS=1, INT=1).

• No acknowledge occurred for the last transfer byte in slave.

• Data is received in slave mode.

• Data is received from a slave in master mode.

[bit2] AAS (Addressed As Slave)

This bit is the slave addressing detection bit.

This bit is cleared when a (repeated) START or STOP condition is detected.

This bit is set when a 7-bit or 10-bit slave address is detected.

[bit1] GCA (General Call Address)

This bit is the general call address (00H) detection bit.

0 Slave acknowledge detected

1 Slave acknowledge not detected

0 Data transmission stopped

1 Data transmission in progress

0 The interface is not specified as a slave.

1 The interface is specified as a slave.

0 General call address is not received as a slave.

1 General call address is received as a slave.

370


This bit is cleared when a (repeated) START or STOP condition is detected.

[bit0] ADT (Address Data Transfer)

This bit is the slave address reception detection bit.

This bit is set to "1" if a START condition is detected. It is cleared after the second byte if theheader section of a slave address is detected during 10-bit write access. Otherwise, it is clearedafter the first byte.

"After the first or second byte" means the following:

• Writing "0" to the MSS bit during master interrupt (MSS=1, INT=1)

• Writing "1" to the SCC bit during master interrupt (MSS=1, INT=1)

• Clearing the INT bit

• Beginning of a transfer byte that is not used for the transfer destination as master or slave

0 Received data is not a slave address (or the bus is idle).

1 Received data is a slave address.

371


16.2.2 Bus Control Register (IBCR)

This section describes the configuration and functions of the bus control register (IBCR).

Bus Control Register (IBCR)

Figure 16.2-3 shows the bit configuration of the bus control register (IBCR).

Figure 16.2-3 Bit Configuration of the Bus Control Register (IBCR)

Bits other than BER and BEIE are cleared if the I2C interface is stopped (ICCR:EN=0).

[bit15] BER (Bus ERror)

This bit is the bus error interrupt request flag bit.

For a read by a read modify instruction, "1" is always read.

During writing

During reading

If this bit is set, the EN bit of the ICCR register is cleared, the I2C interface is stopped, and datatransfer is halted. All bits of the IBSR and IBCR registers except BER and BEIE are cleared.

Clear this bit before the I2C interface is enabled (EN = 1) again.


• An illegal START or STOP condition at a specific location is detected (while an slave

address or data is being transferred). *1

• The header section of a slave address is received during a 10-bit read access before 10-bit

write access with the first byte is performed. *1

• A STOP condition is detected during transfer in master mode.

*1: When the I2C interface is enabled during transfer, this detection flag is set after the firstSTOP condition is received to prevent an incorrect bus error report from being issued.

15 14 13 12 11 10 9 8BER BEIE SCC MSS ACK GCAA INTE INTR/W R/W W R/W R/W R/W R/W R/W0 0 0 0 0 0 0 0

Address:

Initial value

ch.0 0000B4H

ch.1 0000C4H

ch.2 0000D4H

ch.3 0000E4H

bit

0 Clears the bus error interrupt request flag.

1 Has no meaning.

0 Bus error not detected

1 Error condition detected

372


[bit14] BEIE (Bus Error Interrupt Enable)

This bit is the bus error interrupt enable bit.

An interrupt occurs if this bit is set to "1" and the BER bit is set to "1".

[bit13] SCC (Start Condition Continue)

This bit is the repeated [START] condition generation bit.

During writing


If "1" is written to this bit in master mode (MSS = 1, INT = 1), a repeated START condition isgenerated and the INT bit is automatically cleared.

[bit12] MSS (Master Slave Select)

This bit is the master or slave selection bit.

This bit is cleared when arbitration lost occurs during master transmission, causing slave modeto start.

Write "0" to this bit during a master interrupt (MSS=1, INT=1) to automatically clear the INT bit.Then, generate a [STOP] condition to end the transfer.

Note:

The MSS bit functions as a direct reset. To detect a STOP condition, check the BB bit of theIBSR register.

If "1" is written to this bit while the bus is idle (MSS = 0, BB = 0), a START condition isgenerated and the value of IDAR is sent.

If "1" is written to this bit while the bus is busy (BB = 1, TRX = 0, MSS = 0), the I2C interface

starts transmission when the bus becomes idle. If the I2C interface is specified as theaddress for a slave that is accompanied by a write access during this time, the bus becomesidle after the transfer ends. If the interface is transmitting as a slave (IBCR:AAS = 1, TRX =1) during this time, no data is sent even if the bus has become idle. It is important to check

whether the I2C interface is specified as a slave (IBSR:AAS = 1), and whether datatransmission has ended normally (IBCR:MSS = 1) at the next interrupt or otherwise datatransmission has failed with an error (IBSR:AL = 1).

0 Bus error interrupt disabled

1 Bus error interrupt enabled

0 Has no meaning.

1 Generates a repeated START condition in master transfer.

0 Selects slave mode.

1Selects master mode. Generates a START condition to enable the value of the IDAR register to be sent as a slave address.

373


[bit11] ACK (ACKnowledge)

This bit generates an acknowledge according to the setting of the data receive enable bit.

This bit is disabled when a slave address is received in slave mode. When the I2C interfacedetects a 7-bit or 10-bit slave address specification, an acknowledge is returned if thecorresponding enable bits ( ITMK:ENTB, ISMK:ENSB ) are set.

Write to this bit while an interrupt flag is set (INT = 1), the bus is idle (IBSR:BB = 0), or the I2Cinterface is stopped (ICCR:EN = 0).

[bit10] GCAA (General Call Address Acknowledge)

This bit is an acknowledge enable bit used when a general call address is received.

Write to this bit while an interrupt flag is set (INT = 1), the bus is idle (IBSR:BB = 0), or the I2Cinterface is stopped (ICCR:EN = 0).

[bit9] INTE (INTerrupt Enable)

This bit is the interrupt enable bit.

[bit8] INT (INTerrupt)

This bit is the transfer end interrupt request flag bit. For a read by a read modify instruction,"1" is read.

During writing

During reading

0 Acknowledge not generated when data is received

1 Acknowledge generated when data is received

0 Acknowledge not generated when general call address is received

1 Acknowledge generated when general call address is received

0 Interrupts disabled

1 Interrupts enabled

0 Clears the transfer end interrupt request flag.

1 Has no meaning.

0 Transfer not ended, not the transfer target, or bus is idle.

1

This bit is set to "1" if a one-byte transfer that includes the acknowledge bit is completed and the following conditions are met:• Bus master• The interface was specified as a slave address.• A general call address was received.• Arbitration lost occurred.If the interface is specified as a slave address, this bit is set at the end of slave address reception that includes an acknowledge.

374


If this bit is set to "1", the SCL line is maintained at the "L" level. Write "0" to this bit to clear itand to open the SCL line to transfer the next byte. In master mode, a repeated START or STOPcondition is generated.

This bit is cleared when the SCC bit is set to "1" or the MSS bit is cleared.

Notes:

• Contention of SCC, MSS, and INT bits

If data is simultaneously written to the SCC, MSS, and INT bits, contention occurs betweenthe next-byte transfer, repeated START condition generation, and STOP conditiongeneration. If this situation occurs, the priorities are as follows:

1. Next-byte transfer and STOP condition generation

When the INT bit is set to "0" and the MSS bit is set to "0", writing of the MSS bit hasprecedence and a STOP condition is generated.

2. Next-byte transfer and START condition generation

When "0" is written to the INT bit and "1" is written to the SCC bit, writing to the SCC bithas precedence, a repeated START condition is generated, and the value of IDAR issent.

3. Repeated START condition generation and STOP condition generation

When the SCC bit is set to "1" and the MSS bit is set to "1" at the same time, clearing of

the MSS bit has precedence. A STOP condition is generated and the I2C interface entersslave mode.

375


16.2.3 Clock Control Register (ICCR)

This section describes the configuration and functions of the clock control register (ICCR).

Clock Control Register (ICCR)

Figure 16.2-4 shows the bit configuration of the clock control register (ICCR).

Figure 16.2-4 Bit Configuration of the Clock Control Register (ICCR)

[bit15] Test bit

This bit is used for testing.

Be sure to write "0" to it.

[bit14] Reserved bit


Be sure to write "0" to it.

[bit13] EN (ENable)

This bit is the enable bit for the I2C interface.

If this bit is set to "0", all bits of the IBSR and IBCR registers (except the BER and BEIE bits) arecleared. This bit is cleared when a bus error occurs (IBCR:BER = 1).

Note:

If this bit is set to "0" (disabled), the I2C interface immediately stops sending and receiving.

bit 15 14 13 12 11 10 9 8TEST EN CS4 CS3 CS2 CS1 CS0

W R/W R/W R/W R/W R/W R/W0 0

R0 1 1 1 1 1

Address:

Initial value

ch.0 0000BEH

ch.1 0000CEH

ch.2 0000DEH

ch.3 0000EEH

0 Disabled

1 Enabled

376


[bit12 to bit8] CS4 to CS0(Clock Period Select 4-0)

These bits set the frequency of the serial clock.

These bits can be written only when the I2C interface is disabled (EN = 0) or the EN bit iscleared.

The frequency of the shift clock, fsck, is set as shown below.

Table 16.2-1 shows the serial clock frequency settings.

fsck= n 12+16

N > φ : Peripheral machine clock (= CLKP)φ

Table 16.2-1 Serial Clock Frequency Settings

n CS4 CS3 CS2 CS1 CS0

1 0 0 0 0 1

2 0 0 0 1 0

3 0 0 0 1 1

... ... ... ... ... ...

31 1 1 1 1 1

Setting disabled for CS4 to CS0=00000

Clock frequencyCLKP [MHz]

100KB 400KB

n fsck n fsck

20.2 16 97.5 3 389.8

13.5 10 99.4 2 337.8

10.1 7 101.4 1 362.0

6.76 4 105.6 1 241.3

5.79 4 90.5 1 206.8

5.07 3 97.5 1 181.0

377


16.2.4 10-bit Slave Address Register (ITBA)

This section describes the configuration and functions of the 10-bit slave address register (ITBA).

10-bit Slave Address Register (ITBA)

Figure 16.2-5 shows the bit configuration of the 10-bit slave address register (ITBA).

Figure 16.2-5 Bit Configuration of the 10-bit Slave Address Register (ITBA)

Rewrite this register while operation is disabled (ICCR:EN=0).


The values read from these bits are 0s.

[bit9 to bit0] 10-bit slave address bits (A9 to A0)

If a 10-bit address is enabled (ITMK:ENTB = 1) when slave address data is received in slavemode, these bits of ITBA and the received address data are compared.

An acknowledge is sent to the master after the address header of a 10-bit write access isreceived.

Received data in the first and second bytes and the ITBA register are compared. When amatch is detected, an acknowledge signal is sent to the master device and the AAS bit is set.

The I2C interface responds to reception of the address header of a 10-bit read access after arepeated START condition is generated.

All bits of a slave address are masked according to the ITMK setting. The received slaveaddress is overwritten to the ITBA register. This register is enabled only when the AAS bit(IBSR register) is set to "1".

15 14 13 12 11 10 9 8TA9 TA8R/W R/W0 0

7 6 5 4 3 2 1 0TA7 TA6 TA5 TA4 TA3 TA2 TA1 TA0R/W R/W R/W R/W R/W R/W R/W R/W0 0 0 0 0 0

R R R R R R0 0 0 0 0 0

0 0

Address:

Initial value

Initial value

ch.0 0000B6H

ch.1 0000C6H

ch.2 0000D6H

ch.3 0000E6H

ITBAH

ITBAL

bit

bit

378


16.2.5 10-bit Slave Address Mask Register (ITMK)

This section describes the configuration and functions of the 10-bit slave address mask register (ITMK).

10-bit Slave Address Mask Register (ITMK)

Figure 16.2-6 shows the bit configuration of the 10-bit slave address mask register (ITMK).

Figure 16.2-6 Bit Configuration of the 10-bit Slave Address Mask Register (ITMK)

[bit15] ENTB (10-bit slave address enable bit)

This bit is the 10-bit slave address enable bit.

Write to this bit while the I2C interface is stopped (ICCR:EN = 0).

[bit14] RAL (Slave address length bit)

This bit indicates the slave address length.

If the 10-bit and 7-bit slave address enable bits are both enabled (ENTB =1 and ENSB = 1), thisbit can be used to determine whether the transfer length of a 10-bit or 7-bit slave addressbecomes valid.

This bit is valid when the AAS bit (IBSR) is set to "1".

This bit is cleared when the interface is disabled (ICCR:EN = 0).

This bit is read only.


These bits are reserved. The values read from these bits are always 1s.

15 14 13 12 11 10 9 8ENTB RAL TM9 TM8

RR/W R/W R/W0 0

RR1 1

RR1 1 1 1

7 6 5 4 3 2 1 0TM7 TM6 TM5 TM4 TM3 TM2 TM1 TM0R/W R/W R/W R/W R/W R/W R/W R/W1 1 1 1 1 1 1 1

Address:

Initial value

Initial value

ch.0 0000B8H

ch.1 0000C8H

ch.2 0000D8H

ch.3 0000E8H

bit

bit

0 10-bit slave address disabled

1 10-bit slave address enabled

0 7-bit slave address

1 10-bit slave address

379


[bit9 to bit0] 10-bit slave address mask bits

These bits mask the bits of the 10-bit slave address register (ITBA). Write to this register

when the I2C interface is disabled (ICCR:EN = 0).

Setting this bit enables transmission of an acknowledge to a compound 10-bit slave address.When using this register for comparison of 10-bit slave addresses, set this bit to "1". Thereceived slave address is overwritten to ITBA. When ASS = 1 (IBSR), the specified slaveaddress can be determined by reading the ITBA register.

Each of TM9 to TM0 of ITMK corresponds to one bit of the ITBA address. If the value of each ofthe TM9 to TM0 bits is "1", the ITBA address becomes valid; if it is "0", the ITBA addressbecomes invalid.

Example: ITBA address is 0010010111B and ITMK address is 1111111100B:

The slave address is in the space from 0010010100B to 0010010111B.

0 This bit not used for comparison of slave addresses

1 This bit used for comparison of slave addresses

380


16.2.6 7-bit Slave Address Register (ISBA)

This section describes the configuration and functions of the 7-bit slave address register (ISBA).

7-bit Slave Address Register (ISBA)

Figure 16.2-7 shows the bit configuration of the 7-bit slave address register (ISBA).

Figure 16.2-7 Bit Configuration of the 7-bit Slave Address Register (ISBA)

Rewrite this register while operation is stopped (ICCR:EN = 0).

[bit7] Reserved bit


The value read from this bit is "0".

[bit6 to bit0] Slave address bits SA6 to SA0

If a 7-bit slave address is enabled (ISMK:ENSB = 1) when slave address data is received inslave mode, these bits of ISBA and the received slave address data are compared. If a slaveaddress match is detected, an acknowledge is sent to the master and the AAS bit is set.

The I2C interface returns an acknowledge in response to reception of the address header ofa 7-bit read access after a repeated START condition is generated.

All bits of a slave address are masked using the setting of the ISMK. The received slaveaddress data is overwritten to the ISBA register. This register is enabled only when AAS(IBSR register) is set to "1".

The I2C interface does not compare ISBA and the received slave address when a 10-bitslave address is specified or a general call is received.

7 6 5 4 3 2 1 0SA6 SA5 SA4 SA3 SA2 SA1 SA0R/WR R/W R/W R/W R/W R/W R/W00 0 0 0 0 0 0

Address:

Initial value

ch.0 0000BBH

ch.1 0000CBH

ch.2 0000DBH

ch.3 0000EBH

bit

381


16.2.7 7-bit Slave Address Mask Register (ISMK)

This section describes the configuration and functions of the 7-bit slave address mask register (ISMK).

7-bit Slave Address Mask Register (ISMK)

Figure 16.2-8 shows the bit configuration of the 7-bit slave address mask register (ISMK).

Figure 16.2-8 7-bit Slave Address Mask Register (ISMK)

Rewrite this register while operation is stopped (ICCR:EN=0).

[bit15] ENSB (7-bit slave address enable bit)

This bit is the 7-bit slave address enable bit.

[bit14 to bit8] 7-bit slave address mask bits

These bits mask the bits of the 7-bit slave address register (ISBA).

Setting this bit enables transmission of an acknowledge to a compound 7-bit slave address.When using this register for comparison of a 7-bit slave address, set this bit to "1". The receivedslave address is overwritten to ISBA. When ASS = 1 (IBSR), the specified slave address can bedetermined by reading the ISBA register.

After the I2C interface is enabled, the slave address (ISBA) is rewritten by reception operation.When ISMK is rewritten, ISMK must be set again to provide the expected operation.

Each of the SM6 to SM0 bits of ISMK corresponds to one bit of the ISBA address. If the value ofeach of the SM6 to SM0 bit is "1", the ISBA address becomes valid; if it is "0", the ISBA addressbecomes invalid.

Example: If ISBA address is 0010111B and ISMK address is 1111100B:

The slave address is in the space from 0010100B to 0010111B.

15 14 13 12 11 10 9 8ENSB SM6 SM5 SM4 SM3 SM2 SM1 SM0

R/W R/W R/W R/W R/W R/W R/W R/W0 1 1 1 1 1 1 1

Address:

Initial value

ch.0 0000BAH

ch.1 0000CAH

ch.2 0000DAH

ch.3 0000EAH

bit

0 7-bit slave address disabled

1 7-bit slave address enabled

0 This bit not used for comparison of slave addresses

1 This bit used for comparison of slave addresses

382


16.2.8 Data Register (IDAR)

This section describes the configuration and functions of the data register (IDAR).

Data Register (IDAR)

Figure 16.2-9 shows the bit configuration of the data register (IDAR).

Figure 16.2-9 Data Register (IDAR)

[bit7 to bit0] Data bits D7 to D0

Bits D7 to D0 are a data register used for serial transfer. Data is transferred from the MSB.

The writing side of this register has a double buffer. While the bus is busy (BB = 1), writedata is loaded into the register for serial transfer. When the INT bit (IBCR) is cleared or thebus is idle (IBSR:BB = 0), transfer data is loaded into the internal transfer register.

Since data is directly read from the register for serial transfer during reading, receive data inthis register is valid only while the INT bit (IBCR) is set.

7 6 5 4 3 2 1 0D7 D6 D5 D4 D3 D2 D1 D0R/W R/W R/W R/W R/W R/W R/W R/W0 0 0 0 0 0 0 0

Address:

Initial value

ch.0 0000BDH

ch.1 0000CDH

ch.2 0000DDH

ch.3 0000EDH

bit

383


16.2.9 Clock Disable Register (IDBL)

This section describes the configuration and functions of the clock disable register (IDBL).

Clock Disable Register (IDBL)

Figure 16.2-10 shows the bit configuration of the clock disable register (IDBL).

Figure 16.2-10 Clock Disable Register (IDBL)

[bit0] Clock disable bit (DBL)

This bit specifies whether to supply or stop supply of the operating clock for the I2C interface.

This bit can be used in low-power mode.

This bit is initialized to "0" at reset.

When "1" is written to this bit, the values read from other registers become undefined exceptthe values read from this register (IDBL). Writing to other than this bit (this register) becomesineffective.

Note:

When this bit is set to "1", I2C immediately stops even if send and receive operation is inprogress.

7 6 5 4 3 2 1 0DBLR/W0

R0

R0

R0

R0

R0

R0

R0

Address:

Initial value

ch.0 0000BFH

ch.1 0000CFH

ch.2 0000DFH

ch.3 0000EFH

bit

0 Supplies the clock for I2C.

1 Stops supply of the clock for I2C. The I2C line is opened.

384



The I2C bus consists of two bidirectional bus lines used for transfer: one serial data

line (SDA) and one serial clock line (SCL). The I2C interface has two corresponding open-drain I/O pins (SDA and SCL), enabling wired logic.

START Condition

Write "1" to the MSS bit while the bus is open (BB=0, MSS=0) to place the I2C interface inmaster mode and to generate a START condition. The interface sends the value of the IDARregister as a slave address.

Write "1" to the SCC bit while the interrupt flag is set in bus master mode (IBCR:MSS =1, INT =1) to generate a repeated START condition.

Write "1" to the MSS bit while the bus is busy (IBSR:BB = 1, TRX = 0, IBCR:MSS = 0 or INT =0) to release the bus and start transmission.

If a write (reception) access is performed in slave mode, the interface starts transmission aftertransmission is completed and the bus is released. If the interface is sending data, it does notstart transmission even though the bus has been released.

The interface must be checked for the following:

• Whether the interface is specified as a slave (IBCR:MSS=0, IBSR:AAS=1)

• Whether data byte transmission is normal (IBCR:MSS=1) or not (IBSR:AL=1) when the nextinterrupt is received

STOP Condition

Write "0" to the MSS bit in master mode (IBCR:MSS = 1, INT = 1) to generate a STOP conditionand to place the interface in slave mode. Writing 0 to the MSS bit in any other state is ignored.

After the MSS bit is cleared, the interface attempts to generate a STOP condition. However, aSTOP condition will not be generated if the SCL line is driven to L. An interrupt is generatedafter the next byte is transferred.

Note:

After "0" is written to the MSS bit, it takes time until a STOP condition is generated. If the I2Cinterface is disabled (IDBL:DBL=1 or ICCR:EN = 0) before the STOP condition is generated,the operation stops immediately and an incorrect clock is generated on the SCL line.

Disable the I2C interface (IDBL:DBL = 1 or ICCR:EN = 0) after checking that a STOPcondition has been generated (IBSR:BB = 0).

385


Slave Address Detection

In slave mode, BB=1 is set after a START condition is generated. The receive data from themaster is stored in the IDAR register.

When a 7-bit slave address is enabled (ISMK: ENSB=1)

After 8-bit data is received, the IDAR and ISBA register values are compared. However, the bitsmasked in the ISMK register are not compared.

At this time, the values are compared with the values of the bits masked with the ISMK register.

If the comparison result is a match, the AAS bit is set to "1" and an acknowledge is sent to themaster. The value of bit0 of the received data (bit0 of the IDAR register after reception) is theninverted and stored in the TRX bit.

When a 10-bit slave address is enabled (ITMK: ENTB=1)

If the header section of a 10-bit address (11110, TA1, TA0, write) is detected, an acknowledgeis sent to the master and the value of bit0 of received data is inverted and stored in the TRX bit.No interrupt occurs at this time.

Then, the next data to be transferred and the low-order data of the ITBA register are compared.They are compared with the values of the bits masked with the ISMK register.

If the result is a match, the AAS bit is set to "1", an acknowledge is sent to the master, and aninterrupt occurs.

If the address has been specified as a slave and a repeated START condition is detected, theAAS bit is set to "1" and an interrupt occurs after the header section of a 10-bit address (11110,TA1, TA0, read) is received.

The interface has a 10-bit slave address register (ITBA) and a 7-bit slave address register(ISBA). If both registers are enabled (ISMK:ENSB = 1, ITMK:ENTB = 1), an acknowledge canbe sent for the 10-bit and 7-bit addresses.

The receive slave address length in slave mode (AAS = 1) is determined by the RAL bit of theITMK register. In master mode, disabling both registers (ISMK:ENSB = 0, ITMK:ENTB = 0) can

prevent a slave address from being generated for the I2C interface.

All slave addresses can be masked by setting the ITMK and ISMK registers.

Slave Address Mask

The slave address mask registers (ITMK and ISMK) can mask each bit of the slave addressregisters. A bit set to "1" in the mask register is address-compared while a bit set to "0" isignored. In slave mode (IBSR:AAS = 1), a receive slave address can be read from the ITBAregister (for a 10-bit address) or the ISBA register (for a 7-bit address).

If the bit mask is cleared, the interface can be used as the bus monitor because it is alwaysaccessed as a slave.

Note: This feature does not become a real bus monitor because it returns an acknowledge when aslave address is received even though no other slave device is available.

386


Master Addressing

In master mode, BB = 1 and TRX = 1 are set after a START condition is generated and theIDAR register contents are output starting with the MSB. After address data is sent and anacknowledge is received from a slave device, bit0 of the send data (bit0 of the IDAR registerafter transmission) is inverted and stored in the TRX bit. This operation is also performed for arepeated START condition.

Two bytes are sent for a 10-bit slave address during write access. The first byte consists of theheader section (11110, A9, A8, 0) that indicates a 10-bit sequence, and the second byteconsists of the low-order 8 bits of the slave address (A7 to A0).

The 10-bit slave device in the read access state sends the above bytes and generates arepeated START condition as well as the header section (11110, A9, A8, 1) that indicates aread access.

Table 16.3-1 shows the slave accesses and START condition.

Arbitration

Arbitration occurs if other master devices are also sending data during sending in master mode.If data sent by the local device is 1 and the data on the SDA line is the L level, the local deviceassumes arbitration to have been lost and sets AL=1.

AL = 1 is set if the interface detects an unnecessary START condition in the first bit of the dataor neither a START condition nor a STOP condition can be generated.

If arbitration loss is detected, MSS = 0 and TRX = 0 are set and the device enters slave receivemode and returns an acknowledge when it receives the device's own slave address.

Acknowledge

The receiving device sends an acknowledge to the sending device. The ACK bit (IBCR) canspecify whether an acknowledge is sent when data is received.

Even if an acknowledge is not returned from the master during data transmission in slave mode(read access from other master devices), the TRX bit is set to "0" and the device enters receivemode. This allows the master to generate a STOP condition when the slave releases the SCLline.

In master mode, an acknowledge from the slave can be checked by reading the LRB bit (IBSR).

Table 16.3-1 Slave Accesses and START Condition

7-bit slave address

Write START condition - A6 A5 A4 A3 A2 A1 A0 0

Read START condition - A6 A5 A4 A3 A2 A1 A0 1

10-bit slave access

Write START condition - 1 1 1 1 0 A9 A8 0 - A7 A6 A5 A4 A3 A2 A1 A0

Read START condition - 1 1 1 1 0 A9 A8 0 - A7 A6 A5 A4 A3 A2 A1 A0Repeated START condition - 1 1 1 1 0 A9 A8 1

387


Bus Error

A bus error is recognized and the I2C interface is stopped if:

• A violation of the basic convention on the I2C bus during data transfer (including the Ack bit)is detected.

• A stop condition in master mode is detected.

• A violation of the basic convention on the I2C bus while the bus is idle is detected.

Note:

The bus error of a 10-bit mode addressing is detected when a 10-bit address is disabled.

Communication Error that Causes No Error

If an incorrect clock is generated on the SCL line due to noise or some other reason during

transmission in master mode, the transmission bit counter of the I2C interface may run quickly,causing the slave to hang while the L level appears on the SDA line in the ACK cycle. An error(AL = 1, BER = 1) does not occur for such an incorrect clock.

If this situation occurs, perform the following error processing:

1. Determine that when MSS = 1, TRX = 1, INT = 1, and LRB = 1, there is a communicationerror.

2. Set EN to "0", and then set EN to "1" to cause SCL to generate one clock on a pseudo basis.This action causes the slave to release the bus.The period from when EN is set to "0" until EN is set to "1" must be long enough for the slaveto recognize it as a clock (about as long as the H period of a transmission clock).

3. Since IBSR and IBCR are cleared when EN is set to "0", perform retransmission processingfrom the START condition. At this time, a STOP condition cannot be generated even if BSSis set to "0".Insert an interval equal to or longer than n x 7 x tCCP between the point where EN is set to"1" and the point where MSS is set to "1" (START condition).

Example:

High-speed mode: 6 x 7 x 30.3 ≅ about 1.273 µs

Standard mode: 27 x 7 x 30.3 ≅ about 5.727 µs

Note:

When BER is set, it is not cleared even if EN is set to "0". Clear BER, and then retransmit it.

Other Items

• After arbitration lost occurs, check whether or not the local device is addressed usingsoftware.

When arbitration lost occurs, the device becomes a slave in terms of hardware. However,after one-byte transfer is completed, both the CLK and DATA lines are pulled to L. Thus, ifthe device is not addressed, immediately open the CLK and DATA lines. If the device isaddressed, open the CLK and DATA lines after preparing for slave transmission orreception. All of these things must be processed using software.

• Since the I2C bus has only one interrupt, an interrupt source is generated when one-bytetransfer is completed or when an interrupt condition is met.Since multiple interrupt conditions must be checked using one interrupt, each of the flagsmust be checked by the interrupt routine. The following lists the interrupt conditions used

388


when one-byte transfer is completed:

• The device is a bus master.

• The device is an addressed slave.

• A general call address is received.

• Arbitration lost occurs.

• When arbitration lost is detected, an interrupt source is generated, not immediately but afterone-byte transfer is completed. When arbitration lost is detected, the device becomes aslave in terms of hardware. However, in slave mode, a total of nine clocks must be outputbefore an interrupt source can be generated. Thus, since an interrupt source is notimmediately generated, no processing can be performed after arbitration lost occurs.

389



This section provides flowcharts for the following types of operation:• Main routine• Interrupt routine

Main routine

Figure 16.4-1 shows the main routine.

Figure 16.4-1 Main routine

NO

NO

YES

YES

Start

Set the slave address

Bus error interrupt enable

I2C enable

Master reception

Set the transmission data byte number

Slave address set trasmission

(data direction bit = 0)

BBbit = 1 ?

Slave address transmission start condition generates

BBbit = 0 ?

ALbit = 1 ?

I2C disable I2C disable

YESYES

YES

YES

NO

NONO

NO NO

BBbit = 1 ?

Slave address transmission start condition generates

BBbit = 0 ?

ALbit = 1 ?

Master receptionMaster transmissionSet the reception data

byte number

Slave address setreception

(data direction bit = 1)

YES

390

Interrupt routine

Figure 16.4-2 shows the interrupt routine.

Figure 16.4-2 Interrupt routine

NO

NO

NO

YES

YES

YES

NO

YES

NO

YES

2

3

3

1

2

3

1

Start

Bus error generated

AL generated

Master

ACK returned

Data direction bitTRX bit = 1 ?

The remainder of the transmission byte

number = 0 ?

Decrement of the transmission byte number

Set the transmission data

Transfer completed interrupt factor clear

RETI

STOP condition gnerates

RETI

Acknowledge generation enable

To the interrupt routineof slave address

1

1

I2C initial setting

I2C enable

RETI

The remainder of the reception byte

number = 0 ?

The remainder of the reception byte

number = 1 ?

Acknowledge generation enable

Acknowledge generation disable

Reception of the first byte ?ADTbit = 1 ?

Decrement of the transmission byte number

Store the received data to RAM

Transfer completed interrupt factor clear

RETI

NO

YES

NO

NO

NO

YES

YES

YES

391


392


This chapter describes the DMA controller (DMAC), the configuration and functions of registers, and DMAC operation.

17.1 Overview of the DMA Controller (DMAC)

17.2 DMA Controller (DMAC) Registers

17.3 DMA Controller Operation


17.5 Data Bus

393



The DMA controller (DMAC) is a module that implements DMA (Direct Memory Access) transfer on FR family devices. When this module is used to control DMA transfer, various kinds of data can be transferred at high speed by bypassing the CPU, enhancing system performance.The external transfer request pins are connected to DMA transfer requests at end points 1 and 2 of the USB function inside the chip. The USB host does not have a DMA transfer request function.

Hardware Configuration

The DMA controller (DMAC) consists mainly of the following blocks:

• Five independent DMA channels

• 5-channel independent access control circuit

• 32-bit address registers (reload specifiable, two registers for each channel)

• 16-bit rotation count register (reload specifiable, one register for each channel)

• 4-bit block rotation register (one for each channel)

• External transfer request input : DREQ0, DREQ1 (for ch.0, ch.1 only)

• External transfer request acceptance output : DACK0, DACK1 (for ch.0, ch.1 only)

• DMA end output : DEOP0, DEOP1, and DEOP2 (for ch0, 1, and 2 only)

• Fly-by transfer (memory to I/O and I/O to memory) (for ch 0, 1, and 2 only)

• 2-cycle transfer

394


Main Functions

The following are the main functions related to data transfer by the DMA controller (DMAC):

• Data can be transferred independently over multiple channels (5 channels)

• Priority (ch.0>ch.1>ch.2>ch.3>ch.4)

• The priority can be rotated between ch.0 and ch.1.

• DMAC start sources

• External dedicated pin input (edge detection/level detection for ch.0, ch.1, and ch.2 only)

• Built-in peripheral requests (shared interrupt requests, including external interrupts)

• Software request (register write)

• Transfer mode

• Demand transfer, burst transfer, step transfer, and block transfer

• Addressing mode: 32-bit full addressing (increment/decrement/fixed)

• The address increment/decrement range is from -255 to plus 255.

• Data types: Byte, halfword, and word length

• Single shot/reload selectable

395


Block Diagram

Figure 17.1-1 is a block diagram of the DMA controller (DMAC).

Figure 17.1-1 Block Diagram of the DMA Controller (DMAC)

Statetransition

circuit

DMA control

BLK register

DTC 2-stage register DTCR

DSAD 2-stage register

DDAD 2-stage register

DDNO register

TYPE.MOD,WS

DSS[2:0]

ERIR,EDIR

SADM,SASZ[7:0]

DADM,DASZ[7:0]

SADR

DADR

DDNO

Read

Write

Access

address

Selector

Sel

ecto

rS

elec

tor

Sel

ecto

r

Counter

X-b

us

To interrupt controller IRQ[4:0]Priority circuit

Peripheral activation request/stop input

Write back

Write back

Buffer

Selector

Counter

Buffer

MCLREQ

Read/writecontrol

To bus controller

DMA transfer request to the bus controller

DMA activation source

selection circuit & request

acceptance control External pin activation request/stop input

Peripheral interrupt clear

Bus

con

trol

uni

t

Bus

con

trol

uni

t

Add

ress

cou

nter

Cou

nter

buf

fer

Cou

nter

buf

fer

Writ

e ba

ck

Block diagram of 5-channel DMAC

396



This section describes the configuration and functions of the registers used by the DMA controller (DMAC).

DMA Controller (DMAC) registers

Figure 17.2-1 shows the registers used by the DMA controller (DMAC).

Figure 17.2-1 DMA Controller (DMAC) Registers

24 31 23 16 15 8 7 0

ch.0 control/status register A

ch.0 control/status register B

DMACA0 00000200H



DMACB0 00000204H

DMACA1 00000208H







All-channel control register

DMACB1 0000020CH

DMACA2 00000210H

DMACB2 00000214H

DMACA3 00000218H

DMACB3 0000021CH

DMACA4 00000220H

DMACB4 00000224H

DMACR 00000240H

ch.0 transfer source address register

ch.0

DMASA0 00001000H

transfer destination address register DMADA0 00001004H


ch.1 transfer destination address register

DMASA1 00001008H

DMADA1 0000100CH


ch.2

DMASA2 00001010H

transfer destination address register DMADA2 00001014H


ch.3

DMASA3 00001018H

transfer destination address register DMADA3 0000101CH


ch.4 transfer destination address register

DMASA4 00001020H

DMADA4 00001024H

(bit)

397


Notes on Setting Registers

When the DMA controller (DMAC) is set, some bits need to be set while DMA is stopped. If theyare set while DMA is in progress (during transfer), correct operation cannot be guaranteed.

An asterisk following a bit when its function is described later indicates that the operation of thebit is affected if it is set during DMAC transfer. Rewrite this bit while DMAC transfer is stopped(start is disabled or temporarily stopped).

The setting of this bit that is made while DMA transfer start is disabled (when the DMAE bit ofDMACR is "0" or the DENB bit of DMACA is "0") becomes effective when DMA transfer start isenabled.

The setting of this bit that is made while DMA transfer is temporarily stopped (when the DMAH3to DMAH0 bits of DMACR are not "0000B" or the PAUS bit of DMACA is "1") becomes effectivewhen temporary stop of DMA transfer is canceled.

398


17.2.1 Control/Status Registers A (DMACA0 to DMACA4)

Control/status registers A (DMACA0 to DMACA4) control the operation of the DMACA channels. There is a separate register for each channel.

Control/Status Registers A (DMACA0 to 4)

Figure 17.2-2 shows the bit configuration of control/status registers A (DMACA0 to DMACA4).

Figure 17.2-2 Bit Configuration of Control/Status Registers A (DMACA0 to DMACA4)

[bit31] DENB (Dma ENaBle): DMA operation enable bit

This bit, which corresponds to a transfer channel, is used to enable and disable DMAtransfer.

The activated channel starts DMA transfer when a transfer request is generated andaccepted.

All transfer requests that are generated for a deactivated channel are disabled.

When the transfer on an activated channel reaches the specified count, this bit is set to "0"and transfer stops.

The transfer can be forced to stop by writing "0" to this bit. Be sure to stop a transfer forcibly("0" write) only after temporarily stopping DMA using the PAUS bit [bit30 of DMACA]. If thetransfer is forced to stop without first temporarily stopping DMA, DMA stops but thetransferred data cannot be guaranteed. Check whether DMA is stopped using the DSS[2:0]bits [bit18 to bit16 of DMACB].

• If a stop request is accepted during reset: Initialized to "0".


If the operation of all channels is disabled by bit15 (DMAE bit) of the DMAC all-channel controlregister (DMACR), writing "1" to this bit is disabled and the stopped state is maintained. If theoperation is disabled by the above bit while it is enabled by this bit, "0" is written to this bit andthe transfer is stopped (forced stop).

bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DENB BLK[3:0]DDNO[3:0]IS[4:0]STRGPAUS

DTC[15:0]

(Initial value: 00000000_0000XXXX_XXXXXXXX_XXXXXXXX bit)

DENB Function

0 Disables operation of DMA on the corresponding channel (initial value).

1 Enables operation of DMA on the corresponding channel.

399


[bit30] PAUS (PAUSe)*: Temporary stop instruction

This bit temporarily stops DMA transfer on the corresponding channel. If this bit is set, DMAtransfer is not performed before this bit is cleared (While DMA is stopped, the DSS bits are1xx).

If this bit is set before starting, DMA transfer continues to be temporarily stopped.

New transfer requests that occur while this bit is set are accepted, but no transfer startsbefore this bit is cleared (See " Operation from Starting to End/Stopping" in Section "17.3.3General Aspects of DMA Transfer").

• When reset: Initialized to "0".


[bit29] STRG (Software TRiGger): Transfer request

This bit generates a DMA transfer request for the corresponding channel. If "1" is written tothis bit, a transfer request is generated when write operation to the register is completed andtransfer on the corresponding channel is started.

However, if the corresponding channel is not activated, operations on this bit are disabled.

Note:

If starting by a write operation to the DMAE bit and a transfer request occurring due to this bitare simultaneous, the transfer request is enabled and transfer is started. If writing of "1" tothe PAUS bit and a transfer request occurring due to this bit are simultaneous, the transferrequest is enabled, but DMA transfer is not started before "0" is written to the PAUS bit.


• The read value is always "0".

• Only a read value of "1" is valid. If "0" is read, operation is not affected.

PAUS Function

0 Enables operation of the corresponding channel DMA (initial value)

1 Temporarily stops DMA on the corresponding channel.

STRG Function

0 Disabled

1 DMA starting request

400


[bit28 to bit24] IS4 to IS0 (Input Select)*: Transfer source selection

These bits select the source of a transfer request as shown in Table 17.2-1 . Note that thesoftware transfer request by the STRG bit function is always valid regardless of the settingsof these bits.

• When reset: Initialized to "00000B".


Table 17.2-1 Settings for Transfer Request Sources

IS Function

00000 Hardware

00001

01101

01110 External pin (DREQ) H level or edge

01111 External pin (DREQ) L level or edge

10000 UART0 (receiving complete)



10011 UART0 (sending complete)



10110 External interrupt 0


11000 Reload timer 0





11101 PPG 0

11110 PPG 1

11111 PPG 2

Setting disabled

Setting disabled

401

Changed Table 17.2-1 in " Control/Status Registers A (DMACA0 to 4)".


Notes:

• If DMA start resulting from an interrupt from a function is set (IS=1xxxx), disable interruptsfrom the selected peripheral function with the ICR register.

• If demand transfer mode is selected, only IS[4:0]=01110, 01111 can be set. Starting by othersources is disabled.

• External request input is valid only for CH0, 1, and 2. External request input cannot beselected for CH3 and 4. Whether level detection or edge detection is used is determined bythe mode setting. Level detection is selected for demand transfer. (For all other cases, edgedetection is selected.)

[bit23 to bit20] DDNO3 to DDNO0 (direct access number)*: Fly-by function for built-in peripherals

These bits specify the built-in peripheral of the transfer destination/source used by thecorresponding channel.

Table 17.2-2 shows the settings of the direct access number.



Note:

This function is not supported by the MB91310. Any data written is ignored.

Table 17.2-2 Settings of the Direct Access Number

DDNO Function

0000 Setting disabled

0001 No use

0010 No use

0011 No use

0100 No use

0101 No use

0110 No use

0111 No use

1000 No use

1001 No use

1010 No use

1011 No use

1100 No use

1101 No use

1110 No use

1111 Setting disabled

402


[bit19 to bit16] BLK3 to BLK0 (BLocK size): Block size specification

These bits specify the block size for block transfer on the corresponding channel. The valuespecified by these bits becomes the number of words in one transfer unit (more exactly, therepetition count of the data width setting). If block transfer will not be performed, set 01H(size 1). This register value is ignored during demand transfer. The size becomes 1.

Table 17.2-3 shows the specification of the block size.

• When reset: Not initialized.


• If "0" is specified for all bits, the block size becomes 16 words.

• During reading, the block size is always read (reload value).

[bit15 to bit0] DTC (Dma Terminal Count register)*: Transfer count register

These bits compose a register for storing the transfer count. Each register has 16-bit length.

All registers have a dedicated reload register. When the register is used for a channel that isenabled to reload the transfer count register, the initial value is automatically written back tothe register when the transfer is completed.

Table 17.2-4 shows the function of the transfer count register.

When DMA transfer is started, data in this register is stored in the counter buffer of the DMA-dedicated transfer counter and is decremented by 1 (subtraction) after each transfer unit. WhenDMA transfer is completed, the contents of the counter buffer are written back to this registerand then DMA ends. Thus, the transfer count value during DMA operation cannot be read.


• These bits are readable and writable. Always access DTC using halfword length or wordlength.

• During reading, the count value is read. The reload value cannot be read.


Table 17.2-3 Specification of the Block Size

BLK Function

XXXXB Block size of the corresponding channel

Table 17.2-4 Function of the Transfer Count Register

DTC Function

XXXXH Transfer count for the corresponding channel

403


17.2.2 Control/Status Registers B (DMACB0 to DMACB4)

Control/status registers B (DMACB0 to DMACB4) control the operation of each DMACB channel and exist independently for each channel.

Control/Status Register B (DMACB0 to DMACB4)

Figure 17.2-3 shows the bit configuration of control/status registers B (DMACB0 to DMACB4).

Figure 17.2-3 Bit Configuration of Control/Status Registers B (DMACB0 to DMACB4)

[bit31, bit30] TYPE (TYPE)*: Transfer type setting

These bits specify the operation type of the corresponding channel as described below.

• 2-cycle transfer mode: In this mode, the transfer source address (DMASA) and transferdestination address (DMADA) are set and transfer is performed by repeating the readoperation and write operation for the number of times specified by the transfer count. Allareas can be specified as a transfer source or transfer destination (32-bit ADDRESS).

• Fly-by transfer mode: In this mode, external <--> external transfer is performed in one cycleby setting a memory address as the transfer destination address (DMADA). Be sure tospecify an external area for the memory address.

Table 17.2-5 shows the settings of the transfer type.



bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TYPE[1:0] DADM ERIE EDIE DSS[2:0]DADRSADRDTCRSADMWS[1:0]MOD[1:0]

SASZ[7:0] DASZ[7:0]

(Initial value: 00000000_00000000_XXXXXXXX_XXXXXXXX bit)

Table 17.2-5 Settings for the Transfer Types

TYPE Function

00 2-cycle transfer (initial value)

01 Fly-by: Memory → I/O transfer

10 Fly-by: I/O → memory transfer

11 Setting disabled

404


[bit29, bit28] MOD (MODe)*: Transfer mode setting

These bits specify the operation mode of the corresponding channel as shown in Table 17.2-6 .



[bit27, bit26] WS (Word Size)*: Transfer data width selection

These bits are used to select the transfer data width of the corresponding channel. Transferoperations are repeated in units of the data width specified in this register for as many timesas the specified count.

Table 17.2-7 shows the specification of the transfer data width.



Table 17.2-6 Settings for Transfer Modes

MOD Function

00 Block/step transfer mode (initial value)

01 Burst transfer mode

10 Demand transfer mode

11 Setting disabled

Table 17.2-7 Selection of the Transfer Data Width

WS Function

00 Byte-width transfer (initial value)

01 Halfword-width transfer

10 Word-width transfer

11 Setting disabled

405


[bit25] SADM (Source-ADdr. Count-Mode select)*: Transfer source address count mode specification

This bit specifies the address processing of the transfer source address of the correspondingchannel for each transfer operation.

An address increment is added or an address decrement is subtracted after each transferoperation according to the specified transfer source address count width (SASZ). When thetransfer is completed, the next access address is written to the corresponding addressregister (DMASA).

As a result, the transfer source address register is not updated until DMA transfer iscompleted.

To make the address always the same, specify "0" or "1" for this bit and set the addresscount width (SASZ and DASZ) to 0.

Table 17.2-8 shows the specification of the transfer source address count mode.



[bit24] DADM (Destination-ADdr. Count-Mode select)*: Transfer destination address count mode specification

This bit specifies the address processing for the transfer destination address of thecorresponding channel in each transfer operation.

An address increment is added or an address decrement is subtracted after each transferoperation according to the specified transfer destination address count width (DASZ). Whenthe transfer is completed, the next access address is written to the corresponding addressregister (DMADA).

As a result, the transfer destination address register is not updated until the DMA transfer iscompleted.

To make the address always the same, specify "0" or "1" for this bit and set the addresscount width (SASZ and DASZ) to 0.

Table 17.2-9 shows the specification of the transfer destination address count mode.



Table 17.2-8 Specification of the Transfer Source Address Count Mode

SADM Function

0 Increments the transfer source address. (initial value)

1 Decrements the transfer source address.

Table 17.2-9 Specification of the Transfer Destination Address Count Mode

DADM Function

0 Increments the transfer destination address. (initial value)

1 Decrements the transfer destination address.

406


[bit 23] DTCR (DTC-reg. Reload)*: Transfer count register reload specification

This bit controls reloading of the transfer count register for the corresponding channel.

If reloading of the counter is enabled by this bit, the count register value is restored to itsinitial value after transfer is completed, then DMAC stops and starts waiting for a newtransfer request (an activation request by STRG or IS setting). If this bit is "1", the DENB bitis not cleared.

DENB=0 or DMAE=0 must be set to stop the transfer. In either case, the transfer is forciblystopped.

If reloading of the counter is disabled, a single shot operation occurs. In single shotoperation, operation stops after the transfer is completed even if reload is specified in theaddress register. The DENB bit is also cleared in this case.

Table 17.2-10 shows the specification of transfer counter register reloading.



[bit22] SADR (Source-ADdr.-reg. Reload)*: Transfer source address register reload specification

This bit controls reloading of the transfer source address register for the correspondingchannel.

If this bit enables the reload operation, the transfer source address register value is restoredto its initial value after the transfer is completed.

If reloading of the counter is disabled, a single shot operation occurs. In single shotoperation, operation stops after the transfer is completed even if reload is specified in theaddress register. The address register value also stops in this case while the initial value isbeing reloaded.

If this bit disables the reload operation, the address register value when the transfer iscompleted is the address to be accessed next to the final address. When address incrementis specified, the next address is an incremented address.

Table 17.2-11 shows the specification of transfer source address register reloading.



Table 17.2-10 Specification of Transfer Counter Register Reloading

DTCR Function

0 Disables transfer count register reloading (initial value)

1 Enables transfer count register reloading.

Table 17.2-11 Specification of Transfer Source Address Register Reloading

SADR Function

0 Disables transfer source address register reloading. (initial value)

1 Enables transfer source address register reloading.

407


[bit21] DADR (Dest.-ADdr.-reg. Reload)*: Transfer destination address register reload specification

This bit controls reloading of the transfer source address register for the correspondingchannel.

If this bit enables reloading, the transfer source address register value is restored to its initialvalue after the transfer is completed.

The details of other functions are the same as those described for bit22 (SADR).

Table 17.2-12 shows the specification of transfer destination address register reloading.



[bit20] ERIE (ERror Interrupt Enable)*: Error interrupt output enable

This bit controls the occurrence of an interrupt for termination after an error occurs. Thenature of the error that occurred is indicated by DSS2 to DSS0. Note that an interrupt occursonly for specific termination causes and not for all termination causes. Refer to bits DSS2 toDSS0, which are bits 18-16.

Table 17.2-13 shows the specification of the error interrupt request output permission.



[bit19] EDIE (EnD Interrupt Enable)*: End interrupt output enable

This bit controls the occurrence of an interrupt for normal termination.

Table 17.2-14 shows the specification of the end interrupt request output permission.



Table 17.2-12 Specification of Transfer Destination Address Register Reloading

DADR Function

0 Disables transfer destination address register reloading. (initial value)

1 Enables transfer destination address register reloading.

Table 17.2-13 Specification of the Error Interrupt Request Output Permission

ERIE Function

0 Disables error interrupt request output. (initial value)

1 Enables error interrupt request output.

Table 17.2-14 Specification of the End Interrupt Request Output Permission

EDIE Function

0 Disables end interrupt request output. (initial value)

1 Enables end interrupt request output.

408


[bit18 to bit16] DSS2 to DSS0 (DMA Stop Status)*: Transfer stop source indication

These bits indicate a code (end code) of 3 bits that indicates the source of stopping ortermination of DMA transfer on the corresponding channel. For a list of end codes, see Table17.2-15 .

The code indicating a transfer stop request is set only if the request is received from aperipheral circuit and the external pin DSTP function is used.

Note:

The Interrupt column indicates the type of interrupts that can occur.


• These bits can be cleared by writing "000" to them.

• These bits are readable and writable. Note, however, that the only valid written value is"000".

[bit15 to bit8] SASZ (Source Addr count SiZe)*: Transfer source address count size specification

These bits specify the increment or decrement width for the transfer source address(DMASA) of the corresponding channel for each transfer operation. The value set by thesebits becomes the address increment/decrement width for each transfer unit. The addressincrement/decrement width conforms to the instruction in the transfer source address countmode (SADM).

Table 17.2-16 shows the specification of the transfer source address count size.

• When reset: Not initialized


Table 17.2-15 End Codes

DSS Function Interrupt

000 Initial value None

x01 Address error (underflow/overflow) Error

x10 Transfer stop request Error

x11 Normal end End

1xxDMA stopped temporarily (due, for example, to DMAH, PAUS bit, and an interrupt)

None

Table 17.2-16 Specification of the Transfer Source Address Count Size

SASZ Function

XXH Specify the increment/decrement width of the transfer source address. 0 to 255

409


[bit7 to bit0] DASZ (Des Addr count size)*: Transfer destination address count size specification

These bits specify the increment or decrement width for the transfer destination address(DMADA) of the corresponding channel for each transfer operation. The value set by thesebits becomes the address increment/decrement width for each transfer unit. The addressincrement/decrement width conforms to the instruction in the transfer destination addresscount mode (DADM).

Table 17.2-17 shows the specification of the transfer destination address count size.

• When reset: Not initialized


Table 17.2-17 Specification of the Transfer Destination Address Count Size

DASZ Function

XXH Specify the increment/decrement width of the transfer destination address. 0 to 255

410


17.2.3 Transfer Source/Transfer Destination Address Setting Registers (DMASA0 to DMASA4/DMADA0 to DMADA4)

The transfer source/transfer destination address setting registers (DMASA0 to DMASA4/DMADA0 to DMADA4) control the operation of the DMAC channels. There is a separate register for each channel.

Transfer Source/Transfer Destination Address Setting Registers (DMASA0 to DMASA4/DMADA0 to DMADA4)

Figure 17.2-4 shows the bit configuration of the transfer source/transfer destination addresssetting registers (DMASA0 to DMASA4/DMADA0 to DMADA4).

Figure 17.2-4 Bit Configuration of the Transfer Source/Transfer Destination Address Setting Registers (DMASA0 to DMASA4/DMADA0 to DMADA4)

The transfer source/transfer destination address setting registers (DMASA0 to DMASA4/DMADA0 to DMADA4) are a group of registers that store the transfer source/transfer destinationaddresses. Each register is 32 bits.

[bits31 to bit0] DMASA (DMA Source Addr)*: Transfer source address setting

These bits set the transfer source address.

bit

bit

bit

bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16DMASA[31:16]

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0DMASA[15:0]

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16DMADA[31:16]

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0DMADA[15:0]

(Initial value: XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXXbit)

(Initial value: XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXXbit)

411


[bit31 to bit0] DMADA (DMA Destination Addr)*: Transfer destination address setting

If DMA transfer is activated, data in this register is stored in the counter buffer of the DMA-dedicated address counter and then the address is calculated according to the settings forthe transfer operation. When the DMA transfer is completed, the contents of the counterbuffer are written back to this register and then DMA ends. Thus, the address counter valueduring DMA operation cannot be read.

All registers have a dedicated reload register. When the register is used for a channel that isenabled for reloading of the transfer source/transfer destination address register, the initialvalue is automatically written back to the register when the transfer is completed. Otheraddress registers are not affected.


• These bits are readable and writable. For this register, be sure to access these bits as 32-bitdata.

• If these bits are read during transfer, the address before the transfer is read. If they are readafter transfer, the next access address is read. Because the reload value cannot be read, itis not possible to read the transfer address in real time.

Note:

Do not set any of the DMAC’s registers using this register. DMA transfer is not possible forthe DMAC’s registers themselves.

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17.2.4 All-Channel Control Register (DMACR)

The all-channel control register (DMACR) controls the operation of the all five DMAC channels. Be sure to access this register using byte length.

All-Channel Control Register (DMACR)

Figure 17.2-5 shows the bit configuration of the DMAC all-channel control register (DMACR).

Figure 17.2-5 Bit Configuration of the All-Channel Control Register (DMACR)

[bit31] DMAE (DMA Enable): DMA operation enable

This bit controls the operation of all DMA channels.

If DMA operation is disabled with this bit, transfer operations on all channels are disabledregardless of the start/stop settings for each channel and the operating status. Any channelcarrying out transfer cancels the requests and stops transfer at a block boundary. All startoperations on each channel in a disabled state are disabled.

If this bit enables DMA operation, start/stop operations are enabled for all channels. Simplyenabling DMA operation with this bit does not activate each channel.

DMA operation can be forced to stop by writing "0" to this bit. However, be sure to forcestopping ("0" write) only after temporarily stopping DMA using the DMAH[3:0] bits [Bit27-24of DMACR]. If forced stopping is carried out without first temporarily stopping DMA, DMAstops, but the transfer data cannot be guaranteed. Check whether DMA is stopped using theDSS[2:0] bits [Bit18 to 16 of DMACB].

Table 17.2-18 shows the specification of the DMA operation permission.



bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16DMAE - - PM01 DMAH[3:0] - - - - - - - -

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0- - - - - - - - - - - - - - - -

(Initial value: 0XX00000_XXXXXXXX_XXXXXXXX_XXXXXXXX_bit)

Table 17.2-18 Specification of the DMA Operation Permission

DMAE Function

0 Disables DMA transfer on all channels. (initial value)

1 Enables DMA transfer on all channels.

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[bit28] PM01 (Priority mode ch0,1 robin): Channel priority rotation

This bit is set to alternate priority for each transfer between Channel0 and Channel1.

Table 17.2-19 shows the specification of the channel priority rotation.



[bit27 to bit24] DMAH (DMA Halt): DMA temporary stop

These bits control temporary stopping of all DMA channels. If these bits are set, DMAtransfer is not performed on any channel before these bits are cleared.

When DMA transfer is activated after these bits are set, all channels remain temporarilystopped.

Transfer requests that occur on channels for which DMA transfer is enabled (DENB=1) whilethese bits are set are all enabled. The transfer can be started by clearing all these bits.

Table 17.2-20 shows the specification of the DMA temporary stop function.

• When reset: Initialized to 0000B.


[bit30, bit29, and bit23 to bit0] (Reserved): Reserved bits

• These bits are reserved.

• A read value is undefined.

Other Functions

The MB91310 has the DACK, DEOP, and DREQ pins, which can be used for external transfer.These pins can also be used as general-purpose ports.

Pin Function of the DACK, and DEOP, and DREQ pins

To use the DACK, DEOP, and DREQ pins for external transfer, their operation mode must beswitched from the port function to the DMA pin function.

To make the switch, set the PFR register.

Table 17.2-19 Specification of the Channel Priority Rotation

PM01 Function

0 Fixes the priority. (ch.0 > ch.1)(initial value)

1 Alternates priority. (ch.1 > ch.0)

Table 17.2-20 Specification of the DMA Temporary Stop Function

DMAH Function

0000 Enables the DMA operation on all channels. (initial value)

Other than 0000 Temporarily stops DMA operation on all channels.

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A DMA controller (DMAC) is built into all FR family devices. The FR family DMAC is a multi-functional DMAC that controls data transfer at high speed without the use of CPU instructions.

Principal Operations

• Functions can be set for each transfer channel independently.

• Once starting has been enabled, a channel starts transfer operation only after a specifiedtransfer request has been detected.

• After a transfer request is detected, a DMA transfer request is output to the bus controllerand the bus right is acquired by the bus controller before the transfer is started.

• The transfer is carried out as a sequence conforming to the mode settings madeindependently for the channel being used.

Transfer Mode

Each DMA channel performs transfer according to the transfer mode set by the MOD[1:0] bits ofits DMACB register.

Block/step transfer

Only a single block transfer unit is transferred in response to one transfer request. DMA thenstops requesting the bus controller for transfer until the next transfer request is received.

The block transfer unit is the specified block size (BLK[3:0] of DMACA).

Burst transfer

Transfer in response to one transfer request is carried out continuously for the number of timesin the specified transfer count.

The specified transfer count is the transfer count (BLK[3:0] of DMACA × DTC[15:0] of DMACA)× block size.

Demand transfer

Transfer is carried out continuously until the transfer request input (detected with a level at theDREQ pin) from an external device ends or a specified transfer count is reached.

The specified transfer count in a demand transfer is the specified transfer count (DTC[15:0] ofDMACA). The block size is always 1 and the register value is ignored.

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Transfer Type

2-cycle transfer (normal transfer)

The DMA controller operates using as its unit of operation a read operation and a writeoperation.

Data is read from an address in the transfer source register and then written to another addressin the transfer destination register.

Fly-by transfer (memory --> I/O)

The DMA controller operates using as its unit of operation a read operation.

If DMA transfer is performed when fly-by transfer is set, DMA issues a fly-by transfer (read)request to the bus controller and the bus controller lets the external interface carry out the fly-bytransfer (read).

Fly-by transfer (I/O --> memory)

The DMA controller operates using as its unit of operation a write operation.

Otherwise, operation is the same as fly-by transfer (memory --> I/O) operation.

Access areas used for MB91310 fly-by transfer must be external areas.

Transfer Address

The following types of addressing are available and can be set independently for each channeltransfer source and transfer destination.

The method for specifying the address setting register (DMASA/DMADA) for a 2-cycle transferand the method for a fly-by transfer are different.

Specifying the address for a 2-cycle transfer

The value read from a register (DMASA/DMADA) in which an address has been set in advanceis used as the address for access. After receiving a transfer request, DMA stores the addressfrom the register in the temporary storage buffer and then starts transfer.

After each transfer (access) operation, the next access address is generated (increment/decrement/fixed selectable) by the address counter and then written to the temporary storagebuffer. Because the contents of the temporary storage buffer are written back to the register(DMASA/DMADA) after each block transfer unit is completed, the address register (DMASA/DMADA) value is updated after each block transfer unit is completed, making it impossible todetermine the address in real time during transfer.

Specifying the address for a fly-by transfer

In a fly-by transfer, the value read from the transfer destination address register (DMADA) isused as the address for access. The transfer source address register (DMASA) is ignored. Besure to specify an external area as the address to be set.

After receiving a transfer request, DMA stores the address from the register in the temporarystorage buffer and then starts transfer.

After each transfer (access) operation, the next access address is generated (increment/decrement/fixed selectable) by the address counter and then written to the temporary storagebuffer. Because the contents of this temporary storage buffer are written back to the register(DMADA) after each block transfer unit is completed, the address register (DMADA) value isupdated after each block transfer unit is completed, making it impossible to determine theaddress in real time during transfer.

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Transfer Count and Transfer End

Transfer count

The transfer count register is decremented (-1) after each block transfer unit is completed.When the transfer count register becomes 0, counting for the specified transfer ends, and the

transfer stops with the end code displayed or is reactivated*1.

Like the address register, the transfer count register is updated only after each block transferunit.

*1: If transfer count register reloading is disabled, the transfer ends. If reloading is enabled, theregister is initialized and then waits for transfer (DTCR of DMACB)

Transfer end

Listed below are the sources for transfer end. When transfer ends, a source is indicated as theend code (DSS[2:0] of DMACB).

• End of the specified transfer count (DMACA:BLK[3:0] × DMACA:DTC[15:0]) => Normal end

• A transfer stop request from a peripheral circuit or the external pin (DSTP) occurred => Error

• An address error occurred => Error

• A reset occurred => Reset

The transfer stop source is indicated (DSS) and the transfer end interrupt or error interrupt forthe end source is generated.

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17.3.1 Setting a Transfer Request

The following three types of transfer requests are provided to activate DMA transfer:• External transfer request pin• Built-in peripheral request• Software requestSoftware requests can always be used regardless of the settings of other requests.

External Transfer Request Pin

A transfer request is generated by input to the input pin prepared for a channel.

The MB91310 supports channels 0 to 2 (DREQ0, 1, and 2).

If the input is valid at this point, the following sources are selected depending on the settings forthe transfer type and the start source:

Edge detection

If the transfer type is block, step, or burst transfer, select edge detection:

• Falling edge detection: Set with the transfer source selection register. Set when the IS4 toIS0 bits of DMACA are 01110.

• Rising edge detection: Set with the transfer source selection register. Set when the IS4 toIS0 bits of DMACA are 01111.

Level detection

If the transfer type is demand transfer, select level detection:

• H level detection: Set with the transfer source selection register. Set when the IS4 to IS0 bitsof DMACA are 01110.

• L level detection: Set with the transfer source selection register. Set when the IS4 to IS0 bitsof DMACA are 01111.

Built-in Peripheral Request

A transfer request is generated by an interrupt from the built-in peripheral circuit.

For each channel, set the peripheral’s interrupt by which a transfer request is generated (whenthe IS4 to IS0 bits of DMACA are 1xxxxB).

The built-in peripheral request cannot be used together with an external transfer request.

Note:

Because an interrupt request used in a transfer request seems like an interrupt request tothe CPU, disable interrupts from the interrupt controller (ICR register).

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Software Request

A transfer request is generated by writing to the trigger bit of a register (STRG of DMACA).

The software request is independent of the above two types of transfer request and can alwaysbe used.

If a software request occurs concurrently with activation (transfer enable request), a DMAtransfer request is output to the bus controller immediately and transfer is started.

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17.3.2 Transfer Sequence

The transfer type and the transfer mode that determine, for example, the operation sequence after DMA transfer has started can be set independently (Settings for TYPE[1:0] and MOD[1:0] of DMACB).

Selection of the Transfer Sequence

The following sequence can be selected with a register setting:

• Burst 2-cycle transfer

• Demand 2-cycle transfer

• Block/step 2-cycle transfer

• Burst fly-by transfer

• Demand fly-by transfer

• Block/step fly-by transfer

Burst 2-Cycle Transfer

In a burst 2-cycle transfer, as many transfers as specified by the transfer count are performedcontinuously for one transfer source. For a 2-cycle transfer, all 32-bit areas can be specifiedusing a transfer source/transfer destination address.

A peripheral transfer request, software transfer request, or external pin (DREQ) edge inputdetection request can be selected as the transfer source.

Table 17.3-1 shows the specifiable transfer addresses.

[Features of a burst transfer]

• When one transfer request is received, transfer is performed continuously until the transfercount register reaches 0.

• The transfer count is the transfer count x block size (BLK[3:0] of DMACA × DTC[15:0] ofDMACA).

• Another request occurring during transfer is ignored.

• If the reload function of the transfer count register is enabled, the next request is acceptedafter transfer ends.

• If a transfer request for another channel with a higher priority is received during transfer, thechannel is switched at the boundary of the block transfer unit. Processing resumes only afterthe transfer request for the other channel is cleared.

Figure 17.3-1 shows an example of burst transfer.

Table 17.3-1 Specifiable Transfer Addresses

Transfer source addressing Direction Transfer destination addressing

All 32-bit areas specifiable => All 32-bit areas specifiable

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Figure 17.3-1 Example of Burst Transfer Started by Rising Edge Detection at an External Pin. The Number of Blocks is 1, and the Transfer Count is 4.

Burst Fly-by Transfer

A burst fly-by transfer has the same features as a 2-cycle transfer except that the transfer areacan only be external areas, and the transfer unit is read (memory --> I/O) or write (I/O -->memory) only.


Demand Transfer 2-Cycle Transfer

A demand transfer sequence is generated only if H level or L level of an external pin is selectedas a transfer request. Select the level with IS[4:0] of DMACA.

[Features of a continuous transfer]

• The following are some features of a continuous transfer:

• Each transfer operation of a transfer request is checked. While the external input level iswithin the range of the specified transfer request levels, transfer is performed continuouslywithout the request being cleared. If the external input changes, the request is cleared andthe transfer stops at the transfer boundary. This operation is repeated for the number oftimes specified by the transfer count.

• Otherwise, operations are the same as those of a burst transfer.

Figure 17.3-2 shows an example of demand transfer, and Table 17.3-3 shows the specifiabletransfer addresses.

Transfer count

Bus operation CPU SA DA SA DA SA DA SA DA CPU

4 3 12

Transfer end

0

Transfer request ( edge)

Table 17.3-2 Specifiable Transfer Addresses (for Burst Fly-by Transfer)


Specification not required (invalid) None External area

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Figure 17.3-2 Example of Demand Transfer Started by H Level Activation at an External Pin. The Number of Blocks is 1, and the Transfer Count is 3.

Notes:

• For a demand transfer, be sure to set an external area address for the transfer source ortransfer destination or both. Since DMA transfer is adjusted to the external bus timing indemand transfer mode, access to external areas is always needed.

• Since the SDRAM area is not supported as a transfer source/transfer destination duringdemand transfer, this area cannot be set.

Demand Transfer Fly-by Transfer

A demand transfer fly-by transfer has the same features as a 2-cycle transfer except that thetransfer area can only be external areas, and the transfer unit is read (memory --> I/O) or write(I/O --> memory) only.


CPU SA DA SA DA SA DA

3 2 1 0

CPU

Transfer request (H level)

Bus operation

Transfer count

Transfer end

Table 17.3-3 Specifiable Transfer Addresses (for Demand Transfer 2-Cycle Transfer)

Transfer source address Direction Transfer destination address

External area => External area

External area => Built-in IO

External area => Built-in RAM

Built-in IO => External area

Built-in RAM => External area

Table 17.3-4 Specifiable Transfer Addresses (for Demand Transfer Fly-by Transfer)



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Step/Block Transfer 2-Cycle Transfer

For a step/block transfer (Transfer for each transfer request is performed as many times as thespecified block count), all 32-bit areas can be specified as the transfer source/transferdestination address.


Step transfer

If "1" is set as the block size, a step transfer sequence is generated.

[Features of a step transfer]

• If a transfer request is received, the transfer request is cleared after one transfer operationand then the transfer is stopped (The DMA transfer request to the bus controller iscanceled).

• Another request occurring during transfer is ignored.

• If a transfer request for another channel with a higher priority is received during transfer, thechannel is switched after the transfer is stopped and then restarted. Priority in a step transferis valid only if transfer requests occur simultaneously.

Block transfer

If any value other than 1 is specified as the block size, a block transfer sequence is generated.

[Features of a block transfer]

The block transfer has the same features as those of a step transfer except that one transferunit consists of multiple transfer cycle counts (number of blocks).

Figure 17.3-3 shows an example of block transfer.

Figure 17.3-3 Example of Demand Transfer Started by Rising Edge Activation at an External Pin. The Number of Blocks is 2, and the Transfer Count is 2.

Table 17.3-5 Specifiable Transfer Addresses (for Step/Block Transfer 2-Cycle Transfer)


All 32-bit areas specifiable => All 32-bit areas specifiable

CPU SA DA SA DA SA DA SA DA

2 1 120

CPU

2 1Transfer count

Bus operation

Number of blocks

Transfer end

Transfer request ( edge)

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Step/Block Transfer 2-Cycle Transfer Fly-by Transfer

This transfer has the same features as those of a 2-cycle transfer except that the transfer areacan only be external areas, and the transfer unit is read (memory --> I/O) or write (I/O -->memory) only.


Table 17.3-6 Specifiable Transfer Addresses (for Step/Block Transfer 2-Cycle Transfer Fly-by Transfer)



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17.3.3 General Aspects of DMA Transfer

This section describes the block size for DMA transfers and the reload operation.

Block Size

• The unit and increment for transfer data is a set of (the number set in the block sizespecification register × data width) data.

• Since the amount of data transferred in one transfer cycle is determined by the valuespecified as the data width, one transfer unit is consists of the number of transfer cycles forthe specified block size.

• If a transfer request with a higher priority is received during transfer or if a temporary stoprequest for a transfer occurs, the transfer stops only at the transfer unit boundary, whether ornot the transfer is a block transfer. This arrangement makes it possible to protect data forwhich division or temporary stopping is not desirable. However, if the block size is large,response time increases.

• Transfer stops immediately only when a reset occurs, in which case the data beingtransferred cannot be guaranteed.

Reload Operation

In this module, the following three types of reloading can be set for each channel:

Transfer count register reloading

After transfer is performed the specified number of times, the initial value is set in the transfercount register again and waiting for a start request starts.

Set this type of reloading when the entire transfer sequence is to be performed repeatedly.

If reload is not specified, the count register value remains 0 after the transfer is performed thespecified number of times and no further transfer is performed.

Transfer source address register reloading

After transfer is performed the specified number of times, the initial value is set in the transfersource address register again.

Set this type of reloading when transfer is to be repeated from a fixed area in the transfer sourceaddress area.

If reload is not specified, the transfer source address register value after the transfer isperformed the specified number of times becomes the next address. Use this type when theaddress area is not fixed.

Transfer destination address register reloading

After transfer is performed the specified number of times, the initial value is set in the transferdestination address register again.

Set this type of reloading when transfer is to be repeated to a fixed area in the transferdestination address area.

(The processing hereafter is the same as described in "Transfer source address registerreloading" above.)

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• If only reloading of the transfer source/transfer destination register is enabled, restart aftertransfer is performed the specified number of times is not implemented and only the valuesof each address register are set.

Special examples of operating mode and the reload operation

• If transfer is performed in continuous transfer mode by external pin input level detection andtransfer count register reloading is used, transfer continues by reloading even thoughtransfer ends during continuous input. Also in this case, an end code is set.

• If it is preferable that processing stops when data transfer ends and starts after input isdetected again, do not specify reload.

• For a transfer in burst, block, or step transfer mode, transfer stops temporarily after reloadwhen data transfer ends. Transfer does not start until new transfer request input is detected.

Addressing Mode

Specify the transfer destination/transfer source address independently for each transferchannel.

Address Register Specifications

The following two methods are provided to specify an address register. The method specifieddepends on the transfer sequence.

• In 2-cycle transfer mode, set the transfer source address in the transfer source addresssetting register (DMASA) and the transfer destination address in the transfer destinationaddress setting register (DMADA).

• In fly-by transfer mode, specify the memory address in the transfer source address settingregister (DMASA). In this case, the value in the transfer destination address setting register(DMADA) is ignored.

Features of the Address Register

This register has the maximum 32-bit length. With 32-bit length, all space in the memory mapcan be accessed.

Function of the Address Register

• The address register is read in each access operation and the read value is sent to theaddress bus.

• At the same time, the address for the next access is calculated by the address counter andthe address register is updated using the calculated address.

• For address calculation, increment or decrement is selected independently for each channel,transfer destination, and transfer source. The address increment/decrement width isspecified by the address count size register (SASZ/DASZ of DMACB).

• If reloading is not enabled, the address resulting from the address calculation of the lastaddress remains in the address register when the transfer ends.

• If reloading is enabled, the initial value of the address is reloaded.

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Notes:

• If an overflow or underflow occurs as a result of 32-bit length full address calculation, anaddress error is detected and transfer on the relevant channel is stopped. (Refer to thedescription for the items related to the end code).

• Do not set any of the DMAC’s registers as the address register.

• For demand transfer, be sure to set an address in an external area for the transfer source,transfer destination, or both.

• Do not let the DMAC transfer data to any of the DMAC’s registers.

Data Types

Select the data length (data width) transferred in one transfer operation from the following:

• Byte

• Halfword

• Word

Data Length (Data width)

Since the word boundary specification is also observed in DMA transfer, different low-order bitsare ignored if an address with a different data length is specified for the transfer destination/transfer source address.

• Word: The actual access address has a 4-byte length starting with 00 as the lowest-orderbits.

• Halfword: The actual access address has 2-byte length starting with 0 as the lowest-orderbit.

• Byte: The actual access address and the addressing match.

If the lowest-order bits in the transfer source address and transfer destination address aredifferent, the addresses as set are output on the internal address bus. However, each transfertarget on the bus is accessed after the addresses are corrected according to the above rules.

Transfer Count Control

Specify the transfer count within the range of the maximum 16-bit length (1 to 65536).

Transfer Count Control

Set the transfer count value in the transfer count register (DTC of DMACA).

The register value is stored in the temporary storage buffer when the transfer starts and isdecremented by the transfer counter. When the counter value becomes 0, end of transfer endfor the specified count is detected, and the transfer on the channel is stopped or waiting for arestart request starts (when reload is specified).

Features of the group of transfer count registers:

• Each register has 16-bit length.

• All registers have a dedicated reload register.

• If transfer is activated when the register value is 0, transfer is performed 65536 times.

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Reload operation

• The reload operation can be used only if reloading is enabled in a register that allowsreloading.

• When transfer is activated, the initial value of the count register is saved in the reloadregister.

• If the transfer counter counts down to 0, end of transfer is reported and the initial value isread from the reload register and written to the count register.

CPU Control

When a DMA transfer request is accepted, DMA issues a transfer request to the bus controller.

The bus controller passes the right to use the internal bus to DMA at a break in bus operationand DMA transfer starts.

DMA Transfer and Interrupts

• During DMA transfer, interrupts are generally not accepted until the transfer ends.

• If a DMA transfer request occurs during interrupt processing, the transfer request is acceptedand interrupt processing is stopped until the transfer is completed.

• If, as an exception, an NMI request or an interrupt request with a higher level than the holdsuppress level set by the interrupt controller occurs, DMAC temporarily cancels the transferrequest via the bus controller at a transfer unit boundary (one block) to temporarily stop thetransfer until the interrupt request is cleared. In the meantime, the transfer request isretained internally. After the interrupt request is cleared, DMAC issues a transfer request tothe bus controller to acquire the right to use the bus and then restarts DMA transfer.

Suppressing DMA

When an interrupt source with a higher priority occurs during DMA transfer, an FR family deviceinterrupts the DMA transfer and branches to the relevant interrupt routine. This feature is validas long as there are any interrupt requests. When all interrupt sources are cleared, thesuppression feature no longer works and the DMA transfer is restarted by the interruptprocessing routine. Thus, if you want to suppress restart of DMA transfer after clearing interruptsources in the interrupt source processing routine at a level that interrupts DMA transfer, usethe DMA suppress function. The DMA suppress function can be activated by writing any valueother than 0 to the DMAH[3:0] bits of the DMA all-channel control register and can be stoppedby writing 0 to these bits.

This function is mainly used in the interrupt processing routines. Before the interrupt sources inan interrupt processing routine are cleared, the DMA suppress register is incremented by 1. Ifthis is done, then no DMA transfer is performed. After interrupt processing, decrement theDMAH[3:0] bits by 1 before returning. If multiple interrupts have occurred, DMA transfercontinues to be suppressed since the DMAH[3:0] bits are not 0 yet. If a single interrupt hasoccurred, the DMAH[3:0] bits become 0. DMA requests are then enabled immediately.

Notes:

• Since the register has only four bits, this function cannot be used for multiple interruptsexceeding 15 levels.

• Be sure to assign the priority of the DMA tasks at a level that is at least 15 levels higher thanother interrupt levels.

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Hold Arbitration

When a device is operating in external bus extended mode, an external hold function can beused. The relationship between external hold requests and DMA transfer requests by thismodule when the hold function can be used is described below.

DMA Transfer Request during External Hold

The device is externally held. When an external bus area is accessed by DMA transfer, DMAtransfer is temporarily stopped. When the external hold is released, DMA transfer is restarted.

External Hold Request During DMA Transfer

The device is externally held. When an external bus area is accessed by DMA transfer, DMAtransfer is temporarily stopped. When the external hold is released, DMA transfer is restarted.

Simultaneous Occurrence of a DMA Transfer Request and an External Hold Request

The device is externally held and internal DMA transfer is started. When an external bus area isaccessed by DMA transfer, DMA transfer is temporarily stopped. When the external hold isreleased, DMA transfer is restarted.

Operation from Starting to End/Stopping

Starting of DMA transfer is controlled independently for each channel, but before transfer starts,the operation of all channels needs to be enabled. This section describes operation fromstarting to end/stopping.

Operation Start

Enabling operation for all channels

Before activating each DMAC channel, operation for all channels needs to be enabled inadvance with the DMA operation enable bit (DMAE of DMACR). All start settings and transferrequests that occurred before operation is enabled are invalid.

Starting transfer

The transfer operation can be started by the operation enable bit of the control register for eachchannel. If a transfer request to an activated channel is accepted, the DMA transfer operation isstarted in the specified mode.

Starting from a temporary stop

If a temporary stop occurs before starting with channel-by-channel or all-channel control, thetemporary stopped state is maintained even though the transfer operation is started. If transferrequests occur in the meantime, they are accepted and retained. When temporary stopping isreleased, transfer is started.

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Transfer Request Acceptance and Transfer

Sampling for transfer requests set for each channel starts after starting.

If edge detection is selected for the external pin start source and a transfer request is detected,the request is retained within DMAC until the clear conditions are met (when the external pinstart source is selected for block, step, or burst transfer).

If level detection or peripheral interrupt start is selected for the external pin start source, DMACcontinues the transfer until all transfer requests are cleared. When they are cleared, DMACstops the transfer after one transfer unit (demand transfer or peripheral interrupt start).

Since peripheral interrupts are handled as level detection, use interrupt clear by DMA to handlethe interrupts.

Transfer requests are always accepted while other channel requests are being accepted andtransfer performed. The channel that will be used for transfer is determined for each transferunit after priority has been checked.

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Clearing Peripheral Interrupts by DMA

This DMA has a function that clears peripheral interrupts. This function works when peripheralinterrupt is selected as the DMA start source (when IS[4:0]=1xxxx).

Peripheral interrupts are cleared only for the set start sources. That is, only the peripheralfunctions set by IS[4:0] are cleared.

Timing for Clearing an Interrupt

The timing for clearing an interrupt depends on the transfer mode. (See Section "17.4Operation Flowcharts").

Block/step transfer

If block transfer is selected, a clear signal is generated after one block (step) transfer.

Burst transfer

If burst transfer is selected, a clear signal is generated after transfer is performed thespecified number of times.

Demand transfer

Since only start requests from external pins are supported in demand transfer, no clearsignal is generated.

Temporary Stopping

DMA transfer is stopped in the following cases:

Setting of temporary stopping by writing to the control register (Set independently for each channel or all channels simultaneously)

If temporary stopping is set using the temporary stop bit, transfer on the corresponding channelis stopped until release of temporary stopping is set again. You can check the DSS bits fortemporary stopping.

Transfer is restarted when temporary stopping is canceled.

NMI/hold suppress level interrupt processing

If an NMI request or an interrupt request with a higher level than the hold suppress level occurs,all channels on which transfer is in progress are stopped at the boundary of the transfer unit andthe bus right is returned to give priority to NMI/interrupt processing. Transfer interrupts acceptedduring NMI/interrupt processing are retained, initiating a wait for completion of NMI processing.

Channels for which requests are retained restart transfer after NMI/interrupt processing iscompleted.

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Operation End/Stopping

The end of DMA transfer is controlled independently for each channel. It is also possible todisable operation for all channels at once.

Transfer end

If reloading is disabled, transfer is stopped, “Normal end” is displayed as the end code, and alltransfer requests are disabled after the transfer count register becomes 0 (Clear the DENB bit ofDMACA).

If reloading is enabled, the initial value is reloaded, “Normal end” is displayed as the end code,and a wait for transfer requests starts after the transfer count register becomes 0 (Do not clearthe DENB bit of DMACA).

Disabling all channels

If the operation of all channels is disabled with the DMA operation enable bit DMAE, all DMACoperations, including operations on active channels, are stopped. Then, even if the operation ofall channels is enabled again, no transfer is performed unless a channel is restarted. In thiscase, no interrupt whatever occurs.

Stopping Due To an Error

In addition to normal end after transfer for the number of times specified, stopping as the resultof various types of errors and the forced stopping are provided.

Transfer stop requests from peripheral circuits

Depending on the peripheral circuit that outputs a transfer request, a transfer stop request isissued when an error is detected (Example: Error when data is received at or sent from acommunications system peripheral).

The DMAC, when it receives such a transfer stop request, displays “Transfer stop request” asthe end code and stops the transfer on the corresponding channel.

Note:

For details of the conditions under which a transfer stop request is generated, see thespecifications for each peripheral circuit.

00000

01111

10000

10010

10011

11111

Hardware

External pin "L" level or edgeNone

Yes

None

IS Function Transfer stop request

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Occurrence of an address error

If inappropriate addressing, as shown below in parenthesis, occurs in an addressing mode, anaddress error is detected (if an overflow or underflow occurs in the address counter when a 32-bit address is specified).

If an address error is detected, “An address error occurred” is displayed as the end code andtransfer on the corresponding channel is stopped.

DMAC Interrupt Control

Independent of peripheral interrupts that become transfer requests, interrupts can also beoutput for each DMAC channel.

DMAC Interrupt Control

• Transfer end interrupt: Occurs only when operation ends normally.

• Error interrupt: Transfer stop request due to a peripheral circuit (error due to a peripheral)

• Error interrupt: Occurrence of address error (error due to software)

All of these interrupts are output according to the meaning of the end code.

An interrupt request can be cleared by writing "000B" to DSS2 to DSS0 (end code) of DMACS.Be sure to clear the end code by writing "000B" before restarting.

If reloading is enabled, the transfer is automatically restarted. At this point, however, the endcode is not cleared and is retained until a new end code is written when the next transfer ends.

Since only one end source can be displayed in an end code, the result after considering theorder of priority is displayed when multiple sources occur simultaneously. The interrupt thatoccurs at this point conforms to the displayed end code.

The following shows the priority for displaying end codes (in order of decreasing priority):

• Reset

• Clearing by writing "000B"

• Peripheral stop request or external pin input (DSTP) stop request

• Normal end

• Stopping when address error detected

• Channel selection and control

DMA Transfer during Sleep

• The DMAC can also operate in sleep mode.

• If you anticipate operations during sleep mode, note the following:

• Since the CPU is stopped, DMAC registers cannot be rewritten. Make settings beforesleep mode is entered.

• The sleep mode is released by an interrupt. Thus, if a peripheral interrupt is selected asthe DMAC start source, interrupts must be disabled by the interrupt controller.

If you do not want to release sleep mode with a DMAC end interrupt, disable these interrupts.

Channel Selection and Control

Up to five channels can be simultaneously set as transfer channels. In general, an independentfunction can be set for each channel.

433


Priority Among Channels

Since DMA transfer is possible only on one channel at a time, priority must be set for thechannels.

Two modes, fixed and rotation, are provided as the priority settings and can be selected foreach channel group (described later).

Fixed mode

The order of priority is fixed by channel number, with priority decreasing from channel 0 tochannel 4:

(ch.0 > ch.1 > ch.2 > ch.3 > ch.4)

If a transfer request with a higher priority is received during a transfer, the transfer channelbecomes the channel with the higher priority when the transfer for the transfer unit (number setin the block size specification register x data width) ends.

When higher priority transfer is completed, transfer is restarted on the previous channel.

Figure 17.3-4 shows the timing diagram for the transfer operation in fixed mode

Figure 17.3-4 Timing Diagram for the Transfer Operation in Fixed Mode

Rotation mode (ch.0 to ch.1 only)

When operation is enabled, the initial states have the same order that they would have in fixedmode, but at the end of each transfer operation, the priority of the channels is reversed. Thus, ifmore than one transfer request is output at the same time, the channel is switched after eachtransfer unit.

This mode is effective when continuous or burst transfer is set.

Figure 17.3-5 shows the timing diagram for the transfer operation in rotation mode.

CPU SA DA SA DA SA DA SA DA CPU

ch.1 ch.0 ch.0 ch.1

ch0 transfer request


Bus operation

Transfer ch

ch.0 transfer end

ch.1 transfer end

434


Figure 17.3-5 Timing Diagram for the Transfer Operation in Rotation Mode

Channel Group

Table 17.3-7 shows the selection priority of channel groups.

CPU SA DA SA DA SA DA SA DA CPU

ch.1 ch.0 ch.1 ch.0



Bus operation

Transfer ch

ch0 transfer end

ch1 transfer end

Table 17.3-7 Selection Priority of Channel Groups

MODE Priority Remarks

Fixed ch.0 > ch.1 −

RotationThe initial state is the top row.If transfer occurs for the top row, the priority is reversed.

ch.0 > ch.1

ch.0 < ch.1

435



This section contains operation flowcharts for the following transfer modes:• Block transfer• Burst transfer• Demand transfer

Block Transfer

Figure 17.4-1 shows the flowchart for block transfer.

Figure 17.4-1 Operation Flowchart for Block Transfer

Load the initial address,transfer count, and number

of blocks

Activation requestwait

Interrupt clear

DMA transfer end DMA interrupted

BLK=0

DTC=0

DMA stop

DENB=1DENB=>0

Write back the address, transfer count, and number of blocks

Number of blocks - 1

Activation request

One-time access for fly-by

Reload enable

Only when the peripheralinterrupt activation sourceis selected

Calculate the address for transfer source address access

Calculate the address for transferdestination address access

Block transfer- Can be activated by all activation sources (selection).- Can access all areas.- The number of blocks can be set.- Interrupt clear is issued when transfer of the specified number of blocks is completed.- The DMA interrupt is issued when transfer for the number of times specified is completed.

Transfer count - 1

Interrupt cleared

436


Burst Transfer

Figure 17.4-2 shows the operation flowchart for burst transfer.

Figure 17.4-2 Operation Flowchart for Burst Transfer

Load the initial address,transfer count, andnumber of blocks



BLK=0

DTC=0

DMA stop

DENB=1DENB=>0

Write back the address,transfer count, and number

of blocks


Interrupt clear


Reload enable

Only when the peripheral interruptactivation source is selected

Calculate the address fortransfer source address access


Transfer count - 1

Interrupt cleared

Burst transfer- Can be activated by all activation sources (selection).- Can access all areas.- The number of blocks can be set.- Interrupt clear and the DMA interrupt are issued when transfer for the number of times specified is completed.

437


Demand Transfer

Figure 17.4-3 shows the operation flowchart for demand transfer.

Figure 17.4-3 Operation Flowchart for Demand Transfer

Load the initial address,transfer count, andnumber of blocks



DTC=0

DMA stop

DENB=1DENB=>0

Write back the address,transfer count, and number

of blocks

Interrupt clear

Activation request


Reload enable

Only when the peripheral interruptactivation source is selected

Calculate the address fortransfer source address access



Interrupt cleared

None

Demand transfer- Only requests from the external pin (DREQ) are accepted. Activation by

other sources is disabled.- Access to an external area is required (since access to an external area

becomes the next activation source).- The number of blocks is always 1, regardless of the settings.- Interrupt clear and the DMA interrupt are issued when transfer for the

number of times specified is completed.

438

17.5 Data Bus

17.5 Data Bus

This section shows the flow of data during 2-cycle transfer and fly-by transfer.

Flow of Data During 2-Cycle Transfer

Figure 17.5-1 shows examples of six types of transfer during 2-cycle transfer.

439


Figure 17.5-1 Examples of 2-Cycle Transfer (Continued on next page)

DMAC

D-bus

X-busI-bus

F-bus

D-bus

X-busI-bus

F-bus

D-bus

X-busI-bus

F-bus

D-bus

X-busI-bus

F-bus

D-bus

X-busI-bus

F-bus

D-bus

X-busI-bus

F-bus

RAM

CP

UMB91xxx

Read cycle

Read cycle

Read cycle

IO

Bus controller

DMAC

RAM

CP

U

MB91xxx

Data buffer

Bus controller

Data buffer

Write cycle

Write cycle

Write cycle

IO

DMAC

RAM

CP

U

MB91xxx

IO

DMAC

RAM

CP

U

MB91xxx

IO

DMAC

RAM

CP

U

MB91xxx

IO

DMAC

RAM

CP

U

MB91xxx

IO

External area => external area transfer

External area => internal RAM area transfer

External area => built-in IO area transfer

Bus controller

Data buffer

Bus controller

Data buffer

Bus controller

Data buffer

Bus controller

Data buffer

Ext

erna

l bus

I/F

Ext

erna

l bus

I/F

Ext

erna

l bus

I/F

Ext

erna

l bus

I/F

Ext

erna

l bus

I/F

Ext

erna

l bus

I/F

440

17.5 Data Bus

D-bus

X-busI-bus

F-bus

D-bus

X-busI-bus

F-bus

Bus controller

DMAC

RAM

CP

U

MB91xxx

IO

Bus controller

DMAC

RAM

CP

U

MB91xxx

IO

D-bus

X-busI-bus

F-bus

D-bus

X-busI-bus

F-bus

Bus controller

DMAC

RAM

CP

U

MB91xxx

IO

Bus controller

DMAC

RAM

CP

U

MB91xxx

IO

D-bus

X-busI-bus

F-bus

D-bus

X-busI-bus

F-bus

Bus controller

DMAC

RAM

CP

U

MB91xxx

IO

Bus controller

DMAC

RAM

CP

U

MB91xxx

IO

Read cycle

Read cycle

Read cycle

Write cycle

Write cycle

Write cycle

Built-in IO area => internal RAM area transfer

Internal RAM area => external area transfer

Internal RAM area => built-in IO area transfer

Ext

erna

l bus

I/F

Ext

erna

l bus

I/F

Ext

erna

l bus

I/F

Ext

erna

l bus

I/F

Ext

erna

l bus

I/F

Ext

erna

l bus

I/F

Data buffer Data buffer



441


Flow of Data During Fly-By Transfer

Figure 17.5-2 shows examples of two types of transfer during fly-by transfer.

Figure 17.5-2 Examples of Fly-By Transfer

mem

ory

Fly-by transfer by SDRAM disabled

Fly-by transfer by SDRAM disabled

Memory read by RD or CSxX

IO write by RD or DACK

mem

ory Memory write by WR or CSxX

IO read by WR or DACK

D-bus

X-busI-bus

F-bus

Bus controller

DMAC

RAM

CP

U

MB91xxx

IO

IOIO

D-bus

X-busI-bus

F-bus

Bus controller

DMAC

RAM

CP

U

MB91xxx

IO

Read cycle

Read cycle

Fly-by transfer (memory IO)

Fly-by transfer (IO memory)

Ext

erna

l bus

I/F

Data buffer

Data buffer

442


This chapter gives an overview of the USB function, register configuration and functions, operation of the USB function, and supplementary notes on the USB function.

18.1 Overview of the USB Function

18.2 USB Interface Registers

18.3 Operation of the USB Function

18.4 Supplementary Notes on the USB Function

443



The USB function consists of a protocol engine, physical end points (FIFO buffers) required for data transfer, CPU DMA interface, and other components. The USB function carries out the protocol processing to be done by a USB function device.

Overview of the USB Function

The USB function consists of the following blocks:

USB protocol engine

The USB protocol engine handles the basic USB communication protocol to reduce the load onapplication programs.

Note:

The following processing must be handled by application programs:

- Processing of class and vendor requests

- Set_Descriptor, Get_Descriptor, and Synch_Frame processing for standard requests

FIFO buffers for end points

For control:

IN: 8 bytes

OUT: 8 bytes

For bulk transfer:

IN: 64 bytes × 2 (double buffer)

OUT: 64 bytes × 2 (double buffer)

For interrupt transfer:

IN: 8 bytes

Interface (internal bus interface circuit) between end point and protocol engine

Registers

CPU DMA interface circuit

CPU interface: 16 bits

DMA interface: 16 bits

The USB function macro program operates as a self-powered device.

Table 18.1-1 lists the end points of the USB function.

444


Table 18.1-1 End Points of the USB Function

End point

Configuration Interface ALTERNATE TRANS TYPE Max Packet Size (in bytes)

0 - - - CONTROL 8

1 1 0 0 BULK(OUT) 64

2 1 0 0 BULK(IN) 64

3 1 0 0 INTERRUPT (IN) 8

445


Block Diagram

Figure 18.1-1 shows the block diagram of the USB function.

Figure 18.1-1 Block Diagram of the USB Function

Internal bus (8 bits)

Control and status registers

CPU/DMA interface

Internal bus interface

USB (D+,D-)

Protocol engine

FIFOs for ENDPOINT

CPU (16-bit)/DMA (16-bit) bus

446



This section describes the configuration and functions of the registers used for the USB interface.

USB Interface Registers

The USB interface is connected to the CS2 area via an external memory interface. For theexternal memory interface, see "CHAPTER 3 CPU AND CONTROL UNITS" and "CHAPTER 4EXTERNAL BUS INTERFACE".

Byte access to the internal registers of the USB interface is not allowed.

Figure 18.2-1 shows the register map for the USB interface.

447


Figure 18.2-1 Register Map for the USB Interface

Address Register name

0006_0000 FIFO0o

0006_0002 FIFO0i

0006_0004 FIF01

0006_0006 FIF02

0006_0008 FIF03

Reserved

Reserved

Reserved

Reserved

Reserved

0006_0022 CONT1

0006_0024 CONT2

0006_0026 CONT3

0006_0028 CONT4

0006_002A CONT5

0006_002C CONT6

0006_002E CONT7

0006_0030 CONT8

0006_0032 CONT9

0006_0034 CONT10

0006_0036 TTSIZE

0006_0038 TRSIZE

0006_0040 RSIZE0

0006_0044 RSIZE1

0006_0062 ST1

0006_0068 ST2

0006_006A ST3

0006_006C ST4

0006_006E ST5

448


Notations for Registers

The notations described below are used to explain each USB interface register.

Figure 18.2-2 shows the notations for the registers.

Figure 18.2-2 Notations for Registers

*1: Indicates the bit positions (15 to 0) in each register.

*2: Indicates the bit names in each register.

*3: Indicates that the register does not exist physically. The read value is always "0".

*4: Indicates whether the bit is readable and/or writable.

W: Write only

R: Read only

R/W: Readable and writable

*5: Indicates the bit value after reset (RESET = 0)

"X": Undefined

"0": 0

"1": 1

Note:

Each register must be accessed in units of 16 bits.

bit 15*1 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value*5

Address: 0000-0000H *3 *2 XXXXXXXXXXXXXXXXB

R*4 R R R R R R R R R R R R R R R

449


18.2.1 Data Transmission Registers (for End Points)

Data transmission registers are available in the types listed below. Data is read from or written to an end point by reading from or writing to the corresponding data transmission register.• FIFO0o and FIFO0i• FIFO1 to FIFO3

FIFO0o

The FIFO0o register is an 8-byte FIFO buffer for end point 0 (CONTROL OUT end point). Theaddress of the FIFO0o register is 0006_0000H.

Figure 18.2-3 shows the FIFO0o register.

Figure 18.2-3 FIFO0o Register

Note:

USB transfer data is stored in the register in the order of byte 1 (bits 15 to 8) and byte 2 (bits 7to 0). If only 1 byte of data is stored, it is stored in byte 1 (bits 15 to 8).

FIFO0i

The FIFO0i register is an 8-byte FIFO buffer for end point 0 (CONTROL IN end point). Theaddress of the FIFO0i register is 0006_0002H.

Figure 18.2-4 shows the FIFO0i register.

Figure 18.2-4 FIFO0i Register

Note:


FIFO1

The FIFO1 register is a 64-byte FIFO buffer for end point 1 (BULK OUT end point). Theaddress of the FIFO1 register is 0006_0004H.

Figure 18.2-5 shows the FIFO1 register.

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value

Address: 0006_0000H XXXXXXXXXXXXXXXXB

R R R R R R R R R R R R R R R R



W W W W W W W W W W W W W W W W

450


Figure 18.2-5 FIFO1 Register

Notes:

• USB transfer data is stored in the register in the order of byte 1 (bits 15 to 8) and byte 2 (bits 7to 0). If only 1 byte of data is stored, it is stored in byte 1 (bits 15 to 8).

• The FIFO1 register has a double-buffer configuration (64 bytes x 2). The FIFO buffer isswitched at the following timings:

- On the USB bus side: When ACK is transferred

- On the CPU bus side: When the BFOK1 bit of the CONT3 register is set to "1"

Note that switching is done at DMA transfer because the BFOK1 bit ofthe CONT3 register is automatically set to "1" at DMA transfer.

FIFO2

The FIFO2 register is a 64-byte FIFO buffer for end point 2 (BULK IN end point). The addressof the FIFO2 register is 0006_0006H.



Notes:

• USB transfer data is stored in the register in the order of byte 1 (bits 15 to 8) and byte 2 (bits 7to 0). If only 1 byte of data is stored, it is stored in byte 1 (bits 15 to 8).

• The FIFO2 register has a double-buffer configuration (64 bytes × 2). The FIFO buffer isswitched at the following timings:

- On the USB bus side: When ACK is transferred

- On the CPU bus side: When the BFOK2 bit of the CONT3 register is set to "1"

Note that switching is done at DMA transfer because the BFOK2 bit ofthe CONT3 register is automatically set to "1" at DMA transfer.



R R R R R R R R R R R R R R R R




451


FIFO3

The FIFO3 register is an 8-byte FIFO buffer for end point 0 (INTERRUPT IN end point). Theaddress of the FIFO3 register is 0006_0008H.



Note:



Address: 0006-0008H XXXXXXXXXXXXXXXXB


452


18.2.2 Status Registers

Status registers are available in the types listed below. Internal status is monitored by reading the status registers.• ST1 to ST5• RSIZE0 and RSIZE1

ST1

The ST1 register has interrupt source bits and is used to monitor the ACK and NACK signals forUSB transfer. The address of the ST1 register is 0006_0062H.

Figure 18.2-8 shows the ST1 register.

Figure 18.2-8 ST1 Register

Table 18.2-1 lists the bits of the ST1 register and their functions.


Address: 0006_0062H NACK3

ACK3

NACK2

ACK2

NACK1

ACK1

NACK0i

ACK0i

NACK0o

ACK0o

------0000000000B

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Table 18.2-1 Bits of the ST1 Register (1 / 2)

Bit name Polarity Function

ACK0o ActiveHigh This bit indicates that the device received an ACK handshake signal during OUT transfer at end point 0.

NACK0o ActiveHigh This bit indicates that the device received an NACK handshake signal, received a transfer request in stalled status, or detected a packet error during OUT transfer at end point 0.

ACK0i ActiveHigh This bit indicates that the device received an ACK handshake signal during IN transfer at end point 0.

NACK0i ActiveHigh This bit indicates that the device received a transfer request in stalled status or time-out occurred during IN transfer at end point 0.

ACKn(n: 1 to 3)

ActiveHigh This bit indicates that the device sent and received an ACK handshake signal during transfer at end point n.

453


Notes:

• Each bit is cleared to "0" when "1" is written to the bit. Writing "0" to each bit is ignored.

• The ACK1, NACK1, ACK2, and NACK2 bits provide two sides of registers corresponding to thedouble-buffer configuration. The sides of the ACK1, NACK1, ACK2, and NACK2 bits areswitched at the same time as buffer switching. The side of the ST1 register currently availablefor reading and writing by an application program corresponds to the side of the FIFO registerscurrently available for reading and writing.

ST2

Figure 18.2-9 shows the ST2 register. The address of the ST2 register is 0006_0068H.



NACKn(n: 1 to 3)

ActiveHigh The NACKn bit indicates that the device received an NACK handshake signal, received a transfer request in stalled status, or detected a packet error during OUT transfer at end point n.The NACKn bit indicates also that the device received a transfer request in stalled status or time-out occurred during IN transfer at end point n.

Table 18.2-1 Bits of the ST1 Register (2 / 2)



Address: 0006_0068H DCT6

DCT5

DCT4

DCT3

DCT2

DCT1

DCT0

---------0000000B

R R R R R R R

Table 18.2-2 Bits of the ST2 Register


DCT[6:0] ActiveHigh These bits indicate the number of bytes of data that was read from or written to an FIFO register via the USB bus.These bits are updated when an ACK handshake signal is sent and received after USB transfer has ended normally.

454


ST3


The address of the ST3 register is 0006_006AH.




Address: 0006_006AH STDREQ2

STDREQ1

EPOoNULL

CFGVAL

SETUP

CFEND

SOF

SUSP 00-------0000000B

R R R/W R R/W R R/W R



- - This bit is reserved. It is writable, but writing to this bit has no effect on USB transfer. The value read from this bit is "1" or "0".

SUSP ActiveHigh This bit is reset when the device enters the suspended status and is cleared when the device is released from the suspended status.

SOF ActiveHigh This bit indicates that an SOF packet was received.After this bit is set, the set status is retained until "0" is written to this bit.

CFEND ActiveHigh This bit indicates that initialization of the device was completed.

SETUP ActiveHigh It is set when the macro receives a command that is not responded automatically and returns an ACK signal. It is not set for a command that is responded automatically.It is reset when OUT transfer data other than a SETUP packet is received during Control transfer and an ACK signal is returned.

CFGVAL - This bit indicates the current Configuration value.The macro program enters the default status, when itreceives BUS RESET or SetConfiguration0. CFGVALindicates "0" in the default status.

EPOoNULL ActiveHigh It indicates that the OUT side of ENDPOINT0 received a datapacket of zero length.After this bit is set, the set status isretained until "0" is written to this bit.

STDREQ1 ActiveHigh It indicates that DREQ1 is asserted.

STDREQ2 ActiveHigh It indicates that DREQ2 is asserted.

455

Changed Figure 18.2-10 and Table 18.2-3 in " ST3".


Note:

Only "0" is valid for writing to bit0, bit2, and bit4.

ST4


The address of the ST4 register is 0006_006CH.




Address: 0006_006CH FMR10

FMR9

FMR8

FMR7

FMR6

FMR5

FMR4

FMR3

FMR2

FMR1

FMR0

-----00000000000B

R R R R R R R R R R R



FMR[10:0] - These bits indicate the frame number of the latest frame received by USB transfer.The received-frame number is extracted from an SOF packet.

456

The sentence is changed to Note.


ST5

The ST5 register has interrupt source bits. The address of the ST5 register is 0006_006EH.




Notes:

• Each bit other than the STSTALL bits is cleared to "0" when "1" is written to the bit. Writing "0"to each bit is ignored.

• When an STSTALL bit is set, the NACK bit of the ST1 register is set concurrently.

• To reset the TTRSEND bit, write "0" to the TTRSEND bit after writing "0" to the TTCNTEN bit ofthe CONT10 register to disable the TTSIZE counter.To reset the TRCVEND bit, write "0" to the TRCVEND bit after writing "0" to the TRCNTEN bit ofthe CONT10 register to disable the TRSIZE counter.

• All bits (including TTRSEND and TRCVEND bits) of the ST5 register can be interrupt sources.

• USBRESET can be "1", if it takes 2.5 µs or more to set D+ and D- = L simultaneously.


Address: 0006_006EH LPEND

SETCFG

USBRESET

STSTALL3

STSTALL2

STSTALL1

STSTALL0

TRCVEND

TTRSEND

0--00-----000000B

R/W R/W R/W R R R R R/W R/W



TTRSEND ActiveHigh This bit indicates that data transmission for the specified total number of send bytes from the BULK IN FIFO buffer was completed.

TRCVEND ActiveHigh This bit indicates that data reading for the specified total number of receive bytes from the BULK OUT FIFO buffer was completed.

STSTALLn(n: 0 to 3)

ActiveHigh The STSTALLn bits indicate that end point n is in the stalled status. The bit is reset when the end point is released from the stalled status.

USBRESET ActiveHigh This bit indicates that USB bus reset occurred.

SETCFG ActiveHigh The bit is set when Set Configuration is received and an ACKsignal is returned.It is reset when a USB BUS RESET occurs.

LPEND ActiveHigh It indicates that loop back operation is completed.

457


RSIZE0

The RSIZE0 register indicates the size of the latest data transferred at end point 0 (CONTROLOUT end point). The address of the RSIZE0 register is 0006_0040H.

Figure 18.2-13 shows the RSIZE0 register.

Figure 18.2-13 RSIZE0 Register

Table 18.2-6 lists the bits of the RSIZE0 register and their functions.

Note:

The RSIZE0 bits are updated when the USB function macro program transmits an ACK signal.


Address: 0006_0040H RSIZE03

RSIZE02

RSIZE01

RSIZE00

------------0000B

R R R R

Table 18.2-6 Bits of the RSIZE0 Register


RSIZE[3:0] - These bits indicate the size of the latest data transferred at end point 0 (CONTROL OUT end point).

458


RSIZE1

The RSIZE1 register indicates the size of the latest data transferred at end point 1 (BULK OUTend point). The address of the RSIZE0 register is 0006_0044H.

Figure 18.2-4 shows the RSIZE1 register.

Figure 18.2-14 RSIZE1 Register

Table 18.2-7 lists the bits of the RSIZE1 register and their functions.

Notes:

• The RSIZE1 register has two sides corresponding to the double-buffer configuration. The sidesof the RSIZE1 register are switched at the same time as buffer switching. The side of theRSIZE1 register currently available for reading and writing by an application programcorresponds to the side of the FIFO register currently available for reading and writing.

• The RSIZE1 bits are updated when the USB function macro program transmits an ACK signal.


Address: 0006_0044H RSIZE16

RSIZE15

RSIZE14

RSIZE13

RSIZE12

RSIZE11

RSIZE10

---------0000000B

R R R R R R R

Table 18.2-7 Bits of the RSIZE1 Register


RSIZE1[6:0] - These bits indicate the size of the latest data transferred at end point 1 (BULK OUT end point).

459


18.2.3 Control Registers

Control registers are available in the types listed below. The device is controlled by reading from or writing to the control registers.• CONT1 to CONT10• TTSIZE• TRSIZE• RESET

CONT1

The CONT1 register is used to initialize the device and resume device operation. The addressof the CONT1 register is 0006_0022H.

Figure 18.2-15 shows the CONT1 register.

Figure 18.2-15 CONT1 Register


Address: 0006_0022H LPSTART

IODIS

AUTOBFOK

RESUM

S TALL3

S TALL2

S TALL1

S TALL0

CFGEN 000--0-----00000B

R/W R/W R/W R/W R/W R/W R/W R/W R/W

460

Changed Figure 18.2-15 in " CONT1".


Table 18.2-8 lists the bits of the CONT1 register and their functions.

Notes:

• Only "1" is valid for writing to the CFGEN bit.

• The STALL bit may be set for an end point and a transfer request is sent to the end point. Insuch a case, the STALL bit is reset when a STALL handshake signal is sent for the request.

Table 18.2-8 Bits of the CONT1 Register


CFGEN ActiveHigh Writing "1" to this bit executes initialization (setup of(ENDPOINT BUFFER). After this bit is set to "1", the setstatus is retained until "0" is written to the bit.Once the initialization is executed (setup of (ENDPOINTBUFFER), it cannot be initialized (setup of ENDPOINTBUFFER) until the macro program is reset.

STALLn(n: 0 to 3)

ActiveHigh Writing "1" to the STALLn bit sets end point n into the stalled status.Note:

This bit is a self-reset register.After "1" is written to this bit, it is automatically cleared to "0".

RESUM ActiveHigh This bit is used to issue a request to resume operation of the device after the device is set into the suspended status (ST3:SUSP=1). (Writing 1 to this bit sets a resume request.)Writing "1" to this bit is enabled when the SUSP bit of the ST3 register is set to "1".This bit is a self-reset register. After "1" is written to this bit, it is automatically cleared to "0".

AUTOBFOK ActiveHigh Writing "1" to this bit automatically enables USB transfer onthe OUT side of ENDPOINT0, if the number of bytesreceived on the OUT side of ENDPOINT0 is "0". In this case,the interrupt factor ST1:ACK0o is not asserted. (TheBFOK0o bit of the CONT3 register is set to "1"automatically.)

IODIS ActiveHigh Setting this bit to "1" asserts the SUSPEND signal (macrooutput signal).The SUSPEND signal is asserted when this bit is set or thedevice is set into the suspended status.

LPSTART ActiveHigh Setting this bit to "1" starts loop back operation.This bit is a self-reset register. After the completion of theloop back operation, it is automatically cleared to "0".

461

Changed Table 18.2-8 in " CONT1". (The sentence is changed to Notes.)


CONT2

The CONT2 register is used to initialize the FIFO registers. The address of the CONT2 registeris 0006_0024H.





Address: 0006-0024H INI3

INI2

INI1

INI0i

INI0o

-----------00000B

R/W R/W R/W R/W R/W

Table 18.2-9 Bits of the CONT2 Register (1 / 2)


INI0o ActiveHigh Writing "1" to this bit initializes the address counter of the FIFO0o register. At the same time, the ACK0o and NACK0o bits of the ST1 register, the RSIZE0 register, and the BFOK0o bit of the CONT3 register are initialized.This bit is a self-reset register.After "1" is written to this bit, it is automatically cleared to "0".

INI0i ActiveHigh Writing "1" to this bit initializes the address counter of the FIFO0i register. At the same time, the ACK0i and NACK0i bits of the ST1 register, the BFOK0i bit of the CONT3 register, and the LSTD0 bit of the CONT10 register are initialized.This bit is a self-reset register. After "1" is written to this bit, it is automatically cleared to "0".

INI1 ActiveHigh Writing "1" to this bit initializes the address counter of the FIFO1 register. At the same time, the double-buffer switching status, the ACK1 and NACK1 bits of the ST1 register, the RSIZE1 register, the BFOK1 bit of the CONT3 register, and the TRSIZE register are initialized.This bit is a self-reset register.After "1" is written to this bit, it is automatically cleared to "0".

462


Notes:

• Only "1" is valid for writing to every bit of the CONT2 register.

• Each bit of the CONT2 register is cleared to "0" automatically after "1" is written to each bit.Therefore, the value of each bit normally read by the CPU is always "0".

• All bits of the registers (ST1, RSIZE1, CONT3, and CONT10) that have two sides correspondingto the double-buffer configuration (end points 1 and 2) are initialized when the INI1 or INI2 bit isset.

• Reading and writing of the FIFO buffer and other registers initialized by setting the INIn bit (n:0o, 0i, 1, 2, or 3) are disabled until nine cycles are counted by FMCLK0 after the INIn bit is set.

INI2 ActiveHigh Writing "1" to this bit initializes the address counter of the FIFO2 register. At the same time, the double-buffer switching status, the ACK2 and NACK2 bits of the ST1 register, the BFOK2 bit of the CONT3 register, the LSTD2 bit of the CONT10 register, and the TISIZE register are initialized.This bit is a self-reset register.After "1" is written to this bit, it is automatically cleared to "0".

INI3 ActiveHigh Writing "1" to this bit initializes the address counter of the FIFO3 register. At the same time, the ACK3 and NACK3 bits of the ST1 register, the BFOK3 bit of the CONT3 register, and the LSTD3 bit of the CONT10 register are initialized.This bit is a self-reset register.After "1" is written to this bit, it is automatically cleared to "0".

Table 18.2-9 Bits of the CONT2 Register (2 / 2)


463


CONT3

The CONT3 register is used to enable USB transfer at each end point. The address of theCONT3 register is 0006_0026H.




Notes:

• If the ACK0o or ACK0i bit of the ST1 register is set for an end point, the BFOK bit correspondingto the end point cannot be set. However, even if the NACK0o or NACK0i bit of the ST1 registeris set for an end point, the BFOK bit corresponding to the end point can be set. When deviceinitialization is completed (when the CFEND bit of the ST3 register is set) or the INIn bit of theCONT2 register is set, the BFOK bits are set to values as follows:

• End point for IN transfer:BFOK = 0

• End point for OUT transfer: BFOK = 1

• Only "1" is valid for writing to the BFOK1 and BFOK2 bits (for double-buffer end points).To set an FIFO buffer into the busy status after writing "1" to the corresponding BFOK bit of theCONT3, use the CONT4 or CONT5 register to set it into the busy status.

• Writing "1" to the BFOK1 and BFOK2 bits (for double-buffer end points) switches the side of thedouble buffer. At the same time, the side of the CONT3 registers is switched accordingly. Theside of the CONT3 register currently available for reading and writing by an application programcorresponds to the side of the FIFO registers currently available for reading and writing. Anapplication program can access only one side of registers and cannot access the other side ofthe registers.

• Each BFOK bit is reset when ACK transfer occurs at the corresponding end point.

• Each BFOK bit is reset to "0" when the INI bit of CONT2 is set.


Address: 0006-0026H BFOK3

BFOK2

BFOK1

BFOK0i

BFOK0o

-----------00000B

R/W R/W R/W R/W R/W



BFOK0o ActiveHigh Enables USB transfer on the OUT side of ENDPOINT0.

BFOK0i ActiveHigh Enables USB transfer on the IN side of ENDPOINT0.

BFOKn(n: 1 to 3)

ActiveHigh Enables USB transfer on ENDPOINT0[n].

464

Changed " CONT3". (The sentence is changed to Notes.)


CONT4

The CONT4 register is used to set each end point into the USB busy status. The address of theCONT4 register is 0006_0028H.




Note:

To perform transfer by CPU access, write "1" to the FIFOBUSYn bit. Writing "0" to the FIFOBUSYnbit declares the busy status to the host personal computer. Then, the device returns a NACKhandshake signal in response to a token from the host personal computer. Always write "0" to thisbit for DMA transfer.


Address: 0006_0028H FIFOBUSY3

FIFOBUSY2

FIFOBUSY1

FIFOBUSY0i

FIFOBUSY0o

-----------00000B

R/W R/W R/W R/W R/W



FIFOBUSY (n: 0o, 0i, 1

to 3)

ActiveLow This bit is used to set end point n into the busy status.

465


CONT5

The CONT5 register is used to set each end point into USB busy status. The address of theCONT5 register is 0006_002AH.




Notes:

• To perform transfer by DMA, write "1" to the DFIFOBUSYn bit. Writing "0" to the DFIFOBUSYnbit declares the busy status to the host personal computer. Then, the device returns a NACKhandshake signal in response to a token from the host personal computer. Always write "0" tothis bit for transfer by CPU access.

• Be sure to write "0" to the DFIFOBUSYn bit after writing "0" to the MDREQn bit to mask DREQ.


Address: 0006_002AH DFIFOBUSY2

DFIFOBUSY1

------------00--B

R/W R/W



DFIFOBUSYn (n: 1, 2)

ActiveLow This bit is used to set end point n into the busy status.

466


CONT6

The CONT6 register is used to mask DREQ at each end point. The address of the CONT6register is 0006_002CH.





Address: 0006_002CH MDREQ2

MDREQ1

------------00--B

R/W R/W



MDREQn(n: 1, 2)

ActiveLow This bit is used to mask DREQn assertion during transfer at end point n.

467


CONT7

The CONT7 register is used to mask the IRQ due to an ACK source at each end point. Theaddress of the CONT7 register is 0006_002EH.





Address: 0006_002EH MACK3

MACK2

MACK1

MACK0i

MACK0o

-----------00000B

R/W R/W R/W R/W R/W



MACK0o ActiveLow This bit is used to mask IRQ assertion by an ACK signal during OUT transfer at end point 0.

MACK0i ActiveLow This bit is used to mask IRQ assertion by an ACK signal during IN transfer at end point 0.

MACKn(n: 1 to 3)

ActiveLow This bit is used to mask IRQ assertion by an ACK signal during transfer at end point n.

468


CONT8

The CONT8 register is used to mask the IRQ due to an NACK source at each end point. Theaddress of the CONT8 register is 0006_0030H.





Address: 0006-0030H MNACK3

MNACK2

MNACK1

MNACK0i

MNACK0o

-----------00000B

R/W R/W R/W R/W R/W



MNACK0o ActiveLow This bit is used to mask IRQ assertion by a NACK signal during OUT transfer at end point 0.

MNACK0i ActiveLow This bit is used to mask IRQ assertion by a NACK signal during IN transfer at end point 0.

MNACKn(n: 1 to 3)

ActiveLow This bit is used to mask IRQ assertion by a NACK signal during transfer at end point n.

469


CONT9

The CONT9 register is used to mask the IRQ due to a STALL source at each end point. Theaddress of the CONT9 register is 0006_0032H.





Address: 0006-0032H MLPEND

MSETCFG

MUSBRESET

MSTALL3

MSTALL2

MSTALL1

MSTALL0

0--0----0---0000B

R/W R/W R/W R/W R/W R/W R/W



MSTALLn (n: 0 to 3)

ActiveLow This bit is used to mask IRQ assertion by a STALL signal at end point n.

MUSBRESET ActiveLow This bit is used to mask IRQ assertion by a USB bus reset signal.

MSETCFG ActiveLow This bit is used to mask IRQ.

MLPEND ActiveLow This bit is used to mask IRQ assertion by LPEND.

470

Changed Figure 18.2-23 and Table 18.2-16 in " CONT9".



CONT10

The address of the CONT10 register is 0006_0034H.





Address: 0006_0034H DREQCNT

NULLSET3

NULLSET2

NULLSET0

DMAMODE

LSTD3

LSTD2

LSTD0

TRCNTEN

TTCNTEN

ODD

0---000--000000-B

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W



LSTDn(n: 0, 2, 3)

ActiveHigh The LSTDn bit is used to report writing of the last packet to ENDPOINT[n] .This bit is set before writing the last data.

ODD ActiveHigh This bit is used to report writing of a short packet having an odd byte count.This bit is set before writing the last data.

TTCNTEN ActiveHigh This bit is used to enable the total send byte counter.

TRCNTEN ActiveLow This bit is used to enable the total receive byte counter.

DMAMODE ActiveHigh This bit is used to set DMA in single transfer mode.1: Single transfer, 0: Block transfer

NULLSETn (n: 0, 2, 3)

ActiveHigh This bit is set to "1" for automatic transmission of a null packet.

DREQCNT - This bit is used to control DREQ assertion when theamount of data indicated by the total transfer bytecount has been transferred.1: Does not assert DREQ, once the amount of data

indicated by the total transfer byte count has beentransferred, until another total transfer byte count isset.

0: Asserts DREQ, once the amount of data indicated bythe total transfer byte count has been transferred.

471




Notes:

• The LSTD bit need not be reset by the CPU because the bit is reset automatically at reception ofan ACK signal after the last packet has been transmitted. The ODD bit need not be reset by theCPU because the bit is reset automatically after the last data has been written.

• The NULLSET bit is valid for the data stage of control transfer and for BULK IN transfer,interrupt IN transfer. If the NULLSET bit is set to "1", a null packet is transmitted automatically inresponse to the transfer request after the last packet is transmitted when the size of the lastpacket is equal to the maximum packet size. Note that the NULLSET bit does not control thetransmission of 0-byte packets in the status stage of control transfer.

• The LSTD2 bit provides two sides of registers corresponding to the double-buffer configuration.The sides of the LSTD2 bit are switched at the same time as buffer switching. The side of theCONT10 register currently available for reading and writing by an application programcorresponds to the side of the FIFO registers currently available for reading and writing.

• The LSTD2 has the above function. When the value of the LSTD2 bit changes from "1" to "0", itdoes not mean that transfer of the last packet ended.

• If the NULLSET bit is "1", an interrupt by an ACK signal is asserted when transfer of null packetsends with an ACK signal (when an ACK signal is received). If the NULLSET bit is "0", aninterrupt by an ACK signal is asserted when transfer of the last packet ends with an ACK signal(when an ACK signal is received).

• Regardless of which value the DREQCNT bit contains, it does not assert DREQ1, unless thereceive data is stored in FIFO when the amount of data indicated by the total receive bytecounter TRSIZE has been written.

TTSIZE

The TTSIZE register is used to set and count the total send byte count for BULK IN transfer.The address of the TTSIZE register is 0006_0036H.

Figure 18.2-25 shows the TTSIZE register.

Figure 18.2-25 TTSIZE Register

Notes:

• The TTSIZE register (counter) counts down each time send data is written to the FIFO buffer fortransmission.

• To use the TTSIZE counter, set a value other than 0000H in the TTSIZE register, write "1" to theTTCNTEN bit of the CONT10 register, then start write access to the FIFO buffer. Do not startwrite access to the FIFO buffer when 0000H is set in the TTSIZE register and the TTCNTEN bitof the CONT10 is "1".

• Set TTSIZE after making sure that the MDREQ bit of the CONT6 register is set to "0" andDREQ2 is masked.


Address: 0006_0036H 0001000100010001B


472

Changed " TTSIZE". (The sentence is changed to Notes.)

The sentence is changed to Notes.


TRSIZE

The TRSIZE register is used to set and count the total receive byte count for BULK OUTtransfer. The address of the TRSIZE register is 0006_0038H.

Figure 18.2-26 shows the TRSIZE register.

Figure 18.2-26 TRSIZE Register

Notes:

• The TRSIZE register (counter) counts down each time receive data is read from the FIFO bufferfor reception.

• To use the TRSIZE counter, set a value other than 0000H in the TRSIZE register, write "1" to theTRCNTEN bit of the CONT10 register, then start read access to the FIFO buffer. Do not startread access to the FIFO buffer when 0000H is set in the TRSIZE register and the TRCNTEN bitof the CONT10 is "1".

• Set TRSIZE after making sure that the MDREQ1 bit of the CONT6 register is set to "0" andDREQ1 is masked.

RESET

When the USB operation is started, the synchronization RESET is required to input 16 clocksmore than by the USB clock for RESET of USB, see "APPENDIX D USB Clock".


Address: 0006_0038H 0001000100010001B


473

Changed " TRSIZE". (The sentence is changed to Notes.)


Register Map

Address Register name0006_0000 FIFO0o

0006_0002 FIFO0i

0006_0004 FIFO1

0006_0006 FIFO2

0006_0008 FIFO3

Reserved

0006_0022 CONT1

0006_0024 CONT2

0006_0026 CONT3

0006_0028 CONT4

0006_002A CONT5

0006_002C CONT6

0006_002E CONT7

0006_0030 CONT8

0006_0032 CONT9

0006_0034 CONT10

0006_0036 TTSIZE

0006_0038 TRSIZE

Reserved

0006_0040 RSIZE0

Reserved

0006_0044 RSIZE1

Reserved

0006_0062 ST1

Reserved

0006_0068 ST2

0006_006A ST3

0006_006C ST4

0006_006E ST5

Reserved

0006_FFFE RESET

474

Changed the table of " Register Map". (Address: 0006_007E → 0006_FFFE )



This section describes the flow of data transfer, CPU access operation, and DMA operation by the USB function.

Operation of the USB Function

This section explains the following items of operation:

• Flow of data transfer

• Setup stage of control transfer (most standard commands)

• Setup stage of control transfer (class and vendor commands and some standardcommands [Get_Descriptor, Set_Descriptor, and Synch_Frame])

• Status stage of control transfer (most standard commands)

• Status stage of control transfer (class and vendor commands and some standardcommands [Get_Descriptor, Set_Descriptor, and Synch_Frame])

• Control transfer (data stage) or BULK OUT transfer

• Control transfer (data stage), bulk transfer, or INTERRUPT IN transfer

• CPU access operation

• CPU IN transfer

• CPU OUT transfer

• DMA operation

• DMA IN transfer

• DMA OUT transfer

• Read and write timing diagrams for DMA single transfer

• Read and write timing diagrams for DMA block transfer

• Interrupt sources

• Setting of end point buffer

• Examples of software control

• Setup

• Reception at CPU access

• Transmission at CPU access

• DMA reception

• DMA transmission

475


18.3.1 Flow of Data Transfer

This section describes the flow of data transfer by the USB function.

Setup Stage of Control Transfer (Most Standard Commands)

The protocol engine automatically processes almost all standard commands received from thehost to reduce the load on the CPU of the device. The CPU of the device need not perform anyprocessing of these commands. The protocol engine does not even report reception of thesecommands to the CPU of the device. The protocol engine automatically processes thecommands listed below.

• Clear_Feature

• Get_Configuration

• Get_Interface

• Get_Status

• Set_Address

• Set_Configuration

• Set_Feature

• Set_Interface

Figure 18.3-1 shows the flow of the setup stage of control transfer (to process most standardcommands).

Figure 18.3-1 Flow of the Setup Stage of Control Transfer (to Process Most Standard Commands)

The flow shown by the figure is explained below.

1. When a command for the setup stage of control transfer is received from the USB, theprotocol engine asserts the SETUP pin and sets the SETUP bit of the status register.

2. If a standard command other than Get_Descriptor, Set_Descriptor, and Sync Frame isreceived and the setup stage ends, the protocol engine sets the NACKOS bit of the statusregister. In this case, the protocol engine performs the processing required for the commandand does not write data to any FIFO buffer for the end point.

Protocol engine

Inte

rnal

bus

Inte

rnal

bus

I/F


Control and

status registers

CP

U I/

F

1)

2)

CP

U B

US

USB

476


Note:

The CPU (application program) need not perform any processing.

If the setup stage command is received normally, an ACK handshake signal is transferred tothe USB. If the setup stage command is not received normally, nothing is transferred to theUSB (time-out occurs).

Setup Stage of Control Transfer (Class and Vendor Commands and Some Standard Commands [Get_Descriptor, Set_Descriptor, and Synch_Frame])

The class and vendor commands and some standard commands (Get_Descriptor,Set_Descriptor, and Synch_Frame) received from the host are written to the FIFO buffer forOUT transfer at end point 0.

Figure 18.3-2 shows the flow of the setup stage of control transfer (to process class and vendorcommands and some standard commands [Get_Descriptor, Set_Descriptor, andSynch_Frame]).

Figure 18.3-2 Flow of the Setup Stage of Control Transfer (to Process Class and Vendor Commands and Some Standard Commands [Get_Descriptor, Set_Descriptor, and Synch_Frame])


1. When the setup stage of control transfer is started by the USB, the protocol engine assertsthe SETUP pin and sets the SETUP bit of the status register.

2. If a Get_Descriptor, Set_Descriptor, Sync Frame, class, or vendor command is received, theprotocol engine writes the data in the setup stage to the FIFO0o register and increments thevalue of the write transfer size register.

3. If the setup stage ends normally, the protocol engine transmits an ACK handshake signal tothe USB. At this time, the ACK0o bit of the ST1 register (status register) is set and the valueof the write transfer size register is loaded into the RSIZE0 register (status register). Theprotocol engine also asserts the IRQ pin to externally report that data in the setup stage wasreceived.If the setup stage does not end normally because of an error, the protocol engine does notreturn anything to the USB, discards the received data, and sets the NACK0o bit of thestatus register.

4. Valid data is read from the FIFO0o register into the CPU interface.

Note:

A command received as data must be decoded and processed by an application program.

Protocol engine


Control and

status registers

C

PU

I/F

1)

2)

3)

4)

USB

Inte

rnal

bus C

PU

BU

S

Inte

rnal

bus

I/F

477


Status Stage of Control Transfer (Most Standard Commands)

The protocol engine automatically processes all the standard commands (exceptGet_Descriptor, Set_Descriptor, and Sync Frame) as listed below. When these commands areprocessed, the values of the status registers in the device do not change and any interruptsignal IRQ is not asserted.

• Clear Feature

• Get Configuration

• Get Interface

• Get Status

• Set Address

• Set Configuration

• Set Feature

• Set Interface

Status Stage of Control Transfer (Class and Vendor Commands and Some Standard Commands [Get_Descriptor, Set_Descriptor, and Synch_Frame])

For writing control data

The protocol engine transfers 0-byte data to the USB. If the transfer ends normally, the ACK0ibit of the status register is set and the IRQ pin is asserted.

To prepare for the next transfer, the IRQ pin must be deasserted (by resetting the ACK0i bit ofthe status register) and the BFOK0i bit of the control register must be set by the applicationprogram.

Note:

The application program need not make any setting for transfer of 0-byte data.

For reading control data

The protocol engine receives 0-byte data from the USB.

Note:

The RSIZE0 register indicates a receive transfer size of 0 bytes.

When the transfer ends normally, the ACK0o bit of the status register is set and the IRQ pin isasserted.

To prepare for the next transfer, the IRQ pin must be deasserted (by resetting the ACK0o bit ofthe status register) and the BFOK0o bit of the control register must be set by the applicationprogram.

478


Control Transfer (Data Stage) and BULK OUT Transfer

Transfer data is written to the FIFO buffer for OUT transfer at an end point and read via the localbus interface.

Figure 18.3-3 shows the flow of control transfer (data stage) and BULK OUT transfer.

Figure 18.3-3 Flow of Control Transfer (Data Stage) and BULK OUT Transfer


1) When transfer in the OUT direction is started by the USB, the protocol engine outputs theaddress of the transfer-destination end point and transmits transfer data sequentially to theinternal bus while executing a CRC check, bit stripping, and serial-to-parallel conversion.

Notes:

• If the BFOK bit of the control register corresponding to the transfer-destination end point isnot set when the transfer in the OUT direction is started, the protocol engine outputs a NACKhandshake signal to the USB and terminates the transfer.

• If the STALL bit of control register corresponding to the transfer-destination end point is setwhen transfer in the OUT direction is started, the protocol engine outputs a STALLhandshake signal to the USB and terminates the transfer. Then, the NACK bit of the ST1register (status register) and the STSTALL bit of the ST5 register (status register) are set.

2) Received data is written to the FIFO buffer for the transfer-destination end point via theinternal bus, and the value of the transfer size register is incremented.

3) When transfer of one packet ends normally, the protocol engine outputs an ACK handshakesignal to the USB. Then, the ACK bit of the status register is set and the value of thetransfer size register is loaded into the RSIZE0 or RSIZE1 register. The protocol enginealso asserts the IRQ pin to externally report that transfer of one packet has ended. If anerror is detected during transfer, the NACK bit of the status register is set and the transfer isterminated.

4) Valid data is read from the FIFO buffer for the end point via the CPU interface.

Protocol engine


Control and

status registers

1)

2)

3)

4)

USB

Inte

rnal

bus CP

U I/

F

CP

U B

US

Inte

rnal

bus

inte

rfac

e

479


Notes:

• For reading by the CPU, data is read from bits 15 to 0 of the DATAO register in units of 2bytes.

• If the data size of a packet normally received during BULK OUT transfer is 0 bytes, themacro program does not generate any interrupt.

Control Transfer (Data Stage), bulk Transfer, or INTERRUPT IN Transfer

The data written from the local bus interface to the FIFO buffer for IN transfer at an end point istransferred by the protocol engine to the USB bus.

Figure 18.3-4 shows the flow of control transfer (data stage), bulk transfer, and INTERRUPT INtransfer.

Figure 18.3-4 Flow of Control Transfer (Data Stage), Bulk Transfer, and INTERRUPT IN Transfer


1) Before the IN transfer to the USB, data is written from the CPU interface to the FIFO bufferfor an end point by a write operation.

Note:

• Valid data is written from the CPU to bits 15 to 0 of the DATAI register in units of 2 bytes.

2) If the BFOK bit of the control register corresponding to the transfer-destination end point isset, subsequent IN transfer requests from the USB to the end point are processed.

31 . . . . . 8 7 6 5 4 3 2 1 0

63 . . . . . 17 15 13 11 9 7 5 3 1

Writing by protocol

engine

62 . . . . . 16 14 12 10 8 6 4 2 0

FIFO pointer

FIFO buffer for

end point

Via CPU interface

Protocol engine


Controland

status registers

1)

2)

3) 4)

USB

Inte

rnal

bus

Inte

rnal

bus

inte

rfac

e

CP

U I/

F

CP

U B

US

63 . . . . . 8 7 6 5 4 3 2 1 0

63 . . . . . 17 15 13 11 9 7 5 3 1

Reading by the

protocol engine

62 . . . . . 16 14 12 10 8 6 4 2 0

FIFO pointer

Writing from the

CPU I/F

FIFO buffer for end point

480


Notes:

• If an IN transfer request from the USB is received at the end point before the BFOK bit isset, the NACK bit of the status register is set and an NACK handshake signal is returned tothe USB.

• If the STALL bit of control register is set when an IN transfer request from the USB isreceived, a STALL handshake signal is returned to the USB.Then, the NACK bit of the ST1 register (status register) and the STSTALL bit of the ST5register (status register) are set.

3) When an IN transfer request is received from the USB, the protocol engine reads, from theFIFO buffer for the end point, as much transfer data as the number of bytes written to theFIFO buffer.

4) The protocol engine executes parallel-to-serial conversion, CRC generation, and bit stuffingfor the data read from the FIFO buffer for the end point then outputs the processed data tothe USB. If the transfer ends normally (an ACK handshake is received), the ACK bit of thestatus register is set. If the transfer fails, the NACK bit of the status register is set.

Note:

The data of FIFO is not initialized when failing in forwarding. The same data is automaticallyretransmitted to the following IN transfer request.

481


18.3.2 CPU Access Operation

This section describes the CPU access operation by the USB function.

CPU IN Transfer

For CPU IN transfer, data is written to an FIFO buffer for IN transfer, then the BFOK bit of thecontrol register corresponding to the FIFO buffer is set to enable transfer. The USB functionmacro program has a counter function to count the total number of send bytes. This functioncan be used to simplify the setting of the last packet transmission. IN transfer can also be donewithout using the counter function. The setting of the last packet transmission varies dependingon whether the counter function is used.

Total send byte counter (16 bits)

The total send byte counter counts the total number of bytes of the data to be transmitted. Thecounter counts down each time data is written to the FIFO buffer. To use the counter, thesystem must set a total send byte count in the TTSIZE register. The counter cannot be used forcontrol transfer.

Data transmission

For data transmission, one packet (Max 64 bytes) of data is written to an end point buffer, thenthe BFOK bit of the control register corresponding to the end point buffer is set by the system toenable transfer.

Last packet

The setting for transmission of the last packet varies depending on whether the total send bytecounter is used or not. The settings in both cases are explained below.

When using the total send byte counter:

Transmission is done according to the packet size of the last packet* as follows:

• Maximum-size packet

A null packet is sent automatically after packet transmission ends. Automatic transmissionof a null packet can be disabled by using the NULLSET bit of the control register.

• Even-byte short packet

Packet transmission is started when the BFOK bit (to enable transfer) of the control registeris set.

• Odd-byte short packet

Transmission is the same as that for the even-byte short packet.

When the total send byte counter is not used:

The LSDT bit of the control register is used (it is set before writing of the last data) to reportwriting of the last data.



A null packet is sent automatically after packet transmission ends. Automatic transmissionof a null packet can be disabled by using the NULLSET bit of the control register.

482





The ODD bit of the control register is set to report writing of a packet having an odd numberof bytes before writing the last data.


* : Packet size of the last packet

Maximum-size packet: A packet whose packet size is the maximum limit (64 bytes)

Even-byte short packet: A packet whose packet size is less than the maximum limit andwhose number of bytes is even

Odd-byte short packet: A packet whose packet size is less than the maximum limit andwhose number of bytes is odd

Note:

If automatic transmission of a null packet is enabled, no interrupt occurs until transmission ofthe null packet ends normally after the last data has been written.

If automatic transmission of a null packet is disabled, no interrupt occurs until transmission ofthe last packet ends normally after the last data has been written.

Table 18.3-1 lists the register settings for CPU IN transfer.

(O: Setting Required)

Table 18.3-1 Register Settings for CPU IN Transfer

TTSIZE (register

BFOK (register)

LSTD (register)

ODD (register)

Packet other than last packet Used O

Last packet Maximum-size packet

Even-byte packet

Odd-byte packet

Packet other than last packet Not used

Last packet Maximum-size packet O

Even-byte packet O

Odd-byte packet O O

483


CPU OUT Transfer

For CPU OUT transfer, received data is read from an FIFO buffer for OUT transfer, then theBFOK bit of the control register corresponding to the FIFO buffer is set to enable transfer. TheUSB function macro program has a counter function to count the total number of receive bytes.This function can be used to know when reading of all received data is completed. OUTtransfer can also be done without using the counter. The interrupt indicating completion of thetotal transfer is generated only when the counter is used. Therefore, if the counter is not used,the CPU must determine the completion of transfer from the ACK interrupt indicating thecompletion of transmission.

Data reception

When readable data is stored in an end point buffer, the USB function macro program throwsthe interrupt request IRQ. The size of received data is set in the RSIZE register (receive datasize register). After the size of received data is read from the RSIZE register, data of that size isread from the end point buffer. After the data is read from the end point buffer, the BFOK bit ofthe control register corresponding to the end point buffer is set by the system to enable transfer.

Total receive byte counter (16 bits)

The USB function macro program has a counter function to count the total number of receivebytes.

The total receive byte counter counts down each time the CPU reads received data from therelevant FIFO buffer. The initial value of the counter is set in the TRSIZE register. Interrupt IRQis generated when the count reaches 0. This indicates that reading of all received data hasbeen completed. The counter cannot be used for control transfer.

Note:

If the data size of a packet normally received during BULK OUT transfer is 0 byte, the macroprogram does not generate any interrupt.

484


18.3.2.1 DMA Operation

This section describes the DMA operation by the USB function. The DMA transfer by the USB function is available in two modes: single transfer and block transfer.One of the DMA transfer modes (single transfer or block transfer) can be selected using the DMAMODE bit of the CONT10 register (control register).DMA transfer can be applied to BULK IN transfer and BULK OUT transfer.Data other than 0-byte data can be transferred by DMA transfer.

DMA IN Transfer

For DMA IN transfer, data is written to an FIFO buffer for IN transfer, then the BFOK bit of thecontrol register corresponding to the FIFO buffer is automatically set to enable transfer. TheUSB function macro program has a counter function to count the total number of send bytes.Using this counter function enables automatic transmission of the last packet.

Total send byte counter (16 bits)

The total send byte counter counts the total number of bytes of the data to be transmitted. Thecounter counts down each time data is written to the FIFO buffer. For the counter, a total sendbyte count is set in the TTSIZE register by the system. The counter cannot be used for controltransfer or interrupt transfer.

Data transmission

Data transmission is started automatically when the relevant FIFO buffer (64 bytes) becomesfull or writing of the last packet ends.

Transmission of the last packet is explained below.

Transmission of the last packet



Packet transmission is started automatically when the amount of data indicated by the totalsend byte count in the TTSIZE register has been written. A null packet is sent automaticallyafter packet transmission ends. Automatic transmission of a null packet can be disabled byusing the NULLSET bit of the control register.


Packet transmission is started automatically when the amount of data indicated by the totalsend byte count in the TTSIZE register has been written.


Transmission is the same as that for the even-byte short packet.

* : Packet size of the last packet

Maximum-size packet: A packet whose packet size is the maximum limit (64 bytes)Even-byte short packet: A packet whose packet size is less than the maximum limit and

whose number of bytes is even Odd-byte short packet: A packet whose packet size is less than the maximum limit and

whose number of bytes is odd

485


Note:

If automatic transmission of a null packet is enabled, a subsequent DREQ is not generateduntil transmission of the null packet ends normally after the last data has been written.

If automatic transmission of a null packet is disabled, a subsequent DREQ is not generateduntil transmission of the last packet ends normally after the last data has been written.

DMA OUT Transfer

For DMA OUT transfer, received data is read from an FIFO buffer for OUT transfer, then theUSB function macro program automatically sets the BFOK bit of the control registercorresponding to the FIFO buffer to enable transfer. The USB function macro program has acounter function to count the total number of received bytes. This function can be used to knowwhen reading of all received data is completed. OUT transfer can also be done without usingthe counter. The interrupt indicating completion of the total transfer is generated only when thecounter is used. Therefore, if the counter is not used, completion of transfer must bedetermined by another method.

Data reception

When readable data is stored in an end point buffer, the USB function macro program throwsDREQ. After all the data is read from the FIFO buffer, the USB function macro programautomatically sets the BFOK bit of the control register to enable transfer.

Total receive byte counter (16 bits)

The USB function macro program has a counter function to count the total number of receivebytes.

The total receive byte counter counts down each time the DMAC reads received data from therelevant FIFO buffer. The initial value of the counter is set in the TRSIZE register. Interrupt IRQis generated when the count reaches 0. This indicates that reading of all received data hasbeen completed. The counter cannot be used for control transfer.

Note:

To perform BULK OUT transfer by the CPU after DMA OUT transfer ends, the INI1 bit of theCONT2 register must be set to initialize the ACK and NACK bits (interrupt source bits) onboth sides of the ST1 register.

486


Read and Write Timing Diagrams for DMA Single Transfer

FR corresponds to that of block of step transfer.

Figure 18.3-5 shows the read and write timing diagrams for DMA single transfer.

Figure 18.3-5 Read and Write Timing Diagrams for DMA Single Transfer

(Writing)

DREQ2

FMCLK0

DACK2

WR

DATAI[15:0]

Valid data

Last data

DACK and DATAI must not be changed while WR is at the low level.

DREQ is negated at the first rising edge of FMCLK0 after DACK is asserted.

DREQ is negated at the first rising edge of FMCLK0 after DACK is asserted.

Note 1: Frequency of FMCLK0 is 13 MHz or more.

RD

DREQ1

FMCLK0

DACK1

DATAOE

DACK must not be changed while RD is at the low level.

Output of valid data

Note 2:Data is written to the FIFO buffer at the last rising edge of FMCLK0 while WRis at the low level.

(Reading)


Note 2:The same signal input timing is applicable to the DACK1 and RD signals or the DACK2 and WR signals

Valid data

487


Read and Write Timing Diagrams for DMA Block Transfer

FR corresponds to that of demand transfer.

Figure 18.3-6 shows the read and write timing diagrams for DMA block transfer.

Figure 18.3-6 Read and Write Timing Diagrams for DMA Block Transfer

(Writing)

DREQ2

FMCLK0

DACK2

WR

DATAI[15:0]

Valid data

Note 2:Data is written to the FIFO buffer at the last rising edge of FMCLK0 while WR is at the low level.

DATAI must not be changed while WR is at the low level.



WR requires a deassertion period of two or more FMCLK0 cycles.

RD

DREQ

FMCLK

[DATA[15:0]

DACK

DATAOE

DREQ is negated at the first rising edge of FMCLK0 after the last RD for reading of one packet is asserted.

Output of valid data

DREQ is negated at the first rising edge of FMCLK0 after the last WR for writing of one packet is asserted.

(Reading)

RD requires a deassertion period of one or more FMCLK0 cycles.

Note 2:The same signal input timing is applicable to the DACKn signal and RD or WR signal.

Valid data Valid data

Last data

488


18.3.3 Interrupt Sources

Table 18.3-2 lists the sources of interrupts to the USB function.

Interrupt Sources

Table 18.3-2 Interrupt Sources

Interrupt source CPU access

DMA access

Status bit Mask bit

The end point entered the write-enabled status during IN transfer.

O - See the explanation of ST1 register.

See the explanation of CONT7 register.

The end point entered the read-enabled status during OUT transfer.

O - See the explanation of ST1 register.


The macro sent or received NACK. O O See the explanation of ST1 register.


Transmission of total send data from the end point for transmission was completed.

O O TTRSEND bit of ST5 register

Reading of total received data from the end point for reception was completed.

O O TRCVEND bit of ST5 register

The device entered the stalled status. O O STALLn of ST5 register


USB bus reset occurred. O O USBRESET bit of ST5 register


(O: Interrupt IRQ is asserted.)

489


18.3.4 Setting of End Point Buffer

At power-on or after reset, the protocol engine of the USB function must write the settings related to the end points to the end point buffer in the protocol engine. A total of 20 bytes are required to store the settings related to the end points (5 bytes for each end point).

Setting of End Point Buffer

Figure 18.3-7 shows the flow of setting the end point buffer.

Figure 18.3-7 Flow of Setting the End Point Buffer

The flow in the figure is explained below.

1) The USB function macro program is released from the reset status at the signal timing ofhardware or software reset.

2) The CPU writes 20-byte data to the FIFO2 buffer.For the contents of the 20-byte data, see the explanation below.

3) After the operation in step 2) is completed, the CFGEN bit of the CONT1 register (controlregister) is set.

4) When the CFGEN bit is set as described in step 3), the protocol engine automatically readsthe 20-byte data from the FIFO2 buffer. As a result, the end point buffer in the protocolengine is set up.

5) When the setting is completed, the CFEND bit of the ST3 register (status register) is set.

Note:

After the CFGEN bit is set in step 3), it takes about 3.4 µs until the CFEND bit is set in step5).

Protocol engine

Inte

rnal

bus

Inte

rnal

bus

inte

rfac

e

FIFO (FIFO2) buffer for end point buffer

Control and

status registers

CP

U I

/F

2)

3)

4)

5) C

PU

BU

S

End

poi

nt b

uffe

r

490


Setting Contents

Figure 18.3-8 shows the data the CPU writes to the FIFO2 buffer to initialize the device.

Data is written in the order of lines shown in Figure 19.3-8 (the top line is written first, and thetenth line is written last).

On each line, the bit at the left end is the MSB.

Figure 18.3-8 Contents of End Point Buffer Settings

Data set in end point buffer Hexadecimal data

[15] [0]

0000000000000000

0001000010000000

0000000000010100

0010000010000000

1000000000000001

0010010000101000

1000000010000000

0000001000110100

0011100000010000

1000000000000011

0x0000

0x1080

0x0014

0x2080

0x8001

0x2428

0x8080

0x0234

0x3810

0x8003

491


18.3.5 Examples of Software Control

This section describes examples of controlling the USB function software.

Example of Controlling the Setup Operation

Figure 18.3-9 shows an example of controlling the setup operation.

Figure 18.3-9 Example of Controlling the Setup Operation

Release hardware and software from reset status

Write setup data to FIFO2 buffer for initialization

Set the SFGEN bit of CONT1 (control register)

Read the CFEND bit of ST3 (status register)

CFEND=1

YES NO

Start of setup

End of setup

Set the mask bits of CONT7 and CONT8

(control registers) (to reset masks)

492


Example of Controlling Reception at CPU Access

Figure 18.3-10 shows an example of controlling reception at CPU access.

Figure 18.3-10 Example of Controlling Reception at CPU Access

Write total receive byte count to TRSIZE (control register)

Set the TRCNTEN bit of CONT10 (control register)

To use the total receive byte counter, perform these operations before reading data from the FIFO buffer.

To 1)

Start of reception operation

493


SETUP=1

ACK0o = 1

BULK OUT transfer data

Is interrupt request IRQ generated

and asserted?

Read ST1 (status register)

NACK

NO

ACK

YES

Read the setup bit of ST3 (status register)

YES

NO

Read data from FIFO0o register

Process data by application program

(Perform this processing if necessary.)

(Next packet reception is enabled.)

Set the transfer enable bit of CONT3 (control register)

Clear the interrupt source bit of ST1 (status register)

YES

NO

Read the transfer size (RSIZE) for end point 0 from RSIZE0 (status register)

Read the transfer size (RSIZE) for end point 0 from RSIZE0 (status register)

Read data from FIFOn register


From 1)

End of reception operation

Is there an interrupt source?

Read data from FIFO0o register

Read the transfer size (RSIZE) for end point n from RSIZEn (status register)

A setup stage of control transfer is received as data.The data must be decoded because it is a class or vendor command or the Get_Descriptor, Set_Descriptor, or Synch_Frame command.

Data transfer to end point 0 (data stage of control transfer, etc.)

494


Example of Controlling Transmission at CPU Access

Transmission operation

Figure 18.3-11 shows an example of controlling transmission at CPU access.

Figure 18.3-11 Example of Controlling Transmission at CPU Access

Set the TTCNTEN bit of CONT10 (control register)

To use the total send byte counter, perform these operations before writing data to the FIFO buffer.

To 1)

Start of transmission operation

Write total receive byte count to TTSIZE (control register)

495


(Perform this processing if it is required after an interrupt.)

Transmission endsnormally.

Transfer was requested to an end point where transfer was not enabled by the host (where transfer data was not prepared).

Write data to the FIFO buffer for transmission


(Perform this processing if necessary.) Process data by application program.

Has transfer been enabled for the end point?

(Perform this processing when transmission of the next packet is enabled.)

Is interrupt request IRQ generated

and asserted?

Read ST1 (status register)

NACK ACK

Is there an interrupt source?

YES

YES

NO

The same datais transmitted again.

Set the transfer enable bit (BFOK) of CONT3 (control register)


From 1)

End of transmission operation

NO

496


Writing of send data of the last packet

Figure 18.3-12 shows an example of controlling writing of send data of the last packet duringtransmission at CPU access.

Figure 18.3-12 Example of Controlling Writing of Send Data of the Last Packet During Transmission at CPU Access

YES

Is data to be written the last data?(*) NO

Write last data to FIFO buffer for transmission

Set the LSTD bit of CONT10 (control register)

NO YES

Does data to be written have an odd

number of bytes?

Set the ODD bit of CONT10 (control register)

Write data to the FIFO buffer for transmission

*: Judgment is made by the system outside the macro program.

YES

Is total send byte counter (TTSIZE)

used? (*)

NO

Last packet

End of writing of last packet

497


Example of Controlling DMA Reception

Figure 18.3-13 shows an example of controlling DMA reception.

Figure 18.3-13 Example of Controlling DMA Reception

Write total receive byte count to TRSIZE (control register)

Set the TRCNTEN bit of CONT10 (control register) to "1"

*: No interrupts occur if the total receive byte counter is not used. The end of total data transfer must be determined by a method other than the macro program.

To use the total receive byte counter, perform these operations before reading data from the FIFO buffer.

Is DREQ asserted? NO

Read receive data (2 bytes) from FIFO buffer for reception

Is IRQ asserted?

YES

NO

YES

Read the TRCVEND bit of ST5 (status register)(*)

Set the MDREQ1 bit of CONT6 (control register) to "1"

End of reception operation

Start of reception operation

Clear the FIFOBUSY1 bit of CONT4 (control register) to "0"

Set the DFIFOBUSY1 bit of CONT5 (control register) to "1"

498


Example of Controlling DMA Transmission

Transmission operation

Figure 18.3-14 shows an example of controlling DMA transmission.

Figure 18.3-14 Example of Controlling DMA Transmission

Write total send byte count to TTSIZE (control register)

Set the TTCNTEN bit of CONT10 (control register) to “1”

Clear the FIFOBUSY2 bit ofCONT4 (control register) to “0”

To use the total send byte counter, perform these operations before writing data to the FIFO buffer.

*: No interrupts occur if the total send byte counter is not used. The end of total data transfer must be determined by a method other than the macro program.

Start of transmission operation

YES

Is IRQ asserted?

YES

Is DREQ asserted? NO

NO

Write send data (2 bytes) to FIFO buffer for transmission

Read the interrupt source bit(TTRSEND) of ST5 (status register)(*)

End of transmission operation

Set the DFIFOBUSY2 bit of CONT5 (control register) to “1”

Set the MDREQ2 bit ofCONT6 (control register) to “1”

499


Writing of send data of the last packet

Figure 18.3-15 shows an example of controlling writing of send data of the last packet duringDMA transmission.

Figure 18.3-15 Example of Controlling Writing of Send Data of the Last Packet during DMA Transmission

*: Judgment is made by the system outside the macro program.

YES

Is data to be written the last data? (*)

NO

Write last data to FIFO buffer for transmission

Write data to FIFO buffer for transmission

Use total send byte counter (TTSIZE)

Last packet

End of writing of last packet

500



This section gives supplementary notes on using the USB function macro program.

Supplementary Notes on the USB Function

This section gives notes on the following items:

• Double buffer

• Controlling the D+ terminating resistor on the board

• Automatic response of macro program to USB standard request commands

• USB function macro program operation in the default status

• USB clock control in the suspended status

• Detection of USB connector connection and disconnection

• Accuracy of UCLK48

• Setting of transfer enable bit (BFOK) during control transfer

• Precautions for control transfer

• Macro program status after USB bus reset

501


18.4.1 Double Buffer

This section gives supplementary notes on the double buffer of the USB function.

Double Buffer

• The USB function has double buffers (64 bytes × 2) for the end points for bulk transfer.

• During USB data transmission for IN transfer, the next packet data can be written by thesystem to the FIFO buffer for transmission.

• During OUT transfer, the next packet can be received while data is being read from thesystem.

• Buffers in the double buffer configuration are switched to each other in units of packets.

Timing Diagram for BULK IN Transfer (Writing by CPU and Reading by USB)

Figure 18.4-1 shows the timing diagram for double-buffer operation during BULK IN transfer andthe operation diagram.

In the example below, the MNACK bit of the CONT8 register (control register) is set so that anIRQ signal is not asserted by NACK.

502


Figure 18.4-1 Timing Diagram for BULK IN Transfer (Writing by CPU and Reading by USB)

* After the last data has been written, no interrupt occurs until transmission of the last packet ends. The end of transmission of the last packet must be determined from an interrupt because it cannot be determined from polling of the LSTD2 bit of the CONT10 register.

FIFO (a)

FIFO (b)

PACKET N PACKET N+1 PACKET N+1 LAST PACKET

Reading by USB

Writing by CPU

Writing by CPU

Reading by USB

ACK1

Reading by USB

Reading by USB

Writing by CPU

NACK1 ACK2

IRQ

FIFO (b)

FIFO (a)

FIFO (a)

FIFO (b)

FIFO (b)

FIFO (a)

FIFO (b)

FIFO (a)

FIFO (a)

PACKET N+1

ACK1

NACK

ACK2

CPU bus side

FIFO (b)

PACKET N Transmission disabled

FIFO (b)

PACKET N PACKET N+1

Transmission enabled

Writing disabled

PACKET N+1

FIFO (a)

PACKET N+1

Writing enabled

LAST PACKET

Writing enabled

Writing disabled

1)

5)

4)

2)

3)

6)

Shading indicates existence of data.

1) 2) 6)

3) 4)

5)

7)

7)

*

USB bus side

503


The operation shown in the figure is explained below.

1. Data is written from the CPU to FIFO buffer (a) for transmission.

2. When FIFO buffer (a) (64 bytes) becomes full and the transfer enable bit (BFOK) is set,transmission to the USB is started. At the same time, FIFO buffer (b) becomes visible fromthe CPU and the next send data can be written to FIFO buffer (b).

3. When data writing to FIFO buffer (b) ends, the transfer enable bit (BFOK) is set. At thesame time, FIFO buffer (a) becomes visible from the CPU. However, data writing from theCPU to FIFO buffer (a) cannot be started because data transmission from FIFO buffer (a) tothe USB is not completed.If data transmission from FIFO buffer (a) ends without an error, an ACK signal (ACK1) isreturned.

4. When the ACK signal (ACK1) is returned, FIFO buffer (a) enters the write-enabled status.The next data is written from the CPU. FIFO buffer (b) becomes visible from the USB.Transmission to the USB is started because transmission-enabled data has already beenwritten to FIFO buffer (b).

5. When data writing to FIFO buffer (a) ends, the transfer enable bit (BFOK) is set. At thesame time, FIFO buffer (b) becomes visible from the CPU. However, data writing from theCPU to FIFO buffer (b) cannot be started because data transmission from FIFO buffer (b) tothe USB is not completed.If data transmission from FIFO buffer (b) ends with an error, a NACK signal is returned.

6. If a NACK signal is returned, data is retransmitted from FIFO buffer (b) to the USB. Datawriting from the CPU to FIFO buffer (b) cannot be started because data transmission fromFIFO buffer (b) to the USB is not completed.If data retransmission from FIFO buffer (b) ends without an error, an ACK signal (ACK2) isreturned.

7. When the ACK signal (ACK2) is returned, FIFO buffer (b) enters the write-enabled status.However, no interrupt occurs until transmission of the last packet is completed.

Timing Diagram for BULK OUT Transfer (Reading by CPU and Writing by USB)

Figure 18.4-2 shows the timing diagram for double-buffer operation during BULK OUT transferand the operation diagram.

In the example below, the MNACK bit of the CONT8 register (control register) is set so that anIRQ signal is not asserted by NACK.

504


Figure 18.4-2 Timing Diagram for BULK OUT Transfer (Reading by CPU and Writing by USB)

FIFO (a)

FIFO (a)

FIFO (b)

FIFO (b)

FIFO (b)


FIFO (b)

FIFO (b)

PACKET N

PACKET N+1

Reading disabled

Reading enabled

CPU bus side

FIFO (a) Reading disabled

PACKET N

Reading enabled

ACK1

NACK

ACK2


PACKET N+1

PACKET N+1

FIFO (a) PACKET N+1 PACKET N+2

1)

5)

4)

2)

3)

PACKET N PACKET N+1 PACKET N+1 PACKET N+2

FIFO (a)

FIFO (b)

IRQ

Reading by CPU

Writing by USB

Writing by USB

Reading by CPU

Writing by USB

Writing by USB

Reading by CPU

ACK1

NACK1 ACK2

1)

2)

3) 4) 5)

USB bus side

505


The operation shown in the figure is explained below.

1. Receive data is written from the USB to FIFO buffer (a).One packet of receive data is stored in FIFO buffer (a). If there is no error, the macroprogram returns an ACK signal (ACK1).

2. When the ACK signal (ACK1) is returned, FIFO buffer (a) enters the read-enabled status andreading by the CPU is started. FIFO buffer (b) becomes visible from the USB, and writing ofthe next packet from the USB to FIFO buffer (b) is started.

3. When data reading by the CPU from FIFO buffer (a) ends, the transfer enable bit (BFOK) isset. FIFO buffer (b) becomes visible from the CPU. However, data reading by the CPU fromFIFO buffer (b) cannot be started because data writing from the USB to FIFO buffer (b) is notcompleted.One packet of receive data is stored in FIFO buffer (b). If there is an error, the macroprogram returns a NACK signal.

4. If a NACK signal is returned, writing of the same packet to FIFO buffer (b) is retried again.Data reading by the CPU from FIFO buffer (b) is still disabled.If storing the packet of receive data in FIFO buffer (b) ends without an error, the macroprogram returns an ACK signal (ACK2).

5. When the ACK signal (ACK2) is returned, FIFO buffer (b) enters the read-enabled status.Data reading by the CPU from FIFO buffer (b) is started. FIFO buffer (a) becomes visiblefrom the USB. Writing of the next receive packet to FIFO buffer (a) is started.

506


FIFO (a)

FIFO (a)

FIFO (b)

FIFO (b)

FIFO (b)


FIFO (b)

FIFO (b)

PACKET N

PACKET N+1

Reading disabled

Reading enabled

CPU bus side


PACKET N

Reading enabled

ACK1

NACK

ACK2


PACKET N+1

PACKET N+1

FIFO (a) PACKET N+1 PACKET N+2

1)

5)

4)

2)

3)

PACKET N PACKET N+1 PACKET N+1 PACKET N+2

FIFO (a)

FIFO (b)

IRQ

CPU

USB WRITE

USB WRITE

CPU USB WRITE USB WRITE

CPU

ACK1

NACK1 ACK2

1)

2)

3) 4) 5)

USB bus side

507


18.4.2 Controlling the D+ Terminating Resistor on the Board

This section describes those points related to the USB function, which must be noted when controlling connection or cutting of the on-board terminating resistor for the USB D+ signal. This control is performed to reserve the time required for the application (firmware) initialization routine.

Controlling the D+ Terminating Resistor on the Board

The hub detects connection of a function device to a downstream USB port when either of thefollowing conditions is met:

• The power of a function device already connected to the USB is turned on.

• A function device whose power has already been turned on is connected to the USB.

The USB specifications require a function device to be able to accept a transaction within 100ms after the hub has detected its connection to a USB port.

If either of the above conditions for the hub's detection of the connection of a function device toa USB port is met, this macro program must execute a sequence to set up the end point bufferafter reset processing.

If the firmware requires 100 ms or more for the initialization routine, including reset and setup ofthe end point buffer, there is a method to defer the detection of the connection. The method isto cut the terminating resistor for the USB D+ signal to temporarily prevent the hub fromdetecting a port connection . When using this method, take the following precautions for themacro program:

Notes:

• Setup of the end point buffer must be started after the hardware and software are releasedfrom the reset status.

• Control to connect the terminating resistor must be started after end point buffer setup by thefirmware is completed.

USB D+ terminating resistor control1: Connected

Software reset(Negative logic)

Hardware reset(Negative logic)

Moment of power-on or USB connection

Period in which end point buffer setup is enabled

The hub detects connection to the USB.

The hub does not recognize a connection although the device is physically connected to the USB.

508


18.4.3 Automatic Response of Macro Program to USB Standard Request Commands

The USB function automatically responds to most USB standard request commands to reduce the load on the application program.However, the following USB standard request commands must be processed by the application program:SET_DESCRIPTOR, GET_DESCRIPTOR, and SYNCH_FRAME commands

Automatic Response of Macro Program to USB Standard Request Commands

Table 18.4-1 lists the USB standard request commands that this macro program automaticallyresponds to and the details of the automatic responses.

The USB standard request commands conform to those supported by USB Function Ver1.1.

Table 18.4-1 USB Standard Request Commands and Details of Automatic Responses (1 / 2)

USB standard request command automatically responded to by this macro program

Details of automatic response

Data stage Status stage

CLEAR_FEATURE Device: DEVICE_REMOTE_WAKEUP

- Returns null data

End point: ENDPOINT_STALLEnd point number supported by this macro program

- Returns null data

End point: ENDPOINT_STALLEnd point number not supported by this macro program

- Responds with STALL signal

GET_CONFIGURATION Returns the current value of Configuration

Receives null data

GET_INTERFACE Interface number supported by this macro program

Returns the current value of Alternate

Receives null data

Interface number not supported by this macro program

Responds with STALL signal

-

509


GET_STATUS Device Returns the current power supply status of the device and whether the REMOTE_WAKEUP function is enabled

Receives null data

End point:End point number supported by this macro program

Returns the current status of ENDPOINT_STALL

Receives null data

End point:End point number not supported by this macro program

Responds with STALL signal

-

SET_ADDRESS - Returns null data

SET_CONFIGURATION Configuration number supported by this macro program

- Returns null data

Configuration number not supported by this macro program


SET_FEATURE Device: DEVICE_REMOTE_WAKEUP

- Returns null data

End point: ENDPOINT_STALLEnd point number supported by this macro program (except end point 0)

- Returns null data

End point: ENDPOINT_STALLEnd point number not supported by this macro program or end point 0


SET_INTERFACE Interface or Alternate number supported by this macro program

- Returns null data

Interface or Alternate number not supported by this macro program


Table 18.4-1 USB Standard Request Commands and Details of Automatic Responses (2 / 2)

USB standard request command automatically responded to by this macro program

Details of automatic response

Data stage Status stage

510


18.4.4 USB Function Macro Program Operation in the Default Status

The USB function enters the default status after being released from the reset status.The USB function macro program can be set to the configuration status defined by Configuration = 1.

USB Function Macro Program Operation in the Default Status

If the device receives a Set_Configuration command with Configuration = 1 specified from theUSB host, the USB function macro program is set to the configuration status.

Only end point 0 can be used in the default status. Other end points cannot be used in thedefault status. If a transfer request to an end point other than end point 0 is received, the macroprogram does not respond to the request and time-out occurs.

All end points can be used in the configuration status.

Table 18.4-2 lists the responses of the macro program to transfer requests to end points 0 to 3in the default and configuration status.

Table 18.4-2 Responses of Macro Program to Transfer Requests to End Points 0 to 3 in the Default and Configuration Status

Default status Configuration status

End point 0 UsableA response is made to a transfer request.

UsableA response is made to a transfer request.

End points 1 to 3 Not usableNo response is made to a transfer request, and time-out occurs.

UsableA response is made to a transfer request.

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18.4.5 Detection of USB Connector Connection and Disconnection

The USB function cannot detect whether the USB connector is connected . Connection and disconnection of USB connector must be detected by the method described below.

Detection of USB Connector Connection and Disconnection

The USB function cannot use the D+ or D- signal to determine whether the USB connector isconnected.

Whether the USB connector is connected must be determined by detecting VBUS outside of themacro program.

• When the connector is connected: VBUS = 5 V

• When the connector is not connected: VBUS = 0 V

A possible method is to detect changes of VBUS on the board and generate interrupts to theMPU.

When connection of the USB connector is detected, the USB function macro program must bereset.

512


18.4.6 Accuracy of UCLK48

This section describes the accuracy of the UCLK48 clock.

Accuracy of UCLK48

USB Function Ver1.1 has two standards for D+ data and D- data signals.

A crystal oscillator module must be used as the 48 MHz clock input source of the UCLK48clock.

If PLL is used, take special care regarding clock frequency accuracy.

Data rate standard (long-term standard)

The device (entire circuit not limited to an LSI circuit) must satisfy the following: accuracy of -2,500 to +2,500 ppm (-0.25% to +0.25%).

The USB standards require an accuracy of -2,500 to +2,500 ppm for the 12 MHz clock.However, the USB function macro program requires the 48 MHz clock to have a higheraccuracy than -2,500 to +2,500 ppm. This is because it selects the clock edges synchronizedwith data from the clock edges of the 48 MHz clock and uses the selected clock edges as the 12MHz clock.

For this reason, the UCLK48 clock needs a higher accuracy than -2,500 to +2,500 ppm.

Short-term standard

The device (entire circuit not limited to an LSI circuit) must satisfy the following jitterrequirements:

• Jitter within -1 ns to +1 ns until the first crossing point

• Jitter within -2 ns to +2 ns until the second crossing point

Accuracy within -1 ns to +1 ns from each edge of the 48 MHz clock is required because the D+and D- signals may alter at every edge.

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18.4.7 Setting of Transfer Enable bit (BFOK) during Control Transfer

To enable the macro program to receive a command and respond to it with ACK in the setup stage of control transfer, the BFOK0o bit of the CONT3 register must be set to "1". If the BFOK0o bit is "0", the command is ignored and time-out occurs. The same condition also applies to the commands that are automatically processed by the macro program in the setup stage.

Setting of Transfer Enable (BFOK) Bits during Control Transfer

The settings of the BFOK0i and BFOK0o bits during control transfer are explained below.

For a request the macro program processes automatically

• Setup stage

The BFOK0o bit must be set to "1" to enable an ACK response.

If the BFOK0o bit is "0", a time-out occurs.

• Data stage

IN: No request is processed automatically by the macro program.

OUT: ACK response is made regardless of the setting of BFOK0o.

• Status stage

IN: ACK response is made regardless of the setting of BFOK0i.

OUT: ACK response is made regardless of the setting of BFOK0o.

For a request the macro program does not process automatically

• Setup stage

The BFOK0o bit must be set to "1" to enable an ACK response.

• Data stage

IN: The BFOK0i bit must be set to "1" to enable an ACK response.

OUT: The BFOK0o bit must be set to "1" to enable an ACK response.

• Status stage

IN: The BFOK0i bit must be set to "1" to enable an ACK response.

OUT: The BFOK0o bit must be set to "1" to enable an ACK response.

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18.4.8 Precautions for Control Transfer

This section describes the precautions for control transfer.

Precautions for Control Transfer

Precaution 1: Priority of setting the BFOK0o bit

USB specifications allow the USB function to respond to requests with ACK only in the setupstage. If the USB function cannot make an ACK response to a request, a time-out occurs.

If a time-out occurs three times successively in the setup stage, the USB host disconnects thefunction device. For this reason, the USB function should always make an ACK response torequests.

If the status stage ends with an ACK response, the BOK0o bit is cleared to 0. To enable theUSB function to make an ACK response in the next setup stage, the BFOK0o bit must be set to1 before the next setup stage. For this reason, the priority of setting the BFOK0o bit must beset as high as possible.

This requirement applies only to commands the macro program does not process automatically.Even if an ACK response is made to a command that the macro program processesautomatically, the BFOK0o bit is not cleared to "0".

Precaution 2: Cancellation of the data stage by a Get_Descriptor command

When a Get_Descriptor command, which is not automatically responded to by the macroprogram, is processed, the host may cancel the data stage in the middle. This may occur evenif the byte count of data for IN transfer initially requested by the host is not reached. If thiscancellation occurs, the host may not receive all the data previously written to the FIFO bufferfor IN transfer as follows:

Setup stage (16 bytes requested)

↓

Data stage

The CPU writes 8 bytes (data A) to the FIFO buffer for IN transfer.

The host requests IN transfer. The USB function transmits 8 bytes and receives ACK.

The CPU writes 8 bytes (data B) to the FIFO buffer for IN transfer.

Note:

The host may cancel the data stage at this point.

↓

Status stage

0-byte data is received at OUT transfer.

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If the above event occurs, data B, which has already been written to the FIFO buffer, must bediscarded and the FIFO buffer must be initialized before the next IN transfer request is received.The above event in which the host stops receiving data in the middle may be detected bydetecting a USB reset interrupt. Another possible detection method is to check the ACKinterrupt sources as follows:

• Data stage: The interrupt source bit (ACK0i) is set.

• Status stage: The interrupt source bit (ACK0o) is set.(If the data stage is continued, the ACK0i bit is set.)

Transition from the data stage to the status stage can be determined from the change ofinterrupt source (from the ACK0i bit to the ACK0o bit).

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18.4.9 Macro Program Status after USB Bus Reset

This section describes the macro program status after USB bus reset.

Macro Program Status after USB Bus Reset

The register values and FIFO buffer status in the macro program are not reset even when aUSB bus reset occurs. To start transfer on the USB after a USB bus reset, the registers andFIFO buffers must be reset to the initial status by the application program.

Also, the initial settings of the end point buffer are not reset by a USB bus reset. The initialsettings are retained even after a USB bus reset. Therefore, the end point buffer need not beset up again.

Note that the macro program enters the USB default status when a USB bus reset occurs.

517


518


This chapter gives an overview of the USB host interface and explains register configuration and functions.

19.1 Overview of USB Host Interface

19.2 Registers of USB Host Interface

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The USB host interface is an USB host controller equipped with FR IF and SRAM IF.

USB Host Interface

The USB host interface is an OHCI-compliant USB host controller that has the followingfeatures:

This macro is operated at the little endian, the LEND bit of ACR1 register of CS1 is set “1”.

Accessing to this macro is used the word (32-bit) access instruction. In this case, the operationmode is set DBW to 10 (32-bit mode) and does not use other than the word access instruction.Also, when a bit control instruction is executed, the byte access is performed. Do not use the bitcontrol instruction.

• Compliance with USB Specification Version 1.0

• Compliance with OpenHCI Specification Version 1.0aNote that legacy device interfaces are not supported.

• Host controller function

Note:

For the OHCI specification, visit the following URL:

http://www.compaq.com/productinfo/development/openhci.html

This interface supports USB Version 1.0. For the difference between USB Versions 1.0 and1.1, see the following URL. The major difference is that support for Interrupt OUT transferhas been added.

http://www.usb.org/developers/data/usbplus.zip

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Block Diagram

Figure 19.1-1 is a block diagram of the USB host interface.

Figure 19.1-1 Block Diagram of USB Host Interface

FR <=> USB FR/USB <=> SRAM IF

IF

F_USBHO

SRAM IF

PCI BUS

FR BUS

SRAM

FR USB PORT

SRAM BUS

PCI BUS

FR_USBHO

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This section explains the configuration and functions of the registers used by the USB host interface.

Registers of the USB Interface

The USB host is connected to the CS1 area via the external memory interface. For details aboutthe external memory interface, see "CHAPTER 3 CPU AND CONTROL UNITS" and"CHAPTER 4 EXTERNAL BUS INTERFACE".

Table 19.2-1 shows the register map of the USB host interface.

Table 19.2-1 Register Map of USB Host Interface

CPU bus address (in CS2 area)

0x0005_0000

0x0005_0004

0x0005_0008

0x0005_000C

0x0005_0010

0x0005_0014

0x0005_0018

0x0005_001C

0x0005_0020

0x0005_0024

0x0005_0028

0x0005_002C

0x0005_0030

0x0005_0034

0x0005_0038

0x0005_003C

0x0005_0040

0x0005_0044

0x0005_0048

0x0005_004C

0x0005_0050

0x0005_0054

0x0005_0058

0x0005_005C to

0x0005_7FFF

Register

HcRevision

HcControl

HcCommandStatus

HcInterruptStatus

HcInterruptEnable

HcInterruptDisable

HcHCCA

HcPeriodCurrentED

HcControlHeadED

HcControlCurrentED

HcBulkHeadED

HcBulkCurrentED

HcDoneHead

HcFmInterval

HcFmRemaining

HcFmNumber

HcPeriodicStart

HcLSThreshold

HcRhDescriptorA

HcRhDescriptorB

HcRhStatus

HcRhPortStatus[1]

HcRhPortStatus[2]

Reserved

522


SRAM Area

The SRAM area of the USB host interface is as follows:

• Address area (CS1 area) viewed from the CPU

Addresses in CS1: 0x0005_8000 to 0x0005_9FFFF (8 KB area)

• Address area viewed from the USB

Internal PCI bus addresses: 0x4000_0000 to 0x4000_1FFF (8 KB area)

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19.2.1 HcRevision Register

The HcRevision register indicates the version of OHCI specification.

HcRevision Register

Table 19.2-2 shows the bit configuration of the HcRevision register and explains the bits.

Table 19.2-2 Bit Configuration of HcRevision Register

Bit Name Reset R/W Explanation

7 to 0 REV 10H R RevisionIndicates revision of the HOCI specification.Because this macro supports OHCI specification version 1.0, these bits are fixed to 10H.

31 to 8 - 000001H R Reserved

524


19.2.2 HcControl Register

The HcControl register sets the operating mode of the host controller.The bits other than RemoteWakeupConnected can only be rewritten from the host controller driver.

HcControl Register

Table 19.2-3 shows the bit configuration of the HcControl register and explains the bits.

Table 19.2-3 Bit Configuration of HcControl Register (1 / 2)


1, 0 CBSR 00B R/W ControlBulkServiceRatioThese bits are used to code the service count for the control endpoint of each BULK endpoint. N-1 indicates the N-count services to the control endpoint.(Example: 00 = 1 control endpoint, 11 = 4 control endpoints)

2 PLE 0 R/W PeriodicListEnableWhen this bit is set, periodic (interrupt and isochronous) list processing is enabled. This macro checks this bit before periodic frame transfer.

3 IE 0 R/W IsochronousEnableWhen this bit is cleared, isochronous list processing is disabled even when PeriodicListEnable is set. In this case, interrupt ED is processed. This macro checks this bit each time isochronous ED is processed.

4 CLE 0 R/W ControlListEnableWhen this bit is set, control list processing is enabled.

5 BLE 0 R/W BulkListEnableWhen this bit is set, Bulk list processing is enabled.

7, 6 HCFS 00B R/W HostControllerFunctinalStateThis area is used to set the status of this macro. When this macro detects the resume signal from DownPort, it changes the status from USBSuspend to USBResume.00: USBReset01: USBResume10: USBOperational11: USBSuspend

525


8 IR 0 R/W InterruptRoutingThis bit indicates an interrupt path."0" : An interrupt uses the normal function (INT) path."1" : An interrupt uses the SMI path.

9 RWC 0 R RemoteWakeupConnectedThis bit indicates whether the host controller supports the remote wakeup signal. Because this macro does not support the remote wakeup signal, this bit is hard-coded to 0.

10 RWE 0 R/W RemoteWakeupEnableThis bit enables operation of the host controller that supports the remote wakeup signal. Because this macro does not support the remote wakeup signal, this bit is not used.

31 to 11 - 0H - Reserved Read/Write 0’s

Table 19.2-3 Bit Configuration of HcControl Register (2 / 2)


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19.2.3 HcCommandStatus Register

The HcCommandStatus register is used to reflect the host controller state as well as receive instructions issued by the host controller driver.

HcCommandStatus Register

Table 19.2-4 shows the bit configuration of the HcCommandStatus register and explains thebits.

Table 19.2-4 Bit Configuration of HcCommandStatus Register


0 HCR 0 R/W HostControllerResetThis bit is set to start software reset.This bit is cleared by this macro after the completion of reset operation.

1 CLF 0 R/W ControlListFilledThis bit is set to indicate that the control list contains an active ED. Software or this macro sets this bit and clears it each time this macro starts processing the beginning of the control list.

2 BLF 0 R/W BulkListFilledThis bit is set to indicate that the Bulk list contains an active ED. Software or this macro sets this bit and clears it each time this macro starts processing the beginning of the Bulk list.

3 OCR 0 R/W OwnershipChangeRequestWhen this bit is set by software, the bit sets OwnershipChange of the HcInterruptStatus register. Software clears this bit.


17, 16 SOC 00B SchedulingOverrunCountThis area is incremented each time the SchedulingOverrun bit of the HcInterruptStatus register is set. Count is 11, followed by 00.


527


19.2.4 HcInterruptStatus Register

The HcInterruptStatus register indicates the status that causes a hardware interrupt. To generate a hardware interrupt, set the HcInterruptEnable register to set the MIE bit. The host controller sets but does not clear the bits. The host controller driver can write "1" to the bits to clear them, but cannot set the bits.

HcInterruptStatus Register

Table 19.2-5 shows the bit configuration of the HcInterruptStatus register and explains the bits.

Table 19.2-5 Bit Configuration of HcInterruptStatus Register


0 SO 0 R/W SchedulingOverrunThis bit is set when ListProcessor determines that ScheduleOverrun has occurred.

1 WDH 0 R/W WritebackDoneHeadThis bit is set when this macro writes HcDoneHead to HccaDoneHead.

2 SF 0 R/W StartofFrameThis bit is set when the Flame Management block generates a “Start of Frame” event signal.

3 RD 0 R/W ResumeDetectedThis bit is set when this macro detects a resume signal on the down port.

4 UE 0 R UnrecoverableErrorThis macro does not support this event. This bit is hard-coded to 0 and writing to this bit is disabled.

5 FNO 0 R/W FrameNumberOverflowThis bit is set when 15 FrameNumber bits change.

6 RHSC 0 R/W RootHubStatusChangeThis bit is set when the contents of the HcRhStatus or HcRhPortStatus register change. This bit is cleared when the contents of the HcRhStatus or HcRhProtStatus register are cleared.


30 OC 0 R/W OwnershipChangeThis bit is set when the OwnershipChangeRequest bit of the HcCommandStatus register is set.

31 - 0 - Reserved Read/Write 0’s

528


19.2.5 HcInterruptEnable Register

The HcInterruptEnable register controls the generation of hardware interrupts. When the interrupt source setting is enabled and MIE set, a hardware interrupt is enabled.

HcInterruptEnable Register

Table 19.2-6 shows the bit configuration of the HcInterruptEnable register and explains the bits.

Table 19.2-6 Bit Configuration of HcInterruptEnable Register


0 SO 0 R/W SchedulingOverrunEnable"0" : Disabled"1" : An interrupt caused by Schedule Overrun is enabled.

1 WDH 0 R/W WritebackDoneHeadEnable"0" : DisabledAn interrupt caused by Writeback Done Head is enabled.

2 SF 0 R/W StartOfFrameEnable"0" : DisabledAn interrupt caused by Start Of Frame is enabled.

3 RD 0 R/W ResumeDetectedEnable"0" : DisabledAn interrupt caused by Resume Detected is enabled.

4 UE 0 R/W UnrecoverableErrorEnableThis bit is not supported. Writing to this bit is disabled.

5 FNO 0 R/W FrameNumberOverflowEnable"0" : Disabled"1" : An interrupt caused by Frame Number Overflow is enabled.

6 RHSC 0 R/W RootHubStatusChangeEnable"0" : Disabled"1" : An interrupt caused by Root Hub Status Change is enabled.

29 to 7 - 0H - Reserved

30 OC 0 R/W OwnershipChangeEnable"0" : Disabled"1" : An interrupt caused by Ownership Change is enabled.

31 MIE 0 R/W MasterInterruptEnableThis bit enables a global interrupt.When "1" is written to this bit, the above enable bits enable interrupts.

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19.2.6 HcInterruptDisable Register

The HcInterruptDisable register is paired with the HcInterruptEnable register. Writing 1 to this register clears the corresponding bits of the HcInterruptEnable register. Even if 0 is written to this register, the HcInterruptEnable register values remain unchanged. During read operation, the HcInterruptEnable register values are read instead of the HcInterruptDisable register values.

HcInterruptDisable Register

Table 19.2-7 shows the bit configuration of the HcInterruptDisable register and explains the bits.

Table 19.2-7 Bit Configuration of HcInterruptDisable Register


0 SO 0 R/W "0" : Disabled"1" : An interrupt caused by Schedule Overrun is disabled.

1 WDH 0 R/W "0" : Disabled"1" : An interrupt caused by Writeback Done Head is disabled.

2 SF 0 R/W "0" : Disabled"1" : An interrupt caused by Start of Frame is disabled.

3 RD 0 R/W "0" : Disabled"1" : An interrupt caused by Resume Detected is disabled.

4 UE 0 R/W This bit is not supported. Writing to this bit is disabled.

5 FNO 0 R/W "0" : Disabled"1" : An interrupt caused by Frame Number Overflow is disabled.

6 RHSC 0 R/W "0" : Disabled"1" : An interrupt caused by Root Hub Status Change is disabled.

29 to 7 - 0H - Reserved

30 OC 0 R/W "0" : Disabled"1" : An interrupt caused by Ownership Change is disabled.

31 ME 0 R/W This bit disables interrupts on a global basis.Writing "1" to this bit disables all interrupts.

530


19.2.7 HcHCCA Register

The HcHCCA register indicates the physical address of the host controller communication area. Because the minimum unit of alignment is 256 bytes, low-order bits 7 to 0 are fixed to 0. For details about the host controller communication area, refer to Chapter 4 in the OpenHCI Specification.

HcHCCA Register

Table 19.2-8 shows the bit configuration of the HcHCCA register and explains the bits.

Table 19.2-8 Bit Configuration of HcHCCA Register


7 to 0 - 00H R Reserved

31 to 8 HCCA 000000H R/W HCCAPointer to HCCA base address

531


19.2.8 HcPeriodCurrentED Register

The HcPeriodCurrentED register indicates the physical address of the current Isochronous or Interrupt endpoint descriptor.

HcPeriodCurrentED Register

Table 19.2-9 shows the bit configuration of the HcPeriodCurrentED register and explains thebits.

Table 19.2-9 Bit Configuration of HcPeriodCurrentED Register



31 to 4 PCED 0000000H R/W PeriodCurrentEDPointer to current Periodic list ED

532


19.2.9 HcControlHeadED Register

The HcControlHeadED register indicates the physical address of the first endpoint descriptor in the control list.

HcControlHeadED Register

Table 19.2-10 shows the bit configuration of the HcControlHeadED register and explains thebits.

Table 19.2-10 Bit Configuration of HcControlHeadED Register



31 to 4 CHED 0000000H R/W ControlHeadEDPointer to Control List Head ED

533


19.2.10 HcControlCurrentED Register

The HcControlCurrentED register indicates the physical address of the current endpoint descriptor in the control list.

HcControlCurrentED Register

Table 19.2-11 shows the bit configuration of the HcControlCurrentED register and explains thebits.

Table 19.2-11 Bit Configuration of HcControlCurrentED Register



31 to 4 CCED 0000000H R/W ControlCurrentEDPointer to Current Control List ED

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19.2.11 HcBulkHeadED Register

The HcBulkHeadED register indicates the physical address of the first endpoint descriptor in the Bulk list.

HcBulkHeadED Register

Table 19.2-12 shows the bit configuration of the HcBulkHeadED register and explains the bits.

Table 19.2-12 Bit Configuration of HcBulkHeadED Register



31 to 4 BHED 0000000H R/W HcBulkHeadEDPointer to Bulk List Head ED

535


19.2.12 HcBulkCurrentED Register

The HcBulkCurrentED register indicates the physical address of the current endpoint in the Bulk list.

HcBulkCurrentED Register

Table 19.2-13 shows the bit configuration of the HcBulkCurrentED register and explains the bits.

Table 19.2-13 Bit Configuration of HcBulkCurrentED Register



31 to 4 BCED 0000000H R/W BulkCurrentEDPointer to Current Bulk List ED

536


19.2.13 HcDoneHead Register

The HcDoneHead register indicates the physical address of the last completed transfer descriptor added to the Done queue.

HcDoneHead Register

Table 19.2-14 shows the bit configuration of the HcDoneHead register and explains the bits.

Table 19.2-14 Bit Configuration of HcDoneHead Register



31 to 4 DH 0000000H R/W DoneHeadPointer to current Done List Head ED

537


19.2.14 HcFmInterval Register

The HcFmInterval register uses the values of bits 13 to 0 to indicate the bit time interval of a frame (i.e., continuous frame SOF interval). The values of bits 30 to 16 indicate the full-speed maximum packet size.

HcFmInterval Register

Table 19.2-15 shows the bit configuration of the HcFmInterval register and explains the bits.

Table 19.2-15 Bit Configuration of HcFmInterval Register


13 to 0 FI 2EDFH R/W FrameIntervalThis area is used to code the frame length by (bit time - 1).For a 12,000-bit time frame, for example, a length of 11,999 is coded.

15,14 - 00B - Reserved Read/Write 0’s

30 to 16 FSMPS 0H FSLargestDataPacketThis area is used to code the values loaded in the Largest Data Packet Counter at the beginning of the frames.

31 FIT 0 FrameIntervalToggleThe host controller driver toggles this bit each time the driver loads a new value into the FrameInterval register.

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19.2.15 HcFmRemaining Register

The HcFmRemaining register is a 14-bit down counter that indicates the remaining time for the current frame.

HcFmRemaining Register

Table 19.2-16 shows the bit configuration of the HcFmRemaining register and explains the bits.

Table 19.2-16 Bit Configuration of HcFmRemaining Register


13 to 0 FR 0H R FrameRemainingWhen this macro is in USBOperational state, this 14-bit area is decremented in a clock cycle of 12 MHz. If the count value becomes 0 (or end of the frame is reached), the values of FrameInterval are loaded. When this macro changes to the USBOperational state, the values of FrameInterval are also loaded.


31 FRT 0 R FrameRemainingToggleWhen FrameRemaining is loaded, FrameIntervalToggle is loaded.

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19.2.16 HcFmNumber Register

The HcFmNumber register is a 16-bit counter that gives the timing reference for the event generation interval of the host controller and host controller driver.

HcFmNumber Register

Table 19.2-17 shows the bit configuration of the HcFmNumber register and explains the bits.

Table 19.2-17 Bit Configuration of HcFmNumber Register


15 to 0 FN 0000H R FrameNumberThis 16-bit increment counter area is incremented when FrameRemaining is loaded.Count is FFFFH, followed by 0H.


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19.2.17 HcPeriodicStart Register

The HcPeriodStart register uses the 14-bit values to indicate the initial time the host controller should start periodic list processing.

HcPeriodStart Register

Table 19.2-18 shows the bit configuration of the HcPeriodStart register and explains the bits.

Table 19.2-18 Bit Configuration of HcPeriodStart Register


13 to 0 PS 0H R/W PeriodStartThese bits are used to code the values used to determine that the list processor starts periodic transfer list processing in a frame.


541


19.2.18 HcLSThreshold Register

The HcLSThreadhsold register uses 11-bit values to determine whether to commit transmission of an 8-byte LS packet before EOF to the host controller.

HcLSThreshold Register

Table 19.2-19 shows the bit configuration of the HcLSThreshold register and explains the bits.

Table 19.2-19 Bit Configuration of HcLSThreshold Register


11 to 0 LST 628H R/W LSThresholdThese bits are used to code the values used to determine whether the frame management block starts a low-speed transaction in the current frame.


542


19.2.19 HcRhDescriptorA Register

The HcRhDescriptorA register is the first of two registers that code the root hub setting.

HcRhDescriptorA Register

Table 19.2-20 shows the bit configuration of the HcRhDescriptorA register and explains the bits.

Table 19.2-20 Bit Configuration of HcRhDescriptorA Register


7 to 0 NDP 02H R NumberDownstreamPortsThis macro supports two down ports.

8 PSM 0 R/W PowerSwitchingModeThis macro supports Global power switching mode. Note that "0" must be written to this bit.This bit is valid only if NoPowerSwitching is cleared."0" : Global Switching"1" : Individual Switching

9 NPS 0 R/W NoPowerSwitchingThis macro supports Global power switching mode. Code support of the external Port Power Switching device. Therefore, this bit must be set to "0"."0" : The port is controlled by power switch."1" : Port is always ON.

10 DT 0 R DeviceTypeThis macro is the compound device.

11 OCPM 0 R/W OverCurrentProtectionModeThis macro supports Global over-current report. Therefore, this bit must be set to "0".This bit is valid only when NoOverCurrentProtection is cleared."0" : Global over-current"1" : Individual over-current

12 NOCP 0 R/W NoOverCurrentProtectionThis macro supports Global over-current reporting. Code support of external Port over-current device. Therefore, this bit must be set to "0"."0" : Over-current status is reported."1" : Over-current status is not reported.


31 to 24 POTPGT 01H R/W PowerOnToPowerGoodTimeCode the time between power-on and stabilization in units of 2 ms. Only bits 24 and 25 can be read and written by this macro program.

543


19.2.20 HcRhDescriptorB Register

The HcRhDescriptorB register is the second register that codes the root hub setting. This register is written at initialization so that it matches system implementation.

HcRhDescriptorB Register

Table 19.2-21 shows the bit configuration of the HcRhDescriptorB register and explains the bits.

Table 19.2-21 Bit Configuration of HcRhDescriptorB Register


15 to 0 DR 0000H R/W DeviceRemovableThis macro port can be removed by default."0" : The device cannot be removed."1" : The device can be removed.The relationship between bits and ports is as follows:bit0: reservedbit1: port1bit2: port2Bits 3 to 15 are not supported. The read and written values are "0".

31 to 16 PPCM 0000H R/W PortPowerControlMaskThis area indicates whether the Global Power Control command affects processing.This area becomes valid when NoPowerSwitching is cleared and PowerSwitchMode set."0" : The Global Power Control command affects processing."1" : The Global Power Control command does not affect processing.The relationship between bits and ports is as follows:bit16: reservedbit17: port1bit18: port2Bits 19 to 32 are not supported. The read and written values are "0".

544


19.2.21 HcRhStatus Register

The HcRhStatus register is divided into two parts. The low-order 16 bits are the hub status field; the high-order 16 bits are the hub status change field. A value of 0 must always be written to reserved bits.

HcRhStatus Register

Table 19.2-22 shows the bit configuration of the HcRhStatus register and explains the bits.

Table 19.2-22 Bit Configuration of HcRhStatus Register


0 LPS 0 R/W (read) LocalPowerStatusNot supported.(write) ClearGlobalPowerWriting "1" : Issue the ClearGlobalPower command for the port.Writing "0" : Invalid

1 OCI - R OverCurrentIndicatorThis bit reflects the OVRCUR PIN state.This bit is valid when NoOverCurrentProtection and OverCurrentProtectionMode are cleared."0" : No Over Current"1" : Over Current condition


15 DRWE 0 R/W (read) DeviceRemoteWakeupEnableThis bit enables ConnectStatusChange for the port triggered by a remote wakeup event."0" : Disable"1" : Enable(write) SetRemoteWakeupEnableWriting "1" : Set SetRemoteWakeupEnable.Writing "0" : Invalid

16 LPSC 0 R/W (read) LocalPowerStatusChangeNot supported. The read value is always "0".(write) SetGlobalPowerWriting "1" : Issue the SetGlobalPower command.Writing "0" : Invalid

17 OCIC 0 R/W OverCurrentIndicatorChangeThis bit is set when OverCurrentIndicator changes.Writing "1" : Clears this bit.Writing "0" : Invalid


31 CRWE 0 W (write) ClearRemoteWakeupEnableWriting "1" : Clears DeviceRemoteWakeupEnable.Writing "0" : Invalid

545


19.2.22 HcRhPortStatus[1 and 2] Register

The HcRhPortStatus register is used to control ports and report port events. HcRhPortStatus[1] is used for port 1, and HcRhPortStatus[2] is used for port 2. The low-order 16 bits reflect the port status; the high-order 16 bits reflect the status change bit. Some status bits have a special write mechanism. For details, see the explanation of the bits.If a transaction proceeds when the port status is rewritten, rewriting must be deferred until the transaction is completed before rewriting the resulting port status.

HcRhPortStatus [1 and 2] Register

Table 19.2-23 shows the bit configuration of the HcRhPortStatus[1 and 2] register and explainsthe bits.

Table 19.2-23 Bit Configuration of HcRhPortStatus [1 and 2] Register (1 / 3)


0 CCS 0 R/W (read) CurrentConnectStatus"0" : Currently, the device is not connected to this port."1" : Currently, the device is connected to this port.Note: When DeviceRemovable is set, this bit is always "1".(write) ClearPortEnableWriting "1" to this bit clears PortEnableStatus.Writing "0" to this bit is disabled.

1 PES 0 R/W (read) Port EnableStatus"0" : The port is disabled."1" : The port is enabled.(write) SetPortEnableWriting "1" to this bit sets PortEnableStatus.Writing "0" to this bit is disabled.

2 PSS 0 R (read) PortSuspendStatus"0" : The port is not suspended."1" : The port is suspended.(write) SetPortSuspendWriting "1" to this bit sets PortSuspendStatus.Writing "0" to this bit is disabled.

546


3 POCI 0 R/W (read) PortOverCurrentIndicatorThis macro does not report the over-current condition for each port.This bit reflects the OVRCUR pin status.This bit is valid only when NonOverCurrentProtection is cleared and OverCurrentProtectionMode is set."0" : The current of this port is normal."1" : The over-current state occurs in this port.(write) ClearSuspendStatusWriting "1" to this bit executes the resume sequence for the port.Writing "0" to this bit is disabled.

4 PRS 0 R/W (read) PortResetStatus"0" : The reset signal is not active."1" : The reset signal is active.(write) SetPortResetWriting "1" to this bit sets PortResetStatus.Writing "0" to this bit is disabled.


8 PPS 0 R/W (read) PortPowerStatusThis bit indicates the power status of the port regardless of power switching mode."0" : Power to the port is off."1" : Power to the port is on.Note: When NoPowerSwitching is set, the read value from this bit is always "1".(write) SetPortPowerWriting "1" to this bit sets PortPowerStatus.Writing "0" to this bit is disabled.

9 LSDA 0 R/W (read) LowSpeedDeviceAttachedThis bit indicates the speed of the connected device."0" : Full Speed device"1" : Low Speed device(write) ClearPortPowerWriting "1" to this bit clears PortPowerStatus.Writing "0" to this bit is disabled.


16 CSC 0 R/W ConnectStatusChangeThis bit indicates that a connection or disconnection event is detected."0" : No connection or disconnection event is detected."1" : Connection or disconnection is detected.Writing "1" clears this bit.Writing "0" to this bit is disabled.



547


17 PESC 0 R/W PortEnableStatusChangeThis bit indicates that (PortEnableStatus is cleared) or the port is disabled by hardware."0" : The port is disabled."1" : PortEnableStatus is cleared.

18 PSSC 0 R/W PortSuspendStatusChangeThis bit indicates the end of the resume sequence for the port."0" : The port is not resumed."1" : The port has been resumed.

19 OCIC 0 R/W PortOverCurrentIndicatorChangeThis bit is set when OverCurrentIndicator changes.Writing "1" clears this bit.Writing "0" to this bit is disabled.

20 PRSC 0 R/W PortResetStatusChangeThis bit indicates the end of the port reset signal."0" : Port reset is not completed."1" : Port reset is completed.




548


This chapter explains the features, block diagram, display functions, control functions, and display control commands of the on-screen display controller (OSDC).

20.1 Features

20.2 Block Diagram

20.3 Display Functions

20.4 Control Functions

20.5 Display Control Commands

549


20.1 Features

The on-screen display controller (OSDC) can display up to 42 characters by 16 lines at a high resolution of up to 24-by-32 dots per character. The OSDC contains a palette circuit that enables the display of 16 colors of 512 colors to be displayed.The OSDC provides sprite display, screen background text display, and graphics display functions, enabling a variety of GUI displays.

Features of the OSDC

The features of the OSDC are as follows:

Main screen display capacity

Up to 42 characters × 16 lines (672 characters)

Font sizes

L size: 24 × 2h* dots (horizontal × vertical)

M size: 18 × 2h* dots (horizontal × vertical)

S size: 12 × 2h* dots (horizontal × vertical)

*: h = 9 to 16

The L, M, or S size can be set for each character.

• Graphic characters can be displayed only in the L or S size.

• Two values of "h" can be set for each screen, either of which is selected for each line.

Character types

1792 different characters integrated

Note: A graphic character consists of four continuous characters.

Display modes

Normal character/graphic character display (Set for each character)

Trimmed display (horizontal trimming/pattern background) (Set for each screen)

Character background (solid-filled/shaded background) (Set for each character)

Italic display (Set for each character)

Underline display (Set for each character)

Line background (solid-filled/shaded background) (Set for each line)

Enlarged display (normal, double width, double height, double height × double width, quadruplewidth, quadruple height, quadruple height × quadruple width, and others) (Set for each line)

Blink display:

Blink character specification (Set for each character)

Blink mode setting (Set for each character)

Blink cycle and duty ratio (Set for each screen)

550

20.1 Features

Sprite character display (Only in graphics display mode)

Capable of displaying one block (of up to 2 × 2 characters, movable vertically or horizontally in2-dot units) on the main screen

Screen background character display (Only in graphics display mode)

Capable of displaying a repetitive pattern (consisting of up to 2 × 2 characters) below the mainscreen

Display colors

Character color/background color: 16 colors of 512 colors (Set for each character)

Line background color/character trimming color: 16 colors of 512 colors (Set for each line)

Screen background color: 16 colors of 512 colors (Set for each screen)

Graphic character dot color: 16 colors of 512 colors (Set for each dot)

Shaded background frame color (highlight/shadow): 16 colors of 512 colors (Set for eachscreen)

Display position control

Horizontal display position on the main screen: Settable in 4-dot units

Vertical display position on the main screen: Settable in 4-dot units

Horizontal display position on the sprite screen: Settable in 2-dot units

Vertical display position on the sprite screen: Settable in 2-dot units

Line spacing control: Settable in 2-dot units (Set for each line)

Character/color signal output

R[2:0], G[2:0], B[2:0]: OSD color digital output signal

ROUT, GOUT, BOUT (OSD color analog output signal) *1

VOB1 (OSD display period output signal) *2

VOB2 (OSD translucent color period output signal) *2

*1: DAC output signal. The DAC outputs R, G, and B at 8 levels each.

*2: VOB1 and VOB2 are common to digital/analog.

Interrupt functions

Line display end interrupt

Vertical sync signal detection interrupt

VRAM fill end interrupt

Clock frequency

Maximum frequency: 90 MHz

551


20.2 Block Diagram

This section shows the OSDC block diagram.

Block Diagram

Figure 20.2-1 shows the block diagram of the OSDC and peripheral units.

Figure 20.2-1 Block Diagram

Font I/F

VRAM I/FRAM

FLASH

F-BUS

DAC

PLL

OSDCM203

OSDC register control signal

Font data

VRAM data

DAC control signal

InterruptTo CPU

PLL control signal

CPOVGSVDDI (8: For PLL)

R[2:0]G[2:0]B[2:0]

Digital RGB

VOB1VOB2DCKODOCKIFHVSYNCHSYNC

Display period signal

GOUTBOUT

VREFVROVDDRRCOMPVSSRVDDGGCOMPVSSGVDDBBCOMPVSSBROUT

552



This section explains the OSDC display functions.

OSDC Display Functions

This section explains the following OSDC display functions:

• Screen configuration

• Screen display modes

• Screen output control

• Screen display position control

• Font memory configuration

• Display memory (VRAM) configuration

• Writing to display memory (VRAM)

• Palette configuration

• Text display

• Character background display

• Line background display

• Screen background display

• Sprite character display

553


20.3.1 Screen Configuration

The display screen consists of various screen elements.

Screen Configuration

The display screen consists of the screen elements shown in Table 20.3-1 .

Table 20.3-1 Display Screen Elements

Display screen name Screen configuration Display position control

Top layer

Bottom layer

Sprite character 1 sprite character(consisting of 2 × 2 characters max.)

Horizontal/vertical: In 2 dots

Main screen Character (+ trimming)

42 characters × 16 lines Horizontal/vertical: In 4 dots

Character background

42 characters × 16 lines (Character/background concurrent control)

Line background

16 lines (Character/background concurrent control)

Screen background character

1 type (Repeatedly displayed pattern of 2 × 2 characters)

Fixed

Screen background (Full screen display in single color)

Fixed

554


Screen Configuration Drawing

Figure 20.3-1 shows the screen configuration diagram.

Figure 20.3-1 Screen Configuration Drawing

Note:

When a line is displayed on a line, the shaded background shadow frame for the linebackground overrides the character display.

The shaded background shadow frame for the character background overrides the characterdisplay and the shaded background shadow frame for the line background.

17

Screen backbround characters

Character background (character background color)

Source video for synchronization

Screen background (screen background color)

Sprite character+ trimming

Line 0 Line background )line background color

Line 1

Line 2

Line 3

Line 4

Line 5

Line 6

Line 7

Line 10

Line 11

Line 12

Line 13

Line 14

Line 15

42 columns

× × ×

× × × × × × × × × × × × × × × ?× × × × × × × × × × × × × × × × × ?× × × × × × × × ?× × × × ×

Character + trimming

555


20.3.2 Screen Display Modes

This section explains the display modes of the display screen elements.

Screen Display Modes

Table 20.3-2 shows the display modes of the display screen elements.

Table 20.3-2 Screen Display Modes (1 / 2)

Display screen name

Display mode

Screen background Undisplay

Display


Undisplay

DisplayNote: Only graphic character can be used.

Character pattern Consisting of a single character

Consisting of 2 horizontally aligned characters

Consisting of 2 vertically stacked characters

Consisting of 2 × 2 characters

Main screen

Line back-ground

Undisplay Line spacing 0 to 14 dots

Solid-fill display

Shaded background concaved display Shaded back-ground succeed-ing line merge

Indepen-dent

Shaded background convexed display Merge

Charac-ter back-ground

Undisplay

Solid-fill display Character background extended (enabled with line spacing control on)

Normal

Shaded background convexed display

Shaded back-ground succeed-ing charac-ter merge

Indepen-dent

Shaded back-ground succeed-ing line merge

Indepen-dent

Extended

Shaded background convexed display

Merge Merge

556


Main screen

Charac-ter

Graphic character

Normal charac-ter

Undisplay (blank character)

Display Trim-ming output control

Undisplay Trim-ming mode

Horizon-tal trim-ming 1

Trim-ming type

Undis-play

Display with no character background Horizon-tal trim-ming 2

Right trimming

Undisplay only within shaded background

Pattern back-ground 1

Left trimming

Full display Pattern back-ground 2

Both-side trimming

Italic output control

Undisplay

Italic display

Under-line output control

Undisplay

Underline display

Sprite character Undisplay

DisplayNote: Only graphic characters can be used.

Character attribute Consisting of a single character

Consisting of 2 horizontally aligned characters

Consisting of 2 vertically stacked characters

Consisting of 2 × 2 characters

Table 20.3-2 Screen Display Modes (2 / 2)

Display screen name

Display mode

557


20.3.3 Screen Output Control

This section explains the relationship between elements subject to screen output control and the control bits.

Screen Output Control

Table 20.3-3 shows the relationship between the elements subject to screen output control andthe control bits.

Table 20.3-3 Screen Output Control

Display screen control

Elements to be controlled Control bit name (unit of control)

Character + trimming + character background + line background

DSP (screen)

Character + trimming + character background

LDS (line)

Character M8 to M0 (character)

Character trimming

LFD to LFA (line)

Character background MM1, MM0(character), MIT, MUL

Line background LM1, LM0 (line)

Screen background character PDS (screen)

Screen background color UDS (screen)

Sprite character SDS (screen)

558


20.3.4 Screen Display Position Control

The OSDC can control the display positions on the main screen, screen background characters, screen background colors, and sprite characters independently.

Display Position Control on the Main Screen

The MB91310 controls the display start positions of a character (or a line of characters),character trimming, character background, and line background simultaneously.

Vertical display position: Vertical display position control (command 5-2), Bits Y8 to Y0

Set the vertical display start position relative to the VSYNC position.

The position can be set between 0 and 2044 dots in 4-dot units.

Horizontal display position: Horizontal display position control (command 5-3), Bits X8 to X0

Set the vertical display start position relative to the HSYNC position.


Line spacing: Line control data set 1 (command 3), Bits LW2 to LW0

Set the number of dots to specify the width of the areas to be kept above and below thecharacters on each line.

The spacing specified by the set value will be kept both above and below the characters.

The line spacing can be set between 0 and 14 dots in 2-dot units for each line.

(Note: When line double-height display is on, the line spacing is doubled as well.)

Figure 20.3-2 shows the display positions on the main screen.

559


Figure 20.3-2 Display Positions on the Main Screen

Vertical display position (see *1 in Figure 20.3-2 .)

Counting for the vertical display position is started 1Hsync after the sync pulse of the verticalsync signal (VSYNC pin input signal) as shown below.

Figure 20.3-3 shows the count timing for the vertical display position on the main screen.

Figure 20.3-3 Count Timing for the Vertical Display Position on the Main Screen

Note: If VSYNC and HSYNC are as shown above in Figure 20.3-3 , the display start positionremains unchanged due to the setting of the vertical synchronization detection HSYNC edgeselection control (bit VHE) of input-output control 2 (command 13-1).

←VSYNC position

HSYNC position

↓ Line spacing Vertical display position

Line 0

Horizontaldisplay position

Line spacing

Line 1

Line background (horizontal) display positionLine 2

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. . .CharacterCharacterCharacterCharacterCharacterCharacterCharacterCharacterCharacter

. . .CharacterCharacterCharacterCharacterCharacterCharacterCharacterCharacterCharacter

. . .

. . .

CharacterCharacterCharacterCharacterCharacterCharacterCharacterCharacterCharacter*3

*2

*1

VSYNC

HSYNC

Display output timing

Sync signal input timing

↑* Display start position when vertical display start position on the main screen is set to 0

RGB (digital/analog)

VOB1,VOB2

560


Horizontal display position (see *2 in Figure 20.3-2 .)

The horizontal display position is the set value + several dot clocks (see “20.3.5 Screen DisplayPosition Offset”) after the sync pulse significant edge (controlled by bit HE of command 13-1) ofthe horizontal sync signal (HSYNC pin input signal).

Line background display position (see *3 in Figure 20.3-2 .)

The horizontal display position of the line background is several dot clocks (see “20.3.5 ScreenDisplay Position Offset”) after the horizontal sync pulse significant edge (controlled by bit HE ofcommand 13-1).

Reference:

The vertical display position of the line background is controlled by bits Y8 to Y0 of thevertical display position control (command 5-2) to enable the display position to be movedconcurrently with characters on the main screen.

Notes:

• Vertical display position control varies depending on the setting of the interlace control (bitIN) of synchronous control (command 11-0). (For details, see Section "20.4.5 SynchronizationControl")

• Display output of display signal outputs (RGB, VOB1, and VOB2) are off during the specifiedperiod after input of the sync pulse of the vertical sync signal (VSYNC pin input signal) andthe sync pulse of the horizontal sync signal (HSYNC pin input signal).

561


Display Position Control of Screen Background Characters

Figure 20.3-4 shows the display positions of screen background characters.

Figure 20.3-4 Display Positions of Screen Background Characters


The vertical display position is fixed to 1Hsync after the sync pulse of the vertical sync signal(VSYNC pin input signal) and is shown in Figure 20.3-3 .


The horizontal display position is several dot clocks (see “20.3.5 Screen Display PositionOffset”) after the sync pulse significant edge (controlled by bit HE of command 13-1) of thehorizontal sync signal (HSYNC pin input signal).

Note:

Display output of display signal outputs (RGB, VOB1, and VOB2) are off during the specifiedperiod after input of the sync pulse of the vertical sync signal (VSYNC pin input signal) andthe sync pulse of the horizontal sync signal (HSYNC pin input signal).
















• • • •

• • • •

• • • •

• • • •

• • • •

• • • •

• • • •

• • • •

HSYNC positionVSYNC position

Horizontaldisplay position*2

Vertical display position*1

562


Display Position Control of Screen Background Color

Figure 20.3-5 shows the display position of the screen background color.

Figure 20.3-5 Display Position of Screen Background Color


The vertical display position is immediately after the trailing edge of the sync pulse of thevertical sync signal (VSYNC pin input signal).

Figure 20.3-6 shows the vertical display position of the screen background color.

Figure 20.3-6 Display Start Position of Screen Background Color


The horizontal display position is several dot clocks (see “20.3.5 Screen Display PositionOffset”) after the sync pulse significant edge (controlled by bit HE of command 13-1) of thehorizontal sync signal (HSYNC pin input signal).

Note:


←VSYNC position

HSYNC position Vertical display position↓

Horizontal display position*2

*1

VSYNCHSYNC

Display output PO[15: 0], VOB output timing

Sync signal input timing

↑* Display start position of screen background color

RGB (digital/analog)VOB1,VOB2

563


Display Position Control of Sprite Characters

The ODSC controls the display start positions of a sprite character and its trimming.

Sprite character vertical display position: Sprite character control 4 (command 9-0), Bits SY9 to SY0

Set the vertical display position relative to the sync pulse of the vertical sync signal (VSYNC pininput signal).


Sprite character horizontal display position: Sprite character control 5 (command 9-1), Bits SX9 to SX0

Set the horizontal display position relative to the sync pulse of the horizontal sync signal(HSYNC pin input signal).



Figure 20.3-7 shows the display position of sprite characters.

Figure 20.3-7 Display Position of Sprite Characters

The vertical display position reference is the same as on the main screen; it is 1H after the syncpulse signal of the vertical sync signal (VSYNC pin input signal). See Figure 20.3-3 .

Horizontal display position (see *2 in Figure 20.3-7.)

The horizontal display position is several dot clocks (details are "20.3.5 Screen Display PositionOffset") after the sync pulse significant edge (controlled by bit HE of command 13-1) of thehorizontal sync signal (HSYNC pin input signal).

Note:


↓

HSYNCposition

Vertical display position*

Horizontal display position*2

←VSYNC position

1

Sprite character

564


20.3.5 Screen Display Position Offset

There is a display offset for each display position of the main screen, screen background colors, and sprite characters. Also, when the screen background character and the sprite character display is not performed, the offset value of the main screen display is allowed to reduce.

Screen Display Position Offset

The horizontal display position offset value is shown in the Table 20.3-4 ,Table 20.3-5 andTable 20.3-6 .

The display position offset becomes the dot clock number from the effective edge (command13-1 controlled by the HE bit) of the horizontal synchronous signal (HSYNC pin input signal)synchronous pulse.

Also, each operation control is stopped by the PCUT bit of the screen background characteroperation control stop (command 7-1) and the SCUT bit of the sprite character operation controlstop (command 8-1), the offset value of the main screen is allowed to reduce.

• When the main screen, sprite characters, and screen background characters are displayedconcurrently the offset value is shown as follow.

• When either of the operation control for the sprite characters or the screen backgroundcharacters is stopped, the offset value is shown as follow.

Table 20.3-4 Horizontal display position offset value 1

Display screen Offset value

Sprite character 120

Main screen (character) 150

Main screen (line background) 50

Screen background characters 122

Screen background colors 50

Note: The unit of the offset value is the dot clock number.


Display screen Offset value(PCUT=1)

Offset value(SCUT=1)

Sprite character 72 -

Main screen (character) 102 102

Main screen (line background) 50 50

Screen background characters - 74

Screen background colors 50 50


565


Notes:

• When the screen background character operation control is stopped (PCUT=1),setting the PDS of the screen output control 1 (command 5-00) to "0", and do notperform the screen background character display.

• When the sprite character operation control is stopped (SCUT=1), setting the SDS bitof the screen output control 1 (command 5-00) to “0”, and do not perform the screenbackground character display.

• When the main screen is displayed, the offset value is shown as follow.

Notes:

• When the screen background character operation control is stopped (PCUT=1), settingthe PDS of the screen output control 1 (command 5-00) to "0", and do not perform thescreen background character display.

• When the sprite character operation control is stopped (SCUT=1), setting the SDS bitof the screen output control 1 (command 5-00) to “0”, and do not perform the screenbackground character display.


Display screen Offset value

Sprite character -

Main screen (character) 69

Main screen (line background) 50

Screen background characters -

Screen background colors 50


566


20.3.6 Font Memory Configuration

The font memory has a capacity of 1,792 characters of 24 x 32 dots each.• The user can set any of the 1,792 characters.Note:A blank character is not reserved. Set a blank character in any character code if necessary.• Any graphic character/normal character can be set.(However, a graphic character uses the same amount of data as four normal characters.)

Font Memory Configuration

Figure 20.3-8 shows the font memory configuration.

Figure 20.3-8 Font Memory Configuration

Font memory configuration

24 dots

32 dots

(Character configuration example)

0000H (User area)

0001H (User area)

0002H (User area)

037FH (User area)

0380H (User area)

0381H (User area)

06FDH (User area)

06FEH (User area)

06FF H (User area)

Character code

567


20.3.7 Display Memory (VRAM) Configuration

The display memory (VRAM) consists of the character RAM for setting individual characters and the line RAM for setting individual lines.• Character RAM: 42 characters × 16 lines (672 characters in total)• Line RAM: 16 lines

Display Memory and Display Screen

Areas of character RAM and those of line RAM correspond to displayed characters and lines ona one-to-one basis, respectively.

Figure 20.3-9 shows the display memory configuration.

Figure 20.3-9 Display Memory Configuration

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 3 3 3 3 3 4 4

0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1

Character RAM Line RAM

Column addresses

Row addresses

568


20.3.8 Writing to Display Memory (VRAM)

The OSDC command is set at OSDC control addresses 00H to 08H for writing to display

memory.• Writing a single character to character RAM• Writing multiple characters to character RAM collectively• Writing to line RAM

Writing to Display Memory

The OSDC command is issued to OSDC control addresses 00H to 08H for writing to displaymemory.

Writing a Single Character to Character RAM

Use the following commands to write data on an arbitrary character to an arbitrary address incharacter RAM:

Figure 20.3-10 shows the procedure for writing to character RAM.

Figure 20.3-10 Procedure for Writing to Character RAM

*1: When writing to consecutive addresses continuously, you can omit this command for thelatter character RAM write.

*2: You can also omit this command if the current character data is the same as the one set bythe preceding "character data set 1" command.

*1

VRAM write address set (Command 0) Set the row and column addresses

*2

Character data set 1 (Command 1)

Write the character data to character RAM. The VRAM write address is then incremented.


569


Writing Multiple Characters Collectively (VRAM Fill)

Use the following commands to write data on an arbitrary character to an area of character RAMfrom an arbitrary address to the last address, filling the area with that data:

Figure 20.3-11 shows the procedure for writing multiple characters collectively to character RAM(VRAM fill).

Figure 20.3-11 Procedure for Writing Multiple Characters Collectively to Character RAM (VRAM Fill)

*: When VRAM fill ends, the cause of VRAM fill end interrupt is set.

The VRAM fill execution time depends on the dot clock frequency. The reference value forVRAM fill of an entire screen is as follows:

Dot clock 90 MHz: About 0.1 ms

During execution of VRAM fill, command 1-4 cannot be issued.

Issuing command 0 (FL =0) during execution of VRAM fill aborts the VRAM fill.

To set a VRAM write address after VRAM fill has aborted, reissue command 0.

VRAM write address set (Command 0) Set the row and column addressesand specify "VRAM fill".


The character RAM write executesVRAM fill.Character data set 2 (Command 2)

*

570


Writing to Line RAM

Use the following commands to write data on an arbitrary line to an arbitrary address in lineRAM:

Figure 20.3-12 shows the procedure for writing to line RAM.

Figure 20.3-12 Procedure for Writing to Line RAM

*1: The line RAM fill function is not available. (It is prohibited to specify file.)

*2: You can omit this command if the current line control data is the same as the one set by thepreceding "line control data set 1" command.

*3: Any line RAM write does not increment the VRAM write address. You must therefore set aline address for each line.

*1

VRAM write address set (Command 0) Set the row address.

*2

*3

Line control data set 1(Command 3)

Line control data set 2 (Command 4) Write the line data to line RAM.(The VRAM write address remainsunchanged.)

571


20.3.9 Palette Configuration

The palette converts the 4-bit color code output by the OSDC to a 9-bit color code.

Palette RAM Configuration

The palette converts the 4-bit color code to be set in the OSDC to the 3-bit color codes for theRGB signal.

Figure 20.3-13 shows the correspondence between palette-set addresses and OSDC-set colorcodes.

Figure 20.3-13 Palette Configuration

*1 OSDC-set color codes refer to the following settings:

Character (MC3 to MC0), character background (MB3 to MB0), trimming color (LF3 to LF0), linebackground color (L3 to L0), shaded background frame color (BH3 to BH0, BS3 to BS0),graphic color control (GF3 to GF0, GC3 to GC0), screen background color (U3 to U0), andgraphic character color

3CH 3EH 40 H

5AH

42 H

44 H

46 H

48 H

4AH

4CH

4EH

50 H

52 H

54H

56H

58H

Red (3 bits) Green (3 bits) Blue (3 bits)

OSDC control palette write address

Palette configuration

(9 bits)

[ 1 0 : 8 ]

0H

1H

2H

FH

3 H

4 H

5H

6H

7H

8H

9H

A H

B H

CH

DH

E H

OSDC read palette address = OSDC-set color code

* 1

B i t

[ 6 : 4 ]

[ 2 : 0 ]

572


20.3.10 Text Display

This section explains the text display control functions.

Text Display Control Functions

The following text display control functions are available:

• Character sizes

• Character colors

• Italic display

• Underline display

• Character trimming

• Line enlarged display

• Graphic character control

• Blink control

• Transparent/translucent color control

573


20.3.10.1 Character Size

The vertical and horizontal sizes of each character to be displayed can be set.Each character is displayed by clipping the specified size of the specified character data from the font memory, starting at the upper leftmost dot.

Character Horizontal Size Control (Setting for Each Character)

Table 20.3-7 shows the character horizontal sizes of character data set 1 (command 1): BitsMS1 and MS0.

Line Character Vertical Size Type Control (Setting for Each Line)

Table 20.3-8 shows the line character vertical size types of line control data set 1 (command 3):Bit LHS.

Table 20.3-7 Character Horizontal Size Control

MS1 MS0 Character horizontal size

0 0 S size: 12 dots

0 1 M size: 18 dots

1 0 L size: 24 dots

1 1 (Setting prohibited)

Table 20.3-8 Line Character Vertical Size Type Control

LHS Line character vertical size type

0 Character vertical size A

1 Character vertical size B

574


Character Vertical Size A/B

Table 20.3-9 shows the character vertical sizes A and B of character vertical size control(command 6-0): Bits HA2 to HA0/HB2 to HB0.

Display Examples

A character stored in the font memory

Figure 20.3-14 shows an example of displaying a character stored in the font memory.

Figure 20.3-14 Example of Displaying a Character Stored in the Font Memory

Display example 1 (vertical character size = 32 dots)

Figure 20.3-15 shows an example of displaying a character with vertical size = 32 dots.

Table 20.3-9 Character Vertical Sizes A and B

HA2/HB2 HA1/HB1 HA0/HB0 Character vertical size A/B

0 0 0 18 dots

0 0 1 20 dots

0 1 0 22 dots

0 1 1 24 dots

1 0 0 26 dots

1 0 1 28 dots

1 1 0 30 dots

1 1 1 32 dots

24 dots

32 dots

575


Figure 20.3-15 Example of Displaying a Character With Vertical Size = 32 dots

Display example 2 (vertical character size = 22 dots)

Figure 20.3-16 shows an example of displaying a character with vertical size = 22 dots.

Figure 20.3-16 Example of Displaying a Character with Vertical Size = 22 dots

24 dots 18 dots 12 dots 18 dots

32 dots

L size M size S size M size

24 dots 18 dots 12 dots 18 dots

22 dots

L size M size S size M size

576


Applied Display Examples

Example of displaying characters all in the L size

Figure 20.3-17 shows an example of displaying all characters in L size.

Figure 20.3-17 Example of Displaying All Characters in L Size

Example of displaying characters in the L, M, and S sizes

Figure 20.3-18 shows an example of displaying characters in L, M, and S sizes.

Figure 20.3-18 Example of Displaying Characters in L, M, and S Sizes

Example of displaying characters in L/M/S vertical sizes

Figure 20.3-19 shows an example of displaying characters in L/M/S vertical sizes.

Figure 20.3-19 Example of Displaying Characters in L/M/S Vertical Sizes

32 dots

L L L L L L (←Size)

32 dots

L M M S S M (←Size)

18 dots

32 dots

32 dots

18 dots

577


20.3.10.2 Character Colors

Character colors can be selected from among 16 colors and set for each character.

Character Colors (Setting for Each Character, Selected from among 16 Colors)

Character colors can be set for each character by setting color codes in bits MC3 to MC0 ofcharacter data set 1 (command 1).

Note:

If OSDC display color output control (DCX) is set to "0", the set color code is used. If DCX isset to "1", the color code with the bit inverted from 0 to 1 or vice versa becomes the paletteread address.

578


20.3.10.3 Italic Display

The italic display function displays character dots tilted. Italic display can be set for each character.

Italic Display Control

The italic attribute can be set for each character by setting bit MIT of character data set 1(command 1).

Italic Display Rules

• A nonitalic character following an italic character is displayed in italics ((1) in Figure 20.3-20 ).

• If italic character dots protrude from a nonitalic character displayed in italics by italic displayto the subsequent nonitalic character, the protruded dots are not displayed ((2) in Figure20.3-20 ).

• The dot colors that protrude because of italic display depend on the color setting of theprotruding character area ((3) in Figure 20.3-20 ).

• If an italic character has a right frame of shaded character background display, the protrudeddots of the italic character are not displayed ((4) in Figure 20.3-20 ).

• Italic display is disabled for character attributes, character colors, character backgroundcolors, graphic characters, underlines, and shaded character backgrounds.

Table 20.3-10 Italic Character Control (Setting for each Character)

MIT Italic character control

0 Normal character

1 Italic character

579


Display Example

Figure 20.3-20 shows examples of displaying italic characters.

Figure 20.3-20 Example of Displaying Italic Characters

Example of displaying italic characters




*MM: Character background control (command 1)*MR: Shaded background succeeding character merge control (command 2)

MIT=1MM=10MR=1

MIT=0MM=11MR=0

MIT=0

MIT=0 MIT=0 MIT=0

MIT=1MM=10MR=0

MIT=0MM=01MR=0

MIT=1

MIT=1 MIT=0 MIT=0

MIT=1 MIT=0 MIT=0


(4)

(3)

(1) (2)

580


Origin of Italic Character

The tilt origin of an italic character is character height independent and at the lower left of 32 × 24 dots.

Figure 20.3-21 and Figure 20.3-22 show the italic state.

Figure 20.3-21 Italic State in Which 32 Vertical Dots are Displayed

Figure 20.3-22 Italic State in Which 18 Vertical Dots are Displayed

Note:

The tilt origin of italic character display is character height independent and at lower left of 32 × 24 dots.

581


20.3.10.4 Underline Display

The underline display function displays a horizontal line under a character. Underline display can be set for each character.

Underline Display Control

The underline attribute can be set for each character by setting bit MUL of character data set 1(command 1).

Underline Display Rule

An underline is dependent on character vertical size control and is displayed on the third andfourth dots from the bottom dot.

Display Example

Figure 20.3-23 shows an example of displaying an underline.

Figure 20.3-23 Example of Displaying an Underline

Table 20.3-11 Underline Control (Setting for Each Character)

MUL Underline control

0 Normal character

1 Underline display

582


20.3.10.5 Character Trimming

Horizontal synchronous operation can be synchronized with the leading edge or trailing edge.

Trimming Output Control

Trimming output control turns on or off the trimming of characters according to their characterbackground type.

One of the four character background types can be set for each line.

Table 20.3-12 shows the trimming output control of line control data set 1 (command 3): BitsLFD and LFC.

x: Off*

O: On

*: The display is "no pattern background" in pattern background 1 or 2 mode.

Table 20.3-12 Trimming Output Control (Setting for Each Line)

Trimming output control (Setting

for each line)

Character background type (Setting for each character)

Trimming output

LFD LFC MM1 MM0 Background display

0 0

0 0 Undisplay x

0 1 Solid background x

1 0 Concaved, shaded background x

1 1 Convexed, shaded background x

0 1

0 0 Undisplay O

0 1 Solid background x



1 0

0 0 Undisplay O

0 1 Solid background O



1 1

0 0 Undisplay O

0 1 Solid background O

1 0 Concaved, shaded background O

1 1 Convexed, shaded background O

583


Trimming Type Control

Trimming display is controlled by selecting the combination of one of the four trimming types setfor each screen and one of the four trimming outputs set for each line.

Trimming type control (Setting for each screen)

Trimming type control for each screen ensures that four types of display format, for example,horizontal trimming and pattern background, can be selected and used.

Pattern backgrounds 1 and 2 enable the representation of virtual trimming that cannot berepresented by 1-dot and 2-dot horizontal trimming. However, font data must be designed forpattern backgrounds 1 and 2. Displaying this font data in another format (e.g., 1-dot trimming)may distort the display shape.

Table 20.3-13 shows the trimming type control of screen output control 2 (command 5-1): BitsFM1 and FM0.

1-dot horizontal trimming

A character dot (original data) is displayed with 1-dot trimming added to the right and leftends (*) of the character dot.

2-dot horizontal trimming

A character dot (original data) is displayed with 2-dot trimming added to the right and leftends (*) of the character dot.

Pattern background 1

If font data 1 continues for two bits or more in the horizontal direction, the character dots forthe number of continuous bit 1s are displayed with a 1-dot pattern background added to theright and left ends (*) of the character dots.

Pattern background 2

If font data 1 continues for two bits or more in the horizontal direction, the character dots forthe number of continuous bit 1s are displayed with a 2-dot pattern background added to theright and left ends* of the character dots.

*: Control by bits LFB and LFA turns off display of horizontal trimming and pattern backgroundand displays horizontal trimming and pattern background at the left or right end of a characterdot.

Trimming control (Setting for each line)

Trimming control for each line allows specification of whether a trimming dot is displayed on theright, left, or left and right.

Table 20.3-14 shows the trimming control of line control data set 1 (command 3): Bits LFB andLFA.

Table 20.3-13 Trimming Type Control (Setting for Each Screen)

Trimming type control Trimming type

FM1 FM0

0 0 1-dot horizontal trimming

0 1 2-dot horizontal trimming

1 0 Pattern background 1

1 1 Pattern background 2

584


Table 20.3-14 Trimming Control (Setting for Each Line)

Trimming control Trimming output

LFB LFA

0 0 Undisplay

0 1 Right trimming

1 0 Left trimming

1 1 Both-side trimming

585


Display Example

• Display example of single-dot horizontal trimming (FM1, FM0 = 0, 0) Figure 20.3-24 shows a display example of single-dot horizontal trimming (FM1, FM0 = 0, 0).

Figure 20.3-24 Display Example of Single-Dot Horizontal Trimming (FM1, FM0 = 0, 0)

Font ROM (original image data) No trimming (LFB, LFA = 0, 0)

Display

Right trimming(LFB, LFA = 0, 1)

Left trimming(LFB, LFA = 1, 0)

Both-side trimming(LFB, LFA = 1, 1)

586


• Display example of double-dot horizontal trimming (FM1, FM0 = 0, 1) Figure 20.3-25 shows a display example of double-dot horizontal trimming (FM1, FM0 = 0,1).

Figure 20.3-25 Display Example of Double-dot Horizontal Trimming (FM1, FM0 = 0, 1)


DIsplay

Right trimming(LFB, LFA = 0, 1)



587


• Display example of pattern background 1 (FM1, FM0 = 1, 0) Figure 20.3-26 shows a display example of pattern background 1 (FM1, FM = 1, 0)

Figure 20.3-26 Display Example of Pattern Background 1 (FM1, FM = 1, 0)


Display

Right trimming(LGB, LFA = 0, 1)



588


• Display example of pattern background 2 (FM1, FM0 = 1, 1) Figure 20.3-27 shows a display example of pattern background 2 (FM1, FM0 = 1, 1)

Figure 20.3-27 Display Example of Pattern Background 2 (FM1, FM0 = 1, 1)


Display

Right trimming(LGB, LFA = 0, 1)



589


Trimming Colors

Trimming colors can be set for each line by setting color codes in bits LF3 to LF0 of line controldata set 1 (command 3).

Trimming Display Rules

• Trimming dots for a character can be displayed in the right-side or left-side adjacentcharacter area only when the character background types of the two characters are thesame.

• Trimming dots for the character at the left or right end of a line can be displayed beyond thecharacter area only when the character background type is “no character background".

• Trimming dots on a line are also enlarged when the line is displayed enlarged (if bits LG1and LG0 of line control data set 2 [command 4] are set to other than 0, 0).

Note:


590


20.3.10.6 Line Enlarged Display

Line enlarged display control controls the display size of each line including the characters, character backgrounds, and line background on that line (as well as the line spacing portions). Line enlarged display can be set in the vertical or horizontal direction or in both directions.This also controls enlargement of the shadow frames of shaded backgrounds and trimming dots. Note that the lines following the line for which line enlarged display has been specified are shifted down accordingly.

Line Enlargement Control (Setting for Each Line)

Table 20.3-15 and Table 20.3-16 show the line enlarged control of line control data set 2(command 4): Bits LGX1, LGX0, LGY1, and LGY0.

Table 20.3-15 Line Enlarged Control (Setting for Each Line)

LGY1 LGY0 Display size

0 0 Normal size

0 1 Double-height size


1 1 Quadruple-height size

Table 20.3-16 Line Enlarged Control (Setting for Each Line)

LGX1 LGX0 Display size

0 0 Normal size

0 1 Double-width size


1 1 Quadruple-width size

591


Line Enlarged Display Examples

Figure 20.3-28 show examples of line enlarged display in normal, double-width, quadruple-width, double-height, quadruple-height, double-width/height, and quadruple-width/height sizes.

• Normal size

Figure 20.3-28 Example of Line Enlarged Display

• Double-width size

• Quadruple-width size

Line spacing

Line spacing

Character Character Character Character Character Character Character CharacterDisplayedline

Line spacing

Line spacing

Character Character Character CharacterDisplayedline

Line spacing

Line spacing

Character CharacterDisplayedline

592


• Double-height size

• Quadruple-height size

Cha

ract

er

Cha

ract

er

Cha

ract

er

Cha

ract

er

Cha

ract

er

Cha

ract

er

Cha

ract

er

Cha

ract

er

Displayedline

Line spacing

Line spacing

Line spacing

Line spacing

Displayedline

Cha

ract

er

Cha

ract

er

Cha

ract

er

Cha

ract

er

Cha

ract

er

Cha

ract

er

Cha

ract

er

Cha

ract

er

593


• Double-width/height size

• Double-height/quadruple-width size

Line spacing

Line spacing

Character Character Character CharacterDisplayedline

Line spacing

Line spacing

Displayedline

Character Character

594


20.3.10.7 Graphic Character Control

The graphic character display function displays 24 x 32 dots graphic characters in 16 colors based on the 4-character dot patterns set in the font RAM. Graphic characters can be displayed in 16 colors dot by dot.

Character/graphic Character Control (Setting for Each Character)

A graphic character uses four continuous characters in the font RAM. To execute graphiccharacter display, set the two rightmost bits to "0".

Table 20.3-17 shows the character code settings.

Note:

To create a graphic character, use the OSDC pattern editor (PED/WIN) that supports thegraphic character.

Table 20.3-18 and Figure 20.3-29 show the character/graphic character control of characterdata set 2 (command 2): Bit MG.

Table 20.3-17 Specified Graphic Character Codes

Display layer Character code

Arbitrarily set bit Fixed bitSet 0.

Main screen M10 to M2 M1, M0


PM10 to PM2 PM1, PM0

Sprite SM10 to SM2 SM1, SM0

Table 20.3-18 Character/Graphic Character Control (Setting for Each Character)

MG Character/graphic character control

0 Normal character

1 Graphic character

595


Figure 20.3-29 Character/Graphic Character Control (Setting for Each Character)

Note:

Shaded background display is enabled even for graphic characters.

Graphic display example

(MG = 1)

(MM1 = 1, MM0 = 1) (MM1 = 1, MM0 = 0)

596


Graphic Color/Trimming Color Replace Control (Setting for Each Screen)

Table 20.3-19 shows the graphic color/trimming color replace control of graphic color control(command 6-3): Bit GFC.

This control replaces any color (color specified in bits GF3 to GF0) in a graphic character by thetrimming color (bits LF3 to LF0) set by line control data set 1 (command 3).

Code of the Color to be Replaced by the Trimming Color (Setting for Each Screen)

Figure 20.3-30 shows an example of color replacement of graphic color control (command 6-3):Bits GF3 to GF0.

Figure 20.3-30 Example of Replacing Code of the Color to be Replaced by the Trimming Color (Setting for Each Screen)

Notes:

• When graphic color/trimming color replace control is on (bit GFC is set to "1"), transparentcolor control is on (bit TCC of transparent color control [command 6-2] is set to "1"), and thecolor to be replaced by the graphic color/trimming color and transparent color (bits TC3 toTC0) of transparent color control (command 6-2) are the same, priority is given toreplacement by trimming color.

• When graphic color/trimming color replace control is on (bit GFC is set to "1"), transparentcolor control is on (bit TCC of transparent color control [command 6-2] is set to "1"), and thetrimming color (bits LF3 to LF0) of line control data set 1 (command 3) and the transparentcolor (bits TC3 to TC0) of transparent color control (command 6-2) are the same, priority isgiven to the transparent color and the lower-layer color is displayed.

• When graphic color/character color replace control is on (bit GCC is set to "1") and graphic

Table 20.3-19 Graphic Color/Trimming Color Replace Control (Setting for Each Screen)

GFC Graphic color/trimming color replace control

0 The specified color is not replaced.

1 The specified color is replaced by the trimming color.

[Displayed according to color information in the font RAM]

[Displayed in the specified replacing color]

GF3 to GF0:Specified colorto be replaced

Trimming color:

(Specified by bits LF3 to LF0 in command 3)

Replaced by thetrimming color

GFC=1

GFC=0

597


color/trimming color replace control is on (bit GFC is set to "1"), set the difference colors forthe color replaced by the character color (bits GC3 to GC0) and the color replaced by thetrimming color (bits GF3 to GF0).

Graphic Color/Character Color Replace Control (Setting for Each Screen)

Table 20.3-20 shows the graphic color/character color replace control of graphic color control(command 6-3): Bit GCC.

This control replaces any color (color specified in bits GC3 to GC0) in a graphic character by thecharacter color (bits MC3 to MC0) set by character data set 1 (command 1).

Color to be Replaced by the Character Color (Setting for Each Screen)

Figure 20.3-31 shows an example color replacement of graphic color control (command 6-3):Bits GC3 to GC0.

Figure 20.3-31 Example Replacement of the Code of the Color to be Replaced by the Character Color (Setting for Each Screen)

Notes:

• When graphic color/character color replace control is on (bit GCC is set to "1"), transparentcolor control is on (bit TCC of transparent color control [command 6-2] is set to "1"), and thecolor to be replaced by the graphic color/character color and transparent color (bits TC3 toTC0) of transparent color control (command 6-2) are the same, priority is given toreplacement by character color.

• When graphic color/character color replace control is on (bit GCC is set to "1"), transparentcolor control is on (bit TCC of transparent color control [command 6-2] is set to "1"), and the

Table 20.3-20 Graphic Color/Character Color Replace Control (Setting for Each Screen)

GCC Graphic color/character color replace control

0 The specified color is not replaced.

1 The specified color is replaced by the character color.

[Displayed according to color information in the font RAM]

[Displayed in the specified replacing color]

GF3 to GF0:Specified colorto be replaced

Trimming color:

(Specified by bits MC3 to MC0 in command 1)

GCC = 1

GCC = 0

Replaced by the character color

598


character color (bits MC3 to MC0) of character data set 1 (command 1) and the transparentcolor (bits TC3 to TC0) of transparent color control (command 6-2) are the same, priority isgiven to the transparent color and the lower-layer color is displayed.

• When graphic color/character color replace control is on (bit GCC is set to "1") and graphiccolor/trimming color replace control is on (bit GFC is set to "1"), set the difference colors forthe color replaced by the character color (bits GC3 to GC0) and the color replaced by thetrimming color (bits GF3 to GF0).

599


20.3.10.8 Blink Control

The OSDC can turn blinking of each character on or off. The blink cycle and duty ratio can also be set.

Blink Control (Setting for Each Character)

Table 20.3-21 shows the blink control of character data set 2 (command 2): Bits MBL and MBB.

Display Format

Figure 20.3-32 to Figure 20.3-37 show examples of a blinking character in different backgroundcolors.

Figure 20.3-32 Example of a Blinking Character with noBackground (MM1, MM0 = 0, 0)

Table 20.3-21 Blink Control (Setting for Each Character)

MBL MBB Blink control

0 0 Blink OFF (normal display)

1 0 Character blink ON

0 1 Character background blink ON

1 1 Character + character background blink ON

MBL=1 MBB=0

600


Figure 20.3-33 Example 1 of a Blinking Character with a Solid-Filled Background (MM1, MM0 = 0, 1)



[The solid-filled background remains

displayed during blinking when MBB = 0]

MBL=1 MBB=0

MBL=0MBB=1

[The solid-filled background is not displayed during blinking when MBB = 1]

MBL=1MBB=1

[The solid-filled background is not displayed during blinking when MBB = 1]

601


Figure 20.3-36 Example of a Blinking Character with a Shaded Background (MM1, MM0 = 1, 1)

Figure 20.3-37 Example of a Blinking Graphic with No Background (MM1, MM0 = 0, 0)

[A shaded background also remains

displayed during blinking]

MBL=1 MBB=1

MBL=1 MBB=0

602


Blink Cycle

Table 20.3-22 shows the blink cycles of screen output control 2 (command 5-1): Bits BT1 andBT0.

Blink Duty Ratio

Table 20.3-23 shows the blink duty ratio control of screen output control 2 (command 5-1): BitsBD1 and BD0.

Table 20.3-22 Blink Cycle Control (Setting for Each Screen)

BT1 BT0 Blink cycle

0 0 16 x VSYNC

0 1 32 x VSYNC

1 0 48 x VSYNC

1 1 64 x VSYNC

Table 20.3-23 Blink Duty Ratio Control (Setting for Each Screen)

BD1 BD0 (On:Off) Blink duty ratio

0 0 1:0 (Always on)

0 1 1:1

1 0 1:3

1 1 3:1

603


20.3.10.9 Transparent/Translucent Color Control

Transparent/translucent color control allows display of the color on the lower layer than any display color. Translucent color control outputs the translucent display period to allow translucent color processing to be executed externally.

Transparent Color Control (Setting for Each Screen)

Table 20.3-24 shows the transparent color control using [command 6-2]: Bit TCC.

Figure 20.3-38 shows an example of setting a transparent color using transparent color control(command 6-2): Bits TC3 to TC0 (if the areas with the darkest color shown below are set as atransparent color).

Table 20.3-24 Transparent Color Control (Setting for Each Screen)

TCC Transparent color control

0 Disable transparent color control.

1 Enable transparent color control.

604


Figure 20.3-38 Example of Setting a Translucent Color

[Specified transparent color]


Main screen

Sprite character

(Specified transparent color) ↑ TCC=0↓ TCC=1 TC3-TC0:

Screen background color(or original video screen)

605


Translucent Color Control (Setting for Each Screen)

Table 20.3-25 shows the translucent color control (command 6-2): Bit HCC.

Figure 20.3-39 shows an example of setting a translucent color using translucent color control(command 6-2): Bits HC3 to HC0.

Figure 20.3-39 Example of Setting a Translucent Color

Table 20.3-25 Translucent Color Control (Setting for Each Screen)

HCC Translucent color control

0 Disable translucent color control.

1 Enable translucent color control.

[Specified translucent color]

Screen background color(or original video screen)


Main screen character

Character background

Sprite character

Example of VOB2 pin outputfor this raster line

VOB2

(Specified transparent color) ↑ HCC=0HCC=1 HC3 to HC0:

606


20.3.11 Character Background Display

Four character background types and 16 character background colors can be set for each character.

Character Background Control (Setting for Each Character)

Table 20.3-26 shows the character background control of character data set 1 (command 1):Bits MM1 and MM0.

Shaded Background Highlight Color (Setting for Each Screen, Selected from Among 16 Colors)

Shaded background highlight colors can be set by setting color codes in bits BH3 to BH0 ofshaded background frame color control (command 6-1).

Shaded Background Shadow Color (Setting for Each Screen, Selected from Among 16 Colors)

Shaded background shadow colors can be set by setting color codes in bits BS3 to BS0 ofshaded background frame color control (command 6-1).

Character Background Color (Setting for Each Screen, Selected from Among 16 Colors)

Character background colors can be set by setting color codes in bits MB3 to MB0 of characterdata set 1 (command 1).

Note:


Table 20.3-26 Character Background Control (Setting for Each Character)

MM1 MM0 Character background

0 0 No background (undisplay)

0 1 Solid-filled background

1 0 Concaved, shaded background

1 1 Convexed, shaded background

607


Display Examples

Figure 20.3-40 Example of Character Background Display

(1) No background (2) Solid-filled background

Screenbackground coloror synchronizationsource video

Character display

(3) Concaved, shaded background (4) Convexed, shaded background

Shaded backgroundshadow color

Shaded backgroundhighlight color

Shaded backgroundhighlight color

Shaded backgroundshadow color

Characterbackground color



Note: The shaded background frame for a character is displayed inside the circumference of the character area.

608


20.3.11.1 Shaded Background Succeeding Character Merge Display

Specifying "shaded background succeeding character merge display" for a character undisplays the right line of the shadow frame of the character and the left line of the shadow frame of the next character. This enables two or more characters with shaded backgrounds to be joined horizontally.

Shaded Background Succeeding Character Merge Control (Setting for Each Character)

Table 20.3-27 shows the shaded background succeeding character merge control of characterdata set 2 (command 2): Bit MR.

Table 20.3-27 Shaded Background Succeeding Character Merge Control (Setting for Each Character)

MR Shaded background succeeding character merge control

0 OFF

1 ON

609


Display Examples

Independent characters with shaded backgrounds

Figure 20.3-41 shows display examples of independent characters with shaded backgrounds.

Figure 20.3-41 Display Examples of Independent Characters with Shaded Backgrounds

Display examples of merged characters with shaded backgrounds

Figure 20.3-42 shows display examples of merged characters with shaded backgrounds.

Figure 20.3-42 Display Examples of Merged Characters with Shaded Backgrounds

(Succeeding charactermerge = OFF)

(Suceeding charactermerge = OFF)

(Succeding charactermerge = OFF)

(Succeeding charactermerge = ON)



610


20.3.11.2 Shaded Background Succeeding Line Merge Display (Character Background)

Specifying both of "shaded background succeeding line merge display" and “character background extended display” for a line undisplays the lower lines of the shadow frames of the characters on that line and the upper lines of the shadow frames of the characters on the next line. (Shaded background succeeding line merge display and character background extended display must both be executed for the current line, and character background extended display must be executed for the next line.)This enables two or more lines of characters with shaded backgrounds to be joined vertically.

Shaded Background Succeeding Line Merge Control (Setting for Each Line)

Table 20.3-28 shows the shaded background succeeding line merge control of line control dataset 2 (command 4): Bit LD.

Table 20.3-28 Shaded Background Succeeding Line Merge Control (Setting for Each Line)

LD Shaded background succeeding line merge control

0 OFF

1 ON

611


Display Examples

Figure 20.3-43 shows display examples of merged lines of characters with shadedbackgrounds.

Figure 20.3-43 Display Examples of Merged Lines of Characters with Shaded Backgrounds

Note:

If character background extended display is not specified, shaded background succeedingline merge display is disabled for character backgrounds. (Shaded background succeedingline merge display is enabled for line backgrounds.)

Suceeding linemerge = ONand Extended display= ON

Succeeding linemerge = OFFandExtended display= ON




612


20.3.11.3 Character Background Extended Display

Character background extended display extends character backgrounds to line spacing portions.(Note that this setting is required to apply shaded background succeeding line merge display to character backgrounds.)

Character Background Extended Display (Setting for Each Line)

Table 20.3-29 shows the character background extended display of line control data set 2(command 4): Bit LE.

Table 20.3-29 Character Background Extended Display (Setting for Each Line)

LE Character background extended display

0 OFF (Normal display)

1 ON (Extended display)

613


Display Examples

Character background extended display = OFF

Figure 20.3-44 shows a display example with character background extended display = OFF.

Figure 20.3-44 Display Example with Character Background Extended Display = OFF

Character background extended display = ON

Figure 20.3-45 shows a display example with character background extended display = ON.

Figure 20.3-45 Display Example with Character Background Extended Display = ON

Line spacing

Line spacing(No character background) (Solid-filled background) (Convexed, shaded background)

Line spacing

Line spacing(No character background) (Solid-filled background) (Convexed, shaded background)

614


20.3.12 Line Background Display

The background of a line is displayed in the line area of the characters on the line, the areas to the right and left of the area, and the line spacing areas above and below it.

Line Background Control (Setting for Each Line)

Table 20.3-30 shows the line background control of line control data set 2 (command 4): BitsLM1 and LM0.

*1: Concaved, shaded background display displays the highlight color on two dots of the upperside in the line area and the shadow color on two dots of the lower side.

*2: Convexed, shaded background display displays the shadow color on two dots of the upperside in the line area and the highlight color on two dots of the lower side.

Line Background Color (Setting for Each Line, Selected From Among 16 Colors)

Line background colors can be set by setting color codes in bits L3 to L0 of line control data set2 (command 2).

Shaded Background Highlight Color (Setting for Each Screen, Selected from Among 16 Colors)

Shaded background frame color control (command 6-1): Bits BH3 to BH0

Note: Shared with shaded character background display.

Shaded Background Shadow Color (Setting for Each Screen, Selected from Among 16 Colors)

Shaded background frame color control (command 6-1): Bits BS3 to BS0

Note: Shared with shaded character background display.

Note:


Table 20.3-30 Line Background Control (Setting for Each Line)

LM1 LM0 Line background

0 0 No background (undisplay)

0 1 Solid-filled background

1 0 Concaved, shaded background*1

1 1 Convexed, shaded background*2

615


Display Examples

Figure 20.3-46 Line Background Display Examples

0 1 2 3 4 5 6 7 8 9 - A B C D E F G H I J

0 1 2 3 4 5 6 7 8 9 - A B C D E F G H I J

0 1 2 3 4 5 6 7 8 9 - A B C D E F G H I J

0 1 2 3 4 5 6 7 8 9 - A B C D E F G H I J

No line background

Solid-filled background

(Shaded background frame highlight color)Convexed, shaded background(Shaded background frame shadow color)

(Shaded background frame shadow color)Concaved, shaded background(Shaded background frame highlight color)

⇒

⇒

⇒

⇒

←

←

←

←

Character display area

616


20.3.12.1 Shaded Background Succeeding Line Merge Display (Line Background)

Specifying "shaded background succeeding line merge display" for a line enables the line to be displayed with the line background merged with that of the next line.This undisplays the lower line of the line background shadow frame of the current line and the upper line of the line background shadow frame of the next line.

Shaded Background Succeeding Line Merge Control (Setting for Each Line)

Table 20.3-31 shows the shaded background succeeding line merge control of line control dataset 2 (command 4): Bit LD.

Table 20.3-31 Shaded Background Succeeding Line Merge Control (Setting for Each Line)

LD Shaded background succeeding line merge control

0 OFF

1 ON

617


Display Examples

Figure 20.3-47 shows examples of shaded background succeeding line merge display.

Figure 20.3-47 Examples of Shaded Background Succeeding Line Merge Display

Note:

Specifying shaded background succeeding line merge display applies merge control to thecharacter and line backgrounds at the same time.

If character background extended display is off, however, merge control ignores shadedbackground characters.

Figure 20.3-48 to Figure 20.3-52 show display examples of a combination of shaded characterbackground display and shaded line background display.

0 1 2 3 4 5 6 7 8 9 - A B C D E F G H I J

0 1 2 3 4 5 6 7 8 9 - A B C D E F G H I J

0 1 2 3 4 5 6 7 8 9 - A B C D E F G H I J

0 1 2 3 4 5 6 7 8 9 - A B C D E F G H I J

(Shaded background frame highlight color)

(Shaded background frame highlight color)

Convexed, shaded background withsucceeding line merge ON

(Shaded background frame shadow color)

Convexed, shaded background withsucceeding line merge OFF

⇒

←

←

←

(Shaded background frame shadow color)←

⇒

Concaved, shaded background withsucceeding line merge ON

⇒

Convexed, shaded background withsucceeding line merge OFF

⇒

618


Figure 20.3-48 Display Example of a Combination of Shaded Character Background Display and Shaded Line Background Display (1)

Shaded line background

Line spacingShaded character background

Shaded line background Line spacing

Shaded line background

Shaded character background

Shaded character background

Line spacing

Line spacing

Bit LD = 0Bit LE = 0


619




The shaded line backgroundframe at this position isundisplayed.

The shaded characterbackground frame at thisposition is displayed whenbit LE = 0.


620



The character backgroundat this position is extended.



621




The shaded character backgroundframe at this position is undisplayed.


Shaded linebackground

622




The shaded character backgroundframe at this position is undisplayed.


Shaded linebackground

623


20.3.13 Screen Background Display

Screen background display has screen background character display and screen background color display functions.

Screen Background Display

Screen background character display

Screen background character display displays a graphic character on the entire screen byrepeating display of the same blocks of two by two, or four characters.

Screen background color display

Screen background color display displays the background color on the entire screen as thebottom layer output.

624


20.3.13.1 Screen Background Character Display

Screen background character display repeats display of the blocks of two by two characters on the entire screen. Screen background character display is only enabled for graphic characters.

Configuration of Screen Background Character Display

Figure 20.3-53 shows an example of screen background character display.

Figure 20.3-53 Example of Screen Background Character Display

625


Screen Background Character Display Control

Screen background character output control

Table 20.3-32 shows the screen background character output control of screen output control 1(command 5-0): Bit PDS.

Screen background character code

Screen background character control 1 (command 7-1): Bits PM10 to PM0

Set PM1 = 0 and PM0 = 0.

Note:

Only the L size of graphic characters can be used as screen background characters.

Screen background character vertical size control

Table 20.3-33 shows the screen background character vertical size control of screenbackground character control 4 (command 7-3): Bits PH2 to PH0.

Screen background character configuration control

Table 20.3-34 shows the screen background character configuration control of screenbackground character control 1 (command 7-1): Bits PD1 and PD0.

Table 20.3-32 Screen Background Character Output Control

PDS Screen background character display

0 OFF

1 ON

Table 20.3-33 Screen Background Character Vertical Size Control

PH2 PH1 PH0 Display vertical size

0 0 0 18 dots

0 0 1 20 dots

0 1 0 22 dots

0 1 1 24 dots

1 0 0 26 dots

1 0 1 28 dots

1 1 0 30 dots

1 1 1 32 dots

Table 20.3-34 Screen Background Character Configuration Control (1 / 2)

PD1 PD0 Screen background character configuration

0 1 1 character

626


Figure 20.3-54 shows an example of screen background character configuration.

Figure 20.3-54 Example of Screen Background Character Configuration

0 1 Horizontal set of 2 characters

1 0 Vertical set of 2 characters

1 1 2 characters x 2 characters

Table 20.3-34 Screen Background Character Configuration Control (2 / 2)

PD1 PD0 Screen background character configuration

- Screen background character code = nCharacter code

Example of 1-character configuration (PD1, PD0) = (0, 0)

nn

Example of a horizontal 2-character configuration (PD1, PD0) = (0, 1)n+1

n n+1

n+2 Example of a vertical 2-character configuration (PD1, PD0) = (1, 0)

n

n+3n+1

Example of a 4-character configuration (PD1, PD0) = (1, 1)

n n+1

n+2 n+3

627


20.3.13.2 Screen Background Color Display

Screen background color display displays the background color on the entire screen as the bottom layer output of the display screen.

Screen Background Output Control

Table 20.3-35 shows the screen background output control of screen output control 1(command 5-0): Bit UDS.

Screen Background Color Control

Screen background colors can be set by setting color codes in bits U3 to U0 of screenbackground character control 4 (command 7-3).

Note:


Table 20.3-35 Screen Background Output Control

UDS Screen background color output

0 OFF

1 ON

628


20.3.14 Sprite Character Display

Sprite characters are displayed on the top layer. The OSDC supports sprite display of only graphic characters.

Sprite Character Configuration

Figure 20.3-55 shows an example of displaying sprite characters.

Figure 20.3-55 Sprite Character Display Example

Sprite character

629


Sprite Character Display Control

Sprite character output control

Table 20.3-36 shows the sprite character output control of screen output control 1 (command 5-0): Bit SDS.

Sprite character code

Sprite character control 1 (Command 8-1): Bits SM7 to SM0

Set SM1 = 0, SM0 = 0.

Note:

Only the L size of graphic characters can be used as sprite characters.

Sprite character vertical display position control

Sprite character control 3 (Command 9-0): Bits SY9 to SY0

Settable between 0 and 2046 dots in 2-dot units.

Sprite character horizontal display position control

Sprite character control 4 (Command 9-1): Bits SX9 to SX0

Settable between 0 and 2046 dots in 2-dot units.

Sprite character vertical size control

Table 20.3-37 shows the sprite character vertical size control of sprite character control 3(command 8-2): Bits SH2 to SH0.

Table 20.3-36 Sprite Character Output Control

SDS Sprite character output

0 OFF

1 ON

Table 20.3-37 Sprite Character Vertical Size Control

SH2 SH1 SH0 Display vertical size

0 0 0 18 dots

0 0 1 20 dots

0 1 0 22 dots

0 1 1 24 dots

1 0 0 26 dots

1 0 1 28 dots

1 1 0 30 dots

1 1 1 32 dots

630


Sprite character configuration control

Table 20.3-38 shows the sprite character configuration control of sprite character control 2(command 8-1): Bits SD1 and SD0. Figure 21.3-55 shows an example of sprite characterconfiguration.

Figure 20.3-56 Sprite Character Configuration Example

Table 20.3-38 Sprite Character Configuration Control

SD1 SD0 Configuration

0 0 1 character

0 1 Horizontal set of 2 characters

1 0 Vertical set of 2 characters

1 1 2 characters x 2 characters

- Sprite character code = nCharacter code

Example of a 1-character sprite character (SD1, SD0 = 0, 0)

nn

Example of a horizontal 2-character sprite character (SD1, SD0 = 0, 1)n+1

n n+1

n+2 Example of a vertical 2-character sprite character (SD1, SD0 = 1, 0)

n

n+3n+1

Example of a 4-character sprite character (SD1, SD0 = 1, 1)

n n+1

n+2 n+3

631



This section explains the OSDC control functions.

OSDC Control Functions

The OSDC control functions are as follows:

• Dot clock control

• Sync signal input

• Display signal output

• Display period control

• Synchronous control

• Interrupt control

• OSDC operation control

632


20.4.1 Dot Clock Control

Dot clock control allows selection of external dot clock input or internal VCO generation dot clock input. Commands 11-1, 11-2, 11-3, and 17-0 enable dot clock control.

Input Dot Clock Selection Control

Table 20.4-1 shows the dot clock selection control of dot clock control 1 (command 17-1): BitDCK. To use the internal VCO generation dot clock, specify VCO-related control of commands11-1, 11-2, and 11-3 and then use this command to select the input dot clock.

External Dot Clock Input

The OSDC inputs a clock signal from an external oscillator.

The clock signal is assumed to be synchronized with the input horizontal sync signal.

Table 20.4-1 Dot Clock Selection Control

DCK Dot clock control

0 External dot clock input (initial state)

1 Internal VCO generation dot clock input

633


Internal VCO Generation Dot Clock Input

Dot clock circuit configuration

The clock generated by the internal VCO is used as a dot clock through the internal prescaler.

Figure 20.4-1 shows the dot clock circuit block diagram.

Figure 20.4-1 Dot Clock Circuit Block Diagram

Dot clock prescaler control

Table 20.4-2 shows the dot clock prescaler control of dot clock control 1 (command 11-1): BitsDP1 and DP0.

Phase comparison edge selection control

Table 20.4-3 shows the phase comparison edge selection control of dot clock control 1(command 11-1): Bit DHRS.

Note: When input HSYNC is negative logic

HSYNC

CPO

Counter

Phase comparator

VCO

DOCKI

FH

DCKO

Internal dot clock

* HSYNC, FH, DOCKI, DCKO, and CPO are external pins.

Set DHRS.

Set VSEL2 to VSEL0.Set VC.

Set DP1, DP0.

Prescaler

Sel

ecto

r

Set DCO.

Set DK11 to DK0.

Table 20.4-2 Dot Clock Prescaler Control

DP1 DP0 Dot clock prescaler configuration

0 0 VCO oscillation clock/1




Table 20.4-3 Phase Comparison Edge Selection Control

DHRS Phase comparison edge selection control

0 HSYNC rising edge

1 HSYNC falling edge

634


Dot clock control

A dot clock synchronized with the input horizontal sync signal HSYNC is generated by settingthe number of clocks required for the horizontal synchronous width in dot clock control 2(command 11-2): Bits DK11 to DK0.

VCO oscillation control

Table 20.4-4 shows the VCO oscillation control of dot clock control 3 (command 11-3): Bit VC.

Oscillating VCO selection control

Table 20.4-5 shows the VCO selection control of dot clock control 3 (command 11-3): Bit VSL2to VSL0.

Note: The VCO oscillation guarantee band is different from the OSDC operation guaranteefrequency.

VCO phase comparator control

Table 20.4-6 shows the phase comparator control of dot clock control 3 (command 11-3): BitPDE.

Table 20.4-4 VCO Oscillation Control

VC VCO oscillation control

0 VCO oscillation stop state

1 VCO oscillation state

Table 20.4-5 Oscillating VCO Selection Control

VSL2 VSL1 VSL0 VCO selection

configuration

VCO oscillation guarantee frequency

band

0 0 0 VCO1 20 to 40 MHz

0 0 1 VCO2 39 to 53 MHz

0 1 0 VCO3 51 to 70 MHz

0 1 1 VCO4 65 to 91 MHz

1 0 0 VCO5 90 to 125 MHz

1 0 1 VCO6 124 to 160 MHz

1 1 0 - Setting prohibited

1 1 1 - Setting prohibited

Table 20.4-6 Phase Comparator Control

PDE Phase comparator control

0 Stop

1 Normal operation

635


VCO charge pump control

Table 20.4-7 shows the charge pump control of dot clock control 3 (command 11-3): Bit CPE.

VCO charge pump bias current control

Table 20.4-8 shows the charge pump bias current control of dot clock control 3 (command 11-3): Bits CHG1 and CHG0.

Output Dot Clock Control

Output dot clock control controls the dot clock output of the DCKO pin.

Table 20.4-9 shows the output dot clock selection control of dot clock control 1 (command 11-1):Bit DCO.

Table 20.4-7 Charge Pump Control

CPE Charge pump control

0 Stop

1 Normal operation

Table 20.4-8 Charge Pump Bias Current Control

CHG1 CHG0 Charge pump bias current control

0 0 About 100 µA

0 1 About 500 µA

1 0 About 1 mA


Table 20.4-9 Output Dot Clock Control

DCO Output dot clock control

0 Dot clock output OFF

1 Dot clock output ON

636


20.4.2 Sync Signal Input

This section explains vertical synchronization detection and horizontal synchronization operation in sync signal input.

Sync Signal Input

Vertical synchronization detection

The level of vertical sync signal is sensed at the leading or trailing edge of the horizontal syncpulse to detect the transition.

Horizontal synchronous operation


Field detection

The field state for interlaced display is detected by monitoring the falling edge of the verticalsync signal.

637


20.4.2.1 Vertical Synchronization Control

Vertical synchronization detection senses the level of the vertical sync signal at the leading or trailing edge of the horizontal sync pulse to detect the transition. The vertical display position on the screen depends on the vertical synchronization detection position.

Vertical Synchronization Detection

The vertical synchronization operation is required the setting of the vertical synchronizationdetection HSYNC edge selection control of the I/O pin control 2 (command 13-1) and thevertical synchronization signal input logic control.

The vertical synchronization detection HSYNC edge selection control is set of the phase of theinput horizontal synchronous signal and the vertical synchronization signal.

Also, the VSYNC pin input logic control is set the logic of the input vertical synchronizationsignal. The control is shown in Table 20.4-10 and Table 20.4-13 .

Table 20.4-10 Vertical Synchronization Detection HSYNC Edge Selection

VHE Vertical synchronization detection HSYNC edge

0 Vertical synchronization is detected at leading edge of HSYNC.

1 Vertical synchronization is detected at trailing edge of HSYNC.

Table 20.4-11 Vertical Synchronization Signal Input Logic Control

IVX Vertical sync signal input logic

0 VSYNC pin is negative logic input.

1 VSYNC pin is positive logic input.

638


Examples of Vertical Synchronization Detection Operation

Figure 20.4-2 and Figure 20.4-3 show examples of vertical synchronization detection operation.

Figure 20.4-2 Detecting Vertical Synchronization at the Leading Edge of the Horizontal Sync Pulse (Operation When VHE is Set to 0)

Figure 20.4-3 Detecting Vertical Synchronization at the Trailing Edge of the Horizontal Sync Pulse (Operation When VHE is Set to 1)

Note:

When the following setting is performed to the vertical synchronization detection HSYNC edgeselection (VHE) and the horizontal synchronous operation edge (HE), the restriction is displayedin the main screen, the sprite screen, and the screen background characters.

• Setting conditionsVertical synchronization detection HSYNC edge selection:

VHE=1 (vertical synchronization signal detection at trailing edge of the horizontal synchronous signal)

Horizontal synchronous operation edge selection: HE= 1 (horizontal synchronous control operation at leading edge of the horizontal synchronous)

• RestrictionsMain screen display: vertical display position control (command 5-2): When setting the Y8 toY0 bit to “000H”, the main screen is disabled to display. The display is enabled when thesetting value is “001H” or more.

Sprite screen display: Sprite character vertical display position control (command 9-0): Whensetting the SY9 to SY0 bit to “000H”, the sprite screen is disabled to display. The display isenabled when the setting value is “001H” or more.

Screen background character display: the display is disabled.

VSYNC input

HSYNC input

Internally detected VSYNC

VSYNC input

HSYNC input

Internally detected VSYNC

639


20.4.2.2 Horizontal Synchronous Operation


Horizontal Synchronous Operation

The horizontal synchronous operation is required the setting of the horizontal synchronousoperation edge selection of I/O pin control 2 (command 13-1) and the horizontal synchronoussignal input logic control.

Figure 20.4-2 shows the horizontal synchronous operation edge selection.

Example of Horizontal Synchronous Operation

Figure 20.4-4 and Figure 20.4-5 show examples of horizontal synchronous operation.

Figure 20.4-4 Horizontal Synchronous Operation at Trailing Edge (HE=0, IHX=0)

Figure 20.4-5 Horizontal Synchronous Operation at Leading Edge (HE=0, IHX=0)

Table 20.4-12 Horizontal Synchronous Operation Edge Selection

HE Horizontal synchronous operation edge

0 Trailing edge

1 Leading edge

Table 20.4-13 Horizontal Synchronous Signal Input Logic Control

IHX Horizontal sync signal input logic

0 HSYNC pin is negative logic input.

1 HSYNC pin is positive logic input.

HSYNC input

Internally detected HSYNC

HSYNC input

Internally detected HSYNC

640


Note:

When the following setting is performed to the vertical synchronization detection HSYNC edgeselection (VHE) and the horizontal synchronous operation edge (HE), the restriction is displayedin the main screen, the sprite screen, and the screen background characters.

• Setting conditionsVertical synchronization detection HSYNC edge selection:

VHE=1 (vertical synchronization signal detection at trailing edge of the horizontal synchronous signal)

Horizontal synchronous operation edge selection: HE= 1 (horizontal synchronous control operation at leading edge of the horizontal synchronous)

• RestrictionsMain screen display: vertical display position control (command 5-2): When setting the Y8 toY0 bit to “000H”, the main screen is disabled to display. The display is enabled when thesetting value is “001H” or more.

Sprite screen display: Sprite character vertical display position control (command 9-0): Whensetting the SY9 to SY0 bit to “000H”, the sprite screen is disabled to display. The display isenabled when the setting value is “001H” or more.

Screen background character display: the display is disabled.

641


20.4.2.3 Field Control

When interlaced display is performed (the input sync signal is used for display at interlace timing), the field can be detected from the phase timings of the input vertical sync signal and input horizontal sync signal. The font display raster (even/odd) is selected, output, and controlled according to the result of detecting this field.To perform interlaced display during dot clock external input operation, set the number of clocks for the horizontal sync signal period in command 11-2 (bits DK11 to DK0).Control is not required for noninterlaced display.

Field Detection Control

Synchronous control (command 11-0): When setting the interlace of the IN bit, detects the fieldto perform the interlaced display from the phase state of the input horizontal/vertical sync signal.

• Field detection is controlled by observing the level of the vertical sync signal at timings H/4before and after the leading edge of the sync pulse of the vertical sync signal to detect theleading edge of the vertical sync pulse. If the level of the vertical sync signal changes in thevicinity of this detection position, normal field detection might not be performed. If the cycleof the horizontal sync signal changes in the vicinity of the sync pulse of the vertical syncsignal, normal field detection might not be performed. Input the horizontal sync signal afterstabilizing the signal in the external circuit.

• The field detection timing “H/4”, the dot clock control 2 (command 11-2): sets to DK11 toDK0 bit and is calculated the clock number of the horizontal synchronous cycle as 1H.

Note:

The display raster of the font which is displayed in each field during interlacing, see "20.4.5Synchronization Control".

642


Figure 20.4-6 shows the input timing of the vertical synchronizing signal (VSYNC pin inputsignal) to display interlace and the horizontal synchronizing signal(HSYNC pin input signal).

Figure 20.4-6 Field Detection Timing

Field detection timing H/4 is calculated from the value set as H in bits DK11 to DK0 (PLLdivision setting of HSYNC).

H/4H/4

Vertical synchronizationsignal

Horizontal synchronous signal

H/4 H/4

[Field A detection timing]

[Field B detection timing]

Vertical synchronizationsignal

Horizontal synchronous signal

643


Field Correction Control

Field correction control

Field correction control converts the display status of the even raster display field of the font tobe display the field detection control and the add raster display field. If normal display output toeach field is not performed (the output field is abnormal) in interlaced display output mode,corrects the display output.

The synchronous control (command 11-0): the field correction control of the FC bit can beallowed replacement of the output to each field.

Table 20.4-14 shows the field 0 correction control (FC) of synchronous control (command 11-0).

Table 20.4-14 Field Correction

FC Field correction

0 No correction

1 Correction

644


20.4.3 Display Signal Output

This section describes the timing of display signal output.

Display Signal Output Timing

Display signals (outputs)

• Output display period signal: VOB1 pin

• Translucent color display period signal: VOB2 pin

• Display color code: RGB

Example of Display Signal Output (1)

Figure 20.4-7 shows an example of display signal output (with character color display ON,character background color display ON, and trimming color display ON)

645


Figure 20.4-7 Example of Display Signal Output (with Character Color Display ON, Character Background Color Display ON, and Trimming Color Display ON)

Note:

While VOB1 output is inactive, the color code at palette address 0H is output by an OSDCmacro (when DCX = 0).

Example display

Display line Output dot number

Output dot number

RGB output(Color information)

Character background color Character color Character background color VOB1 output Output data position

Note: In this example, I/O signals are set for positive logic.

0 1 2 3 4 5 6 7 8 9 A B

0 1 2 3 4 5 6 7 8 9 A B

Palette data output Palette data output

Trimming color Trimming color

646


Example of Display Signal Output (2)

The examples below show display-disabled periods due to input of horizontal synchronization(HSYNC) and vertical synchronization (VSYNC) signals.

Figure 20.4-8 and Figure 20.4-9 show examples of display-disabled periods due to input ofsynchronization signals.

Figure 20.4-8 Example of Masking Display Signal Output by HSYNC Signal Input

Figure 20.4-9 Example of Masking Display Signal Output by VSYNC Signal Input

VOB output-enabled period

VOB output-disabled period

VOB output-enabled period VOB output-enabled period

VOB output-disabled period

HSYNC input

VOB output timing

VOB output-disabled period VOB output-disabled period

VOB output-enabled period VOB output-enabled period VOB output-enabled period

VSYNC input

HSYNC input

VOB output period

647


20.4.4 Display Period Control

There are two display period control functions:• Vertical display period control• Horizontal display period controlThese functions enable horizontal blanking and vertical blanking to be controlled.

Vertical Display Period Control

Vertical display period control is used to generate vertical display periods for controlling theoutput of display signals. In a vertical display period, signals for display in vertical directions areoutput. Vertical display periods can be set by commands.

Figure 20.4-10 shows an example of vertical display period control.

Figure 20.4-10 Vertical Display Period Control

The start and end of a vertical display period can be specified as follows:

Vertical display start timing

Display period control 1 (command 14-0): bits DYS10 to DYS0 = number of Hsync signals = 0 to2047, set in units of 1 Hsync signals

Vertical display end timing

Display period control 2 (command 14-1): bits DYE10 to DYE0 = number of Hsync signals = 0to 2047, set in units of 1 Hsync signals

Note:

When the following setting is performed, the display end timing setting is invalid. The displayoutput enabled period is set until the synchronization signal inputs.

DYS [10:0] (vertical display start timing) ≥ DYE [10:0] (vertical display end timing)

VSYNC input(VSYNC pin)Internal VSYNC pulseVertical display period Display signal

output disabledDisplay signal output disabled

Display signal output enabled

Display start timing

Display end timing

648


Horizontal Display Period Control

Horizontal display period control is used to generate horizontal display periods for controlling theoutput of display signals. In a horizontal display period, signals for display in horizontaldirections are output. Horizontal display periods can be set by commands. The following twotypes of operation are done according to the setting of the HSYNC edge selection bit (HE bit) ofthe I/O pin control command (command 13-0):

• Operation with the trailing edge selected for horizontal synchronization (HE bit = 0)

• Operation with the leading edge selected for horizontal synchronization (HE bit = 1)

Figure 20.4-11 shows an example of horizontal display period control.

Figure 20.4-11 Horizontal Display Period Control

The start and end of a horizontal display period can be specified as follows:

Horizontal display start timing

Display period control 3 (command 14-2): bits DXS10 to DXS0 = number of dot clock signals =0 to 2047, set in units of 1 dot clock signals

Horizontal display end timing

Display period control 4 (command 14-3): bits DXE10 to DXE0 = number of dot clock signals =0 to 2047, set in units of 1 dot clock signals

Note:

When the following setting is performed, the display end timing setting is invalid. The displayoutput enabled period is set until the synchronization signal inputs.

DXS [10:0] (horizontal display start timing) ≥ DXE [10:0] (horizontal display end timing)

- Operation with the trailing edge selected for horizontal synchronization (HE bit = 0)

- Operation with the leading edge selected for horizontal synchronization (HE bit = 1)

HSYNC input(HSYNC pin)

Horizontal display period

Horizontal display period

HSYNC input(HSYNC pin)

Display signal output disabled








Display end timing

Display end timing

649


20.4.5 Synchronization Control

You can specify interlaced or noninterlaced display by setting the interlace/noninterlace control bit (IN bit) of the synchronization control command (command 11-0).

Synchronization Control (Vertical Enlargement Control)

Table 20.4-15 shows the bit settings for synchronization control.

Display Example

Figure 20.4-12 shows the font memory original data.

Figure 20.4-12 Font Memory Original Data

The examples of interlaced display (IN=0) is shown Figure 20.4-13 .

The interlace display composes the display image of the display of the dot with different fontoriginal picture data in field A and field B detected by "20.4.2.3 Field Control".

Table 20.4-15 Synchronization Control

IN Vertical enlargement control

0 Interlaced display

1 Noninterlaced display

24 dots

32 dots

FontrasterNo.0123456

3031

650


Figure 20.4-13 Examples of Interlaced Display

Note:

When the display raster of the display font data in the interlaced display is inverted, the fieldcorrection control (command 11-0): the correction is allowed by controlling of the FC bit.

• The example of noninterlaced display (IN = 1) is shown Figure 20.4-14 .

The noninterlaced display consists of the image to output the font original data sequentially.

n

n+1

n+2

n+3

n+15

n

n+1

n+2

n+15

Field A: Font even raster displayFont raster

No.

0

2

4

6

30

Font rasterNo.

1

3

5

30

Field B: Font odd raster display

n+3

Horizontal display rasterNo.


(Note) n is an arbitrary display raster No.

651


Figure 20.4-14 Example of Noninterlaced Display

nn+1n+2n+3n+4n+5n+6

n+30n+31

Font rasterNo.

0123456

3031


(Note) n is an arbitrary display raster No.

652


20.4.6 Interrupt Control

There are three factors of OSDC control interrupt:• Detection of line display end• Detection of vertical synchronization signal• Detection of VRAM fill endAn interrupt request is issued to the CPU when any of the three factors occurs.

Interrupt Control

Interrupt control is used to control the interrupts generated by the internal operation status.

Interrupt control is performed according to the interrupt factor flags and interrupt generationcontrol bits of the interrupt control command (command 15-0).

Interrupt Factor Flags

Each interrupt factor flag is set to "1" when the relevant factor occurs.

To clear a set interrupt factor flag, it is set to "0".

There are three interrupt factor flags:

• Line display end flag (bit LIF of command 15-0)

• Vertical synchronization signal input flag (bit VIF of command 15-0)

• VRAM fill end flag (bit FIF of command 15-0)

Line display end flag

The last raster of each line and a line end detection line for the topline immediately start rasterpart as shown in Figure 20.4-15 becomes a factor of line display end.

Figure 20.4-15 Line Display End Detection

Line end detection line



Line widthNo line spacing

Upper line spacing

Lower line spacing

Line widthLine spacing specified Line address: AY=0x1

653


Vertical synchronization signal input flag

The trailing edge of the internal vertical synchronization signal is detected.

The point where a vertical synchronization signal as shown in Figure 20.4-16 is detectedbecomes a factor of vertical synchronization signal input.

Figure 20.4-16 Vertical Synchronization Signal Detection

VRAM fill end flag

The end of VRAM setting started by a VRAM fill command (command 0 to command 2)becomes a factor of VRAM fill end.

VSYNC input(VSYNC pin)

OSDCInternal VSYNC

Point of vertical synchronization signal detection

654


Interrupt Generation Control

The interrupt generation control bits are used to enable or disable interrupts.

There are three interrupt generation control bits:

Line display end interrupt (bit LIE of command 15-0)

Table 20.4-16 shows the bit settings for line display end interrupt control.

Vertical synchronization signal input interrupt (bit VIE of command 15-0)

Table 20.4-17 shows the bit settings for vertical synchronization signal input interrupt control.

VRAM fill end interrupt (bit FIE of command 15-0)

Table 20.4-18 shows the bit settings for VRAM fill end interrupt control.

Table 20.4-16 Line Display End Interrupt Control

LIE Line display end interrupt

0 Interrupt disabled

1 Interrupt enabled

Table 20.4-17 Vertical Synchronization Signal Input Interrupt Control

VIE Vertical synchronization signal input interrupt


1 Interrupt enabled

Table 20.4-18 VRAM Fill End Interrupt Control

FIE VRAM fill end interrupt


1 Interrupt enabled

655


20.4.7 OSDC Operation Control

The OSDC operation control function controls the operation of the OSDC.

OSDC Operation Control

Before OSDC operation control, the input dot clock selection, DAC, and output pin must be setas required and the OSDC must be activated.

Input dot clock selection control

Table 20.4-19 shows the settings of the DCK bit of the OSDC operation control 1 command(command 17-0) for input dot clock control.

To select the clock generated by VCO, make the VCO-related settings of clock control 1, clockcontrol 2, and clock control 3 before setting the DCK bit.

DAC control

Table 20.4-20 shows the settings of the DPD bit of the OSDC operation control 1 command(command 17-0) for DAC control.

Output pin control

Table 20.4-21 shows the settings of bits ANO, DGO, and FHO of the OSDC operation control 2command (command 17-1) for output pin control.

Table 20.4-19 Input Dot Clock Selection Control

DCK Dot clock control

0 Input of external dot clock

1 Input of the dot clock generated by internal VCO

Table 20.4-20 DAC Control

DPD DAC control

0 Stopped

1 Operated

Table 20.4-21 Output Pin Control

ANO Analog RGB output pin control

0 Analog RGB output turned off

1 Analog RGB output turned on

DGO Digital RGB output pin control

0 Digital RGB output turned off

1 Digital RGB output turned on

656


OSDC activation control

Table 20.4-22 shows the settings of the OSDEN bit of the OSDC operation control 2 command(command 17-1) for OSDC activation control.

FHO FH pin output control

0 FH pin output turned off

1 FH pin output turned on

Table 20.4-22 OSDC Activation Control

OSDEN OSDC activation control

0 OSDC disabled

1 OSDC enabled

657



This section describes the display control commands of OSDC.

Display Control Commands of OSDC

The display control commands of OSDC are listed below.

• VRAM write address set (command 0)

• Character data set (commands 1 and 2)

• Line control data set (commands 3 and 4)

• Screen output control (commands 5-00 and 5-1)

• Display position control (commands 5-2 and 5-3)

• Character vertical size control (command 6-0)

• Shaded background frame color control (command 6-1)

• Transparent/translucent color control (command 6-2)

• Graphic color control (command 6-3)

• Screen background character control (commands 7-1 and 7-3)

• Sprite character control (commands 8-1, 8-2, 9-0, and 9-1)

• Synchronization control (command 11-0)

• Dot clock control (commands 11-1 to 11-3)

• I/O pin control (commands 13-0 and 13-1)

• Display period control (commands 14-0 to 14-3)

• Interrupt control (command 15-0)

• Palette control (commands 16-0 to 16-15)

• OSDC operation control (commands 17-0 and 17-1)

658


20.5.1 List of Display Control Commands

Table 20.5-1 shows the display control commands.

List of Display Control Commands

Table 20.5-1 List of Display Control Commands (1 / 3)

Low-order 8 bits of address

OSDC command No.

Data Function

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

00 0 FL AY3 AY2 AY1 AY0 AX5 AX4 AX3 AX2 AX1 AX0 VRAM write address set

02 1 MIT MUL MBL MBB MS1 MS0 MM1 MM0 MB3 MB2 MB1 MB0 MC3 MC2 MC1 MC0 Character data set 1

04 2 MR MG M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 M0 Character data set 2

06 3 LHS LW2 LW1 LW0 LFD LFC LFB LFA LF3 LF2 LF1 LF0 Line control data set 1

08 4 LDS LGY1

LGY0

LGX1

LGX0

LD LE LM1 LM0 L3 L2 L1 L0 Line control data set 2

0A 5-00 SDS UDS PDS DSP Screen output control 1

0C 5-1 FM1 FM0 BT1 BT0 BD1 BD0 Screen output control 2

0E 5-2 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Vertical display position control

10 5-3 X8 X7 X6 X5 X4 X3 X2 X1 X0 Horizontal display position control

12 6-0 HB2 HB1 HB0 HA2 HA1 HA0 Character vertical size control

14 6-1 BH3 BH2 BH1 BH0 BS3 BS2 BS1 BS0 Shaded background frame color control

16 6-2 TCC HCC TC3 TC2 TC1 TC0 HC3 HC2 HC1 HC0 Transparent/translucent color control

18 6-3 GFC GCC GF3 GF2 GF1 GF0 GC3 GC2 GC1 GC0 Graphic color control

1A 7-1 PCUT

PD1 PD0 PM10

PM9 PM8 PM7 PM6 PM5 PM4 PM3 PM2 PM1 PM0 Screen background character control 1

1C 7-3 PH2 PH1 PH0 U3 U2 U1 U0 Screen background character control 2

1E 8-1 SCUT

SD1 SD0 SM10

SM9 SM8 SM7 SM6 SM5 SM4 SM3 SM2 SM1 SM0 Sprite character control 1

20 8-2 SBL SH2 SH1 SH0 Sprite character control 2

22 9-0 SY9 SY8 SY7 SY6 SY5 SY4 SY3 SY2 SY1 SY0 Sprite character control 3

659


24 9-1 SX9 SX8 SX7 SX6 SX5 SX4 SX3 SX2 SX1 SX0 Sprite character control 4

26 11-0 IN FC Synchronization control

28 11-1 DR1 DR0 DP1 DP0 DHRS

DCO Dot clock control 1

2A 11-2 DK11

DK10

DK9 DK8 DK7 DK6 DK5 DK4 DK3 DK2 DK1 DK0 Dot clock control 2

2C 11-3 VC VSL2

VSL1

VSL0

CHG1

CHG0

CPE PDE Dot clock control 3

2E 13-0 OHX OBX OCX I/O pin control 1

30 13-1 VHE HE IHX IVX I/O pin control 2

32 14-0 DYS10

DYS9

DYS8

DYS7

DYS6

DYS5

DYS4

DYS3

DYS2

DYS1

DYS0

Display period control 1

34 14-1 DYE10

DYE9

DYE8

DYE7

DYE6

DYE5

DYE4

DYE3

DYE2

DYE1

DYE0


36 14-2 DXS10

DXS9

DXS8

DXS7

DXS6

DXS5

DXS4

DXS3

DXS2

DXS1

DXS0


38 14-3 DXE10

DXE9

DXE8

DXE7

DXE6

DXE5

DXE4

DXE3

DXE2

DXE1

DXE0


3A 15-0 FIF LIF VIF FIE LIE VIE Interrupt control

3C 16-0 PLR2

PLR1

PLR0

PLG2

PLG1

PLG0

PLB2

PLB1

PLB0

Palette 0

3E 16-1 PLR2

PLR1

PLR0

PLG2

PLG1

PLG0

PLB2

PLB1

PLB0

Palette 1

40 16-2 PLR2

PLR1

PLR0

PLG2

PLG1

PLG0

PLB2

PLB1

PLB0

Palette 2

42 16-3 PLR2

PLR1

PLR0

PLG2

PLG1

PLG0

PLB2

PLB1

PLB0

Palette 3

44 16-4 PLR2

PLR1

PLR0

PLG2

PLG1

PLG0

PLB2

PLB1

PLB0

Palette 4

46 16-5 PLR2

PLR1

PLR0

PLG2

PLG1

PLG0

PLB2

PLB1

PLB0

Palette 5

48 16-6 PLR2

PLR1

PLR0

PLG2

PLG1

PLG0

PLB2

PLB1

PLB0

Palette 6

4A 16-7 PLR2

PLR1

PLR0

PLG2

PLG1

PLG0

PLB2

PLB1

PLB0

Palette 7

4C 16-8 PLR2

PLR1

PLR0

PLG2

PLG1

PLG0

PLB2

PLB1

PLB0

Palette 8

4E 16-9 PLR2

PLR1

PLR0

PLG2

PLG1

PLG0

PLB2

PLB1

PLB0

Palette 9

50 16-10 PLR2

PLR1

PLR0

PLG2

PLG1

PLG0

PLB2

PLB1

PLB0

Palette 10

52 16-11 PLR2

PLR1

PLR0

PLG2

PLG1

PLG0

PLB2

PLB1

PLB0

Palette 11

54 16-12 PLR2

PLR1

PLR0

PLG2

PLG1

PLG0

PLB2

PLB1

PLB0

Palette 12

56 16-13 PLR2

PLR1

PLR0

PLG2

PLG1

PLG0

PLB2

PLB1

PLB0

Palette 13

58 16-14 PLR2

PLR1

PLR0

PLG2

PLG1

PLG0

PLB2

PLB1

PLB0

Palette 14

5A 16-15 PLR2

PLR1

PLR0

PLG2

PLG1

PLG0

PLB2

PLB1

PLB0

Palette 15



OSDC command No.

Data Function

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

660


Note:

Input of a reset signal clears bits SDS, UDS, PDS, and DSP of the screen output control 1Acommand and bits OHX, OBX,and OCX of the I/O pin control 1 command. Other registerbits and VRAM contents are not affected by input of a reset signal.

After input of a reset signal, be sure to set up all register bits and all contents of VRAM(character and line control data).

5C 17-0 DCK DOF OSDC operation control 1

5E 17-1 OSDEN

FHO DGO ANO OSDC operation control 2



OSDC command No.

Data Function

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

661


20.5.2 VRAM Write Address Set (Command 0)

Command 0 specifies a write address of VRAM and a VRAM fill operation.

Command 0 (VRAM Write Address Set)

Address: 00H

Format

[Function]

Command 0 specifies a write address of VRAM and a VRAM fill operation.

Command 0 specifies row and column addresses before being set by commands 1 and 2(character data set commands) and row addresses before being set by commands 3 and 4 (linecontrol data set commands).

A VRAM fill operation is started by executing a character data set 2 command (command 2).

[Supplement]

• A normal write (writing single-character data or single-line control data) is performed with"VRAM fill" set to OFF (FL = 0).

• The VRAM write address specified by command 0 is incremented automatically afterexecution of a character data set 2 command (command 2). (The last column is incremented to the first column of the next line by line feed; the last rowis incremented to the first row.)

• The VRAM fill function writes the same character data specified by character data setcommands (commands 1 and 2) to the character VRAM area from the row/column addressspecified by command 0 to the last column (column 40) on the last row (row 24). A VRAM filloperation is started by issuing of character data set 2 command (command 2).After a VRAM fill operation ends, a VRAM fill interrupt can be generated.Commands 1 to 4 must not be issued while a VRAM fill operation is in progress.

Notes:

• When commands 3 and 4 (line control data set) are set, column addresses (AX5 to AX0) areignored. Execution of command 3 or 4 (line control set command) does not automaticallyincrement the address.

• "VRAM fill" is valid only to commands 1 and 2 (character data set commands).

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FL 0 0 0 AY3 AY2 AY1 AY0 0 AX4 AX3 AX2 AX1 AX0 0 AX5

AY3 to AY0: Row address (0-17H)AX5 to AX0: Column address (0-27H)

FL: Specify VRAM fill (0: OFF, 1: ON)

662


20.5.3 Character Data Set (Commands 1 and 2)

This command sets character data. Executing command 2 (character data set 2) sets VRAM to reflect it on the screen.

Command 1 (Character Data Set 1)

Address: 02H

Format

[Function]

Command 1 sets character data. Executing command 2 (character data set 2) sets VRAM toreflect it on the screen.

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MIT MUL MBL MBB MS1 MS0 MM1 MM0 MB3 MB2 MB1 MB0 MC3 MC2 MC1 MC0

MC3 to MC0:

MB3 to MB0:

MM1, MM0:

MBL, MBB:

MIT:

Character color(From among 16 colors)

Character background color(From among 16 colors)

Character background control(0, 0: OFF)(0, 1: Solid-fill display)(1, 0: Concaved, shaded display)(1, 1: Convexed, shaded display)

Blinking control(0, 0: Blinking OFF)(0, 1: Blinking OFF)(1, 0: Character and trimming dots blinking)(1, 1: Character, trimming dots, and character background blinking)

Italic display control(0: Italic display OFF)(1: Italic display ON)

MS1, MS0: Character horizontal size control0, 0: 12 dots0, 1: 18 dots1, 0: 24 dots1, 1: -

MUL: Underline control(0: Underline OFF)(1: Underline ON)

663


[Supplement]

• The character color, character background color, character background type, characterhorizontal size, italic display, and underline display can be set in an arbitrary combination foreach character.

• Shaded background display enables vertical or horizontal merge display according to thecombination of the MR bit of the character data set 2 command (command 2) and bits LDand LE of the line control data set 2 command (command 4).

• The shaded background frame color is set by command 6-1.

• When blinking control is turned on (MBL = 1), blinking display is executed according to bitsBT1, BT0, BD1, and BD0 of the screen output control 2 command (command 5-1).

Command 2 (Character Data Set 2)

Address: 04H

Format

[Function]

Command 2 writes the above setting data to the area of VRAM specified by command 0 (VRAMwrite address set 1), along with the character data set by command 1 (character data set 1).After this command is executed, the VRAM write address is incremented automatically.

[Supplement]

The shaded background succeeding character merge control bit (MR) has an effect only on thecharacter specified as being shaded by command 1 (MM1 = 1).

Note:

Since reset input makes the contents of the entire area of VRAM undefined, be sure to setVRAM before display.

MR MG 0 0 0 M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 M0

MR:

M10 to M0:

Shaded background succeedingcharacter merge control(0: Do not merge)(1: Merge with the character to theright)

Character code(000H to 6FFH: 1,792 character types)

MG: Character/graphic character control(0: Character, 1: Graphic character)

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

664


20.5.4 Line Control Data Set (Commands 3 and 4)

This command sets line control data. Executing command 4 (line control data set 2) sets line VRAM to reflect it on the screen.

Command 3 (Line Control Data Set 1)

Address: 06H

Format

[Function]

Command 3 sets line control data. Executing command 4 (line control data set 2) sets lineVRAM to reflect it on the screen.

[Supplement]

• The actual size, whose type is specified by the line character vertical size type control bit(LHS), is specified by command 6-0 (character vertical size control).

• The trimming mode is specified by command 5-1 (trimming mode control bits FM1 and FM0).

0 0 0 LHS 0 LW2 LW1 LW0 LFD LFC LFB LFA LF3 LF2 LF1 LF0

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LHS:

LW2 to LW0:

LF3 to LF0:

Line character vertical size typecontrol(0: Character vertical size A)(1: Character vertical size B)

Line spacing control(0 to 14 dots in 2-dot units)

Trimming color(From among 16 colors)

LFD, LFC:

LFB, LFA:

Trimming output control(0, 0: All OFF)(0, 1: Trimming ON for characterwith no character background)(1, 0: Trimming ON for characterwith no solid-filled characterbackground)(1, 1: Trimming output ON)

Trimming control(0, 0: Trimming OFF)(0, 1: Right trimming)(1, 0: Left trimming)(1, 1: Before-side trimming)

665


Command 4 (Line Control Data Set 2)

Address: 08H

Format

[Function]

Command 4 writes the above setting data to the area of line VRAM specified by command 0(VRAM write address set 1), along with the line control data set by command 3 (line control dataset 1).

[Supplement]

The shaded background succeeding line merge control bit (LD) has different effects on thecharacter shaded backgrounds and line shaded backgrounds. For details, see Section"20.3.12.1 Shaded Background Succeeding Line Merge Display (Line Background)".

Notes:

• Since reset input makes the contents of the entire area of VRAM undefined, be sure to setVRAM before display.

• Issuing this command does not automatically increment the VRAM write address. For eachline to be set, set the address using command 0.

0 0 0 LDS LGY1 LGY0 LGX1 LGX0 LD LE LM1 LM0 L3 L2 L1 L0

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LDS:

LGY1, LGY0:

LGX1, LGX0:

Line character output control(0: Off, 1: ON)

Line vertical enlargement control(0, 0: Normal)(0, 1: Double height)(1, 0: Setting prohibited)(1, 1: Quadruple height)

Line horizontal enlargement control(0, 0: Normal)(0, 1: Double width)(1, 0: Setting prohibited)(1, 1: Quadruple width)

LE:

LD:

LM1, LM0:

L3 to L0:

Character background extensioncontrol(0: Normal, 1: Extended)

Shaded background succeeding line merge control(0: Independent, 1: Merge with the next line)

Line background control(0, 0: OFF)(0, 1: Solid-fill display)(1, 0: Concaved, shaded display)(1, 1: Convexed, shaded display)

Line background color(From among 16 colors)

666


20.5.5 Screen Output Control (Commands 5-00 and 5-1)

Commands 5-00 and 5-1 control the screen display output.

Command 5-00 (Screen Output Control A)

Address: 0AH

Format

[Function]

Command 5-00 controls screen display output.

0 0 0 0 0 0 0 0 SDS UDS PDS DSP 0 0 0 0

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SDS:

UDS:

Sprite character output control(0: OFF, 1: ON)

Screen background output control(0: OFF, 1: ON)

PDS:

DSP:

Screen background character output control(0: OFF, 1: ON)

Display output control(Control of character + trimming +character background + linebackground) (0: OFF, 1: ON)

667


Command 5-1 (Screen Output Control 2)

Address: 0CH

Format

[Function]

Command 5-1 controls screen display output.

[Supplement]

The blink cycle and blink duty ratio are controlled for the characters for which blinking control isspecified (MBL = 1) by the character data set 2 command (command 2). They are alsocontrolled for the sprite characters for which sprite character blinking control is specified (SBL =1) by the sprite character control 2 command (command 8-2).

0 0 0 0 0 0 FM1 FM0 BT1 BT0 BD1 BD0 0 0 0 0

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BT1, BT0:

BD1, BD0:

Blink cycle control(0, 0 : 16V)(0, 1 : 32V)(1, 0 : 48V)(1, 1 : 64V)

Blink duty ratio control(0, 0: On-to-off ratio = 1:0, always displayed)(0, 1: On-to-off ratio = 1:1)(1, 0: On-to-off ratio = 1:3)(1, 1: On-to-off ratio = 3:1)

FM1, FM0: Trimming type control(0, 0: 1-dot horizontal trimming(0, 1: 2-dot horizontal trimming)(1, 0: Pattern background 1)(1, 1: Pattern background 2)

668


20.5.6 Display Position Control (Commands 5-2 and 5-3)

Command 5-2 controls the vertical display position of the screen, and command 5-3 controls the horizontal display position of the screen.

Command 5-2 (Vertical Display Position Control)

Address: 0EH

Format

[Function]

Command 5-2 controls the vertical display position of the main screen.

Command 5-3 (Horizontal Display Position Control)

Address: 10H

Format

[Function]

Command 5-3 controls the horizontal display position of the main screen.

0 0 0 0 0 0 0 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Y8 to Y0: Vertical display position control(0 to 2044 in 4-dot units)

0 0 0 0 0 0 0 X8 X7 X6 X5 X4 X3 X2 X1 X0

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

X8 to X0: Horizontal display position control(0 to 2044 in 4-dot units)

669


20.5.7 Character Vertical Size Control (Command 6-0)

This command controls the vertical display size A/B of each character.

Command 6-0 (Character Vertical Size Control)

Address: 12H

Format

[Function]

Command 6-0 controls the vertical display size A or B of each character.

[Supplement]

Character vertical size A or B can be selected for each line on the main screen. Selectcharacter vertical size A or B with the LHS (line character vertical size type control) bit of the linedata set 1 command (command 3), and specify the number of dots by specifying charactervertical size A or B using command 6-0.

0 0 0 0 0 0 0 0 0 HB2 HB1 HB0 0 HA2 HA1 HA0

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

HB2 to HB0:

HA2 to HA0:

Character vertical size control B(18 to 32 dots in 2-dot units)

Character vertical size control A(18 to 32 dots in 2-dot units)

670


20.5.8 Shaded Background Frame Color Control (Command 6-1)

This command controls the frame color of a shaded background.

Command 6-1 (Shaded Background Frame Color Control)

Address: 14H

Format

[Function]

Command 6-1 controls the frame color of a shaded background.

[Supplement]

• This command sets the frame colors of the character for which shaded characterbackground display has been specified (MM1 = 1) by command 1 and of the shadedbackground for which shaded background display has been specified (LM1 = 1) bycommand 4.

• Table 20.5-2 shows the sections of the shaded background frame to be displayed in highlightand shadow colors.

0 0 0 0 0 0 0 0 BH3 BH2 BH1 BH0 BS3 BS2 BS1 BS0

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BH3 to BH0:

BS3 to BS0:

Shaded background frame highlight color(From among 16 colors)Shaded background frameshadow color(From among 16 colors)

Table 20.5-2 Shaded Background Frame Sections to be Displayed in Highlight and Shadow Colors (1 / 2)

Character background Shaded background convexed display

Line background

Shaded background

concaved display

Line background

Shaded background concaved

display

Highlight color on shaded background frame

Bottom and right edges

Top and left edges

Bottom edge Top edge

671


Shadow color on shaded background frame

Top and left edges

Bottom and right edges

Top edge Bottom edge

Table 20.5-2 Shaded Background Frame Sections to be Displayed in Highlight and Shadow Colors (2 / 2)

Character background Shaded background convexed display

Line background

Shaded background

concaved display

Line background

Shaded background concaved

display

672


20.5.9 Transparent/Translucent Color Control (Command 6-2)

Command 6-2 controls transparent and translucent colors.

Command 6-2 (Transparent/Translucent Color Control)

Address: 16H

Format

[Function]

Command 6-2 controls transparent and translucent colors.

[Supplement]

• If an arbitrary color code is specified as a transparent color code (in bits TC3 to TC0) andtransparent color control is set to ON (TCC = 1), the display areas in the specified color canbe made void. The display on the lower layer is output in place of the display areas in thespecified color.

• If an arbitrary color code is specified as a translucent color code (in bits HC3 to HC0) andtranslucent color control is set to ON (HCC = 1), the display areas in the specified color canbe made void. At the same time, the translucent color display period signal can be outputfrom the VOB2 pin. The display on the lower layer is output in place of the display areas inthe specified color.

Note:

The translucent color display period signal from the VOB2 pin is output for areas other than thecharacters, trimming, and graphics on the main screen.

0 0 0 0 0 0 TCC HCC TC3 TC2 TC1 TC0 HC3 HC2 HC1 HC0

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TCC:

HCC:

Transparent color control(0: OFF, 1: ON)

Translucent color control(0: OFF, 1: ON)

TC3 to TC0:

HC3 to HC0:

Transparent color code(From among 16 colors)

Translucent color code(From among 16 colors)

673


20.5.10 Graphic Color Control (Command 6-3)

This command replaces the code-specified graphic color by the character color or character trimming color.

Command 6-3 (Graphic Color Control)

Address: 18H

Format

[Function]

Command 6-3 replaces the specified color of graphic characters by the character color orcharacter trimming color.

[Supplement]

• When bit GFC is set to "1", this command replaces the color (specified with bits GF3 to GF0)of graphic characters by the trimming color specified with bits LF3 to LF0 of the line controldata set 1 command (command 3).

• When bit GCC is set to "1", this command replaces the color (specified with bits GC3 toGC0) of graphic characters by the character color specified with bits MC3 to MC0 of the linedata set 1 command (command 1).

• Replacement by the specified trimming color has priority over transparent color control if:graphic color/trimming color replace control is ON (bit GFC = 1) and transparent color controlis ON (bit TCC of transparent/translucent color control command [command 6-2] = 1) andthecode of the color to be replaced by the graphic color/the trimming color is the same as thetransparent color code specified with bits TC3 to TC0 of the transparent/translucent colorcontrol command (command 6-2).

• Transparent color control has priority over replacement by the specified trimming color andthe color on the lower layer is displayed if: graphic color/trimming color replace control is ON(bit GFC = 1) and transparent color control is ON (bit TCC of the transparent/translucentcolor control command [command 6-2] = 1) and the code of the trimming color (specified withbits LF3 to LF0 of the line control data set 1 command [command 3]) to be replaced is thesame as the transparent color code specified with bits TC3 to TC0 of the transparent/translucent color control command (command 6-2).

0 0 0 0 0 0 GFC GCC GF3 GF2 GF1 GF0 GC3 GC2 GC1 GC0

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

GFC:

GCC:

Graphic color/trimming color replace control(0: OFF, 1: ON)

Graphic color/character color replace control(0: OFF, 1: ON)

GF3 to GF0:

GC3 to GC0:

Code of character to be replaced by trimming color(From among 16 colors)

Code of character to be replaced by character color(From among 16 colors)

674


• Replacement by the specified character color has priority over the transparent color controlif: graphic color/character color replace control is ON (bit GCC = 1) and transparent colorcontrol is ON (bit TCC of the transparent/translucent color control command [command 6-2]= 1) and the code of the color to be replaced by the graphic color/ the character color is thesame as the transparent color code specified with bits TC3 to TC0 of the transparent/translucent color control command (command 6-2).

• Transparent color control has priority over replacement by the specified character color andthe color on the lower layer is displayed if: graphic color/character color replace control isON (bit GCC = 1) and transparent color control is ON (bit TCC of the transparent/translucentcolor control command [command 6-2] = 1) and the code of the character color (specifiedwith bits MC3 to MC0 of the character data set 1 command [command 1]) to be replaced isthe same as the transparent color code specified with bits TC3 to TC0 of the transparent/translucent color control command (command 6-2).

• Specify the codes of colors to be replaced by the character color (bits GC3 to GC0) that aredifferent from the codes of colors to be replaced by the trimming color (bits GF3 to GF0) if:graphic color/character color replace control is ON (bit GCC = 1) and graphic color/trimmingcolor replace control is ON (bit GFC = 1).

Note:

This command applies only to the colors of graphic characters on the main screen.

The colors of sprite characters and those of screen background character dots are notaffected by this command.

675


20.5.11 Screen Background Character Control (Commands 7-1 and 7-3)

Commands 7-1 and 7-3 control screen background characters and the screen background color.

Command 7-1 (Screen Background Character Control 1)

Address: 1AH

Format

[Function]

Command 7-1 controls screen background characters.

[Supplement]

• Screen background characters specified by command 7-1 are displayed when screenbackground character output control is set to ON (PDS = 1) in the screen output control 1Acommand (command 5-00).

• The vertical size of screen background characters can be specified with the screenbackground character vertical size control bits (bits PH2 to PH0) of the screen backgroundcharacter control 2 command (command 7-3).

• The screen background character operation control is stopped the operation (PCUT=1), thehorizontal display position offset value of the main screen etc is allowed to reduce.

Notes:

• Only graphic characters can be displayed as screen background characters.

• The graphic color/trimming color replace control and graphic color/character color replacecontrol by graphic color control command (command 6-3) are not effective for the graphiccolors of screen background characters.

• When the display control is stopped by the screen background character operation control,the screen background character output control of the screen output control 1 (command 5-00) is set to OFF (PDS=0).

PCUT 0 PD1 PD0 0 PM10 PM9 PM8 PM7 PM6 PM5 PM4 PM3 PM2 PM1 PM0

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PD1, PD0: Screen background characterconfiguration control(0, 0: One character)(0, 1: Two characters horizontally)(1, 0: Two characters vertically)(1, 1: Two characters vertically

by two characters horizontally)

PM10 to PM0: Screen background character code(000H to 6FCH for 448 differentcharacters)

PCUT: Screen background characteroperation control(0: screen background character

display is enabled)(1: screen background character

display is stopped)

676


Command 7-3 (Screen Background Character Control 2)

Address: 1CH

Format

[Function]

Command 7-3 controls screen background characters and the screen background color.

[Supplement]

• The screen background color specified by command 7-3 is displayed when screenbackground output control is set to ON (UDS = 1) in the screen output control 1A command(command 5-00).

• Screen background characters are displayed when screen background character outputcontrol is set to ON (PDS = 1) in the screen output control 1A command (command 5-00).

0 0 0 0 0 0 0 0 0 PH2 PH1 PH0 U3 U2 U1 U0

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PH2 to PH0:

U3 to U0:

Screen background character vertical size control(18-32 dots in 2-dot units)

Screen background color(From among 16 colors)

677


20.5.12 Sprite Character Control (Commands 8-1, 8-2, 9-0, and 9-1)

Commands 8-1, 8-2, 9-0, and 9-1 control sprite characters.

Command 8-1 (Sprite Character Control 1)

Address: 1EH

Format

[Function]

Command 8-1 controls sprite characters.

[Supplement]

• Sprite characters are displayed when sprite character output control is set to ON (SDS = 1)in the screen output control 1A command (command 5-00).

• Sprite character display positions are specified by the sprite character control 3 command(command 9-0) and sprite character control 4 command (command 9-1).

• The vertical size of sprite characters is specified with the sprite character vertical size controlbits (bits SH2 to SH0) of the sprite character control 2 command (command 8-2).

• Whether to turn on blinking of sprite characters is specified by the sprite character blinkcontrol bit (SBL bit) of the sprite character control 2 command (command 8-2).

• The sprite character blink cycle and blink duty ratio depend on the settings of bits BT1, BT0,BD1, and BD0 of command 5-1.

• The sprite operation control is stopped the operation(SCUT=1), the horizontal displayposition offset value of the main screen etc is allowed.

SCUT 0 SD1 SD0 0 SM10 SM9 SM8 SM7 SM6 SM5 SM4 SM3 SM2 SM1 SM0

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SD1, SD0: Sprite character configurationcontrol(0, 0: 1 character)(0, 1: Horizontal set of 2 characters)(1, 0: Vertical set of 2 characters)(1, 1: 2 × 2 characters)

SM10 to SM0: Sprite character code(000H to 6FCH for 448 different characters)

SCUT: Sprite operation control(0: sprite display is enabled.)(1: sprite control operation is stopped.)

678


Notes:

• Only graphic characters can be displayed as sprite characters.

• Graphic color/trimming color replace control and graphic color/character color replace controlby the graphic color control command (command 6-3) are not effective for the graphic colorsof sprite characters.

• When the display is stoped by the sprite oeration control, the sprite character outptut controlof the screen output control 1 (command 5-00) is set to OFF (SDS=0).


Address: 20H

Format

[Function]

Command 8-2 controls sprite characters.

[Supplement]

For sprite character control 1 settings, see [Supplement] for command 8-1.


Address: 22H

Format

[Function]

Command 9-0 controls the sprite character vertical display position.

[Supplement]


0 0 0 0 0 0 0 SBL 0 SH2 SH1 SH0 0 0 0 0

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SBL: Sprite character blink control(0: OFF, 1: ON)

SH2 to SH0: Sprite character vertical size control(18 to 32 dots in 2-dot units)

0 0 0 0 0 0 SY9 SY8 SY7 SY6 SY5 SY4 SY3 SY2 SY1 SY0

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SY9 to SY0: Sprite character vertical display position control(0 to 2046 in 2-dot units)

679



Address: 24H

Format

[Function]

Command 9-1 controls the sprite character horizontal display position.

[Supplement]


0 0 0 0 0 0 SX9 SX8 SX7 SX6 SX5 SX4 SX3 SX2 SX1 SX0

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SX9 to SX0: Sprite character horizontal display position control(0 to 2046 in 2-dot units)

680


20.5.13 Synchronization Control (Command 11-0)

Command 11-0 controls synchronization of display.

Command 11-0 (Synchronization Control)

Address: 26H

Format

[Function]

Command 11-0 controls the synchronization system (for interlaced or noninterlaced display).

[Supplement]

Setting of the field correction control bit (FC bit) is valid only for interlaced display (IN = 0).

00 0 0 0 0 0 0 0 0 IN 0 FC 0 0 0

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

IN: Synchronization control(0: Interlaced)(1: Noninterlaced)

FC: Field correction control(0: No correction, 1: Correction)

681


20.5.14 Dot Clock Control (Commands 11-1 to 11-3)

Commands 11-1 to 11-3 control the dot clock.

Command 11-1 (Dot Clock Control 1)

Address: 28H

Format

[Function]

Command 11-1 controls dot clocks

DCO 0 0 0 0 0 0 0 0 0 0 DP1 DP0 0 0 DHRS

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DP1, DP0: Dot clock prescaler control (0, 0 : 1/1)(0, 1 : 1/2)(1, 0 : 1/4)(1, 1 : 1/8)

DCO: Dot clock output pin control(0: OFF, 1: ON)

DHRS: Edge selection for phase comparison(0: Rising edge of horizontal synchronization signal) *Edge on back porch side(1: Falling edge of horizontal synchronization signal) *Edge on front porch side

682



Address: 2AH

Format

[Function]

Command 11-2 adjusts the frequency of the dot clock used.

[Supplement]

This command specifies the value (in 1-dot units) used to divide the frequency of the dot clockoutput by the prescaler (set by bits DP1 and DP0 of command 11-1) to the cycle of thehorizontal synchronization signal.

DK0 0 0 0 0 DK11 DK10 DK9 DK8 DK7 DK6 DK5 DK4 DK3 DK2 DK1

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DK11 to DK0: Number of dot clock frequency-divisions(In 1-dot units, minimum of 129 divisions, maximum of 4,096 divisions)

683



Address: 2CH

Format

[Function]

Command 11-3 controls dot clock oscillation.

PDE0 0 0 0 0 0 0 0 VC VSL2 VSL1 VSL0 CHG1CHG0 CPE

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

VSL2 to VSL0:

CPE:

CHG1, CHG0:

VCO selection control(0, 0, 0: VCO1)(0, 0, 1: VCO2)(0, 1, 0: VCO3)(0, 1, 1: VCO4)(1, 0, 0: VCO5)(1, 0, 1: VCO6)(Other settings prohibited)

Charge pump control(0: OFF, 1: ON)

Charge pump bias current control(0, 0 : approx. 100 µA)(0, 1 : approx. 500 µA)(1, 0 : approx. 1 mA)(1, 1 : setting prohibited)

VC:

PDE:

VCO oscillation control(0: OFF, 1: ON)

Phase comparator control(0: OFF, 1: ON)

684


20.5.15 I/O Pin Control (Commands 13-0 and 13-1)

Commands 13-0 and 13-1 control input/output pins.

Command 13-0 (I/O Pin Control)

Address: 2EH

Format

[Function]

Command 13-0 controls input/output pins.

[Supplement]

• The HSYNC edge selection bit for vertical synchronization detection (VHE) can avoid verticaldancing due to the input timing of vertical and horizontal sync signals. For details, seeSection "20.4.2.1 Vertical Synchronization Control".

• The logic control for display color signal output by the OSDC inverts the color informationlogic set before palette input. This control does not apply to the color information that isconverted by the palette.

0 0 0 0 0 0 0 0 0 0 0 0 0 OHX OBX OCX

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OCX:

OBX:

OHX:

Logic control for display color signal output(0: Positive logic, 1: Negative logic)

Logic control for display output period signal output(0: Positive logic, 1: Negative logic)

Logic control for translucent display period signal output(0: Positive logic, 1: Negative logic)

685


Command 13-1 (I/O Pin Control 2)

Address: 30H

Format

[Function]

This command controls the input/output pins.

0 0 0 0 0 0 0 VHE HE 0 0 0 0 IHX IVX 0

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

VHE:

HE:

HSYNC edge selection for vertical synchronization detection(0: Rising edge, 1: Falling edge)

Edge selection for horizontal synchronization operation(0: Falling edge, 1: Rising edge)

IHX:

IVX:

Logic control for horizontal synchronization signal input(0: Negative logic, 1: Positive logic)

Logic control for vertical synchronization signal input(0: Negative logic, 1: Positive logic)

686


20.5.16 Display Period Control (Commands 14-0 to 14-3)

Commands 14-0 to 14-3 control the display periods.

Command 14-0 (Display Period Control 1)

Address: 32H

Format

[Function]

Command 14-0 controls the timing at which to start vertical display.

0 0 0 0 0 DYS10 DYS9 DYS8 DYS7 DYS6 DYS5 DYS4 DYS3 DYS2 DYS1 DYS0

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DYS10 to DYS0: Vertical display start control(0 to 2047, in 1-dot units)

687



Address: 34H

Format

[Function]

Command 14-1 controls the timing at which to end vertical display.


Address: 36H

Format

[Function]

Command 14-2 controls the timing at which to start horizontal display.

0 0 0 0 0 DYE10 DYE9 DYE8 DYE7 DYE6 DYE5 DYE4 DYE3 DYE2 DYE1 DYE0

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DYE10 to DYE0: Vertical display end control(0 to 2047, in 1-dot units)

0 0 0 0 0 DXE10 DXE9 DXE8 DXE7 DXE6 DXE5 DXE4 DXE3 DXE2 DXE1 DXE0

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DXE10 to DXE0: Horizontal display end control(0 to 2047, in 1-dot units)

688



Address: 38H

Format

[Function]

Command 14-3 controls the timing at which to end horizontal display.

0 0 0 0 0 DXE10 DXE9 DXE8 DXE7 DXE6 DXE5 DXE4 DXE3 DXE2 DXE1 DXE0

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DXE10 to DXE0: Horizontal display end control(0 to 2047, in 1-dot units)

689


20.5.17 Interrupt Control (Command 15-0)

Command 15-0 controls the interrupts.

Command 15-0 (Interrupt Control)

Address: 3AH

Format

[Function]

Command 15-0 controls the interrupts.

To clear a set flag (FIF, LIF, or VIF), write "0" to the flag.

0 0 0 0 0 FIF LIF VIF 0 0 0 0 0 FIE LIE VIE

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FIF:

LIF:

VIF:

FIE:

LIE:

VIE:

VRAM fill end flag(0: VRAM fill end not detected, 1: VRAM fill end detected)

Line display end flag(0: Line display end not detected, 1: Line display end detected)

VSYNC detection flag(0: VSYNC not detected, 1: VSYNC detected)

VRAM fill end interrupt control(0: Interrupt disabled, 1: Interrupt enabled)

Line display end interrupt control(0: Interrupt disabled, 1: Interrupt enabled)

VSYNC detection interrupt control(0: Interrupt disabled, 1: Interrupt enabled)

690


20.5.18 Palette Control (Commands 16-0 to 16-15)

Commands 16-0 to 16-15 control the values of palettes.

Commands 16-0 to 16-15 (Palette Control)

Address: See the table below.

Format

PLR2 to PLR0: Values of red color palette

PLG2 to PLG0: Values of green color palette

PLB2 to PLB0: Values of blue color palette

[Function]

These commands control the values of palettes.

[Supplement]

• RGB colors can be assigned to 4-bit color codes (0 to F) of the OSDC by specifying palettevalues in "commands 16-0" to "commands 16-15".

• There are the following types of color codes:Character colors (MC3 to MC0)Character background colors (MB3 to MB0)

Address (Low-order

8 bits)

Command No.

Data

15-11 10 9 8 7 6 5 4 3 2 1 0

3C 16-0 00000 PLR2 PLR1 PLR0 0 PLG2 PLG1 PLG0 0 PLB2 PLB1 PLB0

3E 16-1 00000 PLR2 PLR1 PLR0 0 PLG2 PLG1 PLG0 0 PLB2 PLB1 PLB0

40 16-2 00000 PLR2 PLR1 PLR0 0 PLG2 PLG1 PLG0 0 PLB2 PLB1 PLB0





4A 16-7 00000 PLR2 PLR1 PLR0 0 PLG2 PLG1 PLG0 0 PLB2 PLB1 PLB0

4C 16-8 00000 PLR2 PLR1 PLR0 0 PLG2 PLG1 PLG0 0 PLB2 PLB1 PLB0

4E 16-9 00000 PLR2 PLR1 PLR0 0 PLG2 PLG1 PLG0 0 PLB2 PLB1 PLB0






5A 16-15 00000 PLR2 PLR1 PLR0 0 PLG2 PLG1 PLG0 0 PLB2 PLB1 PLB0

691


Trimming colors (LF3 to LF0)Line background colors (L3 to L0)Shaded background frame colors (BH3 to BH0 and BS3 to BS0)Graphic color control (GF3 to GF0 and GC3 to GC0)Screen background colors (U3 to U0)Graphic colors

692


20.5.19 OSDC Operation Control (Commands 17-0 and 17-1)

Commands 17-0 and 17-1 control the initial operation of the OSDC.

Command 17-0 (OSDC Operation Control 1)

Address: 5CH

Format

[Function]

Command 17-0 controls access to OSDC-related resources.

[Supplement]

The OSDEN bit of command 17-1 must be set to "1" before setting the DAC enable bit ofcommand 17-0.

0 0 0 0 0 0 0 0 0 0 0 DCK 0 0 0 DPD

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DCK:

DPD:

Input dot clock selection control(0: Input of external clock, 1: Input of dot clock generated by internal PLL)

DAC enable(0: OSDC DAC access OFF, 1: OSDC DAC access ON)

693


Command 17-1 (OSDC Operation Control 2)

Address: 5EH

Format

[Function]

Command 17-1 controls the operation of the OSDC.

[Supplement]

• When analog output control or digital output control is set to ON, the VOB1 and VOB2signals, which are common to the analog and digital systems, are output.

• To turn off the output of the VOB1 and VOB2 signals, analog output control and digital outputcontrol must both be set to OFF.

• The OSDEN bit must be set to "1" if and only if the external clock is normally input or theinternal PLL clock is normally generated.

0 0 0 0 0 0 0 0 0 0 OSDEN 0 FHO DGO ANO0

bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ANO:

FHO:

OSDEN:

Analog output control(0: Output OFF, 1: Output ON)

FH output control(0: Output OFF, 1: Output ON)

OSDC enable(0: OSDC operation OFF, 1: OSDC operation ON)

DGO: Digital output control(0: Output OFF, 1: Output ON)

694


This chapter provides an outline of flash memory and explains its register configuration, register functions, and operations.

21.1 Outline of Flash Memory

21.2 Flash Memory Registers

21.3 Flash Memory Access Modes

21.4 Automatic Algorithm of Flash Memory

21.5 Execution Status of the Automatic Algorithm

21.6 Writing to and Erasing from Flash Memory

695



This product contains a 512K-byte (4M-bit) flash memory where the simultaneous erasure of all sectors, erasure in sector units, and writing in half-word (16 bits) units via the FR-CPU are possible with a single 3 V power supply.

Outline of Flash Memory

The flash memory employed is an internal 512K-byte flash memory that operates on 3 V.

The flash memory employed here is the same as the Fujitsu 4M-bit flash memory MBM29LV400(except for part of the sector configuration) and supports writing using a device-external ROMwriter.

When this memory is used as FR-CPU internal ROM, it becomes possible to read instructionsand data in word units (32 bits), in addition to features equivalent to the features of theMBM29LV400. This enables high-speed device operation.

Along with this manual, refer to the MBM29LV400 Data Sheet.

This product supports the following features by combining flash memory macros and FR-CPUinterface circuits:

• Features for use as CPU memory, for storing programs and data

Accessibility through 32-bit bus when used as ROM

Allowing read, write, and erase (automatic program algorithm*) by the CPU

• Features of a single flash memory product equivalent to MBM29LV400

Allowing read or write (automatic program algorithm*) by a ROM writer

*: Automatic program algorithm: embedded algorithm

This section explains use of the flash memory accessed from the FR-CPU.

For information on using the flash memory accessed from a ROM writer, see the instructionmanual provided with the ROM writer.

696


Block Diagram

Figure 21.1-1 shows a block diagram of flash memory.

Figure 21.1-1 Block diagram of flash memory

Detection of rising edge

Bus

con

trol

sig

nal

FR-F bus (instruction/data)

Address buffer Data buffer

Flash memory

Generation of control signal

RDY WE

FD31-0FA18-0

RESETX

RDY/BUSYX

BYT

OEX

WEX

EX

FA18-0 DI15-0 DO31-0

8M bits

CE

697


Memory Map

Flash memory employs different address mapping depending on whether accessed in flashmemory mode or CPU mode.

Figure 21.1-2 shows the mapping for access in flash memory mode and CPU mode.

Figure 21.1-2 Memory Mapping for Access in Flash Memory Mode/CPU Mode

Note that 64-bit access is used for 64-bit flash memory in CPU mode; 8-bit/16-bit width is usedin flash memory mode.

FLASH

FLASH/Mask-ROM

I/O, etc

0000_0000

FFFF_FFFF

0010_0000

0008_0000

Flash memory modeCPU mode

64 bit

0018_0000

001F_FFFF

512 Kbytes

512 Kbytes

8 bit/16 bit

698


Sector Address Table

Figure 21.1-3 shows the sector configuration in CPU mode.

Figure 21.1-3 Sector Configuration in CPU Mode

63 56,55 48 47 40,39 32 31 24,23 16 15 8,7 0

15 8,7 0

+1/+0

+0/+1

15 8,7 0

+1/+0

+2/+3

15 8,7 0

+1/+0

+4/+5

15 8,7 0

+1/+0

+6/+7

000C_0000H

000D_FFFFH

000E_0000H

000E_7FFFH

000E_FFFFH

000F_0000H

000E_8000H

000F_FFFFH

Bit location in CPU modeBit location in flash memory mode

FLASH(little endian)

CPU(big endian)

6FFFFH 4FFFFH 2FFFFH 0FFFFH

60000H 40000H 20000H 00000H

000B_FFFFH

0008_0000H

SA30(64K)

SA26(64K)

SA22(64K)

SA18(64K)

77FFFH 57FFFH 37FFFH 17FFFH

70000H 50000H 30000H 10000H

SA31(32K)

SA27(32K)

SA23(32K)

SA19(32K)

79FFFH 59FFFH 39FFFH 19FFFH

7BFFFH 5BFFFH 3BFFFH 1BFFFH

7FFFFH 5FFFFH 3FFFFH 1FFFFH

78000H 58000H 38000H 18000H

7A000H 5A000H 3A000H 1A000H

7C000H 5C000H 3C000H 1C000H

SA41(8K)

SA38(8K)

SA35(8K)

SA32(8K)

SA42(8K)

SA39(8K)

SA36(8K)

SA33(8K)

SA43(16K)

SA40(16K)

SA37(16K)

SA34(16K)

699



The flash memory has types of two registers: flash control/status register (FLCR) and flash memory wait register (FMWT).

List of Flash Memory Registers

Figure 21.2-1 shows a list of flash memory registers.

Figure 21.2-1 Flash Memory Registers

7bit 0

Flash control/status register(FLCR)

Flash memory wait register(FMWT)

700


21.2.1 Flash Control/Status Register (FLCR)

The flash control/status register (FLCR) indicates the operation status of flash memory.

Configuration of Flash Control/Status Register (FLCR) (CPU Mode)

This register controls writing to flash memory.

This register can only be accessed in CPU mode. Do not access this register using the ReadModify Write instruction.

Figure 21.2-2 shows the bit configuration of FLCR.

Figure 21.2-2 Bit Configuration of FLCR

[bit7] Reserved

This is a reserved bit. Always set this bit to "0".

[bit6, bit5] Reserved

These are reserved bits. Always set these bits to "1".

[bit4] Reserved

This is a reserved bit. It is initialized to "0" during a reset.

[bit3] RDY

This bit indicates the operation status of the automatic algorithm (write/erase).

When this bit is set to "0", writing or erasure is in progress with the automatic algorithm andno Write and Erase command can be accepted. Moreover, data cannot be read from anyaddress in flash memory.

The read data indicates the flash memory status as listed in the table below.

• This bit is not initialized during a reset.

• Only read operation is possible, but write operation does not affect this bit.

[bit2] Reserved


bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

Reserved Reserved Reserved Reserved RDY Reserved WE Reserved

R/W R/W R/W R R R/W R/W R/W

00007000H

(0) (1) (1) (0) (1) (0) (0) (0)

0 Writing or erasing is in process, flash memory is not ready to accept a new Write/Erase command, and no data can be read from a flash memory address.

1 Flash memory is ready to accept a new Write/Erase command and data can be read from a flash memory address.

701


[bit1] WE (Write Enable)

This bit controls the writing of data and commands to flash memory in CPU mode.

When this bit is set to "0", writing data and commands to flash memory is disabled.

Moreover, data is read from flash memory in 32-bit access mode.

When this bit is set to "1", data and commands can be written to flash memory and theautomatic algorithm can be started. However, data is read from flash memory in 16-bitaccess mode.

If this bit is overwritten, confirm that the RDY bit has stopped the automatic algorithm (write/erase). When the RDY bit is set to "0", the value of this bit cannot be changed.

Notes:

• If this is overwritten, confirm that the RDY bit has stopped the automatic algorithm. Whenthe RDY bit is set to "0", the value of this bit cannot be charged.

• When WE=1, do not respond to the instruction access request and only respond to thedata access request.

Writing is enabled regardless of this bit in flash memory mode.

• This bit is initialized to "0" during reset.

• Read and write operations are enabled.

[bit0] Reserved


0 Writing to flash memory is disabled and data is read from flash memory in 32-bit access mode.

1 Writing to flash memory is enabled and data is read from flash memory in 16-bit access mode.

702


21.2.2 Flash Memory Wait Register (FMWT)

The flash memory wait register (FMWT) controls the wait status of flash memory in CPU mode.

Configuration

Figure 21.2-3 shows the bit configuration of flash memory wait register (FMWT).

Figure 21.2-3 Bit Configuration of Flash Memory Wait Register (FLWC)

[bit7, bit6] Reserved

These are reserved bits. Always set these bits to "01".

[bit5, bit4] FAC1 and FAC0

These bits specify the H width of ATDIN and EQIN.

[bit3] Reserved


[bit2 to bit0] WTC2, WTC1, and WTC0 (wait cycle bits)

These bits control the wait status of flash memory.

bit7

FAC1 FAC0 WTC2 WTC1 WTC0

bit6 bit5 bit4 bit3 bit2 bit1 bit0

R R/W R/W R/W R/W R/W R/W R/W

00007004H

(0) (1) (1) (1) (0) (0) (1) (0)

FAC1 FAC0 ATDIN EQIN

0 0 0.5 clock 1.0 clock



1 1 0.5 clock 1.5 clock 40 MHz (Initial value)

WTC2 WTC1 WTC0 Wait cycle

0 0 0 Setting is disabled.

0 0 1 1

0 1 0 2 40 MHz (Initial value)

0 1 1 3

1 0 0 4

1 0 1 5

1 1 0 6

1 1 1 7

703


• Flash access timing

Access times and the number of access cycles of flash macros are combined as listed in thetable below.

Read Write

40MHz 40MHz

Time 50 ns 90 ns

cycle 3(2) 4(3)

Values enclosed in parentheses are WTC register values.

704



The following two types of access mode are available for the FR-CPU:• 120M mode:

One word (32 bits) can be read but not written in a single cycle.• Programming mode:

Access to data with a length defined in words (32 bits) is prohibited but writing data with a length defined in half-words (16 bits) is enabled.

FR-CPU ROM Mode (32 Bits, Read only)

In this mode, the flash memory serves as FR-CPU internal ROM. This mode enables to readone word (32 bits) in one cycle but does not enable to write to flash memory or to start theautomatic algorithm.

Mode specification

When specifying this mode, set the “WE” bit of the flash memory status register to “0”.

This mode is always set after a reset occurs at CPU run time.

This mode can be set only when the CPU is running.

Detailed operation

In this mode, one word (32 bits) can be read from the flash memory area in one cycle.

Restrictions

• Address assignment and endians in this mode differ from those for writing with the ROMwriter.

• In this mode, commands and data cannot be written to flash memory together.

FR-CPU Programming Mode (16 Bits, Read/Write)

This mode enables data to be written and erased. As one word (32 bits) cannot be accessed inone cycle, program execution in flash memory is disabled in this mode.

Mode specification

When specifying this mode, set the "WE" bit of the flash memory status register to "1".

When a reset occurs at CPU run time, the "WE" bit indicates "0". When setting this mode, setthe "WE" bit to "1". If the "WE" bit is set again to "0" through a writing operation or because of areset, the device enters ROM mode.

When the "RDY" bit of the flash memory status register is "0", the "WE" bit cannot beoverwritten. When overwriting the "WE" bit, ensure that the "RDY" bit is set to "1".

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Detailed operation

One half-word (16 bits) can be read from the flash memory area in one cycle.

The automatic algorithm can be started by writing a command to flash memory.

When the automatic algorithm starts, data can be written to or erased from flash memory. Fordetails on the automatic algorithm, see Section "21.4 Automatic Algorithm of Flash Memory".

For details on the automatic algorithm, see Section "21.4 Automatic Algorithm of FlashMemory".

Restrictions

• Address assignment and endians in this mode differ from those for writing with the ROMwriter.

• This mode inhibits reading data in words (32 bits).

Automatic Algorithm Execution Status

When the automatic algorithm is started in CPU programming mode, the operation status of theautomatic algorithm can be checked using the internal Ready/Busy signal (RDY/BUSYX). Thelevel of this signal can be read as the RDY bit in the flash memory status register.

When the RDY bit is set to "0", data is being written or erased with the automatic algorithm, andno write or erase command can be accepted. Moreover, data cannot be read from any addressin flash memory.

Data read with the RDY bit set to "0" is a hardware sequence flag to indicate flash memorystatus.

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The flash memory automatic algorithm can be started using a Read/Reset, Write, Chip Erase, or Sector Erase command. The Sector Erase command can stop and restart the automatic algorithm.

Command Sequence

At the start of the automatic algorithm, one to six half-words (16 bits) are written. This data iscalled the command.

If the address and data to be written are invalid or are written in an incorrect sequence, the flashmemory is reset to read mode.

Table 21.4-1 lists commands that can be used to write data to or erase data from flash memory.

RA: Flash memory read address

PA: Flash memory write address

SA: Address of sector to be erased in flash memory (Specify an address in a sector.)

RD: Data read from flash memory

FMA: Address

DIN: Written data

Table 21.4-1 Command Sequence

Command sequence

Bus write cycle

First bus write cycle

Second bus write cycle

Third bus write cycle

Fourth bus write cycle

Fifth bus write cycle

Sixth bus write cycle

FMA DIN FMA DIN FMA DIN FMA DIN FMA DIN FMA DIN

Read/Reset

1 AXXXXH F0F0H --- --- ---- --- --- --- --- --- --- ---

Read/Reset

4 AAAAAH AAAAH A5555H 5555H AAAAAH FOFOH RA RD --- --- --- ---

Write 4 AAAAAH AAAAH A5555H 5555H AAAAAH A0A0H PA PD --- --- --- ---

Chip Erase 6 AAAAAH AAAAH A5555H 5555H AAAAAH 8080H AAAAAH AAAAH A5555H 5555H AAAAAH 1010H

Sector Erase

6 AAAAAH AAAAH A5555H 5555H AAAAAH 8080H AAAAAH AAAAH A5555H 5555H SA 3030H

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Read/Reset command

Set flash memory into Read/Reset mode.

The flash memory remains in reading state until another command is entered.

When the power is turned on, flash memory is automatically set to the read or reset state. In thiscase, data can be read without a command of the automatic algorithm.

Upon returning to read mode after the time limit is exceeded, note that a Read/Reset commandsequence can be issued. Data is read from flash memory in the next read cycle.

Program (Write)

In CPU programming mode, data is basically written in half-word units. The write operation isperformed in four cycles of bus operation. The command sequence has two "unlock" cycles,which are followed by a Write Setup command and a write data cycle. Writing to memory startsin the last write cycle.

After an automatic write algorithm command sequence was executed, it becomes unnecessaryto control the flash memory externally. The flash memory itself internally generates write pulsesto check the margin of the cells to which data is written. The data polling function compares bit7of the original data with bit7 of the written data, and if these bits are the same, the automaticwrite operation ends (see “Hardware sequence flag", in Section "21.5 Execution Status of theAutomatic Algorithm"). The automatic write operation then returns to the read mode and acceptsno more write addresses. After that, the flash memory requests the next valid address. In thismanner, the data polling function indicates a write operation in memory.

During a write operation, all commands written to the flash memory are ignored. If a hardwarereset starts during write operation, the data at the address for writing may become invalid.

Writing operations can be performed in any address sequence and outside of sectorboundaries. However, write operations cannot change a data item “0” to "1". If a "0" isoverwritten with a "1", the data polling algorithm either determines that the elements aredefective, or that "1" has been written. In the latter case, however, the respective data item isread as "0" in reset or read mode. A data item "0" can be changed to "1" only after an eraseoperation.

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Chip Erase

The Chip Erase command sequence ("erase all sectors simultaneously") is executed in sixaccess cycles. First, two "unlock" cycles are executed, then a “Setup” command is written. Aftertwo more "unlock" cycles, the Chip Erase command is entered.

During the Chip Erase command sequence, the user does not have to write to flash memorybefore the erase operation. When the automatic erase algorithm is executed, flash memorychecks cell states by writing a pattern of zeros before automatically erasing the contents of allcells (preprogram). In this operation, flash memory does not have to be controlled externally.

The automatic erase operation starts with the write operation of the command sequence andends when bit7 is set to "1", where flash memory returns to the read mode. The chip erase timecan be expressed as follows: time for sector erase x number of all sectors + time for writing tothe chip (preprogram).

Sector Erase

The Sector Erase command sequence is executed in six access cycles. First, two "unlock"cycles are executed, then a "Setup" command is written. After two more “unlock” cycles, theSector Erase command is entered in the sixth cycle for starting the sector erase operation. Thenext Sector Erase command can be accepted within a time-out period of 50 µs after the lastSector Erase command is written.

As already mentioned, multiple Sector Erase commands can be accepted during the six buscycles of the writing operation. During the command sequence, Sector Erase commands (30H)for sectors whose contents are to be erased simultaneously are written consecutively to theaddresses for these sectors. The sector erase operation itself starts from the end of the time-outperiod of 50 µs after the last Sector Erase command is written. When the contents of multiplesectors are erased simultaneously, the subsequent Sector Erase commands must be inputwithin the 50 µs time-out period to ensure that they are accepted. For checking whether thesucceeding Sector Erase command is valid, read bit3 (see "Hardware sequence flag", inSection "21.5 Execution Status of the Automatic Algorithm").

During the time-out period, any command other than Sector Erase and Temporarily Stop Eraseis reset at read time, and the preceding command sequence is ignored. In the case of theTemporary Stop Erase command, the contends of the sector are erased again and the eraseoperation is completed.

Any combination and number (from 0 to 6) of sector addresses can be entered in the sectorerase buffers.

The user does not have to write to flash memory before the sector erase operation.

Flash memory automatically writes to all cells in a sector whose data is automatically erased(preprogram). When the contents of a sector are erased, the other cells remain intact. In theseoperations, flash memory does not have to be controlled externally.

The automatic sector erase operation starts from the end of the 50 µs time-out period after thelast Sector Erase command is written. When bit7 is set to "1", the automatic sector eraseoperation ends and flash memory returns to the read mode. At this time, other commands areignored.

The data polling function is enabled for any sector address in which data has been erased. Thetime required for erasing the data of multiple sectors can be expressed as follows: time forsector erase + time for sector write (preprogram) × number of erased sectors.

Temporarily Stop Erase

The Temporarily Stop Erase command temporarily stops the automatic algorithm in flashmemory when the user is erasing the data of a sector, thereby making it possible to write data toand read data from the other sectors. This command is valid only during the sector eraseoperation and ignored during chip erase and write operations.

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The Temporarily Stop Erase command (B0H) is effective only during sector erasure operationthat includes the sector erase time-out period after a Sector Erase command (30H) is issued.

When this command is entered within the time-out period, waiting for time-out ends and theerase operation is suspended. The erase operation is restarted when a Restart Erase commandwas written. Temporarily Stop Erase and Restart Erase commands can be entered with anyaddress.

When a Temporarily Stop Erase command is entered during sector erase operation, the flashmemory needs a maximum of 20 µs to stop the erase operation. When flash memory enterstemporary erase stop mode, a Ready or Busy signal is output, bit7 outputs “1”, and bit6 stops totoggle. For checking whether the erase operation has stopped, enter the address of the sectorwhose data is being erased and read the values of bit6 and bit7. At this time, anotherTemporarily Stop Erase command entry is ignored.

When the erase operation stops, flash memory enters the temporary erase stop and read mode.Data reading is enabled in this mode for sectors that are not subject to temporary erase. Otherthan that, there is no difference from the standard read operation. In this mode, bit 2 toggles forconsecutive reading operations from sectors subject to temporary erase stop.

After the temporary erase stop and read mode is entered, the user can write to flash memory bywriting a Write command sequence. The write mode in this case is the temporary erase stopand write mode. In this mode, data write operations become valid for sectors that are notsubject to temporary erase stop. Other than that, there is no difference from the standard bytewriting operation. In this mode, bit2 toggles for consecutive reading operations from sectors thatare subject to temporary erase stop. The temporary erase stop bit (bit6) can be used to detectthis operation.

Note that bit 6 can be read from any address, but bit 7 must be read from write addresses.

To restart the sector erase operation, a Restart Erase command (30H) must be entered. AnotherRestart Erase command entry is ignored in this case. On the other hand, a Temporarily StopErase command can be entered after flash memory restarts the erase operation.

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Flash memory is provided with hardware to indicate the internal operation status of flash memory and the completion of write/erase operations in the automatic algorithm. The following two hardware sequence flags for the automatic algorithm can be used to check the operation status of flash memory:• Ready/Busy signal• Hard ware sequence flag

Ready/Busy Signal (RDY/BUSYX)

The flash memory uses the Ready/Busy signal in addition to the hardware sequence flag toindicate whether the internal automatic algorithm is running. The Ready/Busy signal istransmitted to the flash memory interface circuit, where it can be read via the “RDY” bit of theflash memory status register. An interrupt signal can also be generated for the CPU at the risingedge of this Ready/Busy signal.

When the value of the “RDY” bit is "0", the flash memory is executing a write or erase operation,where new Write and Erase commands are not accepted.

When the value of the "RDY" bit is "1", the flash memory is in read/write or erase operation waitstate.

Hardware Sequence Flag

Figure 21.5-1 shows the structure of the hardware sequence flag.

Figure 21.5-1 Structure of the Hardware Sequence Flag

Note:

Reading in units of words is disabled. (Only use this function in FR-CPU programmingmode.)

For obtaining the hardware sequence flag as data, read an arbitrary address (an odd address inbyte access) from flash memory when the automatic algorithm is executed. The data containsfive validity bits which indicate the status of the automatic algorithm.

When the automatic algorithm is executed for ROM1, specify an address in ROM1. Whenexecuted for ROM2, specify an address in ROM2.

The hardware sequence flag becomes invalid in FR-CPU ROM mode. Always use FR-CPUprogramming mode and write only in half-words or bytes.

0

0(Undefined)

15 7

7

bit

bit

8During half-word read

During byte read (from odd address only)

Hardware sequence flag

Hardware sequence flag

02 17DPOLL TOGGLE TLOVER

6 5 4 3SETIMR TOGGL2Undefined

bit(In half-word and byte access)

Undefined Undefined

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Table 21.5-1 lists the possible statuses of the hardware sequence flag.

The hardware sequence flags are explained below.

[bit7] DPOLL (Data polling flag)

This flag is used with the data polling function to report that the automatic algorithm is beingexecuted or terminated.

Automatic write operation status

When read access is performed while the automatic write algorithm is being executed, flashmemory outputs the inversion of bit7 of the last data written regardless of the address indicatedby the address signal. When read access is performed at the end of the automatic writealgorithm, flash memory outputs bit7 of the read data to the address indicated by the addresssignal.

Table 21.5-1 Statuses of the Hardware Sequence Flag

Status DPOLL TOGGLE TLOVER SETIMR TOGGL2

Executing Automatic read operation Reverse data

Toggle 0 0 1

Automatic erase operation 0 Toggle 0 1 Toggle

Temporary erase stop mode

Temporary erase stop and read (from sectors in temporary erase stop)

1 1 0 0 Toggle*1

Temporary erase stop and read (from sectors not in temporary erase stop)

Data Data Data Data Data

Temporary erase stop and write (to sectors not in temporary erase stop)

Reverse data

Toggle*2 0 0 1*3

Time limit exceeded

Automatic write operation Reverse data

Toggle 1 0 1

Automatic erase operation 0 Toggle 1 1 *4

Write operation during temporary erase stop

0 Toggle 1 1 *4

*1: TOGGLE2 toggles continuous read operations from sectors in temporary erase stop status.*2: TOGGLE toggles continuous read operations from any address.*3: During temporary erase stop status and write operations, TOGGLE2 indicates "1" while reading the

address for write operation. However, TOGGLE2 toggles continuous read operations from sectors in temporary erase stop status.

*4: TOGGLE2 toggles continuous read operations for sectors under write/erase operation, but does not toggle read operations for other sectors while TLOVER indicates "1", meaning that the time limit is exceeded.

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Chip/sector erase operation status

When read access is performed while the chip erase/sector erase algorithm is being executed,flash memory outputs "0" from the target sector (sector erase), regardless of the addressindicated by the address signal. Similarly, flash memory outputs "1" at the end of the chip erase/sector erase algorithm.

Temporary sector erase stop status

When read access is performed during temporary sector erase stop status, flash memoryoutputs “1” when the address indicated by the address signal is included in the sector in erasestatus. If the address is not included in the sector in erase status, flash memory outputs bit7 ofthe read value to the address. For checking whether a sector is in temporary sector erase stopstatus and which sector is in erase status, read this bit and the toggle bit flag.

Note

Read access to a specified address is ignored while the automatic algorithm is active. Valuescan be output to other bits after data polling flag operation terminates in data read operation.Therefore, when data is to be read after terminating the automatic algorithm, confirm that datapolling is terminated in the current read access.

[bit6]: TOGGLE (Toggle bit flag)

This flag is used with the toggle bit function to mainly report that the automatic algorithm isbeing executed or terminated.

Write or chip/sector erase operation status

When continuous read operations are performed while the automatic write algorithm or chip/sector erase algorithm is being executed, flash memory outputs "1" and "0" toggle results to bit6regardless of the address indicated by the address signal. When continuous read operations areperformed at the end of the automatic write algorithm or chip/sector erase algorithm, flashmemory stops bit6 from toggling and outputs bit6 (DATA: 6) of the data read from the addressindicated by the address signal.

Temporary sector erase stop status

When a read operation is performed during a temporary sector erase stop operation, flashmemory outputs "1" if the address indicated by the address signal is included in the sector inerase state. If the address is not included in the sector in erase state, flash memory outputs thedata of bit6 of the read value at the address indicated by the address signal.

Reference:

If a write target sector is protected from overwriting during a write operation, the toggle bittries to toggle for about 2 µs and stops toggling without changing data. If all selected sectorsare protected from overwriting, the toggle bit tries to toggle for about 100 µs and the systemreturns to read/reset status without changing data.

[bit 5] TLOVER (Time limit over flag)

This flag is used to report that a time (number of internal pulses) specified internally with flashmemory is exceeded while the automatic algorithm is being executed.


When read access is performed within a specified time (necessary for write or erase) afteractivating the automatic write or chip/sector erase algorithm, flash memory outputs "0". If readaccess is performed beyond the specified time, flash memory outputs "1". Because these outputoperations are not affected by whether the automatic algorithm is being executed or terminated,these operations can be used to check whether write or erase operation is successful. If flash

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memory outputs "1" while the automatic algorithm is being executed with the data pollingfunction or toggle bit function, consider the write operation to be unsuccessful.

For example, when "1" is written to a flash memory address where "0" is written, failure occurs.Flash memory is locked and the automatic algorithm is not terminated. Thus, valid data is notoutput from the data polling flag. The toggle bit flag does not stop toggling, the time limit isexceeded, and "1" is output to the TLOVER flag. This status indicates that flash memory wasnot used correctly, not that it was defective. Execute a Reset command.

[bit3] SETIMR Sector erase timer flag

This flag is used to report that sector erasure is being awaited after starting a Sector Erasecommand.

Sector erase operation status

When read access is performed within a sector erase wait period after starting a Sector Erasecommand, flash memory outputs "0" regardless of the address indicated by the address signalof the target sector. If read access is performed beyond the wait period, flash memory outputs"1" regardless of the address.

When "1" is set in this flag while the data polling or toggle bit function indicates that theautomatic algorithm is being executed, an internally controlled erase operation has started. Thewriting of subsequent sector erase code and commands other than Erase Temporary Stop isignored until erase operation terminates.

When this flag is "0", flash memory accepts another sector erase code entry. In this case, it isrecommended to check the status of this flag by software before writing the succeeding sectorerase code. If this flag is "1" at the second time of status check, the additional sector erase codemay not be accepted.

Sector erase operation status

When a read operation is performed during a temporary sector erase stop operation, flashmemory outputs "1" if the address indicated by the address signal is included in the sector thatis subject to the erase operation. If the address is not included in the sector that is subject to theerase operation, flash memory outputs the data of bit3 of the read value at the addressindicated by the address signal.

[bit2] TOGGL2 (Toggle bit flag 2)

Together with toggle bit6, this toggle bit is used with the toggle bit function to report whetherflash memory is under automatic erase operation or in temporary erase stop status.


This bit toggles the same way as bit2.

Temporary sector erase stop operation status

When continuous read access is performed from a sector in temporary erase stop status whileflash memory is in temporary erase stop status and read mode, bit2 toggles. When continuousread access is performed from a sector not subject to a temporary erase stop operation whileflash memory is in temporary erase stop status and write mode, bit2 becomes "1". Unlike bit2,bit6 only toggles in normal write and erase operations, or in temporary erase stop status andwrite operation.

For example, bit2 and bit6 are used together to detect a temporary erase stop and read mode(bit2 toggles but bit 6 does not). Bit2 is also used to detect sectors that are subject to eraseoperations. If data is read from a sector that is subject to an erase operation for the flashmemory, bit2 toggles.

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This section explains how to issue a command to start the automatic algorithm for a read/reset, write, chip erase, sector erase, temporary sector erase stop, or sector erase restart operation in flash memory.

Writing/Erase

The automatic algorithm can be executed for read/reset, write, chip erase, sector erase,temporary sector erase stop, or erase restart operations by executing bus write cycles for thecorresponding command sequence. The write cycles for each bus must always be executedcontinuously. Termination of the automatic algorithm can be checked with the data pollingfunction and toggle bit function. Flash memory is set again into read/reset status after theautomatic algorithm terminates normally.

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21.6.1 Read/Reset Status

This section explains how to issue Read/Reset commands to set flash memory into read/reset status.

Read/Reset Status

The read/reset operation becomes possible by continuously sending Read/Reset commands(listed in the command sequence table) to target sectors in flash memory.

A bus operation is performed one or three times with a Read/Reset command sequence. Thereis no essential difference between these two sequences. Read/reset status is the initial status offlash memory, and flash memory is set in this status at power-on or when a commandterminates normally. In this status, the system waits for a command other than Read/Reset tobe entered.

Data can be read using normal read access in this status. Programs can be accessed from theCPU the same way the programs in mask ROM are accessed. The Read/Reset command is notnecessary for reading data in normal read access. This command is required, however, toinitialize the automatic algorithm if a command does not terminate normally.

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21.6.2 Data Writing

This section explains how to issue a Write command to write data to flash memory.

Data Writing

The automatic data write algorithm can be started by continuously sending write commands(listed in the command sequence table) to target sectors in flash memory. The automaticalgorithm and automatic writing start when writing data to the target address terminates in thefourth cycle.

How to specify address

Only even-numbered addresses can be specified in write data cycles. If an odd-numberedaddress is specified, data cannot be written correctly. In other words, data must be written toeven-numbered addresses in units of half-words.

Data can be written by freely specifying the order of addresses where data is to be written.Moreover, data can be written beyond sector boundaries. Note that items of data can only bewritten with each write command in units of half-words.

Notes on writing data

Data "0" cannot be changed to "1" in a write operation. If data "1" is overwritten, the data pollingalgorithm or toggle operation does not terminate, and the flash memory device is considereddefective. An error is assumed with the time limit over flag if the specified write time isexceeded, or if only data "1" is apparently written, although data "0" is read in read/reset status.Data "0" can be changed to "1" only with an erase operation. All commands are ignored duringautomatic writing. If a hardware reset is activated during writing, the data being written is notguaranteed.

Write procedure

Figure 21.6-1 shows an example of the write procedure.

The status of the automatic algorithm in flash memory can be checked using the hardwaresequence flag. In the example in Figure 21.6-1 , the data polling flag (DPOLL) is used to checkfor termination of the write operation.

Data for the flag check is read from the address where the last data was written.

The data polling flag (DPOLL) changes together with the time limit over flag (TLOVER).Therefore, DPOLL must be rechecked even though TLOVER is set to "1".

The toggle bit flag (TOGGLE) also stops toggling simultaneously when the value of TLOVER ischanged to "1". Therefore, this flag must also be rechecked.

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Figure 21.6-1 Example of Write Procedure (Half-Word Access)

Write command sequence AAAAA AAAA A5555 5555 AAAAA A0A0 Write address write data

Enable writing to flash memory with WE (bit5) in FLCR.

Writing start

Read internal address.

Data polling (DPOLL)

Data

Data

Data

Time limit (TLOVER)

Read internal address.

1

0

Data polling (DPOLL)

Data

Write error Last address

Next address

NO

Disable writing to flash memory with WE (bit5) in FLCR.

Writing completion

Check hardware sequence flag

YES

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21.6.3 Data Erasure (Chip Erasure)

This section explains how to issue Chip Erase commands to erase all items of data in flash memory.

Data Erasure (Chip Erasure)

All items of data can be erased from flash memory by continuously sending Chip Erasecommands (listed in the command sequence table) to target sectors in flash memory.

Six bus operations are necessary to execute a chip erase operation. The operation starts whenthe sixth write cycle is completed. The user need not write any value to flash memory beforechip erase operation. Flash memory automatically writes "0" to erase all cells.

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21.6.4 Data Erasure (Sector Erasure)

This section explains how to issue Sector Erase commands to erase specified sectors in flash memory. Erasure in sector units is possible and two or more sectors can be specified with this command.

Sector Erasure

Specified sectors can be erased from flash memory by continuously sending Sector Erasecommands (listed in the command sequence table) to the sectors.

How to specify sectors

A sector erase operation can be performed with six bus operations. A 50 µs sector erase waitperiod starts when a sector erase code (30H) is written to an even-numbered addressaccessible in the target sector in the sixth cycle. To erase another sector, a sector code (30H)must be written in the same cycle the same way.

Note on specifying two or more sectors

A sector erase operation starts when the 50-µs sector erase wait period terminates after thefinal sector erase code is written. Therefore, when two or more sectors are to be specified, theaddress and erase code of each target sector must be entered within 50 µs (in the sixth cycle ofthe command sequence) after specifying the preceding sector. Note that an address and erasecode not entered within 50 µs may not be accepted. The sector erase timer (hardwaresequence flag: SETIMR) can be used to check the validity of a written sector erase code. Theaddress at which the read sector erase time is written should indicate the target sector.

Sector erase procedure

The hardware sequence flag can be used to check the status of the automatic algorithm in flashmemory.

Figure 21.6-2 shows an example of the sector erase procedure. In this example, the toggle bitflag (TOGGLE) is used to check for termination of the erase operation.

Note that data for the flag check is read from the sector to be erased.

The toggle bit flag (TOGGLE) stops toggling simultaneously when the value of the time limitover flag (TLOVER) changes to "1". Therefore, TOGGLE must be rechecked even thoughTLOVER is set to "1".

Because the data polling flag (DPOLL) also changes with TLOVER, it must also be rechecked.

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Figure 21.6-2 Sector Erase Procedure

Erase command sequence AAAAA A5555 AAAAA A5555 AAAAA

AAAA5555808055551010

Enable erasure in flash memory with WE (bit5) in FLCR.

Enter code (30H) to sector to be erased.

Is there another sector to be erased?

Time limit (TLOVER)

Internal address read 2

1

0

Erasure error Is final sector erased?

Next sector

YES

NO

Disable erasure in flash memory with WE (bit5) in FLCR.

Erase completion

Is value of sector erase timer 1 or 0?

Internal address read

1

0

YES

NO

YES

NO



Toggle bit (TOGGLE) data 1 = data 2?

YES

NO


Toggle bit (TOGGLE) data 1 = data 2?

Erase start

Check with hardware sequence flag

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21.6.5 Temporary Sector Erase Stop

This section explains how to issue Temporary Sector Erase Stop commands to temporarily stop a sector erase operation in flash memory. Data can be read from a sector not being erased by using this command.

Temporary Sector Erase Stop

A sector erase operation in flash memory can be stopped temporarily by continuously sendingTemporary Sector Erase Stop commands (listed in the command sequence table) to the targetsector in flash memory.

Data can be read from a sector being erased by using the Temporary Sector Erase Stopcommand to temporarily stop the erasure. Data can only be read from the sector; data cannotbe written there. This command is only effective during sector erasure that includes an erasewait period. It is ignored during chip erase operation and write operation.

A sector erase operation is stopped temporarily by writing a temporary erase stop code (B0H).The address where the temporary erase stop code is written should indicate an address in flashmemory. A Temporary Sector Erase Stop command issued during temporary erase stop statusis ignored.

If a Temporary Sector Erase Stop command is entered during a sector erase wait period, thesector erase wait is immediately canceled and erase operation in progress is stopped. If aTemporary Sector Erase Stop command is entered during a sector erase operation after thesector erase wait period elapses, sector erase operation is stopped temporarily after up to 15 µselapse.

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21.6.6 Sector Erase Restart

This section explains how to issue Sector Erase Restart commands to restart a temporarily stopped sector erase operation in flash memory.

Sector Erase Restart

A temporarily stopped sector erase operation can be restarted by sending Sector Erase Restartcommands (listed in the command sequence table) to the target sector in flash memory.

The Sector Erase Restart command can restart a sector erase operation that has temporarilybeen stopped with the Temporary Sector Erase Stop command. Restart operation starts whenan erase restart code (30H) is written. The address where the erase restart code is writtenshould indicate an address in flash memory.

Sector Erase Restart commands issued during a sector erase operation are ignored.

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21.7 Restriction and Notes

This section explains the matter that should be noted in using the FLASH memory.

Restriction and Notes

(1) Do not execute the write access for the following area (I-Bus)

0000_0300H to 0000_037FH0000_03E4H to 0000_03E7H0000_8000H to 0000_BFFFH0001_0000H to 0001_FFFFH

(2) Do not execute the write access to the FLASH memory at WE=0 of FMCS register.

(3) Do not execute the continuous write access for the FLASH memory at WE=1 of FMCS register. In this case, be sure to open more than "NOP"1 instruction.

Example) Command write to FLASH (command sequence) => FLASH readIdi #0xAAAA, r0Idi #0x5555, r1Idi #0xAAAAA, r6Idi #0xA5555, r7Idi #0xA0A0, r8Idi #PA, r2Idi #PD, r3

sth r0, @r6nop : Be sure to open more than “NOP”1 instructionsth r1, @r7nop : Be sure to open more than “NOP”1 instructionsth r8, @r6nop : Be sure to open more than “NOP”1 instructionsth r3, @r2nop : Be sure to open more than “NOP”1 instruction

(4) The write access is enabled only the halfword to FLASH memory at the CPU mode. Do notexecute the byte write access.

(5) Do not execute the branch instruction to the FLASH memory area after rewriting the WE,FIXE, BIRE of the FMCS register. When branching to the FLASH area, obey the followingprogram example once the FMCS register value is read.

STB R1, @R2 / / WE=OFFLDUB @R2, R1 / / FMCS value dummy readBRA _flash_address / / Branch to the FLASH memory

(6) The sector protect cannot be used.

(7) Do not guarantee the read value immediately after rewriting to FLASH. Before reading isexecuted after writing, be sure to insert the dummy read.

STH r0, @r1 / / FLASH writeLDUB @r2, r4 / / Dummy readBRA @r3 r4 / / Polling data read

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APPENDIX

This appendix consists of the following parts: the I/O map, interrupt vector, dot clock generation PLL, USB clock, external bus interface setting, and instruction lists. The appendix contains detailed information that could not be included in the main text and reference material for programming.

APPENDIX A I/O Map

APPENDIX B Interrupt Vector

APPENDIX C Dot Clock Generation PLL

APPENDIX D USB Clock

APPENDIX E USB Low-power Consumption Mode

APPENDIX F External Bus Interface Setting

APPENDIX G Pin state list

APPENDIX H INSTRUCTION LISTS

725

APPENDIX A I/O Map

APPENDIX A I/O Map

Table A-1 shows the correspondence between the memory space area and the peripheral resource registers.

I/O Map

[Reading the table]

Note:

The initial value of bits in a register are indicated as follows:

1: Initial value 1

0: Initial value 0

X: Initial value X

-: A physical register does not exist at the location.

block000000H PDR0[R/W] PDR1[R/W] PDR2[R/W] PDR3[R/W] T-unit

XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Port Data Register

Read/write attribute

Initial value of register after reset

Register name (column 1 of the register is at address 4n, column 2 is at address 4n + 2...)Leftmost register address (For word-length access, column 1 of the register becomes the MSB of the data.)

+2 +3+1+0register

address

726

APPENDIX A I/O Map

Table A-1 I/O Map (1 / 12)

AddressRegister

Block+0 +1 +2 +3

000000H|

00000FH

- - - - Reserved

000010HPDR0[R/W]XXXXXXXX

PDR1[R/W]XXXXXXXX

PDR2[R/W]--XXXXXX

PDR3[R/W]-XXXXXX

R-busPort Data Register

000014H PDR4[R/W]XXXXXXXX

PDR5[R/W]XXXXXXXX

PDR6[R/W]--XXXXXX

PDR7[R/W]---XXXXX

000018H - - - -

00001CH - - - -

000020H ADCTH[R/W]XXXXXX00

ADCTL[R/W]00000X00

ADCH[R/W]00000000_00000000

10bit A/D converter

000024H ADAT0[R]XXXXXX00_00000000

ADAT1[R]XXXXXX00_00000000

000028H ADAT2[R]XXXXXX00_00000000


00002CH ADAT4[R]XXXXXX00_00000000


000030H ADAT6[R]XXXXXX00_00000000


000034H ADAT8[R]XXXXXX00_00000000


000038H - - - - Reserved

00003CH - - - -

000040H EIRR [R/W]00000000

ENIR [R/W]00000000

ELVR [R/W]00000000

Ext int

000044H DICR [R/W]-------0

HRCL [R/W]0--11111

- DLYI/I-unit

000048H TMRLR0 [W]XXXXXXXX XXXXXXXX

TMR0 [R]XXXXXXXX XXXXXXXX

Reload Timer 0

00004CH - TMCSR0 [R/W]----0000 00000000



Reload Timer 1

000054H - TMCSR1 [R/W]----0000 00000000

727

APPENDIX A I/O Map



Reload Timer 2

00005CH - TMCSR2 [R/W]----0000 00000000

000060H SSR [R/W]00001-00

SIDR [R/W]XXXXXXXX

SCR [R/W]00000100

SMR [R/W]00--0-0-

UART0

000064H UTIM [R] (UTIMR [W])00000000 00000000

DRCL [W]--------

UTIMC [R/W]0--00001

U-TIMER 0

000068H SSR [R/W]00001-00

SIDR [R/W]XXXXXXXX

SCR [R/W]00000100

SMR [R/W]00--0-0-

UART1

00006CH UTIM [R] (UTIMR [W])00000000 00000000

DRCL [W]--------

UTIMC [R/W]0--00001

U-TIMER 1

000070H SSR [R/W]00001-00

SIDR [R/W]XXXXXXXX

SCR [R/W]00000100

SMR [R/W]00--0-0-

UART2

000074H UTIM [R] (UTIMR [W])00000000 00000000

DRCL [W]--------

UTIMC [R/W]0--00001

U-TIMER 2

000078H SSR [R/W]00001-00

SIDR [R/W]XXXXXXXX

SCR [R/W]00000100

SMR [R/W]00--0-0-

UART3

00007CH UTIM [R] (UTIMR [W])00000000 00000000

DRCL [W]--------

UTIMC [R/W]0--00001

U-TIMER 3

000080H SSR [R/W]00001-00

SIDR [R/W]XXXXXXXX

SCR [R/W]00000100

SMR [R/W]00--0-0-

UART4

000084H UTIM [R] (UTIMR [W])00000000 00000000

DRCL [W]--------

UTIMC [R/W]0--00001

U-TIMER 4

000088H -------- -------- Reserved

00008CH -------- --------

000090H PWCCL[R/W]0000--00

PWCCH[R/W]00-00000

-------- --------

PWC

000094H PWCD[R]XXXXXXXX_XXXXXXXX

-------- --------

000098H PWCC2[R/W]000-----

Reserved -------- --------

00009CH PWCUD[R]XXXXXXXX_XXXXXXXX

-------- --------

0000A0H -------- -------- -------- --------Reserved

0000A4H -------- -------- -------- --------


AddressRegister

Block+0 +1 +2 +3

728

APPENDIX A I/O Map

0000A8H -------- -------- -------- --------Reserved

0000ACH -------- -------- -------- --------

0000B0H - - - -

0000B4H IBCR [R/W]00000000

IBSR [R/W]00000000

ITBA [R/W]------00 00000000

I2C interface ch.0

0000B8H ITMK [R/W]00----11 11111111

ISMK [R/W]01111111

ISBA [R/W]00000000

0000BCH - IDAR [R/W]00000000

ICCR [R/W]0-011111

IDBL [R/W]-------0

0000C0H - - - - Reserved

0000C4H IBCR [R/W]00000000

IBSR [R/W]00000000

ITBA [R/W]------00 00000000

I2C interface ch.1

0000C8H ITMK [R/W]00----11 11111111

ISMK [R/W]01111111

ISBA [R/W]00000000

0000CCH - IDAR [R/W]00000000

ICCR[R/W]0-011111

IDBL [R/W]-------0

0000D0H - - - - Reserved

0000D4H IBCR [R/W]00000000

IBSR [R/W]00000000

ITBA [R/W]------00 00000000

I2C interface ch.2

0000D8H ITMK [R/W]00----11 11111111

ISMK [R/W]01111111

ISBA [R/W]00000000

0000DCH - IDAR [R/W]00000000

ICCR [R/W]0-011111

IDBL [R/W]-------0

0000E0H - - - - Reserved

0000E4H IBCR [R/W]00000000

IBSR [R/W]00000000

ITBA [R/W]------00 00000000

I2C interface ch.3

0000E8H ITMK [R/W]00----11 11111111

ISMK [R/W]01111111

ISBA [R/W]00000000

0000ECH - IDAR [R/W]00000000

ICCR [R/W]0-011111

IDBL [R/W]-------0

0000F0H T0LPCR [R/W]-----000

T0CCR [R/W]0-010000

T0TCR [R/W]00000000

T0R [R/W]---00000

Multi-function timer


AddressRegister

Block+0 +1 +2 +3

729

APPENDIX A I/O Map

0000F4H T0DRR [R/W]XXXXXXXX XXXXXXXX

T0CRR [R/W]XXXXXXXX XXXXXXXX

Multifunction timer

0000F8H T1LPCR [R/W]-----000

T1CCR [R/W]0-000000

T1TCR[R/W]00000000

T1R [R/W]---00000

0000FCH T1DRR [R/W]XXXXXXXX XXXXXXXX


000100H T2LPCR [R/W]-----000

T2CCR [R/W]0-000000

T2TCR [R/W]00000000

T2R [R/W]---00000

000104H T2DRR [R/W]XXXXXXXX XXXXXXXX


000108H T3LPCR [R/W]-----000

T3CCR [R/W]0-000000

T3TCR [R/W]00000000

T3R [R/W]---00000

00010CH T3DRR [R/W]XXXXXXXX XXXXXXXX


000110H - - - - Reserved

000120H PTMR0 [R]11111111_11111111

PCSR0 [W]XXXXXXXX_XXXXXXXX

PPG0

000124H PDUT0 [W]XXXXXXXX_XXXXXXXX

PCNH0 [R/W]00000000

PCNL0 [R/W]00000000

000128H PTMR1 [R]11111111_11111111


PPG1

00012CH PDUT1 [W]XXXXXXXX_XXXXXXXX

PCNH1 [R/W]00000000

PCNL1 [R/W]00000000

000130H PTMR2 [R]11111111_11111111


PPG2

00134H PDUT2 [W]XXXXXXXX_XXXXXXXX

PCNH2 [R/W]00000000

PCNL2 [R/W]00000000

000138H PTMR3 [R]11111111_11111111

PCSR3[W]XXXXXXXX_XXXXXXXX

PPG3

00013CH PDUT3 [W]XXXXXXXX_XXXXXXXX

PCNH3 [R/W]00000000

PCNL3 [R/W]00000000

000140H|

0001FCH

- - - - Reserved


AddressRegister

Block+0 +1 +2 +3

730

APPENDIX A I/O Map

000200H DMACA0 [R/W]00000000 0000XXXX XXXXXXXX XXXXXXXX

DMAC

000204H DMACB4 [R/W]00000000 00000000 00000000 00000000


00020CH DMACB4 [R/W]00000000 00000000 00000000 00000000


000214H DMACB4 [R/W]00000000 00000000 00000000 00000000


00021CH DMACB4 [R/W]00000000 00000000 00000000 00000000


000224H DMACB4 [R/W]00000000 00000000 00000000 00000000

000228H -

00022CH|

00023CH

- Reserved

000240H DMACR [R/W]0XX00000 XXXXXXXX XXXXXXXX XXXXXXXX

DMAC

000244H|

0002FCH

-

000300H|

0003ECH

-


AddressRegister

Block+0 +1 +2 +3

731

APPENDIX A I/O Map

0003F0H BSD0 [W]XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

Bit Search Module

0003F4H BSD1 [R/W]XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

0003F8H BSDC [W]XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

0003FCH BSRR [R]XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000400H DDR0 [R/W]00000000

DDR1 [R/W]00000000

DDR2 [R/W]--000000

DDR3 [R/W]-0000000

R-bus Port Direction Register

000404H DDR4 [R/W]00000000

DDR5 [R/W]00000000

DDR6 [R/W]--000000

DDR7 [R/W]---00000

000408H - - - -

00040CH - - - -

000410H PFR0 [R/W]0--00000

PFR1 [R/W]00000000

PFR2 [R/W]000---00

PFR3 [R/W]00000000

R-busPort Function Register

000414H - - - -

000418H - - - -

00041CH - - - -

000420H|

00043CH

- Reserved


AddressRegister

Block+0 +1 +2 +3

732

Changed Table A-1. (Address:000414H Deleted PFR4 Register.)

APPENDIX A I/O Map

000440H ICR00 [R/W]---11111

ICR01 [R/W]---11111

ICR02[R/W]---11111

ICR03 [R/W]---11111

Interrupt Control unit

000444H ICR04 [R/W]---11111

ICR05 [R/W]---11111

ICR06 [R/W]---11111

ICR07 [R/W]---11111

000448H ICR08 [R/W]---11111

ICR09 [R/W]---11111

ICR10 [R/W]---11111

ICR11 [R/W]---11111

00044CH ICR12 [R/W]---11111

ICR13 [R/W]---11111

ICR14 [R/W]---11111

ICR15 [R/W]---11111

000450H ICR16 [R/W]---11111

ICR17 [R/W]---11111

ICR18 [R/W]---11111

ICR19 [R/W]---11111

000454H ICR20 [R/W]---11111

ICR21 [R/W]---11111

ICR22 [R/W]---11111

ICR23 [R/W]---11111

000458H ICR24 [R/W]---11111

ICR25 [R/W]---11111

ICR26 [R/W]---11111

ICR27 [R/W]---11111

00045CH ICR28 [R/W]---11111

ICR29 [R/W]---11111

ICR30 [R/W]---11111

ICR31 [R/W]---11111

000460H ICR32 [R/W]---11111

ICR33 [R/W]---11111

ICR34 [R/W]---11111

ICR35 [R/W]---11111

000464H ICR36 [R/W]---11111

ICR37 [R/W]---11111

ICR38 [R/W]---11111

ICR39 [R/W]---11111

000468H ICR40 [R/W]---11111

ICR41 [R/W]---11111

ICR42 [R/W]---11111

ICR43 [R/W]---11111

00046CH ICR44 [R/W]---11111

ICR45 [R/W]---11111

ICR46 [R/W]---11111

ICR47 [R/W]---11111

000470H|

00047CH

-

000480H RSRR [R/W]10000000 (*2)

STCR [R/W]00110011 (*2)

TBCR [R/W]00XXXX00 (*1)

CTBR [W]XXXXXXXX

Clock Control unit

000484H CLKR [R/W]00000000 (*1)

- DIVR0 [R/W]00000011 (*1)

DIVR1[R/W]00000000 (*1)

000488H OSCCR [R/W]XXXXXXX0

00048CH WPCR [R/W] B00---000

Watch timer

000490H OSCR [R/W] B00---000

Main clock oscillation stabilization wait timer


AddressRegister

Block+0 +1 +2 +3

733

Changed Table A-1. (Address:000485H Deleted the WPR Register.)

APPENDIX A I/O Map

000494H|

0005FCH

- Reserved

000600H - - - - T-unitPort Direction Register000604H - - - -

000608H - - - -

00060CH - - - -

000610H - - - - T-unitPort Function Register000614H - - - -

000618H - - - -

00061CH - - - -

000620H -

000624H -

000628H|

00063FH

- Reserved


AddressRegister

Block+0 +1 +2 +3

734

APPENDIX A I/O Map

000640H ASR0 [R/W]00000000 00000000 (*1)

ACR0 [R/W]1111XX00 00000000 (*1)

T-unit

000644H ASR1 [R/W]XXXXXXXX XXXXXXXX (*1)

ACR1 [R/W]XXXXXXXX XXXXXXXX (*1)



00064CH ASR3 [R/W]XXXXXXXX XXXXXXXX (*1)








00065CH ASR7 [R/W]XXXXXXXX XXXXXXXX (*1)


000660H AWR0 [R/W]01111111 111111111 (*1)

AWR1 [R/W]XXXXXXXX XXXXXXXX (*1)

000664H AWR2 [R/W]XXXXXXXX XXXXXXXX (*1)


000668H AWR4 [R/W]XXXXXXXX XXXXXXXX (*1)


00066CH AWR6 [R/W]XXXXXXXX XXXXXXXX (*1)


T-unit

000670H -

000674H -

000678H IOWR0 [R/W]XXXXXXXX

IOWR1 [R/W]XXXXXXXX

IOWR2 [R/W]XXXXXXXX

-

00067CH -

000680H CSER [R/W]00000001

CSHR [R/W]11111111

- TCR [R/W]00000000

000684H -

000684H|

0007F8H

- Reserved

0007FCH - MODR [W]XXXXXXXX

- -


AddressRegister

Block+0 +1 +2 +3

735

APPENDIX A I/O Map

000800H|

000AFCH

- Reserved

000B00H ESTS0 [R/W]X0000000

ESTS1 [R/W]XXXXXXXX

ESTS2 [R]1XXXXXXX

- DSU

000B04H ECTL0 [R/W]0X000000

ECTL1 [R/W]00000000

ECTL2 [W]000X0000

ECTL3 [R/W]00X00X11

000B08H ECNT0 [W]XXXXXXXX

ECNT1 [W]XXXXXXXX

EUSA [W]XXX00000

EDTC [W]0000XXXX

000B0CH EWP1 [R]00000000 00000000

-

000B10H EDTR0 [W]XXXXXXXX XXXXXXXX

EDTR1 [W]XXXXXXXX XXXXXXXX

000B14H|

000B1CH

-

000B20H EIAC [W]XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B24H EIA1 [W]XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX


AddressRegister

Block+0 +1 +2 +3

736

APPENDIX A I/O Map


DSU

000B2CH EIA3 [W]XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX




000B3CH EIA7 [W]XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B40H EDTA [R/W]XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B44H EDTM [R/W]XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B48H EOAC [W]XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B4CH EOA1 [W]XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B50H EPCR [R/W]XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B54H EPSR [R/W]XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B58H EIAM0 [W]XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B5CH EIAM1 [W]XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B60H EOAM0/EODM0 [W]XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B64H EOAM1/EODM1 [W]XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B68H EODC [W]XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B6CH EOD1 [W]XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

000B70H|

000FFCH

- Reserved


AddressRegister

Block+0 +1 +2 +3

737

APPENDIX A I/O Map

001000H DMASA0 [R/W]XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX

DMAC

001004H DMADA0 [R/W]XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX


00100CH DMADA1 [R/W]XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX




00101CH DMADA3 [R/W]XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX



001028H|

006FFCH

- Reserved

007000H FLCR [R/W]0110_X000

- Program FLASH I/F

007004H FLWC [R/W]0001_0011

-

007008H|

00707CH

- Reserved

007080H|

0070FCH

Reserved

007100H FNCR [R/W]0110_X000

- FONT FLASH I/F

007104H FNWC [R/W]0001_0011

-

*1: Register whose initial value depends on the reset level. The registers at the INIT level are indicated.*2: Register whose initial value depends on the reset level. The registers at the INIT level due to the INIT pin

are indicated.


AddressRegister

Block+0 +1 +2 +3

738

APPENDIX A I/O Map

Table A-2 I/OMap (1 / 5)

AddressRegister

Block+0 +1 +2 +3

00050000H HR (HcRevision) [R]00000000_00000000_00000001_00010000

USBHost

00050004H HC (HcControl) [R/W]00000000_00000000_00000000_00000000

00050008H HCS (HcCommandStatus) [R/W]00000000_00000000_00000000_00000000

0005000CH HIS (HcInterruptStatus) [R/W]00000000_00000000_00000000_00000000

00050010H HIE (HcInterruptEnable) [R/W]00000000_00000000_00000000_00000000

00050014H HID (HcInterruptDisable) [R/W]00000000_00000000_00000000_00000000

00050018H HHCCA (HcHCCA) [R/W]00000000_00000000_00000000_00000000

0005000CH HPCED (HcPeriodCurrentED) [R/W]00000000_00000000_00000000_00000000

00050020H HCHED (HcControlHeadED) [R/W]00000000_00000000_00000000_00000000

00050024H HCCED (HcControlCurrentED) [R/W]00000000_00000000_00000000_00000000

00050028H HBHED (HcBulkHeadED) [R/W]00000000_00000000_00000000_00000000

0005002CH HBCED (HcBulkCurrentED) [R/W]00000000_00000000_00000000_00000000

00050030H HDH (HcDoneHead) [R/W]00000000_00000000_00000000_00000000

00050034H HFI (HcFmInterval) [R/W]00000000_00000000_00101110_11011111

00050038H HFR (HcFmRemeining) [R]00000000_00000000_00000000_00000000

0005003CH HFN (HcFmNumber) [R]00000000_00000000_00000000_00000000

00050040H HPS (HcPeriodicStart) [R/W]00000000_00000000_00000000_00000000

00050044H HLST (HcLSThreshold) [R/W]00000000_00000000_00000110_00101000

00050048H HRDA (HcRhDescriptorA) [R/W]00000001_00000000_00000000_00000010

0005004CH HRDB (HcRhDescriptorB) [R/W]00000000_00000000_00000000_00000000

739

APPENDIX A I/O Map

00050050H HRS (HcRhStatus) [R/W]00000000_00000000_00000000_000000X0

USBHost

00050054H HRPS1 (HcRhPortStatus[1]) [R/W]00000000_00000000_00000000_00000X00

00050058H HRPS2 (HcRhPortStatus[2]) [R/W]00000000_00000000_00000000_00000X00

0005005CH|

00057FFFH

-

RESERVED

00058000H|

00059FFFH

SRAM 8KB

0005A000H|

0005FFFFH

-

RESERVED


AddressRegister

Block+0 +1 +2 +3

740

APPENDIX A I/O Map

00060000H FIFO0o [R]XXXXXXXX_XXXXXXXX

FIFO0i [W]XXXXXXXX_XXXXXXXX

USBFunction

00060004H FIFO1 [R]XXXXXXXX_XXXXXXXX

FIFO2 [W]XXXXXXXX_XXXXXXXX

00060008H FIFO3 [R]XXXXXXXX_XXXXXXXX

-

0006000CH|

0006001FH

--------

RESERVED

00060020H -RESERVED

CONT1 [R/W]000XX0XX_XXX00000

00060024H CONT2 [R/W]XXXXXXXX_XXX00000

CONT3 [R/W]XXXXXXXX_XXX00000


CONT5 [R/W]XXXXXXXX_XXXX00XX

0006002CH CONT6 [R/W]XXXXXXXX_XXXX00XX

CONT7 [R/W]XXXXXXXX_XXX00000


CONT9 [R/W]0XX0XXXX_0XXX0000

00060034H CONT10 [R/W]0XXX000X_X000000X

TTSIZE [R/W]00010001_00010001

00060038H TRSIZE [R/W]00010001_00010001

-RESERVED

0006003CH --------RESERVED


AddressRegister

Block+0 +1 +2 +3

741

APPENDIX A I/O Map

00060040H RSIZE0 [R]XXXXXXXX_XXXX0000

-RESERVED

USBFunction

00060044H RSIZE1 [R]XXXXXXXX_X0000000

-RESERVED

00060048H|

0006005FH

--------

RESERVED

00060060H -RESERVED

ST1 [R/W]XXXXXX00_00000000

00060064H --------RESERVED

00060068H ST2 [R]XXXXXXXX_XXX00000

ST3 [R/W]00XXXXXX_XXX00000

0006006CH ST4 [R/W]XXXXX000_00000000

ST5 [R/W]0XX00XXX_XX000000

00060070H|

0006FFFBH

--------

RESERVED

0006FFFCH USBIO--------

- RESET000-0---

-

00070000H|

0007FFFFH

--------

RESERVED

RESERVED

00078000H OSD_VADR [R/W]XXXXXXXX_XXXXXXXX

OSD_CD1 [R/W]XXXXXXXX_XXXXXXXX

OSDC

00078004H OSD_CD2 [R/W]XXXXXXXX_XXXXXXXX

OSD_RCD1 [R/W]XXXXXXXX_XXXXXXXX

00078008H OSD_RCD2 [R/W]XXXXXXXX_XXXXXXXX

OSD_SOC1 [R/W]XXXXXXXX_0000XXXX

0007800CH OSD_SOC2 [R/W]XXXXXXXX_XXXXXXXX

OSD_VDPC [R/W]XXXXXXXX_XXXXXXXX

00078010H OSD_HDPC [R/W]XXXXXXXX_XXXXXXXX

OSD_CVSC [R/W]XXXXXXXX_XXXXXXXX

00078014H OSD_SBFCC [R/W]XXXXXXXX_XXXXXXXX

OSD_THCC [R/W]XXXXXXXX_XXXXXXXX

00078018H OSD_GFCC [R/W]XXXXXXXX_XXXXXXXX

OSD_SBCC1 [R/W]XXXXXXXX_XXXXXXXX

0007801CH OSD_SBCC2 [R/W]XXXXXXXX_XXXXXXXX

OSD_SPCC1 [R/W]XXXXXXXX_XXXXXXXX


AddressRegister

Block+0 +1 +2 +3

742

Changed Table A-2. (Address:00060070H - 0006007DH → 00060070H - 0006FFFBH, Address:0006007EH → 0006FFFCH, Address:00060080H - 0007FFFFH → 00070000H - 0007FFFFH, Address:0006FFFCH Added the USBIO register.)

APPENDIX A I/O Map

00078020H OSD_SPCC2 [R/W]XXXXXXXX_XXXXXXXX

OSD_SPCC3 [R/W]XXXXXXXX_XXXXXXXX

OSDC

00078024H OSD_SPCC4 [R/W]XXXXXXXX_XXXXXXXX

OSD_SYNCC [R/W]XXXXXXXX_XXXXXXXX

00078028H OSD_DCLKC1 [R/W]XXXXXXXX_XXXXXXXX

OSD_DCLKC2 [R/W]XXXXXXXX_XXXXXXXX

0007802CH OSD_DCLKC3 [R/W]XXXXXXXX_XXXXXXXX

OSD_IOC1 [R/W]XXXXXXXX_XXXXXXXX

00078030H OSD_IOC2 [R/W]XXXXXXXX_XXXXXXXX

OSD_DPC1 [R/W]XXXXXXXX_XXXXXXXX

00078034H OSD_DPC2 [R/W]XXXXXXXX_XXXXXXXX

OSD_DPC3 [R/W]XXXXXXXX_XXXXXXXX

00078038H OSD_DPC4 [R/W]XXXXXXXX_XXXXXXXX

OSD_IRC [R/W]XXXXXXXX_XXXXXXXX

0007803CH OSD_PLT0 [R/W]XXXXXXXX_XXXXXXXX

OSD_PLT1 [R/W]XXXXXXXX_XXXXXXXX

00078040H OSD_PLT2 [R/W]XXXXXXXX_XXXXXXXX






0007804CH OSD_PLT8 [R/W]XXXXXXXX_XXXXXXXX








0007805CH OSD_ACT1 [R/W]XXXXXXXX_XXXXXXXX

OSD_ACT2 [R/W]XXXXXXXX_XXXXXXXX

00078060H|

0007FFFFH

--------

RESERVED

RESERVED


AddressRegister

Block+0 +1 +2 +3

743



Table B-1 shows the interrupt vector table, which gives the interrupt sources and interrupt vector/interrupt control register allocations for the MB91310.

Interrupt Vectors

Table B-1 Interrupt Vectors (1 / 4)

Interrupt sourceInterrupt number Interrupt

levelOffset

TBR default address


Reset 0 00 − 3FCH 000FFFFCH −

Mode vector 1 01 − 3F8H 000FFFF8H −



Reserved for system 4 04 − 3ECH 000FFFECH −



No-coprocessor trap 7 07 − 3E0H 000FFFE0H −

Coprocessor error trap 8 08 − 3DCH 000FFFDCH −

INTE instruction 9 09 − 3D8H 000FFFD8H −

Instruction break exception 10 0A − 3D4H 000FFFD4H −

Operand break trap 11 0B − 3D0H 000FFFD0H −

Step trace trap 12 0C − 3CCH 000FFFCCH −

NMI request (tool) 13 0D − 3C8H 000FFFC8H −

Undefined instruction exception 14 0E − 3C4H 000FFFC4H −

NMI request 15 0F15(FH),

fixed3C0H 000FFFC0H −

External Interrupt 0 16 10 ICR00 3BCH 000FFFBCH 6




External interrupt 4 (USB-function)

20 14 ICR04 3ACH 000FFFACH −

External interrupt 5 (USB-Host) 21 15 ICR05 3A8H 000FFFA8H −

744

Changed Table B-1. (Changed the RN of External interrupt 4 (USB-function), External interrupt 5 (USB-Host), PPG0, PPG1, and PPG2.)


External interrupt 6 (OSDC) 22 16 ICR06 3A4H 000FFFA4H −

External interrupt 7 23 17 ICR07 3A0H 000FFFA0H −

Reload Timer 0 24 18 ICR08 39CH 000FFF9CH 8

Reload Timer 1 25 19 ICR09 398H 000FFF98H 9

Reload Timer 2 26 1A ICR10 394H 000FFF94H 10

UART0 (reception completed) 27 1B ICR11 390H 000FFF90H 0

UART1 (reception completed) 28 1C ICR12 38CH 000FFF8CH 1

UART2 (reception completed) 29 1D ICR13 388H 000FFF88H 2

UART0 (transmission completed)

30 1E ICR14 384H 000FFF84H 3


31 1F ICR15 380H 000FFF80H 4


32 20 ICR16 37CH 000FFF7CH 5

DMAC0 (end or error) 33 21 ICR17 378H 000FFF78H -

DMAC1 (end or error) 34 22 ICR18 374H 000FFF74H −


DMAC3 (end or error) 36 24 ICR20 36CH 000FFF6CH −


A/D 38 26 ICR22 364H 000FFF64H −

PPG0 39 27 ICR23 360H 000FFF60H 13

PPG1 40 28 ICR24 35CH 000FFF5CH 14

PPG2 41 29 ICR25 358H 000FFF58H 15

PPG3 42 2A ICR26 354H 000FFF54H −

PWC 43 2B ICR27 350H 000FFF50H −

Reserved for system 44 2C ICR28 34CH 000FFF4CH −

Reserved for system 45 2D ICR29 348H 000FFF48H −

Main clock oscillation wait 46 2E ICR30 344H 000FFF44H −

Time-base timer overflow 47 2F ICR31 340H 000FFF40H −

Reserved for system 48 30 ICR32 33CH 000FFF3CH −

Clock timer 49 31 ICR33 338H 000FFF38H −

I2C ch.0 50 32 ICR34 334H 000FFF34H −



levelOffset

TBR default address


745

Changed Table B-1. (Changed the RN of External interrupt 4 (USB-function), External interrupt 5 (USB-Host), PPG0, PPG1, and PPG2.)


I2C ch.1 51 33 ICR35 330H 000FFF30H −

I2C ch.2 52 34 ICR36 32CH 000FFF2CH −

I2C ch.3 53 35 ICR37 328H 000FFF28H −




56 38 ICR40 31CH 000FFF1CH −


57 39 ICR41 318H 000FFF18H −

Multifunction timer 0 58 3A ICR42 314H 000FFF14H −

Multifunction timer 1 59 3B ICR43 310H 000FFF10H −

Multifunction timer 2 60 3C ICR44 30CH 000FFF0CH −

Multifunction timer 3 61 3D ICR45 308H 000FFF08H −

Reserved for system 62 3E ICR46 304H 000FFF04H −

Delayed interrupt source bit 63 3F ICR47 300H 000FFF00H −

Reserved for system (used by REALOS*1)

64 40 − 2FCH 000FFEFCH −

Reserved for system (used by REALOS*1)

65 41 − 2F8H 000FFEF8H −



Reserved for system 68 44 − 2ECH 000FFEECH −




Reserved for system 72 48 − 2DCH 000FFEDCH −

Reserved for system 73 49 − 2D8H 000FFED8H −

Reserved for system 74 4A − 2D4H 000FFED4H −

Reserved for system 75 4B − 2D0H 000FFED0H −

Reserved for system 76 4C − 2CCH 000FFECCH −

Reserved for system 77 4D − 2C8H 000FFEC8H −

Reserved for system 78 4E − 2C4H 000FFEC4H −

Reserved for system 79 4F − 2C0H 000FFEC0H −



levelOffset

TBR default address


746


Used in INT instruction 80|

255

50|

FF

− 2BCH|

0000H

000FFEBCH|

00FFC00H

−



levelOffset

TBR default address


747



The built-in dot clock generation PLL requires that the LPF be connected to the CPO pin as shown in Figure C-1 .

Dot Clock Generation PLL

The built-in dot clock generation PLL should connect LPF like the figure below with the CPOpin.

Figure C-1 CPO Pin Connection

The LPF constant depends on the oscillation frequency. Contact Fujitsu for the recommendedvalue of the LPF constant.

Table C-1 shows examples of recommended values.

Dot Clock

When the OSDC macro is unused, inputs “0” level to the DCKO pin.

R

C1 C2

CPO

Table C-1 Examples of Recommended Values of LPF Constant

HSYNC (KHz)

Division ratio PLL (MHz)

Output clock (MHz)

VCO CHG[1:0]

External LPF

n m R (Ω) C1 (µF) C2 (pF)

15.75 1204 2 37.93 18.96 VCO1 10 915 0.22 None

31.5 1304 1 41.08 41.08 VCO2 10 915 0.22 None

33.75 1320 1 44.55 44.55 VCO2 10 915 0.22 None

45 1404 1 63.18 63.18 VCO3 10 2K 0.068 2700

48 1428 1 68.54 68.54 VCO3 10 2K 0.068 2700

748



The USB clock is obtained from an external 48 MHz crystal oscillator or an external 48 MHz clock input.

USB Clock

The external crystal oscillator for the USB clock is controlled in the same way as the CPUcrystal oscillator. That is, the external crystal oscillator is stopped in the following modes:

• Stop mode of main clock mode

• Sub clock mode

At transition to and return from the above mode, the USB host macro may cause a "CLOCKPULSE WIDTH ERROR" because the USB clock is not stable. To avoid this problem, set thesoftware reset generation register of the USB host macro to reset the USB host before transitionto the above mode.

Also, when the USB macro is unused, inputs "0" level to the X0B pin.

Figure D-1 shows the USB clock configuration.

Figure D-1 USB Clock Configuration

• OVRCUR

This signal is transferred to the over-current detection port of the USB host.

• USB-F-RST

Reset signal for USB function. Writing "1" to this bit resets the signal, and writing "0" clearsthe signal.

• USB-H-RST

Reset signal for the USB host. Writing "1" to this bit resets the signal, and writing "0" clearsthe signal.

• OSD-RST

Reset signal for the OSDC. Writing "1" to this bit resets the signal, and writing "0" clears thesignal.

7 6 5 4 3 2 1 0

0x0006FFFF OVRCURUSB-F-

RSTUSB-H-

RSTOSD-RST

CS2X area

Initial value- - -0 0 0 - 0

bit

749


Note:

When the USB host and the OSDC is set the corresponding reset bit to "1", the register accessis performed. The CPU is stopped (the external interface is used the RDY enabled) because therespond is not returned.

Also, the CPU is stopped when the clock is not supplied to the USB host and the OSDC.

Accessing to the USB host and the OSDC is used as follow.

• The state which the corresponding reset bit is cleared "0".

• The state which the corresponding clock is supplied.

750



The USB IO of MB91310 series are integrated the low-power consumption mode for the unused USB. Low-power consumption mode is used to set the low-power consumption mode register as follow.

Low-Power Consumption Mode Setting Register

Using way: When writing the data 0x55 at 0x0006FFFC, the USB IO is enabled to transit to thelow-power consumption mode. The initial value of this register is 0x00 when theUSB operation is required to 0x00. Returning from the low-power consumptionmode, be sure to write 0x00 at 0x0006FFFC before the USB operation is started.

7 0

0x0006FFFC

CS2X area

Initial value 0x00 / Write Only

bit

751



This section explains the register settings and recommended setting examples for accessing the macros of the items connected via the external bus interface.

External Bus Interface Setting

The MB91310 has a USB host, USB function, and OSDC connected via the external businterface in the chip.

To access these macros, set the registers of the external bus interface as follows:

CS0 area: Default area (unused)

After reset is canceled, the entire 4 GB CS0 area is indicated. Set the CS0 area in an area thatdoes not overlap other chip select area.

An example of an area that can be set is the area after 0x0020_0000.

CS1 area

The USB host and USB host memory are connected to the CS1 area.

Because the USB host is a 32-bit macro and operates at the little endian that requires anexternal ready, DBW is set to 10 (32 bits), TYP is set to 0001 (external ready), LEND is set to"1" (little endian), and automatic wait (W15 to W12) is set to 01 (1 wait).

In addition to the above, an asynchronous write strobe (W03), write recovery cycle (W05, W04),and read/write idle cycle (W07, W06) are set.

The address is set to the minimum area size of 64 KB starting from 0x0005_0000.

CS2 area

The USB function is connected to the CS2 area.

The USB function is a 16-bit macro. DBW is set to 01 (16 bits), TYP is set to 0000 (no externalready), and automatic wait is set to 02 (2 wait).


CS3 area

The OSDC are connected to the CS3 area.

The memory stick interface and OSDC are 16-bit macros. The OSDC macro requires anexternal ready. DBW is set to 01 (16 bits), TYP is set to 0001 (external ready), and automaticwait is set to 00 (0 wait).


752

Changed " CS2 area".


Recommended Setting Examples

Figure F-1 shows recommended setting examples for the registers of the external bus interface.

Figure F-1 Recommended setting examples for the registers of the external bus interface.

// **start initial header program

//CS0X :

// CS1X : USB-Host(32bit)

// CS2X : USB-Func (16bit)

// CS3X : MemoryStick/OSDC(16bit)

not useldi

ldisthldildi

sthldildisth

ldi

ldisthldildisthldildi

sth

ldi

ldisthldildisthldildi

sth

ldi

ldisthldildisthldilsi

sth

ldildistb

#0x5400,r3

#_ACR0,r4r3,@r4#_AWR0,r6#0x0098,r5

r5,@6#_ASR0,r7#0x0020,r5r5,@r7

#0x0821,r3

#_ACR1,r8r3,@r8#0x0005,r3#_ASR 1, r9r3,@r9#_AWR1,r4#0x1098,r5

r5,@r4

#0x0420,r3

#_ACR2,r8r3,@r8#0x0006,r3#_ASR2,r9r3,@r9#_AWR2,r4#0x200D,r5

r5,@r4

#0x0421.r3

#_ACR3,r8r3,@r8#0x0007,r3#_ASR3,r9r3,@r9#_AWR3,r4#0x0098,r5

r5,@r4

#=CSER,r0#0x0f,r1 // CS0X, CS1X, CS2X, CS3X enabler1,@r0

// ASZ[3:0]=0101,DBW[1:0]=01,BST[1:0]=00,// SREN=0,PFEN=0,WREN=0,LEND=0,TYP[3:0]=0000// ACR0 for CS0X area access mode// set bus-width & area size// AWR0 for CS0X area access wait// W02 =0: CS delay = 0// W01 =1: RE delay = 1// W05,04=01: WR,WR delay = 0// W07,06=10: RD, WR delay = 2// W15-12=0000: auto wait = 0// set bus-wait// ASR0 for CS0X area base address// set CS0X 0x0020_0000 - 0x003f_ffff

// ASZ[3:0]=0000,DBW[1:0]=10,BST[1:0]=00,// SREN=0,PFEN=0,WREN=1,LEND=0,TYP[3:0]=0001

// CS1X 0x0005_0000-0x0005_ffff

// AWR1 for CS1X area access wait// W02 =0: CS delay = 0// W01 =1: RD delay = 1// W05,04=01: WR, WR delay = 0// W07,06=10: RD, WR delay = 2// W15-12=0001: auto wait = 1// set bus-wait

// ASZ[3:0] = 0000,DBW[1:0]=01,BST[1:0]=00,// SREN=0,PFEN=0,WREN=1,LEND=0,TYP[3:0]=0000

// CS2X 0x0006_0000-0x0006_ffff

// AWR2 for CX1X area access wait// W02 =0: CS delay = 0// W01 =1: RD delay = 1// W5,04=00: WR, WR delay = 0// W07,06=10: RD,WR delay = 0// W15-12=0010: auto wait = 2// set bus-wait

// ASZ[3:0]=0000,DBW[1:0]=01,BST[1:0]=00,// SREN=0,PFEN=0,WREN=1,LEND=0,TYP[3:0]=0001

// CS3X 0x0007_0000-0x0007_ffff

// AWR3 for CS3X area access wait// W02 = 0: CS delay = 0// W01 =1: RD delay = 1// W05,04=01: WR,WR delay = 0// W07,06=10: RD,WR delay = 2// W15-12=0000: auto wait = 0// set bus-wait

753

Changed Figure F-1.

Changed Figure F-1.

Changed Figure F-1.



Table G-1 shows the pin state list.

Pin state list

Table G-1 Pin state list (1 / 2)

Pin name Specified function name

Function name

Initial valueSLEEP

STOPRemarks

at INIT=L at INIT=H HZ=0 HZ=1

1 DOCKI − DOCKI Input state Input state Input state Input state Input state2 FH − FH

“L” output “L” outputPrevious state

maintainedPrevious state

maintainedPrevious state

maintained3 VSYNC − VSYNC Input state Input state Input state Input state Input state4 HSYNC − HSYNC

Hi-Z output/input enabled


Previous state maintained



36 P00 SCL0 P0037 P01 SDA0 P0138 P02 SCL1 P0239 P03 SDA1 P0346 P04 SCL2 P0447 P05 SDA2 P0548 P06 SCL3 P0649 P07 SCL4 P0750 P10 SDA3 P1051 P11 SDA4 P1152 P12 SI0 P1253 P13 SO0 P1354 P14 SCK0 P1455 P15 SI1 P1556 P16 SO1 P1657 P17 SCK1 P1758 P20 SI2 P2059 P21 SO2 P2160 P22 SCK2 P2261 P23 SI3 P2362 P24 SO3 P2463 P25 SCK3 P2564 P30 SI4/TIN0 P3065 P31 SO4/TIN1 P3166 P32 SCK4/TIN2 P3267 P33 TO0 P3368 P34 TO1 P3469 P35 TO2 P3570 P36 RIN P3671 P40 TMO0 P4072 P41 TMO1 P4173 P42 TMO2 P4274 P43 TMO3 P4380 P44 PPG0 P4481 P45 PPG1 P4582 P46 PPG2 P4683 P47 PPG3 P4788 P50 TMI0 P5089 P51 TMI1 P5190 P52 TMI2 P5291 P53 TMI3 P5392 P54 TRG0 P5493 P55 TRG1 P5594 P56 TRG2 P5695 P57 TRG3 P5796 P60 PORT0/ATRG P6097 P61 PORT1 P6198 P62 INT0 P62

P: Previous state maintainedF: Input enabled

P: Hi-Z outputF: Input enabled

99 P63 INT1 P63100 P64 INT2 P64101 P65 INT3 P65102 NMI − NMI Input state Input state Input state Input state Input state

754


109 ICS0 − ICS0





Hi-Z output/input fixed

The open pin in MB91F312

110 ICS1 − ICS1111 ICS2 − ICS2112 ICD0 − ICD0113 ICD1 − ICD1114 ICD2 − ICD2115 ICD3 − ICD3116 P70 − P70117 P71 − P71118 P72 − P72119 P73 − P73120 P74 − P74126 UDM − UDM


127 UDP − UDP128 UHM − UHM

Output “L” Output “L”

129 UHP − UHP130 B0 − B0131 B1 − B1132 B2 − B2133 G0 − G0134 G1 − G1135 G2 − G2136 R0 − R0137 R1 − R1138 R2 − R2142 VOB2 − VOB2143 VOB1 − VOB1144 DCKO − DCKO

Table G-1 Pin state list (2 / 2)

Pin name Specified function name

Function name

Initial valueSLEEP

STOPRemarks

at INIT=L at INIT=H HZ=0 HZ=1

755



This section provides lists of the FR family instructions.Before the lists are presented, the following items are explained to make the lists easier to understand:• How to read the instruction lists• Addressing mode symbols• Instruction format

How to Read the Instruction Lists

1. Instruction name.

• An asterisk (*) indicates an extended instruction that is not contained in the CPU specifications

and is obtained by extension of or addition of the instruction with the assembler.

2. Symbols indicating addressing modes that can be specified for the operand.

• For the meaning of symbols, see " Addressing Mode Symbols".

3. Instruction format.

4. Instruction code in hexadecimal notation.

Mnemonic Type OP CYCLE NZVC Operation Remarks

ADD*ADD

Rj, Rj#s5, Rj

,,

AC,,

AGA4,,

11,,

CCCCCCCC

,,

Ri + Rj --> RjRi + s5 --> Ri

,,

↓1.

↓2.

↓3.

↓4.

↓5.

↓6.

↓7.

Code: CM71-00103-1E

756


5. Number of instruction execution cycles.

• a: Memory access cycle that may be extended by the Ready function.

• b: Memory access cycle that may be extended by the Ready function. However, the cycle is

interlocked if a next instruction references a register intended for an LD operation, increasing

the number of execution cycles by 1.

• c: Interlocked if the next instruction is an instruction that reads or writes to R15, SSP, or USP, or

an instruction in instruction format A. The number of execution cycles increases by 1 to

become 2.

• d: Interlocked if the next instruction references MDH/MDL. The number of execution cycles

increases to 2.

Always interlocked, when the special register (TBR, RP, USP, SSP, MDH, and MDL) is accessed

by ST Rs, or @R15 instruction immediately after the DIV1 instruction. The number of

execution cycles increases to 2.

• The minimum cycle for a, b, c, and d is 1.

6. Indicates a flag change.

7. Instruction operation.

Flag change Flag meaning

C: Change N: Negative flag

- : No change Z: Zero flag

0: Clear V: Overflow flag

1: Set C: Carry flag

757


Addressing Mode Symbols

Table H-1 Explanation of Addressing Mode Symbols (1/2)

Symbol Meaning

Ri Register direct (R0 to R15, AC, FP, SP)

Rj Register direct (R0 to R15, AC, FP, SP)

R13 Register direct (R13, AC)

PS Register direct (program status register)

Rs Register direct (TBR, RP, SSP, USP, MDH, MDL)

CRi Register direct (CR0 to CR15)

CRj Register direct (CR0 to CR15)

#i4 Unsigned 4-bit immediate data(0 to 15 or -16 to -1 depending on types of instruction)

#i8 Unsigned 8-bit immediate data (-128 to 255)Note: -128 to -1 are handled as 128 to 255.

#i20 Unsigned 20-bit immediate data (-0x80000 to 0xFFFFF)Note: -0x7FFFF to -1 are handled as 0x7FFFF to 0xFFFFF.

#i32 Unsigned 32-bit immediate data (-0X80000000 to 0XFFFFFFFF)Note: -0x80000000 to -1 are handled as 0x80000000 to 0xFFFFFFFF.

#s5 Signed 5-bit immediate data (-16 to 15)

#s10 Signed 10-bit immediate data (-512 to 508, multiples of 4 only)

#u4 Unsigned 4-bit immediate data (0 to 15)



#u10 Unsigned 10-bit immediate data (0 to 1020, multiples of 4 only)

@dir8 Unsigned 8-bit direct address (0 to 0xFF)

@dir9 Unsigned 9-bit direct address (0 to 0x1FE, multiple of 2 only)

@dir10 Unsigned 10-bit direct address (0 to 0x3FC, multiples of 4 only)

label9 Signed 9-bit branch address (-0x100 to 0xFC, multiples of 2 only)

label12 Signed 12-bit branch address (-0x800 to 0x7FC, multiples of 2 only)

label20 Signed 20-bit branch address (-0x80000 to 0x7FFFF)

label32 Signed 32-bit branch address (-0x80000000 to 0x7FFFFFFF)

@Ri Register indirect (R0 to R15, AC, FP, SP)

@Rj Register indirect (R0 to R15, AC, FP, SP)

@(R13,Rj) Register relative indirect (Rj: R0 to R15, AC, FP, SP)

@(R14,disp10) Register relative indirect (disp10: -0x200 to 0x1FC, multiples of 4 only)

758


• extu()....... indicates a zero extension operation, in which values lacking high-order bits are

complemented by adding "0" as necessary.

• extn()....... indicates a minus extension operation, in which values lacking high-order bits are

complemented by adding "1" as necessary.

• exts() ....... indicates a sign extension operation in which a zero extension is performed for the data

within ( ) in which the MSB is "0" and a minus extension is performed for the data in which

the MSB is "1".

@(R14,disp9) Register relative indirect (disp9: -0x100 to 0xFE, multiples of 2 only)

@(R14,disp8) Register relative indirect (disp8: -0x80 to 0x7F)

@(R15,udisp6) Register relative indirect (udisp6: 0 to 60, multiples of 4 only)

@Ri+ Register indirect with post-increment (R0 to R15, AC, FP, SP)

@R13+ Register indirect with post-increment (R13, AC)

@SP+ Stack pop

@-SP Stack push

(reglist) Register list

Table H-1 Explanation of Addressing Mode Symbols (1/2)

Symbol Meaning

759


Instruction Format

Table H-2 Instruction Format

Type Instruction format

A

B

C

*C’

ADD, ADDN, CMP, LSL, LSR, ASR instructions only

D

E

F

MSB LSB16 bits

OP Rj Ri

8 4 4

OP i8/o8 Ri

4 8 4

OP u4/m4/i4 Ri

8 4 4

OP s5/u5 Ri

7 5 4

OPu8/rel8/dir/

reglist

8 8

OP SUB-OP Ri

8 4 4

OP rel11

5 11

760


H.1 FR Family Instruction Lists

The FR family instruction lists are presented in the order listed below.

FR Family Instruction ListsTable H-3 Add-Subtract Instructions

Table H-4 Compare Operation Instructions

Table H-5 Logic Operation Instructions

Table H-6 Bit Manipulation Instructions

Table H-7 Multiply/Divide Instructions

Table H-8 Shift Instructions

Table H-9 Immediate Set/16-bit/32-bit Immediate Transfer Instructions

Table H-10 Memory Load Instructions

Table H-11 Memory Store Instructions

Table H-12 Register-to-Register Transfer Instructions

Table H-13 Normal Branch (No Delay) Instructions

Table H-14 Delayed Branch Instructions

Table H-15 Other Instructions

Table H-16 20-Bit Normal Branch Macro Instructions

Table H-17 20-Bit Delayed Branch Macro Instructions



Table H-20 Direct Addressing Instructions

Table H-21 Resource Instructions

Table H-22 Coprocessor Control Instructions

761


Add-Subtract Instructions

Compare Operation Instructions

Table H-3 Add-Subtract Instructions


ADD Rj, Ri A A6 1 CCCC Ri + Rj → Ri

*ADD #s5, Ri C’ A4 1 CCCC Ri + s5 → Ri The assembler treats the highest-order bit as the sign.

ADD #i4, Ri C A4 1 CCCC Ri + extu(i4) → Ri Zero extension

ADD2 #i4, Ri C A5 1 CCCC Ri + extn(i4) → Ri Minus extension

ADDC Rj, Ri A A7 1 CCCC Ri + Rj + c → Ri Addition with carry

ADDN Rj, Ri A A2 1 ---- Ri + Rj → Ri

*ADDN #s5, Ri C’ A0 1 ---- Ri + s5 → Ri The assembler treats the highest-order bit as the sign.

ADDN #i4, Ri C A0 1 ---- Ri + extu(i4) → Ri Zero extension

ADDN2 #i4, Ri C A1 1 ---- Ri + extn(i4) → Ri Minus extension

SUB Rj, Ri A AC 1 CCCC Ri - Rj → Ri

SUBC Rj, Ri A AD 1 CCCC Ri - Rj - c → Ri Addition with carry

SUBN Rj, Ri A AE 1 ---- Ri - Rj → Ri

Table H-4 Compare Operation Instructions


CMP Rj, Ri A AA 1 CCCC Ri - Rj

*CMP #s5, Ri C’ A8 1 CCCC Ri - s5 The assembler treats the highest-order bit as the sign.

CMP #i4, Ri C A8 1 CCCC Ri - extu(i4) Zero extension

CMP2 #i4, Ri C A9 1 CCCC Ri - extn(i4) Minus extension

762


Logic Operation Instructions

Table H-5 Logic Operation Instructions


AND Rj, Ri A 82 1 CC-- Ri &= Rj Word

AND Rj, @Ri* A 84 1+2a CC-- (Ri) &= Rj Word

ANDH Rj, @R* A 85 1+2a CC-- (Ri) &= Rj Halfword

ANDB Rj, @Ri* A 86 1+2a CC-- (Ri) &= Rj Byte

OR Rj, Ri A 92 1 CC-- Ri |= Rj Word

OR Rj, @Ri* A 94 1+2a CC-- (Ri) |= Rj Word

ORH Rj, @Ri* A 95 1+2a CC-- (Ri) |= Rj Halfword

ORB Rj, @Ri* A 96 1+2a CC-- (Ri) |= Rj Byte

EOR Rj, Ri A 9A 1 CC-- Ri ^= Rj Word

EOR Rj, @Ri* A 9C 1+2a CC-- (Ri) ^= Rj Word

EORH Rj, @Ri* A 9D 1+2a CC-- (Ri) ^= Rj Halfword

EORB Rj, @Ri* A 9E 1+2a CC-- (Ri) ^= Rj Byte

*: If these instructions are written in the assembler, the general-purpose registers other than R15 is specified to Rj.

763


Bit Manipulation Instructions

Table H-6 Bit Manipulation Instructions


BANDL #u4, @Ri C 80 1+2a ---- (Ri) &= (0xF0+u4) Low-order 4 bits are manipulated.

BANDH #u4, @Ri C 81 1+2a ---- (Ri) &= ((u4<<4)+0x0F) High-order 4 bits are manipulated.

*BAND #u8, @Ri*1 ---- (Ri) &= u8

BORL #u4, @Ri C 90 1+2a ---- (Ri) |= u4 Low-order 4 bits are manipulated.

BORH #u4, @Ri C 91 1+2a ---- (Ri) |= (u4<<4) High-order 4 bits are manipulated.

*BOR #u8, @Ri*2 ---- (Ri) |= u8

BEORL #u4, @Ri C 98 1+2a ---- (Ri) ^= u4 Low-order 4 bits are manipulated.

BEORH #u4, @Ri C 99 1+2a ---- (Ri) ^= (u4<<4) High-order 4 bits are manipulated.

*BEOR #u8, @Ri*3 ---- (Ri) ^= u8

BTSTL #u4, @Ri C 88 2+a 0C-- (Ri) & u4 Low-order 4-bit test.

BTSTH #u4, @Ri C 89 2+a CC-- (Ri) & (u4<<4) High-order 4-bit test.

*1: The assembler generates BANDL if the bit is set at u8&0x0F, and BANDH if the bit is set at u8&0xF0. In some cases, both BANDL and BANDH may be generated.

*2: The assembler generates BORL if the bit is set at u8&0x0F, and BORH if the bit is set at u8&0xF0. In some cases, both BORL and BORH are generated.

*3: The assembler generates BEORL if the bit is set at u8&0x0F, and BEORH if the bit is set at u8&0xF0. In some cases, both BEORL and BEORH are generated.

764


Multiply/Divide Instructions

Table H-7 Multiply/Divide Instructions


MUL Rj,Ri A AF 5 CCC- Ri * Rj → MDH,MDL 32 bits × 32 bits=64 bits

MULU Rj,Ri A AB 5 CCC- Ri * Rj → MDH,MDL No sign

MULH Rj,Ri A BF 3 CC-- Ri * Rj → MDL 16 bits × 16 bits=32 bits

MULUH Rj,Ri A BB 3 CC-- Ri * Rj → MDL No sign

DIV0S Ri E 97-4 1 ---- Step operation

DIV0U Ri E 97-5 1 ---- 32 bits/32 bits=32 bits

DIV1 Ri E 97-6 d -C-C

DIV2 Ri*3 E 97-7 1 -C-C

DIV3 E 9F-6 1 ----

DIV4S E 9F-7 1 ----

*DIV Ri*1 36 -C-C MDL / Ri → MDL,

MDL % Ri → MDH*4

*DIVU Ri*2 33 -C-C MDL / Ri → MDL,

MDL % Ri → MDH*4No sign

*1: DIV0S, DIV1 x 32, DIV2, DIV3, or DIV4S is generated. The instruction code length becomes 72 bytes.*2: DIV0U or DIV1 x 32 is generated. The instruction code length becomes 66 bytes.*3: Be sure to place a DIV3 instruction after a DIV2 instruction.*4: % is remainder operator.

765


Shift Instructions

Immediate Set/16-bit/32-bit Immediate Transfer Instructions

Table H-8 Shift Instructions


LSL Rj, Ri A B6 1 CC-C Ri << Rj → Ri Logical shift

*LSL #u5, Ri (u5:0 to 31) C’ B4 1 CC-C Ri << u5 → Ri

LSL #u4, Ri C B4 1 CC-C Ri << u4 → Ri

LSL2 #u4, Ri C B5 1 CC-C Ri << (u4+16) → Ri

LSR Rj, Ri A B2 1 CC-C Ri >> Rj → Ri Logical shift

*LSR #u5, Ri (u5:0 to 31) C’ B0 1 CC-C Ri >> u5 → Ri

LSR #u4, Ri C B0 1 CC-C Ri >> u4 → Ri

LSR2 #u4, Ri C B1 1 CC-C Ri >> (u4+16) → Ri

ASR Rj, Ri A BA 1 CC-C Ri >> Rj → Ri Arithmetic shift

*ASR #u5, Ri (u5:0 to 31) C’ B8 1 CC-C Ri >> u5 → Ri

ASR #u4, Ri C B8 1 CC-C Ri >> u4 → Ri

ASR2 #u4, Ri C B9 1 CC-C Ri >> (u4+16) → Ri

Table H-9 Immediate Set/16-bit/32-bit Immediate Transfer Instructions


LDI:32 #i32, Ri E 9F-8 3 ---- i32 → Ri

LDI:20 #i20, Ri C 9B 2 ---- i20 → Ri High-order 12 bits are zero-extended.

LDI:8 #i8, Ri B C0 1 ---- i8 → Ri High-order 24 bits are zero-extended.

*LDI # i8 | i20 | i32 ,Ri* i8 | i20 | i32 → Ri

*: If the immediate data is represented as absolute values, the assembler selects automatically from i8, i20, and i32.If immediate data contains a relative value or external reference symbol, i32 is selected.

766


Memory Load Instructions

Table H-10 Memory Load Instructions


LD @Rj, Ri A 04 b ---- (Rj) → Ri

LD @(R13,Rj), Ri A 00 b ---- (R13+Rj) → Ri

LD @(R14,disp10), Ri B 20 b ---- (R14+disp10) → Ri

LD @(R15,udisp6), Ri C 03 b ---- (R15+udisp6) → Ri

LD @R15+, Ri E 07-0 b ---- (R15) → Ri,R15+=4

LD @R15+, Rs E 07-8 b ---- (R15) → Rs, R15+=4 Rs: Special register *

LD @R15+, PS E 07-9 1+a+c CCCC (R15) → PS, R15+=4

LDUH @Rj, Ri A 05 b ---- (Rj) → Ri Zero extension

LDUH @(R13,Rj), Ri A 01 b ---- (R13+Rj) → Ri Zero extension

LDUH @(R14,disp9), Ri B 40 b ---- (R14+disp9) → Ri Zero extension

LDUB @Rj, Ri A 06 b ---- (Rj) → Ri Zero extension

LDUB @(R13,Rj), Ri A 02 b ---- (R13+Rj) → Ri Zero extension

LDUB @(R14,disp8), Ri B 60 b ---- (R14+disp8) → Ri Zero extension

*: Special register Rs: TBR, RP, USP, SSP, MDH, and MDL

Note:

In the o8 and o4 fields of the hardware specifications, the assembler calculates values and sets them as shown below:

- disp10/4 --> o8, disp9/2 --> o8, disp8 --> o8 (disp10, disp9, and disp8 have a sign.)- udisp6/4 --> o4 (udisp6 has no sign.)

767


Memory Store Instructions

Register-to-Register Transfer Instructions

Table H-11 Memory Store Instructions


ST Ri, @Rj A 14 a ---- Ri → (Rj) Word

ST Ri, @(R13,Rj) A 10 a ---- Ri → (R13+Rj) Word

ST Ri, @(R14,disp10) B 30 a ---- Ri → (R14+disp10) Word

ST Ri, @(R15,udisp6) C 13 a ---- Ri → (R15+udisp6)

ST Ri, @-R15 E 17-0 a ---- R15-=4,Ri → (R15)

ST Rs, @-R15 E 17-8 a ---- R15-=4, Rs → (R15) Rs: Special register *

ST PS, @-R15 E 17-9 a ---- R15-=4, PS → (R15)

STH Ri, @Rj A 15 a ---- Ri → (Rj) Halfword

STH Ri, @(R13,Rj) A 11 a ---- Ri → (R13+Rj) Halfword

STH Ri, @(R14,disp9) B 50 a ---- Ri → (R14+disp9) Halfword

STB Ri, @Rj A 16 a ---- Ri → (Rj) Byte

STB Ri, @(R13,Rj) A 12 a ---- Ri → (R13+Rj) Byte

STB Ri, @(R14,disp8) B 70 a ---- Ri → (R14+disp8) Byte


Note:

In the o8 and o4 fields of the hardware specifications, the assembler calculates values and sets them as shown below:

- disp10/4 --> o8, disp9/2 --> o8, disp8 --> o8 (disp10, disp9, and disp8 have a sign.)- udisp6/4 --> o4 (udisp6 has no sign.)

Table H-12 Register-to-Register Transfer Instructions


MOV Rj, Ri A 8B 1 ---- Rj → Ri Transfer between general-purpose registers

MOV Rs, Ri A B7 1 ---- Rs → Ri Rs: Special register *

MOV Ri, Rs A B3 1 ---- Ri → Rs Rs: Special register *

MOV PS, Ri E 17-1 1 ---- PS → Ri

MOV Ri, PS E 07-1 c CCCC Ri → PS


768


Normal Branch (No Delay) Instructions

Table H-13 Normal Branch (No Delay) Instructions


JMP @Ri E 97-0 2 ---- Ri → PC

CALL label12 F D0 2 ---- PC+2→ RP ,PC+2+(label12-PC-2)→PC

CALL @Ri E 97-1 2 ---- PC+2→RP ,Ri→PC

RET E 97-2 2 ---- RP → PC Return

INT #u8 D 1F 3+3a ---- SSP-=4,PS → (SSP),SSP-=4,PC+2 → (SSP),0→ I flag, 0 → S flag,(TBR+0x3FC-u8x4) → PC

INTE E 9F-3 3+3a ---- SSP-=4,PS → (SSP),SSP-=4,PC+2 → (SSP),0 → S flag,(TBR+0x3D8) →PC

For emulator

RETI E 97-3 2+2a CCCC (R15) → PC,R15+=4,(R15) → PS,R15+=4

BRA label9 D E0 2 ---- PC+2+(label9-PC-2) → PC

BNO label9 D E1 1 ---- No branch

BEQ label9 D E2 2/1 ---- if(Z==1) thenPC+2+(label9-PC-2) → PC

BNE label9 D E3 2/1 ---- if(Z==0) thenPC+2+(label9-PC-2) → PC

BC label9 D E4 2/1 ---- if(C==1) thenPC+2+(label9-PC-2) → PC

BNC label9 D E5 2/1 ---- if(C==0) thenPC+2+(label9-PC-2) → PC

BN label9 D E6 2/1 ---- if(N==1) thenPC+2+(label9-PC-2) → PC

BP label9 D E7 2/1 ---- if(N==0) thenPC+2+(label9-PC-2) → PC

BV label9 D E8 2/1 ---- if(V==1) thenPC+2+(label9-PC-2) → PC

BNV label9 D E9 2/1 ---- if(V==0) thenPC+2+(label9-PC-2) → PC

BLT label9 D EA 2/1 ---- if(V xor N==1) thenPC+2+(label9-PC-2) → PC

BGE label9 D EB 2/1 ---- if(V xor N==0) thenPC+2+(label9-PC-2) → PC

BLE label9 D EC 2/1 ---- if((V xor N) or Z==1) thenPC+2+(label9-PC-2) → PC

BGT label9 D ED 2/1 ---- if((V xor N) or Z==0) thenPC+2+(label9-PC-2) → PC

BLS label9 D EE 2/1 ---- if(C or Z==1) thenPC+2+(label9-PC-2) → PC

BHI label9 D EF 2/1 ---- if(C or Z==0) thenPC+2+(label9-PC-2) → PC

Notes:• "2/1" in CYCLE indicates 2 when branching occurs and 1 when branching does not occur.• In the rel11 and rel8 fields of the hardware specifications, the assembler calculates values and sets them as shown below:

(label12-PC-2)/2 --> rel11, (label9-PC-2)/2 --> rel8 (label12 and label9 have a sign.)• To execute the RETI instruction, the S flag must be 0.

769


Delayed Branch Instructions

Table H-14 Delayed Branch Instructions


JMP:D @Ri E 9F-0 1 ---- Ri → PC

CALL:D label12 F D8 1 ---- PC+4 → RP ,PC+2+(label12-PC-2) → PC

CALL:D @Ri E 9F-1 1 ---- PC+4 → RP ,Ri → PC

RET:D E 9F-2 1 ---- RP→ PC Return

BRA:D label9 D F0 1 ---- PC+2+(label9-PC-2) → PC

BNO:D label9 D F1 1 ---- No branch

BEQ:D label9 D F2 1 ---- if(Z==1) thenPC+2+(label9-PC-2) → PC

BNE:D label9 D F3 1 ---- if(Z==0) thenPC+2+(label9-PC-2) → PC

BC:D label9 D F4 1 ---- if(C==1) thenPC+2+(label9-PC-2) → PC

BNC:D label9 D F5 1 ---- if(C==0) thenPC+2+(label9-PC-2) → PC

BN:D label9 D F6 1 ---- if(N==1) thenPC+2+(label9-PC-2) → PC

BP:D label9 D F7 1 ---- if(N==0) thenPC+2+(label9-PC-2) → PC

BV:D label9 D F8 1 ---- if(V==1) thenPC+2+(label9-PC-2) → PC

BNV:D label9 D F9 1 ---- if(V==0) thenPC+2+(label9-PC-2) → PC

BLT:D label9 D FA 1 ---- if(V xor N==1) thenPC+2+(label9-PC-2) → PC

BGE:D label9 D FB 1 ---- if(V xor N==0) thenPC+2+(label9-PC-2) → PC

BLE:D label9 D FC 1 ---- if((V xor N) or Z==1) thenPC+2+(label9-PC-2) → PC

BGT:D label9 D FD 1 ---- if((V xor N) or Z==0) thenPC+2+(label9-PC-2) → PC

BLS:D label9 D FE 1 ---- if(C or Z==1) thenPC+2+(label9-PC-2) → PC

BHI:D label9 D FF 1 ---- if(C or Z==0) thenPC+2+(label9-PC-2) → PC

Notes:

• In the rel11 and rel8 fields of the hardware specifications, the assembler calculates values and sets them as shown below:(label12-PC-2)/2 --> rel11, (label9-PC-2)/2 --> rel8 (label12 and label9 have a sign.)

• A delayed branch always occurs after the next instruction (delay slot) is executed.• Instructions that can be placed in the delay slot are all 1-cycle, a-, b-, c-, and d-cycle instructions.

Multicycle instructions cannot be placed in the delay slot.

770


Other Instructions

Table H-15 Other Instructions


NOP E 9F-A 1 ---- No change

ANDCCR #u8 D 83 c CCCC CCR and u8 → CCR

ORCCR #u8 D 93 c CCCC CCR or u8 → CCR

STILM #u8 D 87 1 ---- u8 → ILM ILM immediate set

ADDSP #s10*1 D A3 1 ---- R15 += s10 ADD SP instruction

EXTSB Ri E 97-8 1 ---- Sign extension 8 bits → 32 bits

EXTUB Ri E 97-9 1 ---- Zero extension 8 bits → 32 bits

EXTSH Ri E 97-A 1 ---- Sign extension 16 bits → 32 bits

EXTUH Ri E 97-B 1 ---- Zero extension 16 bits → 32 bits

LDM0 (reglist) D 8C ---- (R15) → reglist,R15 increment

Load multi R0 to R7

LDM1 (reglist) D 8D ---- (R15) → reglist,R15 increment

Load multi R8 to R15

*LDM (reglist)*2 ---- (R15) → reglist,R15 increment

Load multi R0 to R15

STM0 (reglist) D 8E ---- R15 decrement,reglist → (R15)

Store multi R0 to R7

STM1 (reglist) D 8F ---- R15 decrement,reglist → (R15)


*STM (reglist)*3 ---- R15 decrement,reglist → (R15)


ENTER #u10*4 D 0F 1+a ---- R14 → (R15 - 4),R15 - 4 → R14,R15 - u10 → R15

Entry processing of a function

LEAVE E 9F-9 b ---- R14 + 4 → R15,(R15 - 4) → R14

Exit processing of a function

XCHB @Rj, Ri*5 A 8A 2a ---- Ri → TEMP(Rj) → RiTEMP → (Rj)

For semaphore managementByte data

*1: For s10, the assembler calculates s10/4 and then changes to s8 to set a value. s10 has a sign.*2: If any of R0 to R7 is specified in reglist, LDM0 is generated. If any of R8 to R15 is generated, LDM1 is generated. In some cases,

both LDM0 and LDM1 are generated.*3: If any of R0 to R7 is specified in reglist, STM0 is generated. If any of R8 to R15 is generated, STM1 is generated. In some cases,

both STM0 and STM1 are generated.*4: For u10, the assembler calculates u10/4 and then changes to u8 to set a value. u10 has no sign.*5: If this instruction is written in the assembler, the general-purpose registers other than R15 is specified to Ri.

Notes:• The number of execution cycles for LDM0(reglist) and LDM1(reglist) can be calculated as a × (n-1)+b+1 cycles

if the number of specified registers is n.• The number of execution cycles for STM0(reglist) and STM1(reglist) can be calculated as a × n+1 cycles

if the number of specified registers is n.

771


20-Bit Normal Branch Macro Instructions

Reference 1:CALL201) If label20-PC-2 is between -0x800 and +0x7fe, create an instruction as shown below:

CALL label122) If label20-PC-2 is outside the range in 1) or contains an external reference symbol, create an instruction as shown

below:LDI:20 #label20,RiCALL @Ri

Reference 2:BRA20

1) If label20-PC-2 is between -0x100 and +0xfe, create an instruction as shown below:BRA label9

2) If label20-PC-2 is outside the range in 1) or contains an external reference symbol, create an instruction as shown below:

LDI:20 #label20,RiJMP @Ri

Reference 3:Bcc20

1) If label20-PC-2 is between -0x100 and +0xfe, create an instruction as shown below:Bcc label9


Bxcc false ; xcc is the opposite condition of cc.LDI:20 #label20,RiJMP @Ri

false:


Mnemonic Operation Remarks

*CALL20 label20,Ri Address of the next instruction → RP,label20 → PC

Ri: Temporary register (See Reference 1)

*BRA20 label20,Ri label20 → PC Ri: Temporary register (See Reference 2)

*BEQ20 label20,Ri if(Z==1) then label20 → PC Ri: Temporary register (See Reference 3)

*BNE20 label20,Ri if(Z==0) then label20 → PC ↑

*BC20 label20,Ri if(C==1) then label20 → PC ↑

*BNC20 label20,Ri if(C==0) then label20 → PC ↑

*BN20 label20,Ri if(N==1) then label20 → PC ↑

*BP20 label20,Ri if(N==0) then label20 → PC ↑

*BV20 label20,Ri if(V==1) then label20 → PC ↑

*BNV20 label20,Ri if(V==0) then label20 → PC ↑

*BLT20 label20,Ri if(V xor N==1) then label20 → PC ↑

*BGE20 label20,Ri if(V xor N==0) then label20 → PC ↑

*BLE20 label20,Ri if((V xor N) or Z==1) then label20 → PC ↑

*BGT20 label20,Ri if((V xor N) or Z==0) then label20 → PC ↑

*BLS20 label20,Ri if(C or Z==1) then label20 → PC ↑

*BHI20 label20,Ri if(C or Z==0) then label20 → PC ↑

772


20-Bit Delayed Branch Macro Instructions

Reference 1:CALL20:D1) If label20-PC-2 is between -0x800 and +0x7fe, create an instruction as shown below:

CALL:D label122) If label20-PC-2 is outside the range in 1) or contains an external reference symbol, create an instruction as shown

below:LDI:20 #label20,RiCALL:D @Ri

Reference 2:BRA20:D1) If label20-PC-2 is between -0x100 and +0xfe, create an instruction as shown below:

BRA :D label92) If label20-PC-2 is outside the range in 1) or contains an external reference symbol, create an instruction as shown

below:LDI:20 #label20,RiJMP:D @Ri

Reference 3:Bcc20:D

1) If label20-PC-2 is between -0x100 and +0xfe, create an instruction as shown below:Bcc:D label9


Bxcc false ; xcc is the opposite condition of cc.LDI:20 #label20,RiJMP:D @Ri

false:



*CALL20:D label20,Ri Address of the next instruction +2 → RP,label20 → PC


*BRA20:D label20,Ri label20 → PC Ri: Temporary register (See Reference 2)

*BEQ20:D label20,Ri if(Z==1) then label20 → PC Ri: Temporary register (See Reference 3)

*BNE20:D label20,Ri if(Z==0) then label20 → PC ↑

*BC20:D label20,Ri if(C==1) then label20 → PC ↑

*BNC20:D label20,Ri if(C==0) then label20 → PC ↑

*BN20:D label20,Ri if(N==1) then label20 → PC ↑

*BP20:D label20,Ri if(N==0) then label20 → PC ↑

*BV20:D label20,Ri if(V==1) then label20 → PC ↑

*BNV20:D label20,Ri if(V==0) then label20 → PC ↑

*BLT20:D label20,Ri if(V xor N==1) then label20 → PC ↑

*BGE20:D label20,Ri if(V xor N==0) then label20 → PC ↑

*BLE20:D label20,Ri if((V xor N) or Z==1) then label20 → PC ↑

*BGT20:D label20,Ri if((V xor N) or Z==0) then label20 → PC ↑

*BLS20:D label20,Ri if(C or Z==1) then label20 → PC ↑

*BHI20:D label20,Ri if(C or Z==0) then label20 → PC ↑

773


32-Bit Normal Branch Macro Instructions

Reference 1:CALL321) If label32-PC-2 is between -0x800 and +0x7fe, create an instruction as shown below:

CALL label122) If label32-PC-2 is outside the range in 1) or contains an external reference symbol, create an instruction as shown

below:LDI:32 #label32,RiCALL @Ri

Reference 2:BRA321) If label32-PC-2 is between -0x100 and +0xfe, create an instruction as shown below:

BRA label92) If label32-PC-2 is outside the range in 1) or contains an external reference symbol, create an instruction as shown

below:LDI:32 #label32,RiJMP @Ri

Reference 3:Bcc32

1) If label32-PC-2 is between -0x100 and +0xfe, create an instruction as shown below:Bcc label9


Bxcc false ; xcc is the opposite condition of cc.LDI:32 #label32,RiJMP @Ri



*CALL32 label32,Ri Address of the next instruction → RP,label32 → PC


*BRA32 label32,Ri label32 → PC Ri: Temporary register (See Reference 2)

*BEQ32 label32,Ri if(Z==1) then label32 → PC Ri: Temporary register (See Reference 3)

*BNE32 label32,Ri if(Z==0) then label32 → PC ↑

*BC32 label32,Ri if(C==1) then label32 → PC ↑

*BNC32 label32,Ri if(C==0) then label32 → PC ↑

*BN32 label32,Ri if(N==1) then label32 → PC ↑

*BP32 label32,Ri if(N==0) then label32 → PC ↑

*BV32 label32,Ri if(V==1) then label32 → PC ↑

*BNV32 label32,Ri if(V==0) then label32 → PC ↑

*BLT32 label32,Ri if(V xor N==1) then label32 → PC ↑

*BGE32 label32,Ri if(V xor N==0) then label32 → PC ↑

*BLE32 label32,Ri if((V xor N) or Z==1) then label32 → PC ↑

*BGT32 label32,Ri if((V xor N) or Z==0) then label32 → PC ↑

*BLS32 label32,Ri if(C or Z==1) then label32 → PC ↑

*BHI32 label32,Ri if(C or Z==0) then label32 → PC ↑

774


false: 32-Bit Delayed Branch Macro Instructions

Reference 1:CALL32:D1) If label32-PC-2 is between -0x800 and +0x7fe, create an instruction as shown below:

CALL:D label122) If label32-PC-2 is outside the range in 1) or contains an external reference symbol, create an instruction as shown

below:LDI:32 #label32,RiCALL:D @Ri

Reference 2:BRA32:D

1) If label32-PC-2 is between -0x100 and +0xfe, create an instruction as shown below:BRA:D label9


LDI:32 #label32,RiJMP:D @Ri

Reference 3:Bcc32:D1) If label32-PC-2 is between -0x100 and +0xfe, create an instruction as shown below:

Bcc:D label92) If label32-PC-2 is outside the range in 1) or contains an external reference symbol, create an instruction as shown

below:Bxcc false ; xcc is the opposite condition of cc.LDI:32 #label32,RiJMP:D @Ri

false:



*CALL32:D label32,Ri Address of the next instruction +2 → RP,label32 → PC


*BRA32:D label32,Ri label32 → PC Ri: Temporary register (See Reference 2)

*BEQ32:D label32,Ri if(Z==1) then label32 → PC Ri: Temporary register (See Reference 3)

*BNE32:D label32,Ri if(Z==0) then label32 → PC ↑

*BC32:D label32,Ri if(C==1) then label32 → PC ↑

*BNC32:D label32,Ri if(C==0) then label32 → PC ↑

*BN32:D label32,Ri if(N==1) then label32 → PC ↑

*BP32:D label32,Ri if(N==0) then label32 → PC ↑

*BV32:D label32,Ri if(V==1) then label32 → PC ↑

*BNV32:D label32,Ri if(V==0) then label32 → PC ↑

*BLT32:D label32,Ri if(V xor N==1) then label32 → PC ↑

*BGE32:D label32,Ri if(V xor N==0) then label32 → PC ↑

*BLE32:D label32,Ri if((V xor N) or Z==1) then label32 → PC ↑

*BGT32:D label32,Ri if((V xor N) or Z==0) then label32 → PC ↑

*BLS32:D label32,Ri if(C or Z==1) then label32 → PC ↑

*BHI32:D label32,Ri if(C or Z==0) then label32 → PC ↑

775


Direct Addressing Instructions

Resource Instructions

Table H-20 Direct Addressing Instructions


DMOV @dir10, R13 D 08 b ---- (dir10) → R13 Word

DMOV R13, @dir10 D 18 a ---- R13 → (dir10) Word

DMOV @dir10, @R13+ D 0C 2a ---- (dir10) → (R13),R13+=4 Word

DMOV @R13+, @dir10 D 1C 2a ---- (R13) → (dir10),R13+=4 Word

DMOV @dir10, @-R15 D 0B 2a ---- R15-=4,(R15) → (dir10) Word

DMOV @R15+, @dir10 D 1B 2a ---- (R15) → (dir10),R15+=4 Word

DMOVH @dir9, R13 D 09 b ---- (dir9) → R13 Halfword

DMOVH R13, @dir9 D 19 a ---- R13 → (dir9) Halfword

DMOVH @dir9, @R13+ D 0D 2a ---- (dir9) → (R13),R13+=2 Halfword

DMOVH @R13+, @dir9 D 1D 2a ---- (R13) → (dir9),R13+=2 Halfword

DMOVB @dir8, R13 D 0A b ---- (dir8) → R13 Byte

DMOVB R13, @dir8 D 1A a ---- R13 → (dir8) Byte

DMOVB @dir8, @R13+ D 0E 2a ---- (dir8) → (R13),R13++ Byte

DMOVB @R13+, @dir8 D 1E 2a ---- (R13) → (dir8),R13++ Byte

Note:

In the dir8, dir9, and dir10 fields, the assembler calculates values and sets them as shown below:dir8 --> dir, dir9/2 --> dir, dir10/4 --> dir (dir8, dir9, and dir10 have no sign.)

Table H-21 Resource Instructions


LDRES @Ri+, #u4 C BC a ---- (Ri) → u4 resourceRi+=4

u4: Channel number

STRES #u4, @Ri+ C BD a ---- u4 resource → (Ri)Ri+=4

u4: Channel number

Note:

This series cannot use these instructions because it has no resource with the channel number used for the resource instructions.

776


Coprocessor Control Instructions

Table H-22 Coprocessor Control Instructions


COPOP #u4, #u8, CRj, CRi E 9F-C 2+a ---- Operation instruction

COPLD #u4, #u8, Rj, CRi E 9F-D 1+2a ---- Rj → CRi

COPST #u4, #u8, CRj, Ri E 9F-E 1+2a ---- CRj → Ri

COPSV #u4, #u8, CRj, Ri E 9F-F 1+2a ---- CRj → Ri No error trap

Notes:

• CRi | CRj:= CR0 | CR1 | CR2 | CR3 | CR4 | CR5 | CR6 | CR7 | CR8 | CR9 | CR10 | CR11 | CR12 | CR13 |CR14 | CR15u4:= Channel specifiedu8:= Command specified

• Since this series has no coprocessor, these instructions cannot be used.

777


778

INDEX

INDEX

The index follows on the next page.This is listed in alphabetic order.

779

INDEX

Index

Numerics

0 Detection0 Detection ..................................................... 322

0 Detection Data Register0 Detection Data Register (BSD0) .................... 320

1 Detection1 Detection ..................................................... 322

1 Detection Data Register1 Detection Data Register (BSD1) .................... 320

10-Bit A/D ConverterFeatures of the 10-Bit A/D Converter ................ 326Registers of the 10-Bit A/D Converter............... 328

10-bit Slave Address Mask Register10-bit Slave Address Mask Register (ITMK)

......................................................... 37910-bit Slave Address Register

10-bit Slave Address Register (ITBA) ............... 37816 Color

Character Colors (Setting for Each Character, Selectedfrom among 16 Colors) ....................... 578

16-bitImmediate Set/16-bit/32-bit Immediate Transfer

Instructions ........................................ 76616-Bit Pulse Width Counter

16-Bit Pulse Width Counter.............................. 276Registers of the 16-Bit Pulse Width Counter

......................................................... 27716-bit Reload Register

Bit Configuration of the 16-bit Reload Register (TMRLR) .......................................... 234

16-bit Reload TimerOverview of the 16-bit Reload Timer ................ 228

16-bit Timer RegisterBit Configuration of the 16-bit Timer Register

(TMR) ...............................................23316-Bit Width Pulse Counter

Basic Operation of the 16-Bit Width Pulse Counter ..............................................285

20-Bit Delayed Branch Macro Instructions20-Bit Delayed Branch Macro Instructions .........773

20-Bit Normal Branch Macro Instructions20-Bit Normal Branch Macro Instructions ..........772

2-Cycle Transfer2-Cycle Transfer (External ->I/O)......................2062-Cycle Transfer (I/O ->External)......................2072-Cycle Transfer (Internal RAM ->

External I/O,RAM) .............................205Burst 2-Cycle Transfer .....................................420Demand Transfer 2-Cycle Transfer ....................421Flow of Data During 2-Cycle Transfer ...............439Step/Block Transfer 2-Cycle Transfer ................423Step/Block Transfer 2-Cycle Transfer Fly-by Transfer

.........................................................42432-bit

Immediate Set/16-bit/32-bit Immediate Transfer Instructions ........................................766

32-Bit Delayed Branch Macro Instructions32-Bit Delayed Branch Macro Instructions .........775

32-Bit Normal Branch Macro Instructions32-Bit Normal Branch Macro Instructions ..........774

7-bit Slave Address Mask Register7-bit Slave Address Mask Register (ISMK) ........382

7-bit Slave Address Register7-bit Slave Address Register (ISBA)..................381

780

INDEX

A

A/D ConversionA/D Conversion Started by External Trigger

..........................................................334A/D Conversion Started by Software .................334

A/D Conversion Result RegisterA/D Conversion Result Register (ch.0 to ch.9)

..........................................................332A/D Converter

A/D Converter .....................................................4Features of the 10-Bit A/D Converter.................326Registers of the 10-Bit A/D Converter ...............328

A/D Converter Test RegisterA/D Converter Test Register .............................333

A/DC Control RegisterA/DC Control Register (ADCTH,ADCTL).........329

AccessData Access.......................................................41Program Access .................................................41

AcknowledgeAcknowledge...................................................387

ACRConfiguration of Area Configuration Registers 0 to 7

(ACR0 to ACR7) ................................132Functions of Bits in the Area Configuration Registers

(ACR0 to ACR7) ................................134ADCTH

A/DC Control Register (ADCTH,ADCTL).........329ADCTL

A/DC Control Register (ADCTH,ADCTL).........329Address/Data Multiplex Access

Normal Access or Address/Data Multiplex Access..........................................................141

AddressingAddressing Mode .............................................426Direct Addressing Instructions ..........................776Master Addressing ...........................................387

Addressing ModeAddressing Mode .............................................426Addressing Mode Symbols ...............................758

Add-Subtract InstructionsAdd-Subtract Instructions .................................762

All-Channel Control RegisterAll-Channel Control Register (DMACR) ...........413

All-HPPG Output All-L and All-H.............................256

All-LPPG Output All-L and All-H.............................256

Applied Display ExamplesApplied Display Examples................................577

ArbitrationArbitration.......................................................387Hold Arbitration ..............................................429

ArchitectureInternal Architecture .......................................... 28

Area Configuration RegistersConfiguration of Area Configuration Registers 0 to 7

(ACR0 to ACR7) ................................ 132Functions of Bits in the Area Configuration Registers

(ACR0 to ACR7) ................................ 134Area Select Registers

Configuration of Area Select Registers 0 to 7 (ASR0 to ASR7)................................. 130

Functions of Bits in the Area Select Registers (ASR0 to ASR7)................................. 131

Area Wait RegistersConfiguration of the Area Wait Registers

(AWR0 to AWR7) .............................. 139Functions of Bits in the Area Wait Registers

(AWR0 to AWR7) .............................. 142ASR

Configuration of Area Select Registers 0 to 7 (ASR0 to ASR7)................................. 130

Functions of Bits in the Area Select Registers (ASR0 to ASR7)................................. 131

AsynchronousAsynchronous (Start-stop Synchronization) Mode

......................................................... 353Automatic Algorithm

Automatic Algorithm Execution Status .............. 706Automatic Response

Automatic Response of Macro Program to USB Standard Request Commands............... 509

Auto-Wait CycleAuto-Wait Cycle Timing .................................. 184

AWRConfiguration of the Area Wait Registers

(AWR0 to AWR7) .............................. 139Functions of Bits in the Area Wait Registers

(AWR0 to AWR7) .............................. 142

B

Background CharacterCommand 7-1 (Screen Background Character

Control 1) .......................................... 676Command 7-3 (Screen Background Character

Control 2) .......................................... 677Configuration of Screen Background Character

Display .............................................. 625Display Position Control of Screen Background

Characters .......................................... 562Screen Background Character Display Control

......................................................... 626Background Color

Character Background Color (Setting for Each Screen,Selected from Among 16 Colors)......................................................... 607

781

INDEX

Display Position Control of Screen Background Color................................................. 563

Line Background Color (Setting for Each Line,Selected From Among 16 Colors)......................................................... 615

Screen Background Color Control..................... 628Background Control

Line Background Control (Setting for Each Line)......................................................... 615

Background Extended DisplayCharacter Background Extended Display

(Setting for Each Line)........................ 613Background Frame Color

Command 6-1 (Shaded Background Frame Color Control)............................................. 671

Background Highlight ColorShaded Background Highlight Color (Setting for Each

Screen,Selected from Among 16 Colors)................................................. 607, 615

Background OutputScreen Background Output Control................... 628

Background Shadow ColorShaded Background Shadow Color (Setting for Each


Background Succeeding CharacterShaded Background Succeeding Character Merge

Control (Setting for Each Character)......................................................... 609

Background Succeeding LineShaded Background Succeeding Line Merge Control

(Setting for Each Line)................ 611, 617Base Clock Division Setting Register

Base Clock Division Setting Register 0 (DIVR0)........................................................... 93


Basic Block DiagramBasic Block Diagram of the I/O Port ................. 214

Basic Programming ModelBasic Programming Model ................................. 33

Basic TimingBasic Timing (For Successive Accesses) ........... 179

Baud RateCalculation of Baud Rate ................................. 226Example of Setting U-TIMER Baud Rates and Reload

Values ............................................... 361BFOK

Setting of Transfer Enable (BFOK) Bits during Control Transfer ...................... 515

Big EndianDifferences between Little Endian and Big Endian

......................................................... 165

Bit ConfigurationBit Configuration of PPG Cycle Setting Register

(PCSR) ..............................................248Bit Configuration of PPG Duty Setting Register

(PDUT)..............................................249Bit Configuration of PPG Timer Register (PTMR)

.........................................................250Bit Configuration of the 16-bit Reload Register

(TMRLR)...........................................234Bit Configuration of the 16-bit Timer Register

(TMR) ...............................................233Bit Configuration of the Control Status Register

(TMCSR) ...........................................230Bit Configuration of the Interrupt Control Register

(ICR) .................................................294Bit Manipulation Instructions

Bit Manipulation Instructions ............................764Bit Ordering

Bit Ordering ......................................................40Bit Search Module

Bit Search Module (Used by REALOS) .................3Bit Search Module Registers .............................320Block Diagram of the Bit Search Module ...........319

Blink ControlBlink Control (Setting for Each Character) .........600

Blink CycleBlink Cycle .....................................................603

Blink Duty RatioBlink Duty Ratio..............................................603

Block DiagramBasic Block Diagram of the I/O Port..................214Block Diagram.............................................................

6, 82, 112, 118, 126, 222, 228, 260, 276, 291, 326, 337, 365, 396, 446, 521, 552, 697

Block Diagram for One Channel of PPG Timer .........................................242

Block Diagram of the Bit Search Module ...........319Block Diagram of the Delayed Interrupt Module

.........................................................316Block Diagram of the External Interrupt and

NMI Controller...................................306Overall Block Diagram of PPG Timer................241

Block SizeBlock Size.......................................................425

Block TransferBlock Transfer.................................................436

BoardControlling the D+ Terminating Resistor on the Board

.........................................................508Branch

Delayed Branch Instructions .............................770Normal Branch (No Delay) Instructions .............769

Branch InstructionBranch Instruction with Delay Slot ......................43

782

INDEX

Branch Instruction without Delay Slot..................45BSD

0 Detection Data Register (BSD0) .....................3201 Detection Data Register (BSD1) .....................320

BSDCChange Point Detection Data Register (BSDC)

..........................................................321BSRR

Detection Result Register (BSRR) .....................321Built-in Peripheral

Built-in Peripheral Request ...............................418Built-in RAM

Built-in RAM ......................................................3BULK IN Transfer

Timing Diagram for BULK IN Transfer (Writing by CPU and Reading by USB) ..................502

BULK OUT TransferControl Transfer (Data Stage) and BULK OUT

Transfer .............................................479Timing Diagram for BULK OUT Transfer (Reading

by CPU and Writing by USB) ..............504bulk Transfer

Control Transfer (Data Stage),bulk Transfer,or INTERRUPT IN Transfer ....................480

Burst 2-Cycle TransferBurst 2-Cycle Transfer .....................................420

Burst AccessBurst Access Operation ....................................192

Burst Fly-by TransferBurst Fly-by Transfer .......................................421

Burst TransferBurst Transfer..................................................437

Bus Control RegisterBus Control Register (IBCR) ............................372

Bus ErrorBus Error ........................................................388

Bus InterfaceBus Interface .......................................................2Ordinary Bus Interface .....................................178

Bus ModesBus Modes ........................................................62

Bus RightAcquiring the Bus Right ...................................209Releasing the Bus Right....................................208

Bus Status RegisterBus Status Register (IBSR) ...............................369

Bus WidthData Bus Width .......................................159, 167Relationship between Data Bus Width and Control

Signal ................................................157BUSYX

Ready/Busy Signal (RDY/BUSYX)...................711

Byte AccessByte Access .................................................... 174

Byte OrderingByte Ordering ................................................... 40

C

Cache Enable RegisterConfiguration of the Cache Enable Register (CHER)

......................................................... 152Functions of Bits in the Cache Enable Register

(CHER) ............................................. 152Capture Control Register

Capture Control Register (TxCCR) ................... 263Capture Data Register

Capture Data Register (TxCRR)........................ 269Capture Mode

Capture Mode ................................................. 273Change Point Detection

Change Point Detection.................................... 323Change Point Detection Data Register

Change Point Detection Data Register (BSDC)......................................................... 321

Channel GroupChannel Group ................................................ 435

Channel SelectionChannel Selection and Control .......................... 433

CharacterCommand 1 (Character Data Set 1) ................... 663Command 2 (Character Data Set 2) ................... 664Command 6-0 (Character Vertical Size Control)

......................................................... 670Command 7-1 (Screen Background Character


Control 2) .......................................... 677Command 8-1 (Sprite Character Control 1) ........ 678Command 8-2 (Sprite Character Control 2) ........ 679Command 9-0 (Sprite Character Control 3) ........ 679Command 9-1 (Sprite Character Control 4) ........ 680Display Position Control of Screen Background

Characters .......................................... 562Display Position Control of Sprite Characters

......................................................... 564Origin of Italic Character.................................. 581Screen Background Character Display Control

......................................................... 626Shaded Background Succeeding Character Merge

Control (Setting for Each Character)......................................................... 609

Sprite Character Configuration.......................... 629Sprite Character Display Control....................... 630Writing a Single Character to Character RAM

......................................................... 569Writing Multiple Characters Collectively

(VRAM Fill) ...................................... 570

783

INDEX

Character Background ColorCharacter Background Color (Setting for Each

Screen,Selected from Among 16 Colors)......................................................... 607

Character Background ControlCharacter Background Control

(Setting for Each Character) ................ 607Character Background Extended Display

Character Background Extended Display (Setting for Each Line)........................ 613

Character ColorCharacter Colors (Setting for Each Character, Selected

from among 16 Colors) ....................... 578Color to be Replaced by the Character Color

(Setting for Each Screen) .................... 598Graphic Color/Character Color Replace Control

(Setting for Each Screen) .................... 598Character Horizontal Size Control

Character Horizontal Size Control (Setting for Each Character) ................ 574

Character RAMWriting a Single Character to Character RAM

......................................................... 569Character Vertical Size

Character Vertical Size A/B ............................. 575Character Vertical Size Control

Command 6-0 (Character Vertical Size Control)......................................................... 670

Character/graphic Character ControlCharacter/graphic Character Control

(Setting for Each Character) ................ 595CHER

Configuration of the Cache Enable Register (CHER) ............................................. 152

Functions of Bits in the Cache Enable Register (CHER) ............................................. 152

Chip ErasureData Erasure (Chip Erasure) ............................. 719

Chip Select AreaExample of Setting the Chip Select Area ........... 156

Chip Select Enable RegisterConfiguration of the Chip Select Enable Register

(CSER) ............................................. 150Functions of Bits in the Chip Select Enable Register

(CSER) ............................................. 150Circuit

Input-Output Circuit Types ................................ 16Quartz Oscillation Circuit .................................. 22

Class CommandSetup Stage of Control Transfer (Class and Vendor

Commands and Some Standard Commands [Get_Descriptor, Set_Descriptor, and Synch_Frame]) .................................. 477

Status Stage of Control Transfer (Class and Vendor Commands and Some Standard Commands [Get_Descriptor, Set_Descriptor, and Synch_Frame]) ...................................478

CLKBCPU Clock (CLKB) ...........................................79

CLKPPeripheral Clock (CLKP)....................................80

CLKRClock Source Control Register (CLKR) ...............90

CLKTExternal Bus Clock (CLKT)................................80

ClockClock Division...................................................81Clock Generation Control ...................................74Clock Synchronous Mode .................................354Command 11-1 (Dot Clock Control 1) ...............682Command 11-2 (Dot Clock Control 2) ...............683Command 11-3 (Dot Clock Control 3) ...............684Count Clock Selection ......................................286CPU Clock (CLKB) ...........................................79Dot Clock........................................................748Dot Clock Generation PLL ...............................748Example of USB Clock Control in the Suspended

Status.................................................512External Bus Clock (CLKT)................................80External Dot Clock Input ..................................633Input Dot Clock Selection Control .....................633Internal Clock Operation ..................................235Internal VCO Generation Dot Clock Input..........634Main Clock Oscillation Stabilization Wait Timer

(for the sub clock select) ......................100Operation of Clock Supply Function ..........115, 121Output Dot Clock Control.................................636Peripheral Clock (CLKP)....................................80Selecting a Clock for the UART ........................353Selection of Source Clock...................................74USB Clock ......................................................749

Clock Control RegisterClock Control Register (ICCR) .........................376

Clock Disable RegisterClock Disable Register (IDBL) .........................384

Clock DivisionClock Division...................................................81

Clock Generation ControlClock Generation Control ...................................74

Clock Source Control RegisterClock Source Control Register (CLKR) ...............90

Clock SupplyOperation of Clock Supply Function ..........115, 121

Clock Synchronous ModeClock Synchronous Mode .................................354

784

INDEX

ColorCharacter Background Color (Setting for Each

Screen,Selected from Among 16 Colors)..........................................................607

Character Colors (Setting for Each Character, Selectedfrom among 16 Colors)........................578

Code of the Color to be Replaced by the Trimming Color (Setting for Each Screen) ............597

Color to be Replaced by the Character Color (Setting for Each Screen) .....................598

Command 6-1 (Shaded Background Frame Color Control) .............................................671

Command 6-2 (Transparent/Translucent Color Control) .............................................673

Command 6-3 (Graphic Color Control) ..............674Display Position Control of Screen Background

Color .................................................563Graphic Color/Character Color Replace Control

(Setting for Each Screen) .....................598Graphic Color/Trimming Color Replace Control

(Setting for Each Screen) .....................597Line Background Color (Setting for Each

Line,Selected From Among 16 Colors)..........................................................615

Screen Background Color Control .....................628Shaded Background Highlight Color (Setting for Each

Screen,Selected from Among 16 Colors)..................................................607, 615

Shaded Background Shadow Color (Setting for EachScreen,Selected from Among 16 Colors)..................................................607, 615

Trimming Colors .............................................590Command

Automatic Response of Macro Program to USB Standard Request Commands ...............509

Command 0 (VRAM Write Address Set) ...........662Command 1 (Character Data Set 1)....................663Command 11-0 (Synchronization Control) .........681Command 11-1 (Dot Clock Control 1) ...............682Command 11-2 (Dot Clock Control 2) ...............683Command 11-3 (Dot Clock Control 3) ...............684Command 13-0 (I/O Pin Control) ......................685Command 13-1 (I/O Pin Control 2)....................686Command 14-0 (Display Period Control 1).........687Command 14-1 (Display Period Control 2).........688Command 14-2 (Display Period Control 3).........688Command 14-3 (Display Period Control 4).........689Command 15-0 (Interrupt Control) ....................690Command 17-0 (OSDC Operation Control 1)

..........................................................693Command 17-1 (OSDC Operation Control 2)

..........................................................694Command 2 (Character Data Set 2)....................664Command 3 (Line Control Data Set 1) ...............665Command 4 (Line Control Data Set 2) ...............666Command 5-00 (Screen Output Control A).........667Command 5-1 (Screen Output Control 2) ...........668

Command 5-2 (Vertical Display Position Control)......................................................... 669

Command 5-3 (Horizontal Display Position Control) ............................................. 669

Command 6-0 (Character Vertical Size Control)......................................................... 670

Command 6-1 (Shaded Background Frame Color Control) ............................................. 671

Command 6-2 (Transparent/Translucent Color Control) ............................................. 673

Command 6-3 (Graphic Color Control).............. 674Command 7-1 (Screen Background Character


Control 2) .......................................... 677Command 8-1 (Sprite Character Control 1) ........ 678Command 8-2 (Sprite Character Control 2) ........ 679Command 9-0 (Sprite Character Control 3) ........ 679Command 9-1 (Sprite Character Control 4) ........ 680Commands 16-0 to 16-15 (Palette Control) ........ 691Display Control Commands of OSDC ............... 658List of Display Control Commands ................... 659Setup Stage of Control Transfer

(Most Standard Commands)................ 476Status Stage of Control Transfer

(Most Standard Commands) ................ 478Communication Error

Communication Error that Causes No Error ....... 388Compare Instructions

Compare Operation Instructions........................ 762Connector

Detection of USB Connector Connection and Disconnection .................................... 513

CONTCONT1........................................................... 460CONT10......................................................... 471CONT2........................................................... 462CONT3........................................................... 464CONT4........................................................... 465CONT5........................................................... 466CONT6........................................................... 467CONT7........................................................... 468CONT8........................................................... 469CONT9........................................................... 470

Control Status RegisterBit Configuration of the Control Status Register

(TMCSR)........................................... 230Register Configurations of Control Status Registers

(PCNH and PCNL) ............................. 244Control Transfer

Control Transfer (Data Stage) and BULK OUT Transfer ............................................. 479

Control Transfer (Data Stage),bulk Transfer,or INTERRUPT IN Transfer.................... 480

Precautions for Control Transfer ....................... 516

785

INDEX

Setting of Transfer Enable (BFOK) Bits during Control Transfer ...................... 515

Setup Stage of Control Transfer (Class and Vendor Commands and Some Standard Commands [Get_Descriptor, Set_Descriptor, and Synch_Frame]) .................................. 477

Setup Stage of Control Transfer (Most Standard Commands) ................ 476

Status Stage of Control Transfer (Class and Vendor Commands and Some Standard Commands [Get_Descriptor, Set_Descriptor, and Synch_Frame]) .................................. 478

Status Stage of Control Transfer (Most Standard Commands) ................ 478

Control/Status RegisterControl/Status Register B

(DMACB0 to DMACB4) .................... 404Control/Status Registers A (DMACA0 to 4)

......................................................... 399Coprocessor

Coprocessor Error Trap...................................... 61No-coprocessor Trap ......................................... 60

Coprocessor Control InstructionsCoprocessor Control Instructions ...................... 777

Coprocessor Error TrapCoprocessor Error Trap...................................... 61

CorrectionField Correction Control .................................. 644

Count ClockCount Clock Selection ..................................... 286

CPUCPU Control ................................................... 428FR CPU.............................................................. 2FR-CPU ROM Mode (32 Bits,Read only).......... 705Timing Diagram for BULK IN Transfer (Writing by

CPU and Reading by USB) ................. 502Timing Diagram for BULK OUT Transfer (Reading

by CPU and Writing by USB).............. 504CPU Access

Example of Controlling Reception at CPU Access......................................................... 493

Example of Controlling Transmission at CPU Access......................................................... 495

CPU ClockCPU Clock (CLKB) .......................................... 79

CPU IN TransferCPU IN Transfer ............................................. 482

CPU ModeConfiguration of Flash Control/Status Register

(FLCR) (CPU Mode) .......................... 701CPU OUT Transfer

CPU OUT Transfer ......................................... 484CSER

Configuration of the Chip Select Enable Register (CSER) ............................................. 150

Functions of Bits in the Chip Select Enable Register (CSER) ..............................................150

CSXCSX ->RD/WR Setup ......................................196Operation Timing for the CSX ->RD/WR Setup and

RD/WR ->CSX Hold Settings ..............189CSX Delay Setting

Operation Timing for the CSX Delay Setting.........................................................188

CTBRTime-Base Counter Clear Register (CTBR) ..........90

CycleAuto-Wait Cycle Timing ..................................184External Wait Cycle Timing..............................185

D

D+ Terminating ResistorControlling the D+ Terminating Resistor on the Board

.........................................................508Data Access

Data Access.......................................................41Data Bus Width

Data Bus Width .......................................159, 167Relationship between Data Bus Width and Control

Signal ................................................157Data Direction Registers

Configuration of the Data Direction Registers (DDR).........................................................217

Data FormatData Format ............................................158, 166

Data RegisterData Register (IDAR).......................................383

Data SetCommand 1 (Character Data Set 1)....................663Command 2 (Character Data Set 2)....................664Command 3 (Line Control Data Set 1) ...............665Command 4 (Line Control Data Set 2) ...............666

Data StageControl Transfer (Data Stage) and BULK OUT

Transfer .............................................479Control Transfer (Data Stage),bulk Transfer,or

INTERRUPT IN Transfer ....................480Data Types

Data Types ......................................................427DDR

Configuration of the Data Direction Registers (DDR).........................................................217

Default StatusUSB Function Macro Program Operation

in the Default Status ............................511Delay

Operation Timing for the CSX Delay Setting.........................................................188

786

INDEX

Delay SlotBranch Instruction with Delay Slot ......................43Branch Instruction without Delay Slot..................45Precaution on Delay Slot ....................................61

Delayed Branch20-Bit Delayed Branch Macro Instructions .........77332-Bit Delayed Branch Macro Instructions .........775

Delayed Branch InstructionsDelayed Branch Instructions .............................770

Delayed Interrupt Control RegisterDelayed Interrupt Control Register (DICR: Delayed

Interrupt Control Register) ...................317Delayed Interrupt Module

Block Diagram of the Delayed Interrupt Module..........................................................316

Delayed Interrupt Module Registers...................317Demand Transfer

Demand Transfer .............................................438Detection

0 Detection ......................................................3221 Detection ......................................................322Change Point Detection ....................................323Detection of USB Connector Connection and

Disconnection.....................................513Examples of Vertical Synchronization Detection

Operation ...........................................639Field Detection Control ....................................642Slave Address Detection ...................................386Vertical Synchronization Detection....................638

Detection Result RegisterDetection Result Register (BSRR) .....................321

Device InitializationReset (Device Initialization)................................65

Device State ControlDevice State Control ........................................101

Device StatesTransition of Device States ...............................102

DevicesExample of Connection with External Devices

..........................................................164Examples of Connection with External Devices

..........................................................168DICR

Delayed Interrupt Control Register (DICR: Delayed Interrupt Control Register) ...................317

DLYI Bit of DICR ...........................................318Dimensions

Dimensions of the MB91310.................................7Direct Addressing Instructions

Direct Addressing Instructions ..........................776Display Control Command

Display Control Commands of OSDC................658Display Control Commands

List of Display Control Commands....................659

Display ExampleApplied Display Examples ............................... 577Display Example ..................... 580, 582, 586, 650

Display ExamplesDisplay Examples

......... 575, 608, 610, 612, 614, 616, 618Line Enlarged Display Examples ...................... 592

Display FormatDisplay Format................................................ 600

Display FunctionsOSDC Display Functions ................................. 553

Display MemoryDisplay Memory and Display Screen ................. 568Writing to Display Memory .............................. 569

Display PeriodCommand 14-0 (Display Period Control 1) ........ 687Command 14-1 (Display Period Control 2) ........ 688Command 14-2 (Display Period Control 3) ........ 688Command 14-3 (Display Period Control 4) ........ 689

Display Period ControlCommand 14-0 (Display Period Control 1) ........ 687Command 14-1 (Display Period Control 2) ........ 688Command 14-2 (Display Period Control 3) ........ 688Command 14-3 (Display Period Control 4) ........ 689

Display PositionCommand 5-2 (Vertical Display Position Control)

......................................................... 669Command 5-3 (Horizontal Display Position Control)

......................................................... 669Display Position Control

Display Position Control of Screen Background Characters .......................................... 562

Display Position Control of Screen Background Color ................................................. 563

Display Position Control of Sprite Characters......................................................... 564

Display Position Control on the Main Screen......................................................... 559

Display ScreenDisplay Memory and Display Screen ................. 568

Display SignalDisplay Signal Output Timing .......................... 645Example of Display Signal Output (1) ............... 645Example of Display Signal Output (2) ............... 647

DivisionClock Division .................................................. 81

DIVRBase Clock Division Setting Register 0 (DIVR0)

........................................................... 93Base Clock Division Setting Register 1 (DIVR1)

........................................................... 94DLYI Bit

DLYI Bit of DICR ........................................... 318

787

INDEX

DMAClearing Peripheral Interrupts by DMA ............. 431DMA Access Operation ................................... 200DMA Transfer during Sleep ............................. 433Example of Controlling DMA Reception ........... 498Example of Controlling DMA Transmission

......................................................... 499Notes on UART Communication Using DMA

......................................................... 338Read and Write Timing Diagrams for DMA Block

Transfer............................................. 488Read and Write Timing Diagrams for DMA Single

Transfer............................................. 487DMA Block Transfer

Read and Write Timing Diagrams for DMA Block Transfer............................................. 488

DMA ControllerDMA Controller (DMAC) registers................... 397DMAC (DMA Controller).................................... 3

DMA Fly-By TransferDMA Fly-By Transfer (I/O ->Memory)............. 201DMA Fly-By Transfer (Memory ->I/O)............. 203Operation Timing for DMA Fly-By Transfer

(I/O ->Memory) ................................. 190Operation Timing for DMA Fly-By Transfer

(Memory ->I/O) ................................. 191DMA IN Transfer

DMA IN Transfer............................................ 485DMA OUT Transfer

DMA OUT Transfer ........................................ 486DMA Reception

Example of Controlling DMA Reception ........... 498DMA Single Transfer

Read and Write Timing Diagrams for DMA Single Transfer............................................. 487

DMA TransmissionExample of Controlling DMA Transmission

......................................................... 499DMAC

Configuration of the I/O Wait Registers for DMAC (IOWR0 to IOWR2) ........................... 147

DMA Controller (DMAC) registers................... 397DMAC (DMA Controller).................................... 3DMAC Interrupt Control.................................. 433Functions of Bits in the I/O Wait Registers for DMAC

(IOWR0 to IOWR2) ........................... 147DMAC Interrupt Control

DMAC Interrupt Control.................................. 433DMACA

Control/Status Registers A (DMACA0 to 4) ...... 399DMACB

Control/Status Register B (DMACB0 to DMACB4) .................... 404

DMACRAll-Channel Control Register (DMACR)........... 413

DMADATransfer Source/Transfer Destination Address Setting

Registers (DMASA0 to DMASA4/DMADA0 to DMADA4) .....................411

DMASATransfer Source/Transfer Destination Address Setting


Dot ClockCommand 11-1 (Dot Clock Control 1) ...............682Command 11-2 (Dot Clock Control 2) ...............683Command 11-3 (Dot Clock Control 3) ...............684Dot Clock........................................................748Dot Clock Generation PLL ...............................748External Dot Clock Input ..................................633Input Dot Clock Selection Control .....................633Internal VCO Generation Dot Clock Input..........634Output Dot Clock Control.................................636

Dot Clock ControlCommand 11-1 (Dot Clock Control 1) ...............682Command 11-2 (Dot Clock Control 2) ...............683Command 11-3 (Dot Clock Control 3) ...............684

Dot Clock Generation PLLDot Clock Generation PLL ...............................748

Double BufferDouble Buffer..................................................502

DRCL RegisterDRCL Register ................................................351

Duty RatioBlink Duty Ratio..............................................603

E

EIRRExternal Interrupt Request Register (EIRR) ........309

EITEIT (Exception,Interrupt,and Trap)......................47EIT Causes........................................................47EIT Operations ..................................................58EIT Vector Table ...............................................52Priority of EIT Causes To Be Accepted................56Return from EIT ................................................47

EIT CausesEIT Causes........................................................47Priority of EIT Causes To Be Accepted................56

ELVRExternal Interrupt Request Level Setting Register

(ELVR)..............................................310End Point Buffer

Setting of End Point Buffer ...............................490End/Stopping

Operation End/Stopping ...................................432Endian

Differences between Little Endian and Big Endian.........................................................165

788

INDEX

Restrictions on the Little Endian Area ................165ENIR

Interrupt Enable Register (ENIR) ......................308Enlargement Control

Line Enlargement Control (Setting for Each Line)..........................................................591

Enter Timer Control RegisterEnter Timer Control Register (TxR)...................267

EraseSector Erase Restart .........................................723Temporary Sector Erase Stop ............................722Writing/Erase ..................................................715

ErasureData Erasure (Chip Erasure)..............................719Sector Erasure .................................................720

ErrorBus Error ........................................................388Communication Error that Causes No Error........388Stopping Due To an Error .................................432

Event Count ModeEvent Count Mode ...........................................272

Example of ConnectionExample of Connection with External Devices


..........................................................168Example of Setting

Example of Setting the Chip Select Area ............156Example of Setting U-TIMER Baud Rates and Reload

Values................................................361Exception

EIT (Exception,Interrupt,and Trap) ......................47Operation of Undefined Instruction Exception

............................................................60Execution Status

Automatic Algorithm Execution Status ..............706Extended Display

Character Background Extended Display (Setting for Each Line) ........................613

External BusExternal Bus Access.........................................160External Bus Interface Setting ...........................752

External Bus ClockExternal Bus Clock (CLKT)................................80

External DevicesExample of Connection with External Devices


..........................................................168External Dot Clock

External Dot Clock Input ..................................633External I/O

2-Cycle Transfer (Internal RAM ->External I/O,RAM) .............................205

External InterruptBlock Diagram of the External Interrupt and

NMI Controller................................... 306External Interrupt and NMI Controller Registers

......................................................... 307Operating Procedure for an External Interrupt

......................................................... 311Operation of an External Interrupt ..................... 311

External Interrupt Request LevelExternal Interrupt Request Level ....................... 312

External Interrupt Request Level Setting RegisterExternal Interrupt Request Level Setting Register

(ELVR) ............................................. 310External Interrupt Request Register

External Interrupt Request Register (EIRR)........ 309External Transfer

External Transfer Request Pin........................... 418External Trigger

A/D Conversion Started by External Trigger ...... 334External Wait

With External Wait .......................................... 195Without External Wait ..................................... 194

External Wait CycleExternal Wait Cycle Timing ............................. 185

F

Field Correction ControlField Correction Control................................... 644

Field Detection ControlField Detection Control .................................... 642

FIFOFIFO0i............................................................ 450FIFO0o........................................................... 450FIFO1............................................................. 450FIFO2............................................................. 451FIFO3............................................................. 452

FilterLow-Pass Filter ............................................... 274

FlagHardware Sequence Flag .................................. 711I Flag................................................................ 48Interrupt Factor Flags....................................... 653Occurrence of Interrupts and Timing for Setting

Flags ................................................. 356Flash Control/Status Register

Configuration of Flash Control/Status Register (FLCR) (CPU Mode) .......................... 701

Flash MemoryList of Flash Memory Registers ........................ 700Outline of Flash Memory ................................. 696

FLCRConfiguration of Flash Control/Status Register

(FLCR) (CPU Mode) .......................... 701

789

INDEX

Fly-By TransferBurst Fly-by Transfer ...................................... 421Demand Transfer Fly-by Transfer ..................... 422DMA Fly-By Transfer (I/O ->Memory)............. 201DMA Fly-By Transfer (Memory ->I/O)............. 203Flow of Data During Fly-By Transfer................ 442Operation Timing for DMA Fly-By Transfer

(I/O ->Memory) ................................. 190Operation Timing for DMA Fly-By Transfer

(Memory ->I/O) ................................. 191Step/Block Transfer 2-Cycle Transfer Fly-by

Transfer............................................. 424Font

Font Memory Configuration ............................. 567FR

FR CPU.............................................................. 2FR Family Instruction Lists

FR Family Instruction Lists .............................. 761Frame Color

Command 6-1 (Shaded Background Frame Color Control)............................................. 671

FR-CPUFR-CPU Programming Mode (16 Bits,Read/Write)

......................................................... 705FR-CPU ROM Mode (32 Bits,Read only).......... 705

FR-CPU Programming ModeFR-CPU Programming Mode (16 Bits,Read/Write)

......................................................... 705FR-CPU ROM Mode

FR-CPU ROM Mode (32 Bits,Read only).......... 705

G

Get_DescriptorSetup Stage of Control Transfer (Class and Vendor

Commands and Some Standard Commands [Get_Descriptor, Set_Descriptor, and Synch_Frame]) .................................. 477


graphic CharacterCharacter/graphic Character Control (Setting for Each

Character).......................................... 595Graphic Color Control

Command 6-3 (Graphic Color Control) ............. 674Graphic Color/Character Color Replace Control

Graphic Color/Character Color Replace Control (Setting for Each Screen) .................... 598

Graphic Color/Trimming Color Replace ControlGraphic Color/Trimming Color Replace Control

(Setting for Each Screen) .................... 597

H

Halfword AccessHalfword Access..............................................172

Hardware ConfigurationHardware Configuration ...........................303, 394Hardware Configuration of the Interrupt Controller

.........................................................290Hardware Sequence Flag

Hardware Sequence Flag ..................................711HcBulkCurrentED Register

HcBulkCurrentED Register...............................536HcBulkHeadED Register

HcBulkHeadED Register ..................................535HcCommandStatus Register

HcCommandStatus Register..............................527HcControl Register

HcControl Register ..........................................525HcControlCurrentED Register

HcControlCurrentED Register...........................534HcControlHeadED Register

HcControlHeadED Register ..............................533HcDoneHead Register

HcDoneHead Register ......................................537HcFmInterval Register

HcFmInterval Register .....................................538HcFmNumber Register

HcFmNumber Register.....................................540HcFmRemaining Register

HcFmRemaining Register.................................539HcHCCA Register

HcHCCA Register ...........................................531HcInterruptDisable Register

HcInterruptDisable Register..............................530HcInterruptEnable Register

HcInterruptEnable Register...............................529HcInterruptStatus Register

HcInterruptStatus Register ................................528HcLSThreshold Register

HcLSThreshold Register...................................542HcPeriodCurrentED Register

HcPeriodCurrentED Register ............................532HcPeriodStart Register

HcPeriodStart Register .....................................541HcRevision Register

HcRevision Register.........................................524HcRhDescriptorA Register

HcRhDescriptorA Register ...............................543HcRhDescriptorB Register

HcRhDescriptorB Register................................544HcRhPortStatus

HcRhPortStatus [1 and 2] Register ....................546

790

INDEX

HcRhStatus RegisterHcRhStatus Register ........................................545

Highlight ColorShaded Background Highlight Color (Setting for Each

Screen,Selected from Among 16 Colors)..........................................................607

HoldOperation Timing for the CSX ->RD/WR Setup and

RD/WR ->CSX Hold Settings ..............189Hold Arbitration

Hold Arbitration ..............................................429Hold Request Cancel Request

Hold Request Cancellation Request (HRLC: Hold Request Cancel Request) .....................301

Hold Request Cancellation RequestHold Request Cancellation Request (HRLC: Hold

Request Cancel Request) .....................301Hold Request Cancellation Request Level Setting

RegisterHold Request Cancellation Request Level Setting

Register (HRCL).................................296Hold Request Cancellation Request Sequence

Hold Request Cancellation Request Sequence..........................................................304

Horizontal Display Period ControlHorizontal Display Period Control .....................649

Horizontal Display Position ControlCommand 5-3 (Horizontal Display Position Control)

..........................................................669Horizontal Size

Character Horizontal Size Control (Setting for Each Character) .................574

Horizontal Synchronous OperationExample of Horizontal Synchronous Operation

..........................................................640Horizontal Synchronous Operation ....................640

HostUSB Host Function ..............................................5

Host InterfaceUSB Host Interface ..........................................520

How to Read the Instruction ListsHow to Read the Instruction Lists ......................756

HRCLHold Request Cancellation Request Level Setting

Register (HRCL).................................296HRLC

Hold Request Cancellation Request (HRLC: Hold Request Cancel Request) .....................301

I

I FlagI Flag ................................................................48

I/O MapI/O Map .......................................................... 726

I/O PinCommand 13-0 (I/O Pin Control) ...................... 685Command 13-1 (I/O Pin Control 2) ................... 686I/O Pins .......................................................... 127

I/O Pin ControlCommand 13-0 (I/O Pin Control) ...................... 685Command 13-1 (I/O Pin Control 2) ................... 686

I/O PortBasic Block Diagram of the I/O Port ................. 214I/O Port Modes................................................ 215I/O Ports ............................................................. 5

I/O Wait RegistersConfiguration of the I/O Wait Registers

for DMAC (IOWR0 to IOWR2)........... 147Functions of Bits in the I/O Wait Registers

for DMAC (IOWR0 to IOWR2)........... 147I2C Interface

I2C Interface ....................................................... 4I2C Interface Registers ..................................... 366

IBCRBus Control Register (IBCR) ............................ 372

IBSRBus Status Register (IBSR)............................... 369

ICCRClock Control Register (ICCR) ......................... 376

ICRBit Configuration of the Interrupt Control Register

(ICR) ................................................. 294Configuration of Interrupt Control Register (ICR)

........................................................... 50Mapping of Interrupt Control Register (ICR)........ 50

IDARData Register (IDAR) ...................................... 383

IDBLClock Disable Register (IDBL) ......................... 384

ILMInterrupt Level Mask (ILM) Register ................... 49

Immediate SetImmediate Set/16-bit/32-bit Immediate Transfer

Instructions ........................................ 766Immediate Transfer Instructions

Immediate Set/16-bit/32-bit Immediate Transfer Instructions ........................................ 766

INITINIT Pin Input (Settings Initialization Reset Pin)

........................................................... 67Setting Initialization Reset (INIT) Clear Sequence

........................................................... 69Settings Initialization Reset (INIT) ...................... 66Settings Initialization Reset (INIT) State ............ 105

791

INDEX

Initial ValuesInitial Values and Functions of the Port Function

Registers (PFRs) ................................ 219Initialization

INIT Pin Input (Settings Initialization Reset Pin)........................................................... 67

Operation Initialization Reset (RST) ................... 66Operation Initialization Reset (RST) Clear Sequence

........................................................... 69Operation Initialization Reset (RST) State ......... 104Reset (Device Initialization) ............................... 65Setting Initialization Reset (INIT) Clear Sequence

........................................................... 69Settings Initialization Reset (INIT)...................... 66Settings Initialization Reset (INIT) State ........... 105Wait Time after Setting Initialization .................. 77

Input Dot Clock Selection ControlInput Dot Clock Selection Control .................... 633

Input-Output CircuitInput-Output Circuit Types ................................ 16

Instruction20-Bit Delayed Branch Macro Instructions ........ 77320-Bit Normal Branch Macro Instructions ......... 77232-Bit Delayed Branch Macro Instructions ........ 77532-Bit Normal Branch Macro Instructions ......... 774Add-Subtract Instructions................................. 762Bit Manipulation Instructions ........................... 764Branch Instruction with Delay Slot ..................... 43Compare Operation Instructions ....................... 762Coprocessor Control Instructions ...................... 777Delayed Branch Instructions............................. 770Direct Addressing Instructions.......................... 776FR Family Instruction Lists .............................. 761How to Read the Instruction Lists ..................... 756Immediate Set/16-bit/32-bit Immediate Transfer

Instructions ........................................ 766Instruction Format ........................................... 760Logic Operation Instructions ............................ 763Memory Load Instructions ............................... 767Memory Store Instructions ............................... 768Multiply/Divide Instructions............................. 765Normal Branch (No Delay) Instructions ............ 769Operation of INT Instruction .............................. 59Operation of INTE Instruction ............................ 59Operation of RETI Instruction ............................ 61Operation of Undefined Instruction Exception

........................................................... 60Other Instructions............................................ 771Register-to-Register Transfer Instructions.......... 768Resource Instructions....................................... 776Shift Instructions ............................................. 766

InstructionsOverview of Instructions.......................31Instruction Format

Instruction Format ........................................... 760INT

Operation of INT Instruction .............................. 59

INTEOperation of INTE Instruction.............................59

InterfaceBus Interface .......................................................2External Bus Interface Setting ...........................752I2C Interface........................................................4

Internal ArchitectureInternal Architecture ..........................................28

Internal ClockInternal Clock Operation ..................................235

Internal RAM2-Cycle Transfer (Internal RAM ->

External I/O,RAM) .............................205Internal VCO

Internal VCO Generation Dot Clock Input..........634Interrupt

Block Diagram of the External Interrupt and NMI Controller...................................306

Clearing Peripheral Interrupts by DMA..............431Command 15-0 (Interrupt Control) ....................690DMAC Interrupt Control ..................................433EIT (Exception,Interrupt,and Trap)......................47External Interrupt and NMI Controller Registers

.........................................................307External Interrupt Request Level .......................312Interrupt Control ..............................................653Interrupt Controller ..............................................4Interrupt Factor Flags .......................................653Interrupt Generation Control .............................655Interrupt Levels .................................................48Interrupt Number .............................................318Interrupt Request Generation ............................287Interrupt Resources and Timing Chart................255Interrupt Stack ...................................................51Level Mask for Interrupt and NMI .......................49Main Clock Oscillation Stabilization Wait Timer

Interrupt .............................................120Occurrence of Interrupts and Timing for Setting

Flags..................................................356Operating Procedure for an External Interrupt

.........................................................311Operation of an External Interrupt .....................311Operation of User Interrupt/NMI .........................58Watch Timer Interrupt ......................................114

Interrupt ControlCommand 15-0 (Interrupt Control) ....................690

Interrupt Control RegisterBit Configuration of the Interrupt Control Register

(ICR) .................................................294Configuration of Interrupt Control Register (ICR)

...........................................................50Mapping of Interrupt Control Register (ICR) ........50

Interrupt ControllerHardware Configuration of the Interrupt Controller

.........................................................290

792

INDEX

Interrupt Controller ..............................................4Interrupt Controller Registers ............................292

Interrupt Enable RegisterInterrupt Enable Register (ENIR) ......................308

Interrupt FactorInterrupt Factor Flags .......................................653

Interrupt GenerationInterrupt Generation Control .............................655

INTERRUPT IN TransferControl Transfer (Data Stage),bulk Transfer,or

INTERRUPT IN Transfer ....................480Interrupt Level Mask

Interrupt Level Mask (ILM) Register ...................49Interrupt Levels

Interrupt Levels .................................................48Interrupt Number

Interrupt Number .............................................318Interrupt Request

Interrupt Request Generation.............................287Interrupt Resources

Interrupt Resources and Timing Chart................255Interrupt routine

Interrupt routine ...............................................391Interrupt Sources

Interrupt Sources..............................................489Interrupt Stack

Interrupt Stack ...................................................51Interrupt Vectors

Interrupt Vectors ..............................................744Interval Timer

Interval Timer Mode ........................................271Operation of Interval Timer Function.........115, 121Other Interval Timers ...........................................5

Interval Timer ModeInterval Timer Mode ........................................271

IOWRConfiguration of the I/O Wait Registers for DMAC

(IOWR0 to IOWR2) ............................147Functions of Bits in the I/O Wait Registers for DMAC

(IOWR0 to IOWR2) ............................147ISBA

7-bit Slave Address Register (ISBA)..................381ISMK

7-bit Slave Address Mask Register (ISMK) ........382Italic

Italic Display Rules ..........................................579Italic Character

Origin of Italic Character ..................................581Italic Display Control

Italic Display Control .......................................579Italic Display Rules

Italic Display Rules ..........................................579

ITBA10-bit Slave Address Register (ITBA) ............... 378

ITMK10-bit Slave Address Mask Register (ITMK)

......................................................... 379

L

Latch upPreventing a Latch up ........................................ 22

Level MaskLevel Mask for Interrupt and NMI ...................... 49

LimitationsLimitations........................................................ 23

LineCommand 3 (Line Control Data Set 1) ............... 665Command 4 (Line Control Data Set 2) ............... 666

Line Background ColorLine Background Color (Setting for Each

Line,Selected From Among 16 Colors)......................................................... 615

Line Background ControlLine Background Control

(Setting for Each Line) ........................ 615Line Character Vertical Size Type

Line Character Vertical Size Type Control (Setting for Each Line) ....................... 574

Line Enlargement ControlLine Enlargement Control (Setting for Each Line)

......................................................... 591Line RAM

Writing to Line RAM....................................... 571Little Endian

Differences between Little Endian and Big Endian ......................................... 165

Restrictions on the Little Endian Area ............... 165Logic Instructions

Logic Operation Instructions............................. 763Low-Pass Filter

Low-Pass Filter ............................................... 274Low-Pass Filter Control Register

Low-Pass Filter Control Register (TxLPCR)......................................................... 262

Low-Power Consumption ModeLow-Power Consumption Mode Setting Register

......................................................... 751Low-Power Consumption Mode Setting Register

Low-Power Consumption Mode Setting Register......................................................... 751

Low-power ModesLow-power Modes..................................... 24, 106

LPF Sampling IntervalsLPF Sampling Intervals .................................... 286

793

INDEX

M

Macro20-Bit Delayed Branch Macro Instructions ........ 77320-Bit Normal Branch Macro Instructions ......... 77232-Bit Delayed Branch Macro Instructions ........ 77532-Bit Normal Branch Macro Instructions ......... 774Automatic Response of Macro Program to USB

Standard Request Commands .............. 509Macro Program Status after USB Bus Reset....... 518USB Function Macro Program Operation

in the Default Status .......................... 511Main Clock Oscillation Stabilization Wait Timer

Main Clock Oscillation Stabilization Wait Timer......................................................... 117

Main Clock Oscillation Stabilization Wait Timer (for the sub clock select) ..................... 100

Operation of the Main Clock Oscillation Stabilization Wait Timer ........................................ 122

Precautions on Using the Main Clock Oscillation Stabilization Wait Timer ..................... 122

Main Clock Oscillation Stabilization Wait Timer Control Register

Main Clock Oscillation Stabilization Wait Timer Control Register ................................. 119

Main Clock Oscillation Stabilization Wait Timer Interrupt

Main Clock Oscillation Stabilization Wait Timer Interrupt ............................................ 120

Main routineMain routine ................................................... 390

Main ScreenDisplay Position Control on the Main Screen

......................................................... 559Mask

Level Mask for Interrupt and NMI ...................... 49Slave Address Mask ........................................ 386

Master AddressingMaster Addressing........................................... 387

MB91310Dimensions of the MB91310 ................................ 7Pin Layout of the MB91310 ................................. 8

MDMode Pins (MD0 to MD3) ................................. 22

Memory Load InstructionsMemory Load Instructions ............................... 767

Memory MapMemory Map ...................................... 26, 42, 698

Memory SpaceMemory Space .................................................. 26

Memory Store InstructionsMemory Store Instructions ............................... 768

ModeAddressing Mode ............................................ 426

Asynchronous (Start-stop Synchronization) Mode.........................................................353

Bus Modes ........................................................62Capture Mode..................................................273Clock Synchronous Mode .................................354Configuration of Flash Control/Status Register

(FLCR) (CPU Mode) ..........................701Event Count Mode ...........................................272FR-CPU Programming Mode (16 Bits,Read/Write)

.........................................................705FR-CPU ROM Mode (32 Bits,Read only) ..........705I/O Port Modes ................................................215Interval Timer Mode ........................................271Low-power Modes .....................................24, 106Mode Settings....................................................63One-shot Mode ................................................253One-shot Mode Timing Charts ..........................253Operating Modes .......................................62, 352PWM Mode.....................................................251PWM Mode Timing Chart ................................251Return from Standby Mode (Sleep/Stop) ............302Screen Display Modes ......................................556Synchronous Mode Software Reset......................23Transfer Mode .................................................415Wait Time after Returning from Stop Mode .........78

Mode PinsMode Pins (MD0 to MD3) ..................................22

Multifunction TimerFeatures of the Multifunction Timer ..................260Multifunction Timer.............................................4Registers of the Multifunction Timer .................261

Multiplex AccessNormal Access or Address/Data Multiplex Access

.........................................................141Multiply Instructions

Multiply/Divide Instructions .............................765Multiply-by Rate

PLL Multiply-by Rate ........................................76Wait Time after Changing the PLL Multiply-by

Rate .....................................................77

N

NMIBlock Diagram of the External Interrupt and

NMI Controller...................................306External Interrupt and NMI Controller Registers

.........................................................307Level Mask for Interrupt and NMI .......................49NMI .......................................................300, 312Operation of User Interrupt/NMI .........................58

NMI ControllerBlock Diagram of the External Interrupt and

NMI Controller...................................306External Interrupt and NMI Controller Registers

.........................................................307

794

INDEX

No DelayNormal Branch (No Delay) Instructions .............769

No-coprocessor TrapNo-coprocessor Trap ..........................................60

Normal Branch20-Bit Normal Branch Macro Instructions ..........77232-Bit Normal Branch Macro Instructions ..........774Normal Branch (No Delay) Instructions .............769

Normal ResetNormal Reset Operation .....................................72

O

OffsetScreen Display Position Offset ..........................565

One-shot ModeOne-shot Mode ................................................253One-shot Mode Timing Charts ..........................253

Operating ModesOperating Modes .......................................62, 352

Operation InitializationOperation Initialization Reset (RST) ....................66Operation Initialization Reset (RST) Clear Sequence

............................................................69Operation Initialization Reset (RST) State ..........104

Operation TimingOperation Timing for DMA Fly-By Transfer

(I/O ->Memory) ..................................190Operation Timing for DMA Fly-By Transfer

(Memory ->I/O) ..................................191Operation Timing for Synchronous Write Enable

Output................................................186Operation Timing for the CSX ->RD/WR Setup and

RD/WR ->CSX Hold Settings ..............189Operation Timing for the CSX Delay Setting

..........................................................188Operation Timing of Read ->Write ....................182Operation Timing of the WR + Byte Control Type

..........................................................180Ordering

Bit Ordering ......................................................40Byte Ordering ....................................................40

Ordinary Bus InterfaceOrdinary Bus Interface .....................................178

OSCCROscillation Control Register (OSCCR) .................96

OscillationQuartz Oscillation Circuit ...................................22Source Oscillation Input at Power-on ...................23

Oscillation Control RegisterOscillation Control Register (OSCCR) .................96

Oscillation Stabilization WaitOscillation Stabilization Wait Reset (RST) Status

..........................................................104Oscillation Stabilization Wait RUN State ...........104

Sources of an Oscillation Stabilization Wait ......... 70Oscillation Stabilization Wait Time

Selecting an Oscillation Stabilization Wait Time........................................................... 71

OSDCCommand 17-0 (OSDC Operation Control 1)

......................................................... 693Command 17-1 (OSDC Operation Control 2)

......................................................... 694Display Control Commands of OSDC ............... 658Features of the OSDC ...................................... 550OSDC Control Functions.................................. 632OSDC Display Functions ................................. 553OSDC Operation Control ................................. 656

OSDC FunctionOSDC Function ................................................... 5

OSDC Operation ControlCommand 17-0 (OSDC Operation Control 1)

......................................................... 693Command 17-1 (OSDC Operation Control 2)

......................................................... 694OSDC Operation Control ................................. 656

Other InstructionsOther Instructions ............................................ 771

Output Dot Clock ControlOutput Dot Clock Control ................................ 636

Overall Block DiagramOverall Block Diagram of PPG Timer ............... 241

P

Palette ControlCommands 16-0 to 16-15 (Palette Control) ........ 691

Palette RAMPalette RAM Configuration .............................. 572

PCNHRegister Configurations of Control Status Registers

(PCNH and PCNL) ............................. 244PCNL

Register Configurations of Control Status Registers (PCNH and PCNL) ............................. 244

PCSRBit Configuration of PPG Cycle Setting Register

(PCSR) .............................................. 248PDR

Configuration of the Port Data Registers (PDR)......................................................... 216

PDUTBit Configuration of PPG Duty Setting Register

(PDUT) ............................................. 249Peripheral Clock

Peripheral Clock (CLKP) ................................... 80Peripheral Interrupts

Clearing Peripheral Interrupts by DMA ............. 431

795

INDEX

PFRConfiguration of the Port Function Registers (PFR)

......................................................... 218PFRs

Initial Values and Functions of the Port Function Registers (PFRs) ................................ 219

Pin FunctionsList of Pin Functions............................................ 9

Pin LayoutPin Layout of the MB91310 ................................. 8

Pin state listPin state list .................................................... 754

Pin/Timing Control RegisterConfiguration of the Pin/Timing Control Register

(TCR) ............................................... 153Functions of Bits in the Pin/Timing Control Register

(TCR) ............................................... 153PLL

Dot Clock Generation PLL............................... 748PLL Multiply-by Rate........................................ 76PLL Operation Enable ....................................... 75Wait Time after Changing the PLL Multiply-by

Rate .................................................... 77Wait Time after Enabling a PLL ......................... 77

Port Data RegistersConfiguration of the Port Data Registers (PDR)

......................................................... 216Port Function Registers

Configuration of the Port Function Registers (PFR)......................................................... 218

Initial Values and Functions of the Port Function Registers (PFRs) ................................ 219

Power Supply PinsPower Supply Pins ............................................ 22

Power-OffPrecautions at Power-On/Power-Off ................... 23

Power-OnPower-on .......................................................... 23Precautions at Power-On/Power-Off ................... 23Source Oscillation Input at Power-on .................. 23Wait Time after Power-On ................................. 77

PPGPPG ................................................................... 4PPG Output All-L and All-H ............................ 256

PPG Cycle Setting RegisterBit Configuration of PPG Cycle Setting Register

(PCSR).............................................. 248PPG Duty Setting Register

Bit Configuration of PPG Duty Setting Register (PDUT) ............................................. 249

PPG TimerBlock Diagram for One Channel of PPG Timer

......................................................... 242

Overall Block Diagram of PPG Timer................241Precautions on Using the PPG Timer .................257Registers of the PPG Timer...............................243

PPG Timer RegisterBit Configuration of PPG Timer Register (PTMR)

.........................................................250Prefetch

Prefetch Operation ...........................................197Principal Operations

Principal Operations.........................................415Priority

Priority Decision..............................................297Priority of EIT Causes To Be Accepted................56Priority of State Transition Requests ..................105

Program AccessProgram Access .................................................41

Programming ModeFR-CPU Programming Mode (16 Bits,Read/Write)

.........................................................705Programming Model

Basic Programming Model .................................33PTMR

Bit Configuration of PPG Timer Register (PTMR).........................................................250

Pulse Width Counter16-Bit Pulse Width Counter ..............................276Registers of the 16-Bit Pulse Width Counter

.........................................................277PWC

PWC...................................................................4PWC Control Register

PWC Control Register (PWCC2).......................283PWC Control Register (PWCCH) ......................280PWC Control Register (PWCCL) ......................278

PWC Data RegisterPWC Data Register (PWCD) ............................282

PWCCPWC Control Register (PWCC2).......................283

PWCCHPWC Control Register (PWCCH) ......................280

PWCCLPWC Control Register (PWCCL) ......................278

PWCDPWC Data Register (PWCD) ............................282

PWCUDUpper Value Setting Register (PWCUD)............284

PWMPWM Mode.....................................................251PWM Mode Timing Chart ................................251

PWM ModePWM Mode.....................................................251PWM Mode Timing Chart ................................251

796

INDEX

Q

Quartz Oscillation CircuitQuartz Oscillation Circuit ...................................22

R

RAM2-Cycle Transfer (Internal RAM ->

External I/O,RAM) .............................205Built-in RAM ......................................................3Palette RAM Configuration...............................572Writing a Single Character to Character RAM

..........................................................569Writing to Line RAM .......................................571

RD/WRCSX ->RD/WR Setup.......................................196Operation Timing for the CSX ->RD/WR Setup and

RD/WR ->CSX Hold Settings ..............189RDY

Ready/Busy Signal (RDY/BUSYX)...................711Read

Operation Timing of Read ->Write ....................182Read and Write Timing Diagrams for DMA Block

Transfer .............................................488Read and Write Timing Diagrams for DMA Single

Transfer .............................................487Read/Reset Status

Read/Reset Status ............................................716Ready/Busy Signal

Ready/Busy Signal (RDY/BUSYX)...................711REALOS

Bit Search Module (Used by REALOS) .................3Reload Timer (including One Channel for REALOS)

..............................................................3Reception

Example of Controlling DMA Reception............498Example of Controlling Reception at CPU Access

..........................................................493Recommended Setting

Recommended Setting Examples.......................753Register

0 Detection Data Register (BSD0) .....................3201 Detection Data Register (BSD1) .....................32010-bit Slave Address Mask Register (ITMK)

..........................................................37910-bit Slave Address Register (ITBA)................3787-bit Slave Address Mask Register (ISMK) ........3827-bit Slave Address Register (ISBA)..................381A/D Conversion Result Register

(ch.0 to ch.9) ......................................332A/D Converter Test Register .............................333A/DC Control Register (ADCTH,ADCTL).........329All-Channel Control Register (DMACR) ...........413Base Clock Division Setting Register 0 (DIVR0)

............................................................93


Bit Configuration of PPG Cycle Setting Register (PCSR) .............................................. 248

Bit Configuration of PPG Duty Setting Register (PDUT) ............................................. 249

Bit Configuration of PPG Timer Register (PTMR)......................................................... 250

Bit Configuration of the 16-bit Timer Register (TMR) ............................................... 233

Bit Configuration of the Control Status Register (TMCSR)........................................... 230

Bit Configuration of the Interrupt Control Register (ICR) ................................................. 294

Bus Control Register (IBCR) ............................ 372Bus Status Register (IBSR)............................... 369Capture Control Register (TxCCR) ................... 263Capture Data Register (TxCRR)........................ 269Change Point Detection Data Register (BSDC)

......................................................... 321Clock Control Register (ICCR) ......................... 376Clock Disable Register (IDBL) ......................... 384Clock Source Control Register (CLKR) ............... 90Configuration of Area Configuration Registers 0 to 7

(ACR0 to ACR7) ................................ 132Configuration of Area Select Registers 0 to 7

(ASR0 to ASR7)................................. 130Configuration of Flash Control/Status Register

(FLCR) (CPU Mode) .......................... 701Configuration of Interrupt Control Register

(ICR) ................................................... 50Configuration of the Area Wait Registers

(AWR0 to AWR7) .............................. 139Configuration of the Cache Enable Register

(CHER) ............................................. 152Configuration of the Chip Select Enable Register

(CSER) .............................................. 150Configuration of the Data Direction Registers

(DDR) ............................................... 217Configuration of the I/O Wait Registers for DMAC

(IOWR0 to IOWR2) ........................... 147Configuration of the Pin/Timing Control Register

(TCR)................................................ 153Configuration of the Port Data Registers (PDR)

......................................................... 216Configuration of the Port Function Registers (PFR)

......................................................... 218Control/Status Register B (DMACB0 to DMACB4)

......................................................... 404Control/Status Registers A (DMACA0 to 4)....... 399Data Register (IDAR) ...................................... 383Delayed Interrupt Control Register (DICR: Delayed

Interrupt Control Register)................... 317Detection Result Register (BSRR)..................... 321DMA Controller (DMAC) registers ................... 397DRCL Register................................................ 351Enter Timer Control Register (TxR) .................. 267

797

INDEX

External Interrupt Request Level Setting Register (ELVR) ............................................. 310

External Interrupt Request Register (EIRR) ....... 309Functions of Bits in the Area Configuration Registers

(ACR0 to ACR7) ............................... 134Functions of Bits in the Area Select Registers

(ASR0 to ASR7) ................................ 131Functions of Bits in the Area Wait Registers

(AWR0 to AWR7) ............................. 142Functions of Bits in the Cache Enable Register

(CHER) ............................................. 152Functions of Bits in the Chip Select Enable Register

(CSER) ............................................. 150Functions of Bits in the I/O Wait Registers for DMAC

(IOWR0 to IOWR2) ........................... 147Functions of Bits in the Pin/Timing Control Register

(TCR) ............................................... 153Functions of Bits in the Serial Status Register

(SSR) ................................................ 348HcBulkCurrentED Register .............................. 536HcBulkHeadED Register ................................. 535HcCommandStatus Register ............................. 527HcControl Register.......................................... 525HcControlCurrentED Register .......................... 534HcControlHeadED Register ............................. 533HcDoneHead Register ..................................... 537HcFmInterval Register..................................... 538HcFmNumber Register .................................... 540HcFmRemaining Register ................................ 539HcHCCA Register........................................... 531HcInterruptDisable Register ............................. 530HcInterruptEnable Register .............................. 529HcInterruptStatus Register ............................... 528HcLSThreshold Register .................................. 542HcPeriodCurrentED Register............................ 532HcPeriodStart Register..................................... 541HcRevision Register ........................................ 524HcRhDescriptorA Register............................... 543HcRhDescriptorB Register ............................... 544HcRhPortStatus [1 and 2] Register .................... 546HcRhStatus Register........................................ 545Hold Request Cancellation Request Level Setting

Register (HRCL) ................................ 296Initial Values and Functions of the Port Function

Registers (PFRs) ................................ 219Interrupt Enable Register (ENIR)...................... 308Interrupt Level Mask (ILM) Register .................. 49Low-Pass Filter Control Register (TxLPCR) ...... 262Low-Power Consumption Mode Setting Register

......................................................... 751Main Clock Oscillation Stabilization Wait Timer

Control Register ................................. 119Mapping of Interrupt Control Register (ICR) ....... 50Oscillation Control Register (OSCCR) ................ 96Procedure for Setting a Register........................ 210PWC Control Register (PWCC2) ...................... 283PWC Control Register (PWCCH) ..................... 280

PWC Control Register (PWCCL) ......................278PWC Data Register (PWCD) ............................282Register Configurations of Control Status Registers

(PCNH and PCNL) .............................244Reload Register (UTIMR) ................................223Reset Source Register/Watchdog Timer Control

Register (RSRR) ...................................83Serial Control Register (SCR) ...........................343Serial Input Data Register (SIDR)/Serial Output Data

Register (SODR).................................346Serial Mode Register (SMR) .............................341Serial Status Register (SSR)..............................347Software Conversion Analog Input Select Register

.........................................................331Standby Control Register (STCR)........................85Table Base Register (TBR) .................................52Test Data Register (TTEST)..............................270Time-Base Counter Clear Register (CTBR) ..........90Time-Base Counter Control Register (TBCR)

...........................................................87Timer Compare Data Register (TxDRR) ............268Timer Setting Register (TxTCR) .......................265Transfer Source/Transfer Destination Address Setting


Upper Value Setting Register (PWCUD)............284U-TIMER Control Register (UTIMC)................224Watch Timer Control Register...........................113

Register MapRegister Map ...................................................474

Register TypesRegister Types.................................................129

Register-to-Register Transfer InstructionsRegister-to-Register Transfer Instructions ..........768

ReloadReload Operation .............................................425

Reload RegisterBit Configuration of the 16-bit Reload Register

(TMRLR)...........................................234Reload Register (UTIMR) ................................223

Reload TimerOverview of the 16-bit Reload Timer.................228Reload Timer (including One Channel for REALOS)

.............................................................3Reload Values

Example of Setting U-TIMER Baud Rates and ReloadValues ...............................................361

RequestHold Request Cancellation Request (HRLC: Hold

Request Cancel Request) .....................301Reset

INIT Pin Input (Settings Initialization Reset Pin)...........................................................67

Macro Program Status after USB Bus Reset .......518Normal Reset Operation .....................................72

798

INDEX

Operation Initialization Reset (RST) ....................66Operation Initialization Reset (RST) Clear Sequence

............................................................69Operation Initialization Reset (RST) State ..........104Oscillation Stabilization Wait Reset (RST) Status

..........................................................104Read/Reset Status ............................................716RESET............................................................473Reset (Device Initialization)................................65Setting Initialization Reset (INIT) Clear Sequence

............................................................69Settings Initialization Reset (INIT) ......................66Settings Initialization Reset (INIT) State ............105Software Reset (STCR: SRST Bit Writing) ..........67Synchronous Mode Software Reset......................23Synchronous Reset Operation..............................72Tool Reset Pins (TRST)......................................22Watchdog Reset .................................................68

Reset Source Register/Watchdog Timer Control Register

Reset Source Register/Watchdog Timer Control Register (RSRR) ...................................83

ResistorControlling the D+ Terminating Resistor on the Board

..........................................................508Resource Instructions

Resource Instructions .......................................776RETI

Operation of RETI Instruction .............................61ROM

FR-CPU ROM Mode (32 Bits,Read only) ..........705routine

Interrupt routine ...............................................391Main routine ....................................................390

RSIZERSIZE0...........................................................458RSIZE1...........................................................459

RSRRReset Source Register/Watchdog Timer Control

Register (RSRR) ...................................83RST

Operation Initialization Reset (RST) ....................66Operation Initialization Reset (RST) Clear Sequence

............................................................69Operation Initialization Reset (RST) State ..........104Oscillation Stabilization Wait Reset (RST) Status

..........................................................104RUN State

Oscillation Stabilization Wait RUN State ...........104RUN State (Normal Operation) .........................103

S

Sampling IntervalsLPF Sampling Intervals ....................................286

Save/Restore ProcessingSave/Restore Processing................................... 324

SCRSerial Control Register (SCR) ........................... 343

Screen Background CharacterDisplay Position Control of Screen Background

Characters .......................................... 562Screen Background Character Control

Command 7-1 (Screen Background Character Control 1) .......................................... 676

Command 7-3 (Screen Background Character Control 2) .......................................... 677

Screen Background Character DisplayConfiguration of Screen Background Character

Display .............................................. 625Screen Background Character Display Control

Screen Background Character Display Control......................................................... 626

Screen Background ColorDisplay Position Control of Screen Background

Color ................................................. 563Screen Background Color Control

Screen Background Color Control ..................... 628Screen Background Display

Screen Background Display .............................. 624Screen Background Output Control

Screen Background Output Control ................... 628Screen Configuration

Screen Configuration ....................................... 554Screen Configuration Drawing.......................... 555

Screen Display ModesScreen Display Modes...................................... 556

Screen Display PositionScreen Display Position Offset.......................... 565

Screen Output ControlCommand 5-00 (Screen Output Control A) ........ 667Command 5-1 (Screen Output Control 2) ........... 668Screen Output Control...................................... 558

SectorSector Address Table ....................................... 699Sector Erase Restart ......................................... 723Temporary Sector Erase Stop............................ 722

Sector Address TableSector Address Table ....................................... 699

Sector EraseSector Erase Restart ......................................... 723Temporary Sector Erase Stop............................ 722

Sector ErasureSector Erasure ................................................. 720

Serial Control RegisterSerial Control Register (SCR) ........................... 343

Serial Input Data RegisterSerial Input Data Register (SIDR)/Serial Output Data

Register (SODR) ................................ 346

799

INDEX

Serial Mode RegisterSerial Mode Register (SMR) ............................ 341

Serial Output Data RegisterSerial Input Data Register (SIDR)/Serial Output Data

Register (SODR) ................................ 346Serial Status Register

Functions of Bits in the Serial Status Register (SSR) ................................................ 348

Serial Status Register (SSR) ............................. 347Set_Descriptor



Setting InitializationINIT Pin Input (Settings Initialization Reset Pin)

........................................................... 67Setting Initialization Reset (INIT) Clear Sequence

........................................................... 69Settings Initialization Reset (INIT)...................... 66Settings Initialization Reset (INIT) State ........... 105Wait Time after Setting Initialization .................. 77

Setup OperationExample of Controlling the Setup Operation

......................................................... 492Setup Stage


Shaded Background Frame Color ControlCommand 6-1 (Shaded Background Frame Color

Control)............................................. 671Shaded Background Highlight Color

Shaded Background Highlight Color (Setting for EachScreen,Selected from Among 16 Colors)................................................. 607, 615

Shaded Background Shadow ColorShaded Background Shadow Color (Setting for Each


Shaded Background Succeeding Character Merge Control

Shaded Background Succeeding Character Merge Control (Setting for Each Character)......................................................... 609

Shaded Background Succeeding Line Merge ControlShaded Background Succeeding Line Merge Control

(Setting for Each Line)................ 611, 617

Shadow ColorShaded Background Shadow Color (Setting for Each

Screen,Selected from Among 16 Colors).................................................607, 615

Shift InstructionsShift Instructions..............................................766

SIDRSerial Input Data Register (SIDR)/Serial Output Data

Register (SODR).................................346Slave Address Detection

Slave Address Detection ...................................386Slave Address Mask

Slave Address Mask .........................................386Slave Address Mask Register

10-bit Slave Address Mask Register (ITMK).........................................................379

7-bit Slave Address Mask Register (ISMK) ........382Slave Address Register

10-bit Slave Address Register (ITBA)................3787-bit Slave Address Register (ISBA)..................381

Sleep StateSleep State ......................................................103

SlotBranch Instruction with Delay Slot ......................43Branch Instruction without Delay Slot .................45Precaution on Delay Slot ....................................61

SMRSerial Mode Register (SMR) .............................341

SODRSerial Input Data Register (SIDR)/Serial Output Data

Register (SODR).................................346Software Conversion Analog Input Select Register

Software Conversion Analog Input Select Register.........................................................331

Software RequestSoftware Request .............................................419

Software ResetSoftware Reset (STCR: SRST Bit Writing) ..........67Synchronous Mode Software Reset......................23

Source ClockSelection of Source Clock...................................74

Source OscillationSource Oscillation Input at Power-on ...................23

Sprite CharacterDisplay Position Control of Sprite Characters

.........................................................564Sprite Character Configuration ..........................629

Sprite Character ControlCommand 8-1 (Sprite Character Control 1) ........678Command 8-2 (Sprite Character Control 2) ........679Command 9-0 (Sprite Character Control 3) ........679Command 9-1 (Sprite Character Control 4) ........680

Sprite Character Display ControlSprite Character Display Control .......................630

800

INDEX

SRAMSRAM Area ....................................................523

SRSTSoftware Reset (STCR: SRST Bit Writing) ..........67

SSPSystem Stack Pointer (SSP) ................................51

SSRFunctions of Bits in the Serial Status Register

(SSR).................................................348Serial Status Register (SSR) ..............................347

STST1.................................................................453ST2.................................................................454ST3.................................................................455ST4.................................................................456ST5.................................................................457

StackInterrupt Stack ...................................................51

Standard CommandSetup Stage of Control Transfer (Class and Vendor

Commands and Some Standard Commands [Get_Descriptor, Set_Descriptor, and Synch_Frame]) ...................................477

Setup Stage of Control Transfer (Most Standard Commands) .................476

Status Stage of Control Transfer (Class and Vendor Commands and Some Standard Commands [Get_Descriptor, Set_Descriptor, and Synch_Frame]) ...................................478

Status Stage of Control Transfer (Most Standard Commands) ................478

StandbyReturn from Standby ........................................311

Standby Control RegisterStandby Control Register (STCR)........................85

Standby ModeReturn from Standby Mode (Sleep/Stop) ............302

StartOperation Start ................................................429

START ConditionSTART Condition ............................................385

Start-stop SynchronizationAsynchronous (Start-stop Synchronization) Mode

..........................................................353State

Operation Initialization Reset (RST) State ..........104Oscillation Stabilization Wait RUN State ...........104RUN State (Normal Operation) .........................103Settings Initialization Reset (INIT) State ............105Sleep State ......................................................103Stop State ........................................................103

State TransitionPriority of State Transition Requests ..................105

StatusOscillation Stabilization Wait Reset (RST)

Status ................................................ 104Status Stage

Status Stage of Control Transfer (Class and Vendor Commands and Some Standard Commands [Get_Descriptor, Set_Descriptor, and Synch_Frame]) ................................... 478

STCRSoftware Reset (STCR: SRST Bit Writing) .......... 67Standby Control Register (STCR) ....................... 85

Step TraceOperation of Step Trace Trap .............................. 60

Step Trace TrapOperation of Step Trace Trap .............................. 60

Step/Block TransferStep/Block Transfer 2-Cycle Transfer................ 423Step/Block Transfer 2-Cycle Transfer Fly-by

Transfer ............................................. 424STOP Condition

STOP Condition .............................................. 385Stop Mode

Wait Time after Returning from Stop Mode ......... 78Stop State

Stop State ....................................................... 103Stopping

Stopping Due To an Error................................. 432sub clock

Main Clock Oscillation Stabilization Wait Timer (for the sub clock select)...................... 100

Successive AccessesBasic Timing (For Successive Accesses)............ 179

Suspended StatusExample of USB Clock Control

in the Suspended Status ....................... 512Sync Signal

Sync Signal Input ............................................ 637Synch_Frame

Setup Stage of Control Transfer (Class and Vendor Commands and Some Standard Commands [Get_Descriptor, Set_Descriptor, and Synch_Frame]) ................................... 477

Status Stage of Control Transfer (Class and Vendor Commands and Some Standard Commands [Get_Descriptor, Set_Descriptor, and Synch_Frame]) ................................... 478

SynchronizationAsynchronous (Start-stop Synchronization) Mode

......................................................... 353Examples of Vertical Synchronization Detection

Operation ........................................... 639Synchronization Control

(Vertical Enlargement Control) ............ 650Vertical Synchronization Detection ................... 638

801

INDEX

Synchronization ControlCommand 11-0 (Synchronization Control)......... 681Synchronization Control

(Vertical Enlargement Control)............ 650Synchronous Mode

Synchronous Mode Software Reset ..................... 23Synchronous Operation

Example of Horizontal Synchronous Operation......................................................... 640

Horizontal Synchronous Operation ................... 640Synchronous Reset

Synchronous Reset Operation ............................. 72Synchronous Write

Operation Timing for Synchronous Write Enable Output ............................................... 186

System Stack PointerSystem Stack Pointer (SSP)................................ 51

T

Table Base RegisterTable Base Register (TBR)................................. 52

TBCRTime-Base Counter Control Register (TBCR) ...... 87

TBRTable Base Register (TBR)................................. 52

TCRConfiguration of the Pin/Timing Control Register

(TCR) ............................................... 153Functions of Bits in the Pin/Timing Control Register

(TCR) ............................................... 153Temporary Sector Erase Stop

Temporary Sector Erase Stop ........................... 722Temporary Stopping

Temporary Stopping ........................................ 431Test Data Register

Test Data Register (TTEST) ............................. 270Text Display Control

Text Display Control Functions ........................ 573Time-Base Counter

Time-Base Counter............................................ 97Time-Base Counter Clear Register

Time-Base Counter Clear Register (CTBR) ......... 90Time-Base Counter Control Register

Time-Base Counter Control Register (TBCR)........................................................... 87

Timer Compare Data RegisterTimer Compare Data Register (TxDRR)............ 268

Timer RegisterBit Configuration of the 16-bit Timer Register

(TMR)............................................... 233Timer Setting Register

Timer Setting Register (TxTCR)....................... 265

Timing ChartInterrupt Resources and Timing Chart................255One-shot Mode Timing Charts ..........................253PWM Mode Timing Chart ................................251

Timing DiagramRead and Write Timing Diagrams for DMA Block

Transfer .............................................488Read and Write Timing Diagrams for DMA Single

Transfer .............................................487Timing Diagram for BULK IN Transfer (Writing by

CPU and Reading by USB) ..................502Timing Diagram for BULK OUT Transfer (Reading

by CPU and Writing by USB) ..............504TMCSR

Bit Configuration of the Control Status Register (TMCSR) ...........................................230

TMRBit Configuration of the 16-bit Timer Register

(TMR) ...............................................233TMRLR

Bit Configuration of the 16-bit Reload Register (TMRLR)...........................................234

Tool Reset PinsTool Reset Pins (TRST)......................................22

TraceOperation of Step Trace Trap ..............................60

Transfer2-Cycle Transfer (External ->I/O)......................2062-Cycle Transfer (I/O ->External)......................2072-Cycle Transfer (Internal RAM ->

External I/O,RAM) .............................205Block Transfer.................................................436Burst 2-Cycle Transfer .....................................420Burst Fly-by Transfer .......................................421Burst Transfer..................................................437Control Transfer (Data Stage) and BULK OUT

Transfer .............................................479Control Transfer (Data Stage),bulk Transfer,or

INTERRUPT IN Transfer ....................480CPU IN Transfer..............................................482CPU OUT Transfer ..........................................484Demand Transfer .............................................438Demand Transfer 2-Cycle Transfer ....................421Demand Transfer Fly-by Transfer......................422DMA Fly-By Transfer (I/O ->Memory) .............201DMA Fly-By Transfer (Memory ->I/O) .............203DMA IN Transfer ............................................485DMA OUT Transfer.........................................486DMA Transfer during Sleep ..............................433Flow of Data During 2-Cycle Transfer ...............439Flow of Data During Fly-By Transfer ................442Operation Timing for DMA Fly-By Transfer

(I/O ->Memory)..................................190Operation Timing for DMA Fly-By Transfer

(Memory ->I/O)..................................191Precautions for Control Transfer........................516

802

INDEX

Read and Write Timing Diagrams for DMA Single Transfer .............................................487

Selection of the Transfer Sequence ....................420Setting of Transfer Enable (BFOK) Bits during

Control Transfer .................................515Setup Stage of Control Transfer

(Most Standard Commands) .................476Status Stage of Control Transfer

(Most Standard Commands) .................478Step/Block Transfer 2-Cycle Transfer ................423Step/Block Transfer 2-Cycle Transfer Fly-by

Transfer .............................................424Timing Diagram for BULK IN Transfer (Writing by

CPU and Reading by USB) ..................502Timing Diagram for BULK OUT Transfer (Reading

by CPU and Writing by USB) ..............504Transfer Address..............................................416Transfer Count and Transfer End.......................417Transfer Count Control.....................................427Transfer Mode .................................................415Transfer Request Acceptance and Transfer .........430Transfer Type ..................................................416

Transfer 2-Cycle TransferDemand Transfer 2-Cycle Transfer ....................421

Transfer AddressTransfer Address..............................................416

Transfer CountTransfer Count and Transfer End.......................417

Transfer EnableSetting of Transfer Enable (BFOK) Bits

during Control Transfer .......................515Transfer End

Transfer Count and Transfer End.......................417Transfer Fly-by Transfer

Demand Transfer Fly-by Transfer......................422Transfer Mode

Transfer Mode .................................................415Transfer Request

Transfer Request Acceptance and Transfer .........430Transfer Source/Transfer Destination Address

Setting RegistersTransfer Source/Transfer Destination Address Setting


Transfer TypeTransfer Type ..................................................416

TransitionPriority of State Transition Requests ..................105Transition of Device States ...............................102

Translucent ColorCommand 6-2 (Transparent/Translucent Color

Control) .............................................673Translucent Color Control

Translucent Color Control (Setting for Each Screen)...............................................606

TransmissionExample of Controlling DMA Transmission

......................................................... 499Example of Controlling Transmission at CPU Access

......................................................... 495Transparent


Transparent Color ControlTransparent Color Control (Setting for Each Screen)

......................................................... 604Transparent/Translucent Color Control


TrapCoprocessor Error Trap ...................................... 61EIT (Exception,Interrupt,and Trap) ..................... 47No-coprocessor Trap.......................................... 60Operation of Step Trace Trap .............................. 60

Trimming ColorCode of the Color to be Replaced by the Trimming

Color (Setting for Each Screen)............ 597Graphic Color/Trimming Color Replace Control

(Setting for Each Screen)..................... 597Trimming Colors ............................................. 590

Trimming Display RulesTrimming Display Rules .................................. 590

Trimming Output ControlTrimming Output Control................................. 583

Trimming Type ControlTrimming Type Control ................................... 584

TRSIZETRSIZE .......................................................... 473

TRSTTool Reset Pins (TRST) ..................................... 22

TTESTTest Data Register (TTEST) ............................. 270

TTSIZETTSIZE .......................................................... 472

TxCCRCapture Control Register (TxCCR) ................... 263

TxCRRCapture Data Register (TxCRR)........................ 269

TxDRRTimer Compare Data Register (TxDRR) ............ 268

TxLPCRLow-Pass Filter Control Register (TxLPCR)

......................................................... 262TxR

Enter Timer Control Register (TxR) .................. 267TxTCR

Timer Setting Register (TxTCR) ....................... 265

803

INDEX

U

UARTExample of Using the UART............................ 359Notes on UART Communication Using DMA

......................................................... 338Selecting a Clock for the UART ....................... 353UART ................................................................ 3

UART CommunicationNotes on UART Communication Using DMA

......................................................... 338UCLK

Accuracy of UCLK48 ...................................... 514Undefined Instruction

Operation of Undefined Instruction Exception........................................................... 60

Underflow OperationUnderflow Operation ....................................... 236

Underline Display ControlUnderline Display Control ............................... 582

Underline Display RuleUnderline Display Rule.................................... 582

Unused Input PinsUnused Input Pins ............................................. 22

Upper Value Setting RegisterUpper Value Setting Register (PWCUD) ........... 284

USBAutomatic Response of Macro Program to USB

Standard Request Commands .............. 509Detection of USB Connector Connection and

Disconnection .................................... 513Example of USB Clock Control in the Suspended

Status ................................................ 512Macro Program Status after USB Bus Reset....... 518Registers of the USB Interface.......................... 522Timing Diagram for BULK IN Transfer (Writing by

CPU and Reading by USB) ................. 502Timing Diagram for BULK OUT Transfer (Reading

by CPU and Writing by USB).............. 504USB Host Interface ......................................... 520

USB BusMacro Program Status after USB Bus Reset....... 518

USB ClockUSB Clock ..................................................... 749

USB Clock ControlExample of USB Clock Control in the Suspended

Status ................................................ 512USB Connector

Detection of USB Connector Connection and Disconnection .................................... 513

USB FunctionOperation of the USB Function......................... 475Overview of the USB Function ......................... 444Supplementary Notes on the USB Function

......................................................... 501

USB Function......................................................5USB Function Macro Program Operation

in the Default Status ............................511USB Host Function

USB Host Function ..............................................5USB Host Interface

USB Host Interface ..........................................520USB Interface

Registers of the USB Interface ..........................522USB Interface Registers ...................................447

USB Standard Request CommandsAutomatic Response of Macro Program to USB

Standard Request Commands ...............509User Interrupt

Operation of User Interrupt/NMI .........................58UTIM

U-TIMER (UTIM) ...........................................223UTIMC

U-TIMER Control Register (UTIMC)................224U-TIMER

Example of Setting U-TIMER Baud Rates and ReloadValues ...............................................361

Overview of the U-TIMER ...............................222U-TIMER (UTIM) ...........................................223U-TIMER Registers .........................................223

U-TIMER Control RegisterU-TIMER Control Register (UTIMC) ................224

UTIMRReload Register (UTIMR) ................................223

V

VCOInternal VCO Generation Dot Clock Input..........634

Vector TableEIT Vector Table ...............................................52

Vender CommandStatus Stage of Control Transfer (Class and Vendor


Vendor CommandSetup Stage of Control Transfer (Class and Vendor


Vertical Display Period ControlVertical Display Period Control.........................648

Vertical Display Position ControlCommand 5-2 (Vertical Display Position Control)

.........................................................669Vertical Enlargement Control

Synchronization Control (Vertical Enlargement Control) ............650

804

INDEX

Vertical SizeCharacter Vertical Size A/B ..............................575Command 6-0 (Character Vertical Size Control)

..........................................................670Line Character Vertical Size Type Control

(Setting for Each Line) .......................574Vertical Synchronization Detection

Examples of Vertical Synchronization Detection Operation ...........................................639

Vertical Synchronization Detection....................638VRAM

Command 0 (VRAM Write Address Set) ...........662Writing Multiple Characters Collectively

(VRAM Fill) ......................................570

W

Wait CycleAuto-Wait Cycle Timing ..................................184External Wait Cycle Timing..............................185

Wait TimeWait Time after Changing the PLL Multiply-by

Rate .....................................................77Wait Time after Enabling a PLL ..........................77Wait Time after Power-On ..................................77Wait Time after Returning from Stop Mode..........78Wait Time after Setting Initialization ...................77

Wait TimerMain Clock Oscillation Stabilization Wait Timer

..........................................................117Main Clock Oscillation Stabilization Wait Timer

(for the sub clock select) ......................100Operation of the Main Clock Oscillation Stabilization

Wait Timer .........................................122

Precautions on Using the Main Clock OscillationStabilization Wait Timer ..................... 122

Watch TimerOperation of The Watch Timer ......................... 116Precautions for Using the Watch Timer.............. 116Watch Timer ............................................. 99, 111Watch Timer Interrupt...................................... 114

Watch Timer Control RegisterWatch Timer Control Register .......................... 113

Watchdog ResetWatchdog Reset ................................................ 68

Width Pulse CounterBasic Operation of the 16-Bit Width Pulse Counter

......................................................... 285Word Access

Word Access ................................................... 170WR + Byte Control Type

Operation Timing of the WR + Byte Control Type......................................................... 180

WriteOperation Timing for Synchronous Write Enable

Output ............................................... 186Operation Timing of Read ->Write.................... 182Write ->Write Operation .................................. 183

Write Timing DiagramsRead and Write Timing Diagrams

for DMA Block Transfer .................... 488Read and Write Timing Diagrams

for DMA Single Transfer..................... 487Writing

Data Writing ................................................... 717Writing/Erase .................................................. 715

805

INDEX

806

CM71-10119-2E

FUJITSU MICROELECTRONICS • CONTROLLER MANUAL

FR60

32-BIT MICROCONTROLLER

MB91310 Series

HARDWARE MANUAL

February 2009 the second edition

Published FUJITSU MICROELECTRONICS LIMITEDEdited Sales Promotion Dept.

32-BIT MICROCONTROLLER MB91310 Series … microelectronics controller manual fr60 32-bit...

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Transcript of 32-BIT MICROCONTROLLER MB91310 Series … microelectronics controller manual fr60 32-bit...