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Charge Steering: A Low-Power Design Paradigm

[1] Razavi, B., "Charge steering: A low-power design

paradigm," Custom Integrated Circuits Conference (CICC),

2013 IEEE , vol., no., pp.1,8, 22-25 Sept. 2013

doi: 10.1109/CICC.2013.6658443

INTRODUCTION

BASIC IDEA

CHARGE-STEERING LOGIC

CDR AND DEMUX DESIGN

CHARGE STEERING ADCs

CONCLUSION

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Introduction/Basic Idea

Transformation from current steering to charge steering [1]

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CHARGE-STEERING LOGIC

CDR AND DEMUX DESIGN

CHARGE-STEERING ADCs

Implementation

A 25Gb/s 5.8mW CMOS Equalizer [ISSCC 2014]

A 25-Gb/s 5-mW CMOS CDR/Deserializer [JSSC 2013]

A 10-bit 800-MHz 19-mW CMOS ADC [JSSC 2014]

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Summary

Take Away Message

Motivation

Proposed Solution Authors Evaluation

My Analysis

Future Directions Open Questions

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Future Work

Apply technique on other type of data converters, Equalizer

Circuit(FFE,CTLE, DFE)

A 25Gb/s 5.8mW CMOS equalizer

A 10-Bit 800-MHz 19-mW CMOS ADC

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References

[1] Razavi, B., "Charge steering: A low-power design paradigm," Custom Integrated Circuits

Conference (CICC), 2013 IEEE, vol., no., pp.1,8, 22-25 Sept. 2013

doi: 10.1109/CICC.2013.6658443[2] Jun Won Jung; Razavi, B., "A 25-Gb/s 5-mW CMOS CDR/Deserializer," Solid-State Circuits, IEEE

Journal of, vol.48, no.3, pp.684,697, March 2013

doi: 10.1109/JSSC.2013.2237692

[3] Chiang, S.-H.W.; Hyuk Sun; Razavi, B., "A 10-Bit 800-MHz 19-mW CMOS ADC," Solid-State

Circuits, IEEE Journal of, vol.49, no.4, pp.935,949, April 2014

doi: 10.1109/JSSC.2014.2300199[4] Jun Won Jung; Razavi, B., "2.4 A 25Gb/s 5.8mW CMOS equalizer," Solid-State Circuits

Conference Digest of Technical Papers (ISSCC), 2014 IEEE International , vol., no., pp.44,45, 9-13

Feb. 2014doi: 10.1109/ISSCC.2014.6757330