NJU7388B

- 1 - Ver.2019-04-10

3-PHASE BRUSHLESS DC MOTOR CONTROL IC with 150 SQUARE WAVE

GENERAL DESCRIPTION PACKAGE OUTLINE The NJU7388B is a 3-phase brushless DC motor controller with 150°

commutation and lead angle control functions, which provides low vibration, low noise and high efficiency motor driving. The NJU7388B generates 150° commutation 3-phase sequence

based on external hall signal and arbitrary lead angle setup. It has Clock Generator for reference clock of various functions such as

commutation angle, lead angle, PWM, lock protection, current detection. The NJU7388B is a 5V logic operation-specific control IC. Therefore, it corresponds to various applications by selecting Pch

MOSFETs and Nch MOSFETs as power stage. FEATURES Operating Voltage VDD=4.5V to 5.5V

150° Commutation Control Lead Angle Control 4bit A/D Input (0 to 28.125° / 16 steps) Internal Clock Generator fPWM=20kHz ±5% Hall Element Input Current Detection VDETLIM=0.5V 5% (Pulse by pulse)

PWM Control 6bit A/D (Duty=98.43% max. / 63 steps) FG Output Synchronized with H1 Forward / Reverse Direction Lock Protection (Latching type)

UVLO Protection Package SSOP20-C3

NJU7388BVC3

NJU7388B

- 2 - Ver.2019-04-10

BLOCK DIAGRAM

VREF UVLO

VERR

GND

VDD

OutputLogic

ControlLogic

-+

WL

VL

UL

WH

VH

UH

ILIMIT

PWMLogic

VLA

ClockGenerator

Lead Angle4Bit

A/D Conv.

6BitA/D

Conv.

H1-

H2-

H3-

H3+

H2+

H1+

FG

Lock DetCT

FR

NJU7388B

- 3 - Ver.2019-04-10

PIN CONFIGURATION SSOP20-C3 PIN DESCRIPTION

PIN No. PIN NAME FUNCTION NOTE 1 H1- Hall Input Pin H1- - 2 H1+ Hall Input Pin H1+ - 3 H2- Hall Input Pin H2- - 4 H2+ Hall Input Pin H2+ - 5 H3- Hall Input Pin H3- - 6 H3+ Hall Input Pin H3+ -

7 VLA Lead Angle Setting Pin Input the DC voltage for setting the lead angle At not using, connect to ground or OPEN

8 VERR Speed Control Pin Input the DC Voltage for setting the PWM Duty

9 FR Direction Setting Pin L or OPEN= Forward Rotation H= Reverse Rotation

10 FG FG Output Pin Rotation signal output synchronized with H1

11 CT Lock Protection Setting Pin Connect a capacitor between GND for setting ON time of lock protection. At not using, connect to Ground

12 GND Ground Pin Connect to Ground

13 ILIMIT Over Current Detection Pin Connect a detection resistor to the motor output element side to detect the motor current. At not using, connect to Ground

14 WH WH Output Pin W Phase High Side Output 15 VH VH Output Pin V Phase High Side Output 16 UH UH Output Pin U Phase High Side Output 17 WL WL Output Pin W Phase Low Side Output 18 VL VL Output Pin V Phase Low Side Output 19 UL UL Output Pin U Phase Low Side Output 20 VDD Power Supply Pin -

WL

20 19 18 17 16 15 14 13 12 11

1 2 3 4 5 6 7 8 9 10

H1- H1+ H2- H2+ H3- H3+ VLA

VERR FR FG

VDD UL VL

UH VH WH ILIMIT GND CT

NJU7388B

- 4 - Ver.2019-04-10

ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATINGS UNIT NOTES

Power Supply Pin Voltage VDD 7 V VDD Pin Output Pin Voltage Vo -0.3 to 7 V UH, VH, WH, UL, VL, WL Pin Output Pin Current Io 10 mA UH, VH, WH, UL, VL, WL Pin Hall Input Pin Voltage VIH -0.3 to 7 V H1+, H1-, H2+, H2-, H3+, H3- Pin A/D Input Pin Voltage VIN -0.3 to 7 V VLA , VERR Pin FR Input Pin Voltage VFR -0.3 to 7 V FR Pin ILIMIT Pin Voltage VILIM -0.3 to 7 V ILIMIT Pin FG Output Pin Voltage VFG -0.3 to 7 V FG Pin FG Output Pin Current IFG 5 mA FG Pin

Power Dissipation (Ta=25 C) PD 1.0 W Mounted on 2Layers PCB (*1) 1.5 W Mounted on 4Layers PCB (*2)

Junction Temperature Tj -40 to +150 C - Operating Temperature Topr -40 to +105 C - Storage Temperature Tstg -50 to +150 C -

(*1): Mounted on glass epoxy board. (76.2×114.3×1.6mm: based on EIA/JEDEC standard, 2Layers FR-4) (*2): Mounted on glass epoxy board. (76.2×114.3×1.6mm: based on EIA/JEDEC standard, 4Layers FR-4, inner Cu area 74.2×74.2mm) RECOMMENDED OPERATING CONDITIONS

PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT Power Supply Pin Voltage VDD 4.5 - 5.5 V Output Pin Current Io -3 - 3 mA A/D Input Pin Voltage VIN 0 - 5.5 V FG Output Pin Voltage VFG 0 - 5.5 V

PIN OPERATING CONDTIONS (VDD=5V, Ta=25 C)

PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT Hall Input Pin (H1+, H1-, H2+, H2-, H3+, H3- Pin) Hall Input Sensitivity VMIH peak to peak 0.04 - - V Hall Input Voltage Range VICMIH 0.6 - 4.0 V ILIMIT Pin ILIMIT Input Voltage Range VICMILIM 0 - 3.0 V FR Pin H Level Input Voltage VHFR 2.3 - 5.5 V L Level Input Voltage VLFR 0 - 0.8 V

NJU7388B

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ELECTRICAL CHARACTERISTICS (VDD=5V, Ta=25 C) PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT

GENERAL Operating Voltage VDD 4.5 5 5.5 V Quiescent Current IDD Non Load - 2.3 5.0 mA Internal Reference Voltage Vref 4.116 4.2 4.284 V UNDER VOLTAGE LOCK OUT BLOCK UVLO Detection Voltage VDUVLO Output Disable, VDD Decreasing 3.6 3.9 4.3 V UVLO Recovery Voltage VRUVLO Output Enable, VDD Increasing 3.8 4.1 4.5 V UVLO Hysteresis Voltage VUVLO - 0.2 - V HALL INPUT BLOCK Hysteresis Voltage Range VHYSIH 10 20 30 mV Input Bias Current IBIH Per 1 Input - - 1 µA HIGH SIDE / LOW SIDE OUTPUT BLOCK H Level Output Voltage VOH ISOURCE=3mA 4.3 4.8 - V L Level Output Voltage VOL ISINK=3mA - 0.02 0.7 V FG OUTPUT BLOCK L Level Output Voltage VFGL IFG=2mA - 0.01 0.7 V Leak Current IFGLEAK VFG=5.5V - - 1 µA OVER CURRENT DETECTION BLOCK Detection Voltage VDETLIM 0.475 0.5 0.525 V Input Bias Current IBLIM VLIM=0.5V - - 1 µA Blanking Time tBLIM 0.2 0.4 0.6 µs Delay Time tDLIM - 500 - ns VLA BLOCK

Lead Angle 1 ФVLA1 VINVLA=0V, fIH=100Hz,

ФIH(H1,H2,H3)=120° - 0 - °

Lead Angle 2 ФVLA2 VINVLA=4.5V, fIH=100Hz,

ФIH(H1,H2,H3)=120° - 28.125 - °

Input Bias Current IBVLA VINVLA=0V - - 1 µA Input Pull Down Resistance RVLA - 100 - kΩ VERR BLOCK PWM Oscillation Frequency fPWM 19 20 21 kHz Minimum PWM Duty PWMMIN VINVERR=1.317V - 1.56 - % Maximum PWM Duty PWMMAX VINVERR=4.5V - 98.43 - % LSB Threshold Voltage VPWMMIN 1.26 1.3 1.34 V Input Bias Current IBVERR VINVERR=0V - - 1 µA Input Pull Down Resistance RVERR - 100 - kΩ FR BLOCK Input Bias Current IBFR VFR=0V - - 1 µA Input Pull Down Resistance RFR - 120 - kΩ LOCK DETECTION BLOCK Lock Protection ON Time tONCT CCT=0.01µF - 5 - s H Level Detection Voltage VHCT - 3.5 - V L Level Detection Voltage VLCT - 1.0 - V Lock Charge Current ICHGCT 1.0 3.0 5.5 µA Lock Discharge Current IDCHGCT 1.0 3.0 5.5 µA

NJU7388B

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OPERATIONAL DEFINITION (PIN and CIRCUIT) Hall Input Pin Voltage Range Hall Input Hysteresis Voltage Width Under Voltage Protection Operating Voltage

VICMIH

4.0V

0.6V

<At VDD=5V> VICMIH

ΔVHYSIH

4.0V

0.6V

LogicInversion

LogicInversion

<At VDD=5V>

VDD

VRUVLO

VDUVLO

5.5V

4.5V

0V

ΔVUVLO : Hysteresis Voltage

UVLO Recovery Volage(Nomral Operation)

UVLO Detection Voltage(Output Stop)

Recommended Operating Voltage (min.)

Recommended Operating Voltage (max.)

NJU7388B

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VLA Pin Input the DC voltage for setting the lead angle. The VLA function has a built-in 4-bit A/D converter, and it can set the range of lead angle 0 to 28.125° in 16 steps.

*Theoretical Value

VLA PinVoltage [V] Lead Angle [ º]

0.000 0.0000.263 1.8750.525 3.7500.788 5.6251.050 7.5001.313 9.3751.575 11.2501.838 13.1252.100 15.0002.363 16.8752.625 18.7502.888 20.6253.150 22.5003.413 24.3753.675 26.2503.938 28.125

0

15

30

0 1 2 3 4 5

Lead

Ang

le [

º]

VLA Pin Voltage [V]

VLA Pin Voltage vs. Lead Angle(Theoretical Value)

NJU7388B

- 8 - Ver.2019-04-10

VERR Pin Input the DC voltage for speed control. The VERR function has a built-in 6-bit A/D converter, and it can set the PWM Duty in 63 steps. The maximum PWM duty is 98.43%. When 0V ≤ VINVERR < 1.294V typ., both high side and low side are L outputs. Also, if the speed command is directly supplied PWM signal, input after converting it into a DC signal by configuring two

RC filters externally. *Theoretical Value

0

10

20

30

40

50

60

70

80

90

100

0 1 2 3 4 5

PWM

Dut

y [%

]

VERR Pin Voltage [V]

VERR Pin Voltage vs. PWM Duty(Theoretical Value)

Output ON Period Output OFF Period

1.294 1.561.340 3.121.386 4.681.432 6.251.478 7.811.524 9.371.570 10.931.617 12.501.663 14.061.709 15.621.755 17.181.801 18.751.847 20.311.893 21.871.939 23.431.986 25.002.032 26.562.078 28.122.124 29.682.170 31.252.216 32.812.262 34.372.309 35.932.355 37.502.401 39.062.447 40.622.493 42.182.539 43.752.585 45.312.631 46.872.678 48.432.724 50.002.770 51.562.816 53.122.862 54.682.908 56.252.954 57.813.001 59.373.047 60.933.093 62.503.139 64.063.185 65.623.231 67.183.277 68.753.323 70.313.370 71.873.416 73.433.462 75.003.508 76.563.554 78.123.600 79.683.646 81.253.693 82.813.739 84.373.785 85.933.831 87.503.877 89.063.923 90.623.969 92.184.015 93.754.062 95.314.108 96.874.154 98.43

PWM Duty [%]VERR PinVoltage [V]

NJU7388B

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ILIMIT Pin The LIMIT function detects the over current of the motor current. When an overcurrent is detected, the low side outputs become L level after the internal circuit delay time (tDELAY). It resets the overcurrent function at fPWM cycle so that it operates with pulse-by-pulse. The detection voltage is 0.5V typ. Set the current detection resistance according to the detecting current value. When a spike current occurs due to the capacitance component of the output element etc., configure a low pass filter

externally for preventing false detection. For the low pass filter, the resistance is 5k to 10kΩ and the capacitor is about 1000pF as a guide.

CT Pin The lock status of motor rotation is detected by the time between the edges of each hall signal input. If the time between the edges of each hall signal input exceeds tH_LOCK(102.4ms typ.), the lock protection is activated. However, when VINVERR < 1.294V typ., the lock protection isn’t activated. During lock protection operation, CT pin performs charge / discharge operation to CCT. This cycle is internally counted, and an output period (tON) is generated. Even in the output period (tON), the lock detection is continued, and if the hall input signal period less than tH_LOCK is

detected, it becomes the normal operation state. If the output period (tON) has passed, then the low side outputs are latched to the L output as output OFF state. The state of the lock protection circuit is reset when the power restart or VINVERR voltage is less than 1.294V typ. If there is a possibility of misdetection of lock protection like low speed startup, it should be set enough output period (tON).

<Calculation formula>

tON [s] = 500 CCT [µF] e.g.) CCT=0.01µF: tON = 500 0.01= 5 [s]

VLCT

VHCT

tON

t

1.294V typ.

tON

4.1V typ.

Stopped Motor Rotation

Normal

Output ON, Lock Detection Period

Lock Protection

Output OFF, Lock Non-Detection Period

Operation

Output, Lock Detecton Status

Release the latching status Release the latching status

CT Pin Voltage

VERR Pin Voltage

Power Supply Pin Voltage

Low Side Output

ILIMIT Detection Signal(H=Detection)

tDELAY

PWM DUTY

L Output

PWM DUTY PWM DUTY PWM DUTY

Detection

tDELAY

Detection

L Output

NJU7388B

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INPUT vs. OUTPUT TRUTH TABLE <Hall Input pattern> The logic control block can receive the following input pattern only.

*The Starting point is free. If inputting other patterns, there is a possibility which causes a malfunction.

1 2 3 4 5 6

(H1+>H1-,H2+>H2-,H3+>H3-="H", Don't Care="X")No. H1 H2 H3 FR UVLO VERR ILIMIT CT UH VH WH UL VL WL FG STATUS

1 H L L L L H H/L L L L2 H H L L L H L H/L L L3 L H L H L L L H/L L Hi-Z4 L H H H L L L L H/L Hi-Z5 L L H L H L L L H/L Hi-Z6 H L H L H L H/L L L L1 H L L L2 H H L L3 L H L Hi-Z4 L H H Hi-Z5 L L H Hi-Z6 H L H L

1 H L L L L H L2 H H L L L H L3 L H L H L L Hi-Z4 L H H H L L Hi-Z5 L L H L H L Hi-Z6 H L H L H L L

1 H L L L L H L2 H H L L L H L3 L H L H L L Hi-Z4 L H H H L L Hi-Z5 L L H L H L Hi-Z6 H L H L H L L1 H L L L2 H H L L3 L H L Hi-Z4 L H H Hi-Z5 L L H Hi-Z6 H L H L

1 H L H H L L L H/L L L2 L L H L L H L H/L L Hi-Z3 L H H L L H H/L L L Hi-Z4 L H L L H L H/L L L Hi-Z5 H H L L H L L L H/L L6 H L L H L L L L H/L L1 H L H L2 L L H Hi-Z3 L H H Hi-Z4 L H L Hi-Z5 H H L L6 H L L L

1 H L H H L L L2 L L H L L H Hi-Z3 L H H L L H Hi-Z4 L H L L H L Hi-Z5 H H L L H L L6 H L L H L L L1 H L H H L L L2 L L H L L H Hi-Z3 L H H L L H Hi-Z4 L H L L H L Hi-Z5 H H L L H L L6 H L L H L L L

1 H L H L2 L L H Hi-Z3 L H H Hi-Z4 L H L Hi-Z5 H H L L6 H L L L

L L L L UVLO Detection(Reverse)

ON X X X L L

LLock Detection

(Reverse)(Output OFF Period)

OFF X H X L L LOver Current Detection

(Reverse)(Output OFF Period)

L L LOutput OFF Operation

(Reverse)VERR Pin Voltage < 1.294V typ..

OFF X X H L L

L X X L L L

L L

H

OFF H L L

Normal Operation(Reverse)

1.294V typ. VERR Pin VoltageLow Side PWM Output

OFF

UVLO Detection(Forward)

L

ON X X X L L L L

Over Current Detection(Forward)

(Output OFF Period)OFF X H X L L

OFF X X H L L L

Output OFF Operation(Forward)

VERR Pin Voltage < 1.294V typ..

Lock Detection(Forward)

(Output OFF Period)

L L L L L L

L

OFF H L L

OFF L X X

Normal Operation(Forward)

1.294V typ. VERR Pin VoltageLow Side PWM Output

NJU7388B

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TIMING CHART (1) 120° Commutation Mode (At FR=L) The high side and the low side commutation periods at H level output is 120°. The PWM output is controlled on the low side, and the high side is 100% output.

Low Side Maximum PWM Width : tPWMMAX=49.22µs typ. Low Side Minimum PWM Width : tPWMMIN=0.78µs typ.

UH

VH

WH

UL

VL

WL

60º

H1

H2

H3

Zoom in

UH

UL

tPWMMAXtPWMMIN

No. 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6

NJU7388B

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(2) 120° Commutation Mode (At FR=H) The high side and low side commutation periods at H level output is 120°. The PWM output is controlled on the low side, and the high side is 100% output.

Low Side Maximum PWM Width : tPWMMAX=49.22µs typ. Low Side Minimum PWM Width : tPWMMIN=0.78µs typ.

No. 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6

UH

VH

WH

UL

VL

WL

H1

H2

H3

60º

Zoom in

WH

WL

tPWMMAXtPWMMIN

NJU7388B

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(3)150° Commutation Mode (At FR=L) The high side and the low side commutation periods at H level output is 150°. It overlaps 15° before and after compared with 120° commutation mode. The PWM output is controlled on the low side, and the high side is 100% output.

Low Side Maximum PWM Width : tPWMMAX=49.22µs typ. Low Side Minimum PWM Width : tPWMMIN=0.78µs typ.

UH

VH

WH

UL

VL

WL

60º

H1

H2

H3

Zoom in

UH

UL

tPWMMAXtPWMMIN

No. 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6

NJU7388B

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(4)150° Commutation Mode (At FR=H) The high side and the low side commutation periods at H level output is 150°. It overlaps 15° before and after compared with 120° commutation mode. The PWM output is controlled on the low side, and the high side is 100% output.

Low Side Maximum PWM Width : tPWMMAX=49.22µs typ. Low Side Minimum PWM Width : tPWMMIN=0.78µs typ.

Zoom in

WH

WL

tPWMMAXtPWMMIN

No. 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6

UH

VH

WH

UL

VL

WL

H1

H2

H3

60º

NJU7388B

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APPLICATION NOTE (1) Commutation Control and Lead Angle Control At start-up, it operates with 120° commutation. When the following conditions A, B, and C are satisfied in order, the operation shifts to 150° commutation angle

operation and the lead angle setting becomes effective. A) Hall signal period is detected When the time between the edges of each hall signal input is less than tHALL120-150(37.5ms typ.). B) The hall pattern is confirmed In order to prevent malfunctions from noise etc., the pattern of hall signal input is simply confirmed. At FR=L : When detected "H2=H→L" and "H3=H→L" sequentially from point of "H1=H→L".

At FR=H : When detected "H3=H→L" and "H2=H→L" sequentially from point of "H1=H→L". (Refer to "a → b → c" in below figure) C) The number of pulses for hysteresis is counted

When detected 5 edges of each hall signal input. (Refer to "1 → 2 → 3 → 4 → 5" in below figure) If the time between edges of each hall signal input becomes over than tHALL150-120(51.1ms typ.) during 150° commutation

mode, the commutation mode is switched to 120° commutation and the lead angle setting becomes ineffective.

NJU7388B

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(2) Low Side Output (UL, VL, WL) These are composed totem-pole outputs for the low side control of 3-phase motor. The PWM function and LIMIT function are controlled by this low side outputs. Although these can directly drive external output FETs, the output current rating is 10 mA. If the large output current for driving FETs are required, configure buffer circuits externally. Transient current and ringing during switching can be reduced by inserting output series resistors externally. Especially when driving FETs directly, these should be used resistors larger than 500Ω.

(3) High Side Output (UH, VH, WH) These are composed totem-pole outputs for the high side control of 3-phase motor. These pins can’t directly drive FETs, therefore constitute drive circuits using one external transistor.

(4) Hall Input (H1+, H1-, H2+, H2-, H3+, H3-) These are hall signal input pins. These are connected to input differential amplifiers (hall amplifiers) internally. The internal circuit detects the voltage level like following that H+ > H- is “H” and H+ < H- is “L”. The hall amplifiers have the input hysteresis voltage range of 30mV (max). Therefore, it should be input the amplitude larger than 100mVp-p with considering the margin. And, the hall signal peak value must not exceed the hall input voltage range VICMIH.

Some noise might overlap to the hall signal based on the GND level fluctuations by phase current or the unbalance of

output signal path, etc. If the malfunction of the output chattering etc. occurs, it should be connected between the positive pins and the negative

pins with filter capacitors in range of 1nF to 100nF. e.g.) Application circuit at using Hall IC

0.6V

4.0V

VICMIH

t

R24.7kΩ

5V

Hall ICs H1+/H2+/H3+ Input signal

R14.7kΩ

R3/R6/R94.7kΩ

R4/R7/R1012kΩ

H1- to H3- Common reference voltage

R5/R8/R111kΩ

4.0V

H1- to H3- Common reference voltage

0.6V

Hall input pin voltage

t

Hall input voltage range

H1+/H2+/H3+ Input signal

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(5) FG Output FG pin outputs the signal synchronized with H1 as a pulse with a cycle proportional to motor rotation. FG pin is an open-drain output with an absolute maximum rating of 7 V, so it should be connected to the power supply

up to 5V with a pull-up resistor. Do not connect this pin to power supply for motor (VM).

<FG Truth Table (the signal synchronized with H1）> Forward Rotation (FR=L) Reverse Rotation (FR=H)

H1 H2 H3 FG H L L L H H L L L H L Hi-Z L H H Hi-Z L L H Hi-Z H L H L

H1 H2 H3 FG H L H L L L H Hi-Z L H H Hi-Z L H L Hi-Z H H L L H L L L

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(6) VLA Input Generally, the period of current flow to the motor becomes shorter as the higher rotation speed, because the ratio of

electrical delay increases. Therefore, when using at high-speed rotation, it is necessary to consider efficiency and speed performance in particular. The lead angle function can arbitrarily correct the commutation phase which is delayed from the predetermined value.

< When setting fixed lead angle value > < Application for simply automatic lead angle control > As an easy way to apply the automatic lead angle control, set the VLA pin voltage to be linked with the VERR pin

voltage according to the rotation speed. 1. When VERR=VLA setting 2. When arbitrarily setting with R1/R2

e.g.) When setting to the lead angle of 15° at the maximum rotation speed VVERR=4.5 V.

The VLA pin voltage required to set the lead angle of 15° is 2.36V. Therefore, the resistance ratio of R1 and R2 is as follows.

For example, there is a combination of R1=9.1kΩ and R2=10kΩ.

01.8753.75

5.6257.5

9.37511.25

13.12515

16.87518.75

20.62522.5

24.37526.25

28.12530

0 1 2 3 4 5

Lead

Ang

le[°

]

VERR Pin Voltage [V]

VERR Pin Voltage vs. Lead Angle(Theoretical Value)

1. VERR=VLA Setting

2. R1/R2=0.9 Setting

VDD

VLA

Speed ControlVERR

VLA

Speed ControlVERR

VLA

R1

R2

VINVLA = 11 + R1R2

VINVERR

R1R2 = VINVERRVINVLA − 1 = 4.52.36− 1 = 0.906

NJU7388B

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TYPICAL APPLICATION

*FR pin must not switch until motor stopped completely. When switching the direction of rotation, FR pin should be switched after motor stopped completely.

VREF UVLO

VERR

GND

VDD

OutputLogic

ControlLogic

-+

WL

VL

UL

WH

VH

UH

ILIMIT

PWMLogic

VLA

ClockGenerator

+24V

GND

Lead Angle4Bit

A/D Conv.

5VReg

6BitA/D

Conv.

H1-

H2-

H3-

H3+

H2+

H1+

FG

Lock DetCT

FR

N

N

SS

Motor

NJU7388B

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TYPICAL CHARACTERISTICS

0.0

0.5

1.0

1.5

2.0

2.5

3.0

0 1 2 3 4 5 6 7

I DD

[mA]

VDD [V]

IDD vs. VDDTa=25ºC, Io=0mA

18

19

20

21

22

4 4.5 5 5.5 6 6.5 7

f PW

M[k

Hz]

VDD [V]

fPWM vs. VDDTa=25ºC

4

4.5

5

0 5 10

V OH

[V]

IO_SOURCE [mA]

VOH vs. IO_SOURCEVDD=5V, Ta=25ºC

0

0.1

0.2

0 5 10

V OL

[V]

IO_SINK [mA]

VOL vs. IO_SINKVDD=5V, Ta=25ºC

0

0.05

0.1

0 1 2 3 4 5

V FG

L[V

]

IFG [mA]

VFGL vs. IFGVDD=5V, Ta=25ºC

8

10

12

14

16

18

20

22

24

26

28

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

V HYS

IH[m

V]

VICMIH [V]

VHYSIH vs. VICMIHVDD=5V, Ta=25ºC

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TYPICAL CHARACTERISTICS

1.6

1.8

2.0

2.2

2.4

2.6

2.8

-50 -25 0 25 50 75 100 125 150

I DD

[mA]

Tj [ºC]

IDD vs. TjVDD=5V, Io=0mA

16

18

20

22

24

-50 -25 0 25 50 75 100 125 150

f PW

M[k

Hz]

Tj [ºC]

fPWM vs. TjVDD=5V

4.5

4.6

4.7

4.8

4.9

5

-50 -25 0 25 50 75 100 125 150

V OH

[V]

Tj [ºC]

VOH vs. TjVDD=5V, IO_SOURCE=3mA

0

0.02

0.04

0.06

0.08

0.1

-50 -25 0 25 50 75 100 125 150

V OL

[V]

Tj [ºC]

VOL vs. TjVDD=5V, IO_SINK=3mA

3.8

3.9

4.0

4.1

4.2

4.3

4.4

-50 -25 0 25 50 75 100 125 150

V DU

VLO, V

RUV

LO[V

]

Tj [°C]

VDUVLO,VRUVLO vs. Tj

VDUVLO

VRUVLO

0

5

10

15

20

25

30

35

40

-50 -25 0 25 50 75 100 125 150

V HYS

IH[m

V]

Tj [ºC]

VHYSIH vs. TjVDD=5V, VIH=2V

NJU7388B

- 22 - Ver.2019-04-10

TYPICAL CHARACTERISTICS

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

-50 -25 0 25 50 75 100 125 150

I CH

GC

T, I D

CH

GC

T[µ

A]

Tj [ºC]

ICHGCT,IDCHGCT vs. TjVDD=5V

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

-50 -25 0 25 50 75 100 125 150

V HC

T,VLC

T[V

]Tj [ºC]

VHCT,VLCT vs. TjVDD=5V

VHCT

VLCT

0.4

0.42

0.44

0.46

0.48

0.5

0.52

0.54

0.56

0.58

0.6

-50 -25 0 25 50 75 100 125 150

V DET

LIM

[V]

Tj [ºC]

VDETLIM vs. TjVDD=5V

80

90

100

110

120

130

-50 -25 0 25 50 75 100 125 150

R VLA

,RVE

RR[kΩ]

Tj [ºC]

RVLA,RVERR vs. Tj

90

100

110

120

130

140

-50 -25 0 25 50 75 100 125 150

RFR[kΩ]

Tj [ºC]

RFR vs. Tj

NJU7388B

- 23 - Ver.2019-04-10

[CAUTION] The specifications on this datasheets are only

given for information, without any guarantee as regards either mistakes or omissions. The application circuits in this datasheets are

described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights.