3 DesignSD-TWG2012-WinterConf-final-v2.ppt

8/10/2019 3 DesignSD-TWG2012-WinterConf-final-v2.ppt

1/32

ITRS Design ITWG 2012 1

Design + System Drivers Update

Design ITWG

ITRS Public ConferenceHsinchu, 5 Dec 2012


2/32


MTM roadmap

RF+AMSDrivercontinued

UpdatedDrivers(MPU,SoC,)

UpgradedDFM, SL,verificationsections

Powerdesign

technologyroadmap

ConsumerStat ionary,Portable,Networking

Drivers

Past Trajectory (2004-2011) 1. Increasingly quantitative roadmap

2. Increasingly complete driver set3. Increasing MTM content

2

2004

2005

2006

2007

ExploreDesignmetrics

DesignTechnologymetrics

RevisedDesignmetrics

RevisedDesignTechnologyMetrics

ConsumerPortableDriver

ConsumerStationary,PortableDrivers

ConsumerStationary,Portable,NetworkingDrivers

More ThanMoore(MTM)analysis+ iNEMI

Driverstudy

SystemDriversChapter

DesignChapter

2008

RevisedDesignMetricsDFMextension

UpdatedConsumerStationary,Portable,

andNetworkingDrivers

MTMextension+ iNEMI+ SW !!

2009

AdditionalDesignMetricsDFMExtension

System levelextension

UpdatedConsumerStationary,Portablearchitecture,andNetworking

Drivers

MTMextension+ iNEMIsynch+ SW !!

MTM

RF+AMSDriver start

UpdatedConsumerSOC andMPU Drivers

UpgradedRF+AMSsection

2010

2011


3/32


Work Toward 2013 and BeyondDesign Chapter

Version 2 of the Power-Aware Design Technology roadmap

Version 2 of the 3D IC design technology roadmap Design technology for More Than Moore fabrics (SW, AMS/RF, MEMS) Updates of LCP, DFT, Design Verification, Design for Resilience Design of on-chip memory hits the wall at 16nm HP

System Drivers Chapter Rethinking the MPU Driver: Core + LLC + uncore ; microserver class Revising the SOC-Consumer Portable Driver Elimination of SOC-Networking, SOC-Consumer Stationary drivers ? Update of Embedded Memory

Continue development of AMS/RF sub -driver of SOC-CP DriverCross-TWG CTSG: node timing pull-in, A-factor updates for FinFET, vertical devices How will FinFET, UTBB SOI timing change PPA projections? Renewal of the PIDS HP, LP roadmaps (compact modeling interaction)

3D effort with other TWGs


4/32





System Drivers Chapter Rethinking the MPU Driver: Core + LLC + uncore ; microserver class Revising the SOC-Consumer Portable Driver Elimination of SOC-Networking, SOC-Consumer Stationary drivers ? Update of Embedded Memory Continue development of AMS/RF sub -driver of SOC-CP Driver

Cross-TWG CTSG: node timing pull-in, A-factor updates for FinFET, vertical devices How will FinFET, UTBB SOI timing change PPA projections? Renewal of the PIDS HP, LP roadmaps (compact modeling interaction)



5/32


Design Cost Roadmap

$-

$20.0

$40.0

$60.0

$80.0

$100.0

2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026

ITRS 2011 Cost Chart

Total HW Engineering Costs + EDA Tool Costs Total SW Engineering Costs + ESDA Tool Costs

Total HW Engineering Costs + EDA Tool Costs (smoothed) Total SW Engineering Costs + ESDA Tool Costs (smoothed)

S o

f t w a r e

V i r t u a

l P r o

t o t y p e

I n t e l l i g e n

t T e s

t b e n c

h

R e u s a

b l e P l a t f o r m

B l o c

k

S i l i c o n

V i r t u a

l P r o

t o t y p e

A M P P a r a

l l e l P r o c e s s

i n g

M a n y

C o r e

D e v e

l . T o

o l s

C o n c u r r e n

t M e m o r y

S y s

t e m

D e s

i g n

A u t o m a

t i o n

E x e c u

t a b l e S p e c

i f i c a

t i o n


6/32


Design Power Roadmap


7/32ITRS Design ITWG 2012 7

Low-Power Design Technology Roadmap

NEW: approximate computing, adaptivity, power gatingreplacement, dark silicon, extreme heterogeneity,



NEW in Low-Power Design Tech RoadmapApproximate Computing

Variable-accuracy computing (e.g., flexibly from 64b 16b)

4D computing: reconfiguration on the fly AVS ? (e.g., part of DVFS) Margin reduction?Adaptivity

Recapture overdesign from wearout, variation marginsPower Gating Replacement

HVT device as power switch hits headroom, area wall ? Dark Silicon

normally -off computing = extreme power gating



Dark Silicon Analysis in 2001 ITRS Power management gap amount of (switched)

logic content in an SOC goes to zero Challenge: keeping the chip value above zero

1998 2000 2002 2004 2006 2008 2010 2012 20140

10

20

30

40

50

Constant area region1999-2004

Constant Power (90W)

Constant Power Density (90W/1.57cm 2)

% o

f a r e a

d e v o

t e d t o

l o g

i c

Year

Today: turn ononly 2-6% oflogic on SOC !



NEW in Low-Power Design Tech RoadmapApproximate Computing

Variable-accuracy computing (e.g., flexibly from 64b 16b)

4D computing: reconfiguration on the fly AVS ? (e.g., part of DVFS) Margin reduction?Adaptivity

Recapture overdesign from wearout, variation marginsPower Gating Replacement

HVT device as power switch hits headroom, area wall ? Dark Silicon

normally -off computing = extreme power gating Extreme Heterogeneity

coprocessor -dominated architectures (pervasive heterogeneity; energy-efficiency from specialization; HW

accelerators) 10 x 10, 13 dwarves, Intel accelerators for MPU vs. Tensilica (or, GPUs, xPUs)



Design Tech for More Than Moore Fabrics Key areas: SW, AMS/RF, MEMS, 3D / novel packaging

Current design technology still insufficient; must broadenbeyond current ideas

New 3D / TSV design flows New multi-physics modeling, simulation, analysis tools

Example : thermal / mechanical analysis (base station)

Example : MEMS + electrical analysis (mobile gaming)

Example : sensors + signal processing (industrial, medical)

Example : software + HW simulation (data center network)



Memory as a Key Factor in Future DT

Figure DESN12 Possible Variability Abstraction Levels

Physical

Device

Gate

Chip

Bit Cell

Circuit Array



Memory as a Key Factor in Future DT

Figure DESN8 Variability-Induced Failure Rates for Three Canonical Circuit Types


14/32



Changes to MPU Model

Item Current 2011

model

Proposed 2013 model

Die area 140mm 2 (CP),260mm 2 (HP)

140mm 2 (CP), 260mm 2 (HP)

Area ratio Core :: 1 Core : LLC : UnCore :: 1: 1: 1

LLC NA 12MB (2011) + 1.4x every technode[Borkar10, Borkar07]

UnCore NA Uncore Scaling

SRAM A-factor

(USRAM )

60F 2 (6T), 84F 2 (8T)

(bulk)

60F 2 (6T), 84F 2 (8T) (bulk,

FinFET)40F 2 (6T), 56F 2 (8T) (high-densityFinFET) ***

* CP Cost-Performance; HP High Performance **L2$ and L1$ is per core



Uncore (increasing portion of MPU) consists of: Memory controller(s)

Graphics and display controller(s) I/O and bus interface controller(s)

Updated MPU Model: UnCore Scaling

Item Proposed model

Memory controller N/2 (CP), N (HP); N = # cores[Borkar07, Borkar11, 80-core, IVB]

Graphics and Display controller 2x every tech node[NHM, SNB, NVIDIA]

I/O and bus interface controller N/6[SNB, IVB]

Logic (# transistors) growth Same as core

Logic density Same as core

SRAM (# bitcells) growth 512MB * # GPU-Cores[IVB, NVIDIA]

SRAM density Same as core



New Drivers Catching Up to Old Ones ?

1. SoC-ification of Drivers brings similarities

2. Need to isolate the parameters driven by each (and only) driver



New Drivers Replacing Old Ones ? 1. Potential future system driver list (Markets dimension)

a) High performance computing MPU Office/Server b) Mobile (Application) MPU Consumer Portable c) Low power computing MPU Microserver



SoC MPU Convergence: MicroServers ? Observation: mobile computing SoCs competing in server space

Beginning to be used in data centers and cloud computing Extreme core efficiency (active power < 4W, sleep power < 0.5W) #Cores, frequency scaling similar to conventional MPUs

Microserver product class (Calxeda , Marvell, Intel, )

re-examine the MPU model or possibly create a new driver !

Clock frequency growing at 1.5X every 2 years Number of cores growing at 2X every 4 years Networking-like SoC scaling: off-chip latency, accelerators, L3 cache Power budget under 4W per core (HPC example) Off-chip bandwidth as high as 200+ Gbps



A&DNetwork Consumer/Mobile

Office/Server

Medical Automotive ConsumerStationary

MPU

PE/DSP

AMS

Memory

Fabrics

Markets

System Drivers So Many ? 1. Fabs will be filled primarily by 2-3 major applications



A&DNetwork Consumer/Mobile

Office/Server

Medical Automotive ConsumerStationary

MPU

PE/DSP

AMS

Memory

Fabrics

Markets

System Drivers So Many ? 1. Fabs will be filled primarily by 2-3 major applications2. Drivers will follow suit applications drive technology



Evolution of System Drivers Inventory

1. Upcoming years may see a smaller list of key Drivers2. As fabs consolidate, applications and drivers do so as well3. All remaining applications will ride on existing technology curve

System Driver (Market based) Technology Parameters Driven Potentialaction

High performance(computing) MPU Frequency, number of cores,memory architecture Keep

Mobile / consumer MPU Leakage power efficiency Keep

Low power computing MPUMicroserver

Operating power efficiency Introduce?

Networking switch Number of I/Os / total I/O BW Keep?

Various fabrics (memory,AMS)

Various fabric-specificparameters

Keep

Networking MPU Number of cores, I/O BW Keep??



Qualitative changes in SoC-CP High resolution, large screen size video interface require high

performance GPU Cloud-based service over wireless connection eliminates dedicatedPEs for speech, character and image recognition, dictionary, etc.

SoC-CP model Current model: CPU + PE + Peripheral (+ RF, AMS)

Next model: CPU + GPU + Logic Block + IO Peripheral

+ Baseband

(+ RF, AMS)

SOC-CP Model Revision

2D/3Dgraphics

Audio codec,Video codec,

Security

Multi-band multi-protocol SDR

DRAM-IF, USB,

MIPI, HDMI, LVDS


25/32


More Than Moore AMS/RF Subdriver

Several emphases in DT, DFT: System verification, Hetero systems

Plan : paste high-level block model from AMS/RF -- core model Hope to obtain model from additional groups, market analysis

E.G. WiFi/GPS/cellular/BT/NFC front-end blocks, tuner/demodulator

blocks


26/32









27/32


Ongoing for 2013 revision Initial draft models developed in April 2012Many issues to work through Gridded layout with device grid, metal grid alignment Dummy poly isolation Unimportant design rules become important e.g., gate

contact to active contact spacing SRAM devices have integral sizing, no Vt control except

with Lgate biasing challenge to maintaining SRAM A-Factor

Current densities and resistivity CD (width) scaling of VDD, VSS traces Comprehension of wiring loads in future designs Specs for high-performance, low-power cell libraries

A-Factor Updates (e.g., FinFET)


28/32


Device Model / PIDS interaction

Agreed to only one low power device in the roadmap

Removed LOP device flavor from 3 to 2 devices Still questioning how much CD variation can be tolerated

Should Design content change as we move toward 450 mm ?

Should Design care about node definitions ?

(foundry names vs. ITRS)


29/32


Observation: 14 years to get beyond-CMOS idea to products ITRS groups must start to think about and act on beyond-2020

devices and their use in design (technology by itself is not a complete solution)

What will be the earliest insertions into which products? MRAM replaces SRAM

3D with vertical nanowires (7nm) bring BEOL interfacingchallenge (and: P, N in different vs. same layers?) Spintronics

Demands Design ITWG collaboration with PIDS, Litho,Interconnect, ERD/ERM and expanding the scope of ITRS

Beyond 2020


30/32


1. Design technology continues on roadmap of low-power techniques

2. Design ITWG still clarifying impact of new devices (FinFET A-factor)3. Design technology for 3D continues to spread across chapter

4. Design technology for resilience a fundamental portion of DFM

5. More Than Moore fabrics will require increasingly specialized DT

6. Memory an increasingly important factor for design technology

7. Still pushing to integrate AMS/RF on SoC/SiP despite 3D prospects

8. System Drivers: SoC-CP revision and will soaring applications (DTV,

microservers) overhaul the driver list ?9. ITRS groups must think about Beyond-CMOS based products and

insertion points

Summary: 2012 Design / SysDrivers Messages


31/32


THANK YOU


32/32

Systems

ICs

System Device Domain Space

Chip level System level

Tech

requirements

Marketrequirements

SystemDemandWill drivedevicedemand

3 DesignSD-TWG2012-WinterConf-final-v2.ppt

Documents

Transcript of 3 DesignSD-TWG2012-WinterConf-final-v2.ppt