3. DAC Architectures and CMOS Circuits - cnm.espserra/uab/ihsd/ihsd-3-dac.pdf · decoder natural...
Transcript of 3. DAC Architectures and CMOS Circuits - cnm.espserra/uab/ihsd/ihsd-3-dac.pdf · decoder natural...
3. DAC Architectures and CMOS Circuits
Integrated Heterogeneous Systems Design F. Serra Graells
1/30Class Flash PWM Delta-Sigma
3. DAC Architecturesand CMOS Circuits
Francesc Serra Graells
[email protected] de Microelectrònica i Sistemes Electrònics
Universitat Autònoma de Barcelona
[email protected] Circuits and Systems
IMB-CNM(CSIC)
3. DAC Architectures and CMOS Circuits
Integrated Heterogeneous Systems Design F. Serra Graells
2/30Class Flash PWM Delta-Sigma
DAC Classification1
Flash Techniques2
Pulse-Width Modulation Techniques3
Delta-Sigma Modulation Techniques4
3. DAC Architectures and CMOS Circuits
Integrated Heterogeneous Systems Design F. Serra Graells
3/30Class Flash PWM Delta-Sigma
DAC Classification1
Flash Techniques2
Pulse-Width Modulation Techniques3
Delta-Sigma Modulation Techniques4
3. DAC Architectures and CMOS Circuits
Integrated Heterogeneous Systems Design F. Serra Graells
4/30Class Flash PWM Delta-Sigma
DAC Families
Classification based on architecture approach:
Amplitude vs time domainsSingle vs multiple stagesFeedforward vs feedback control
Distinctive characteristics:
Typically mixed solutions...
DAC
Digitalsignal
Analogsignal
Digitaltimebase
voltage/currentamplitude
code
High dynamicrange
High speed
Parallel
Predictive
Algorithmic
Flash
PWM
Delta-Sigma
...and manymore!
3. DAC Architectures and CMOS Circuits
Integrated Heterogeneous Systems Design F. Serra Graells
5/30Class Flash PWM Delta-Sigma
DAC vs ADC Design
Asymmetrical system architecture and signal purpose:
...typically ADC is more performance demanding!
ADCcore
antialias
AGC/limiter
preamp
clockgenerator
decimator
DSP
DACcore
reconstructionpoweramp
interpolator
sensore.g. microphone
actuatore.g. motor
information
action
M
3. DAC Architectures and CMOS Circuits
Integrated Heterogeneous Systems Design F. Serra Graells
6/30Class Flash PWM Delta-Sigma
DAC Classification1
Flash Techniques2
Pulse-Width Modulation Techniques3
Delta-Sigma Modulation Techniques4
3. DAC Architectures and CMOS Circuits
Integrated Heterogeneous Systems Design F. Serra Graells
7/30Class Flash PWM Delta-Sigma
Basic Flash Architecture
All parallel and segmented (unitary) resistive ladder:
DAC
e.g. single-ended10-bit flash DAC
e.g. 32x32-1
3. DAC Architectures and CMOS Circuits
Integrated Heterogeneous Systems Design F. Serra Graells
8/30Class Flash PWM Delta-Sigma
Basic Flash Architecture
All parallel and segmented (unitary) resistive ladder:
DAC
e.g. single-ended10-bit flash DAC
e.g. 32x32-1
3. DAC Architectures and CMOS Circuits
Integrated Heterogeneous Systems Design F. Serra Graells
9/30Class Flash PWM Delta-Sigma
Basic Flash Architecture DAC
e.g. single-ended10-bit flash DAC
Digitaldecoder
naturalbinarycode
5-to-32
5-to
-32
5 (LSB)
(MSB) 5
10
Non-constantoutput impedance
All parallel and segmented (unitary) resistive ladder:
e.g. 32x32-1
3. DAC Architectures and CMOS Circuits
Integrated Heterogeneous Systems Design F. Serra Graells
10/30Class Flash PWM Delta-Sigma
Basic Flash Architecture DAC
e.g. single-ended10-bit flash DAC
Digitaldecoder
naturalbinarycode
5-to-32
5-to
-32
5 (LSB)
(MSB) 5
10
Distortion due toswitch on-resistancevariability
All parallel and segmented (unitary) resistive ladder:
e.g. 32x32-1
3. DAC Architectures and CMOS Circuits
Integrated Heterogeneous Systems Design F. Serra Graells
11/30Class Flash PWM Delta-Sigma
Switch Optimization
Thermometric switched-resistor flash DAC:
DAC
Thermometricencoder
naturalbinarycode
currentsource/sink like
3. DAC Architectures and CMOS Circuits
Integrated Heterogeneous Systems Design F. Serra Graells
12/30Class Flash PWM Delta-Sigma
Switch Optimization
Thermometric switched-resistor flash DAC:
DAC
Thermometricencoder
naturalbinarycode
Poor scalabilitywith ENOB
Switch non-linearityminimized thanks toits signal independentbias point
currentsource/sink like
3. DAC Architectures and CMOS Circuits
Integrated Heterogeneous Systems Design F. Serra Graells
13/30Class Flash PWM Delta-Sigma
CMOS Circuits
Thermometric switched-current (SI) fully differential flash DAC:
Thermometricencoder
naturalbinarycode
Always-on Si cellto reduce outputvoltage glitches
Return-to-zero (RTZ)digital signalingminimizes inter-symbolinterference
continuous-timewaveform!
time10 0
time10 0waveform
asymmetry
3. DAC Architectures and CMOS Circuits
Integrated Heterogeneous Systems Design F. Serra Graells
14/30Class Flash PWM Delta-Sigma
CMOS Circuits
Thermometric switched-current (SI) fully differential flash DAC:
Thermometricencoder
naturalbinarycode
Poor scalability with ENOB
Always-on Si cellto reduce outputvoltage glitches
Power and area overheads (x2)
Return-to-zero (RTZ)digital signalingminimizes inter-symbolinterference
continuous-timewaveform!
Full-scale reduction due to RTZ duty cycletime1
0 0
3. DAC Architectures and CMOS Circuits
Integrated Heterogeneous Systems Design F. Serra Graells
15/30Class Flash PWM Delta-Sigma
CMOS Circuits
Thermometric SI fully differential flash DAC:
Thermometricencoder
SI CMOS modular cell:
M1i
M2i
M6i
M3i M4i
M5i
M7i M8i
cascodetopologies
OpAmpvirtual ground +
Good linearitythanks to...
MOSFET noisecontributions!
3. DAC Architectures and CMOS Circuits
Integrated Heterogeneous Systems Design F. Serra Graells
16/30Class Flash PWM Delta-Sigma
Coarse-Fine Architectures
Mixed segmented (coarse) and binary weighted (fine) solutions:
1
e.g. 8-bit coarse-finesingle-ended SI flash DAC
Good ENOBscalability
Unlike in ADCcounterparts, it isstill single step!
1 1 1 1 1 11
1 2 4 8 161
5-bit(LSB) 3-bit
(MSB)
smoothtransitions
compact layoutand simple digital control
Therm.encoder
7
3. DAC Architectures and CMOS Circuits
Integrated Heterogeneous Systems Design F. Serra Graells
17/30Class Flash PWM Delta-Sigma
DAC Classification1
Flash Techniques2
Pulse-Width Modulation Techniques3
Delta-Sigma Modulation Techniques4
3. DAC Architectures and CMOS Circuits
Integrated Heterogeneous Systems Design F. Serra Graells
18/30Class Flash PWM Delta-Sigma
Digital Pulse Width Modulation
Discrete amplitude and continuous-time domains:
DAC
Register
inputbuffer
Counter
ALU
>=?
continuous-timereconstruction filter
Powerdriver
time
3. DAC Architectures and CMOS Circuits
Integrated Heterogeneous Systems Design F. Serra Graells
19/30Class Flash PWM Delta-Sigma
Digital Pulse Width Modulation
Discrete amplitude and continuous-time domains:
DAC
Register
inputbuffer
Counter
ALU
>=?
continuous-timereconstruction filter
Powerdriver
Overclocking
Ouptut actuator can be reusedas reconstruction filter:
timee.g. Class-D audio driver
Output filterselectivity
Energy closeto fs
3. DAC Architectures and CMOS Circuits
Integrated Heterogeneous Systems Design F. Serra Graells
20/30Class Flash PWM Delta-Sigma
Digital Pulse Width Modulation
Discrete amplitude and continuous-time domains:
Register
inputbuffer
Counter
ALU
>=?
continuous-timereconstruction filter
Powerdriver
Overclocking
Relaxing output filter selectivityby employing non-monotoniccounters (e.g. LFSR, flipped...)
time
Energy closeto fs
time
Energy closeto fclk
3. DAC Architectures and CMOS Circuits
Integrated Heterogeneous Systems Design F. Serra Graells
21/30Class Flash PWM Delta-Sigma
Dual-Ramp Analog Integration
Continuous-amplitude and continuous-time domains:
Register
Counter
>=?
e.g. 16-bit dual ramp DAC
time
>=?
Register
MSB 8
LSB 8
Coarse PDM
Fine PDM
3. DAC Architectures and CMOS Circuits
Integrated Heterogeneous Systems Design F. Serra Graells
22/30Class Flash PWM Delta-Sigma
Dual-Ramp Analog Integration
Continuous-amplitude and continuous-time domains:
Register
Counter
>=?
e.g. 16-bit dual ramp DAC
Coarse-fine matching
Strong reduction of clock speed requirements
time
>=?
Register
MSB 8
LSB 8
Relaxing output filter selectivity
Coarse PDM
Fine PDM
3. DAC Architectures and CMOS Circuits
Integrated Heterogeneous Systems Design F. Serra Graells
23/30Class Flash PWM Delta-Sigma
DAC Classification1
Flash Techniques2
Pulse-Width Modulation Techniques3
Delta-Sigma Modulation Techniques4
3. DAC Architectures and CMOS Circuits
Integrated Heterogeneous Systems Design F. Serra Graells
24/30Class Flash PWM Delta-Sigma
Analog vs Digital DSM
integrator
S/H
gaincoefficient
high-pass filter(quantization noise shaping)
quantizer
3. DAC Architectures and CMOS Circuits
Integrated Heterogeneous Systems Design F. Serra Graells
25/30Class Flash PWM Delta-Sigma
Analog vs Digital DSM DAC
integrator
Possibility of loopinstability for N>2
S/H
gaincoefficient
high-pass filter(quantization noise shaping)
quantizer
bit-shifting(2+/-k gain coefficient)
discrete timedomain already
register register
full-adder truncation
flashoutput DAC
Flash output DAC withreduced number of levels
3. DAC Architectures and CMOS Circuits
Integrated Heterogeneous Systems Design F. Serra Graells
26/30Class Flash PWM Delta-Sigma
Multi-Stage Noise Shaping (MASH)flash
output DAC
Canc
ella
tion
filte
r Cascade of 1st-order DSM
Forward digital cancellation
Intrinsically stable
3. DAC Architectures and CMOS Circuits
Integrated Heterogeneous Systems Design F. Serra Graells
27/30Class Flash PWM Delta-Sigma
Multi-Stage Noise Shaping (MASH) Cancellation filter
Differentiator
Delay
3. DAC Architectures and CMOS Circuits
Integrated Heterogeneous Systems Design F. Serra Graells
28/30Class Flash PWM Delta-Sigma
Multi-Stage Noise Shaping (MASH)
Not suitable for ADCDSM due to possible cancellationmismatching
Cancellation filter
N-order noise shaping
Differentiator
Delay
Each DSM cancelsquantization errorsof previous one
3. DAC Architectures and CMOS Circuits
Integrated Heterogeneous Systems Design F. Serra Graells
29/30Class Flash PWM Delta-Sigma
Multi-Stage Noise Shaping (MASH)
Compact solution:
Example for 1-bit quantization 1st-order DSM stage:
Carry
Register
Adder
3. DAC Architectures and CMOS Circuits
Integrated Heterogeneous Systems Design F. Serra Graells
30/30Class Flash PWM Delta-Sigma
Multi-Stage Noise Shaping (MASH)
Cancellation filter
Compact solution:
Example for 1-bit quantization 1st-order DSM stage:
Carry
Register
Adder
RegisterRegister
Register
RegisterRegister