3-D Stacked Package Technology and Trends

INV ITEDP A P E R

3-D Stacked PackageTechnology and TrendsDeveloped for mobile equipment, packages of stacked logic and

memory devices continue to improve and new variations are being developed to

meet future needs.

By Flynn P. Carson, Young Cheol Kim, and In Sang Yoon

ABSTRACT | The need to integrate more device technology in a

given board space for handheld applications such as mobile

phones has driven the adoption of innovative packages which

stack such devices in the vertical or third dimension (3-D).

Stacking of device chips in small and thin fine-pitch ball grid

array packages has evolved into the stacking of packages

themselves to achieve the same end. The advantage of stacking

packages rather than device chips is that packages can be fully

tested good prior to stacking. There are two primary ways to

stack packages to achieve such vertical integration: package-

on-package (PoP) and package-in-package (PiP). Innovative

variations of PoP and PiP are being developed to address

specific packaging needs and market trends. This paper will

detail some of the key technology supporting PoP and PiP

packages currently in production and the development of new

variations of such packages to address future trends.

KEYWORDS | Package-in-package; package-on-package; semi-

conductor device packaging; three-dimensional packaging

I . INTRODUCTION

The establishment and evolution of three-dimensional(3-D) packaging is a relatively recent phenomenon. The

growth of 3-D packaging from a niche to a commodity

package type is linked to the explosive growth of mobile

phone features and performance. By the end of 2008, more

than 50% of the world’s population of 6.6 billion will own

a mobile phone, a U.N. agency reported [1]. On average,

every handset shipped today has a 3-D package in it. This

trend, by all accounts, is bound to continue. The mobile

phone of today is becoming the personal computing device

of the future. The size of the phone is not growing

significantly, so all this functionality and performance

needs to be packed into the same form-factor. Three-

dimensional packaging is a key to enabling this trend in the

handsets and mobile devices of tomorrow.

The initial 3-D package in the mobile phone was thestacked-die package. As the features and performance of

handsets increased in the late 1990s, they required more

memory to drive their applications. Instead of mounting

more memory packages, primarily fine-pitch ball grid arrays

(FBGAs), side by side on the phone printed circuit board

(PCB) and taking up a lot of space, stacking of the memory

devices in the same FBGA package was developed. This was

an enormous success not only because such vertical stackingsaves PCB space but also because the package itself is

cheaper than the two or three separate memory packages it

replaces. Growth of the 3-D package has skyrocketed, and

there is no end in sight. The success and quick maturation of

the stacked-die package for memory prompted the use of it

for other applications. It was soon used to integrate digital

and analog baseband as well as other applications combining

digital, analog, and even radio frequency (RF).Attempts to extend stacked-die packaging to integrate

logic and memory ran into some problems. DRAM

memory was especially difficult to integrate with logic,

since it is difficult to integrate truly known-good-die

(KGD) without compromising the yield at final electrical

test. In general, logic integrated device manufacturers

(IDMs) are averse to taking on the liability and test issues

associated with integrating memory into their products.Memory has lower value content, uses a different test

platform, and is not their core competency. Also, not all

memory IDMs want to sell memory wafers to logic IDMs.

Ownership of liability if memory fails in the finished

package is a sticky issue. A few logic IDMs who initially

attempted logic and memory die-stacked packages quickly

ran into major problems and were seeking better solutions.

Manuscript received March 8, 2008; revised May 29, 2008.

Current version published February 27, 2009.

F. P. Carson is with STATS ChipPAC, Inc., Fremont, CA 94358 USA

(e-mail: [email protected]).

Y. C. Kim and I. S. Yoon are with STATS ChipPAC Korea Ltd., Kyoungki-do, 46789

Korea (e-mail: [email protected]; [email protected]).

Digital Object Identifier: 10.1109/JPROC.2008.2007460

Vol. 97, No. 1, January 2009 | Proceedings of the IEEE 310018-9219/$25.00 �2009 IEEE

A better 3-D solution arrived in the form of the stackedpackage. The stacked package allows for the memory

device(s) to be packaged, tested, and supplied by the

memory IDM, and the logic device(s) to be packaged, tested,

and supplied by the logic IDM. Each IDM is leveraging their

core competency, and liability is clear. The handset original

equipment manufacturer (OEM) benefits by leveraging their

traditional logic and memory suppliers as well as having

flexibility to configure memory and logic as needed. Packagestacking is very desirable from a business standpoint.

The main type of package stacking in production today

is package-on-package (PoP). PoP has standards in place to

facilitate its adoption and has experience significant growth

the last few years. PoP is already inside many of the more

advanced handsets from the major OEMs. Another type of

stacked package is package-in-package (PiP). PiP also has

standards governing the package (typically memory pack-age) stacked within. The PiP has been adopted by some

major IDMs and has some unique features relative to the

PoP type. Both PoP and PiP are shipping in mass production

today and are forecasted, by marketing firms, to have

explosive growth for the next several years.

This paper will explore the technology behind the

current 3-D stacked package offerings as well as the

variations of such packages being developed to addressthe demands of future mobile phones.

II . 3-D STACKED PACKAGES

A. PoPThe structure of the PoP can be seen in Fig. 1. The PoP

has two distinct packages. The bottom package is usually

reserved for the logic device, such as mobile phone

baseband (modem) processor or application processor.

This logic device can be wire-bond or flip-chip type. The

bottom package can support high pin-count on the bottom

surface. The top peripheral surface of the bottom PoP ispopulated with land pads in order to allow for the

interconnection of the top PoP. This top peripheral surface

is free from any encapsulant mold compound (EMC), as

shown in Fig. 2. Interconnection is done by means of

reflowing the top package to the bottom package, typically

simultaneously with reflow to the PCB.The top PoP has peripheral balls on the bottom that

match the lands on top of the bottom PoP. The top PoP is

usually reserved for the memory device stack, such as a

Flash (NAND and/or NOR type) and DRAM stack. It is

well suited for this purpose because memory devices are

relatively low pin-count (to date), and such pin-count can

be accommodated in a few peripheral rows.

JEDEC standards have been developed to govern theelectrical and mechanical interface of the top PoP [2], [3].

This standardization has greatly influenced the adoption of

the PoP, as it has allowed the memory IDMs to focus on

making standard product offerings based on package size

and ball pitch without worrying about a myriad of

variations that might have promulgated without a standard

in place. The logic IDM benefits as well and can design the

logic device to best incorporate the known memory inputsto enable easier routing. Of course, the handset OEM also

wins, as the standard enables flexibility in mixing and

matching components and suppliers, as they are all

producing compatible products.

B. PiPThe structure of the PiP can be seen in Fig. 3. The PiP

also has two packages, but instead of reflowing anotherpackage on top of the base package, as in PoP, the other

package is stacked and embedded within the base package.

The package stacked and molded within the base package

is called the internal stacking module (ISM). Some details

of the ISM can be seen in Fig. 4. The ISM is essentially a

very thin land grid array (LGA) type of FBGA package,

which has an array of lands pads, in order to properly test

the package using commercially available test sockets, butalso has a row of terminals at the edge of the packageFig. 1. Stacked PoP structure (wire-bond device type in bottom PoP).

Fig. 2. Bottom PoP topside showing peripheral lands.

Carson et al. : 3-D Stacked Package Technology and Trends

32 Proceedings of the IEEE | Vol. 97, No. 1, January 2009

(essentially bond fingers) that allow the ISM to be wire-

bond interconnected to the base package substrate.

The ISM usually houses the memory device or device

stack that is to be integrated with a logic device or device

combination in the base package. The logic device in the

base package can be wire-bond or flip-chip type. The ISM

can be fully tested and burned-in prior to stacking in thebase package. In a sense, the ISM is a true KGD that can be

stacked and wire-bonded to the base package substrate like

a die, but without the uncertainty and potential yield loss

of stacking a probed good memory device or bare KGD.

There is a JEDEC standard governing the electrical and

mechanical interface of the ISM [2], [4]. This allows for

the ISM of a standardized memory type to be easily

designed into the PiP. However, standardization is notquite as important as in the PoP case, because the ISM is

stacked within the PiP and not mounted externally. It is

important that ISMs stacked in a particular PiP have the

same interconnect terminals and signal assignments. This

is what the current JEDEC standards specify.

The memory IDM can focus on supplying a tested goodpackage. Usually this is supplied to the logic IDM who will

integrate it into the PiP. This differs from the PoP business

model. The logic IDM typically supplies the fully tested PiP to

the OEM with the ISM embedded within. However, the

ownership and liability of the memory ISM within is that of

the memory supplier. The logic IDM has less risk and liability

with respect to test yield and reliability issues related to

integrating the memory, unlike if the IDM had purchasedbare memory device(s) and stacked with their logic device(s).

The PiP is suited for logic IDMs that wish to configure the

memory with their logic in a smaller, more conventional

package. The finished PiP looks like any other FBGA in the

IDMs product portfolio, can be reflowed to the PCB the same,

and has the same level of package and board-level reliability.

III . PoP TECHNOLOGY AND TRENDS

A. General RequirementsThe challenge during the development of the PoP is to

make it competitive in size, thickness, and cost to an

equivalent stacked-die FBGA, which would have the smallest

form factor and cost but has yield, liability, and business flow

problems (for memory and logic combinations), as men-tioned previously. Achieving this is difficult because the top

and bottom PoP are connected by means of solder balls at the

periphery of each package, so allowance in size and thickness

must be made to achieve this connection. Thus, the

peripheral interconnection pitch should be minimized to

minimize the impact on package size and thickness.

The first PoPs developed focused on 0.65 mm PoP

interconnection pitch with a wire-bonded logic devicehoused in the bottom package. The size of these initial PoP

offerings was 12� 12 mm to 15� 15 mm, and the ball-count

of the bottom package was in the 400–600 range. From two

to five memory devices were stacked in the top package. The

stacked PoP height requirement was initially less than 1.

8 mm, but quickly migrated to 1.6 mm. In 2008, the target

for PoP size is 12 � 12 mm or less and 1.4 mm maximum

stacked height. Since the ball count has not decreased, thistypically requires finer ball pitch on the bottom package

(0.4 mm) and is driving 0.5 mm interconnect ball pitch.

Controlling the warpage of the top and bottom package

during the reflow process is one of the most important areas

to consider during the package development. Reflow of the

top PoP to bottom PoP to PCB in one reflow pass is desired

by most handset OEMs. In order to have acceptable reflow

yields and board-level reliability, the warpage of each PoP inthe stack must be controlled within a certain range at the

temperature above the solder ball melting temperature.

Lead-free solder balls are used, so this temperature is 220 �Cto 260 �C. The warpage control requirement varies from

customer to customer but is always less than the coplanarity

requirement for each package at room temperature (less

than 0.10 mm). This warpage allowance is decreasing asFig. 4. ISM showing test lands and interconnect terminals (stacked

in PiP with wire-bond interconnect to base package).

Fig. 3. PiP structure (wire-bond device type in base package).


Vol. 97, No. 1, January 2009 | Proceedings of the IEEE 33

understanding and methodology of characterizing the

impact on surface mount technology (SMT) yields matures

and the interconnect ball pitch of the PoP decreases [5]. TheSMT process and advancements thereof also influence the

PoP SMT yield and package warpage requirement.

The PoP must meet the package and board-level

reliability (BLR) requirements of mobile and handset

applications. At the package level, this requirement is

moisture sensitivity level (MSL) 3 at 260 �C peak temper-

ature per JEDEC precondition test specification [6]. The

other package-level requirements are shown in Table 1.The most important BLR requirement for mobile

applications is the drop test. Drop test per JEDEC JESD-

B111 must be met [7]. Several handset manufacturers have

their own drop-test methodology and requirement, but

clearly passing the JEDEC drop-test specification will

usually guarantee passing such OEM-specific require-

ments. Such testing is done without any package underfill.

The SMT process is also an important considerationinfluencing the PoP BLR and must be done per industry

standard practice in order to get a result representative of

mass production. Board-level temperature cycle and bend

test are also important tests, but if the drop-test

requirement is met, these tests typically follow suit and

are not a major concern.

B. Bottom PoPThe bottom PoP structure does not have the mold cap

extending to the edge of the package (Fig. 2). This requires

each unit on the strip to be molded without a runner or

connection of the mold cap from unit to unit. Top center

mold gate (TCMG) technology was utilized to perform this

molding (Fig. 5). The gate in which the EMC is transferred

into the cavity is at the top center of each mold cap. Care in

design and tooling of the gate is required to minimize thedimple left in the mold cap and the stress imparted during

degating. Otherwise, delamination can occur between

EMC and device top surface as the gap from gate to die top

is minimal (as small as 0.13 mm). This mold cap is 0.27 to

0.32 mm in thickness for 0.65 mm PoP interconnect pitch.

This requires the device within to be 0.075 to 0.100 mm

thick. Die attach material thickness must be tightly

controlled, necessitating the use of die attach films instead

of pastes in many instances. Thinner die and thicker mold

cap (within specified range) are required if the device hasmultiple bond pad rows requiring two tiers of wire-bond

loop heights. Wire loop height control and optimization is

essential to achieve the desired result. The TCMG process

allows for the mold cavity to fill in a radial fashion. This

helps prevent and minimize any wire sweep issues during

mold that could lead to electrical shorts.

Such die thinning and wire-bonding processes required

for the bottom PoP had already been developed andimplemented into production for stacked-die FBGAs.

Adapting this technology for the bottom PoP during the

development process was relatively straightforward. The

bigger challenge proved to be optimizing the materials in

order to meet acceptable warpage. The bottom PoP is

especially prone to warpage due to the mold cap’s not

extending to the edge of the package [8], [9]. The

unsupported package substrate at the periphery can experi-ence large fluctuations in warpage from room temperature

(RT) to reflow temperature. Control of warpage for larger

PoP size (15� 15 mm) with large die size (9� 9 mm) proved

to be most difficult. The bottom PoP invariably has a positive

or convex warpage at room temperature and negative or

concave warpage at reflow temperature, as shown in Fig. 6.

Warpage convention is per JEDEC specification [10].

Many variables related to the structure and materialproperties of the package materials influence the warpage.

These variables and their relative impact on warpage can

be seen in Table 2. Optimization of substrate thickness and

material, die attach thickness and material (die thickness is

usually constrained), and EMC material are key to meet

Table 1 3-D Package Reliability Requirements for Mobile Products

Fig. 5. TCMG molding.



Table 2 Factors Impact on Bottom PoP Warpage (14 mm and Above Size)

Fig. 6. Bottom PoP warpage trend.



the warpage requirement for the most difficult cases. Newmaterials are being developed and implemented in order to

meet the increasingly tight warpage targets of bottom PoP

users and applications.

The lessons learned from controlling bottom PoP

warpage for the most difficult large packages translate to

even tighter control for smaller packages. This fact that

smaller packages have less warpage is a factor driving

smaller PoP sizes.

C. Top PoPThe top PoP is essentially a stacked-die FBGA with a

peripheral array on the bottom of the package (Fig. 1).

Most products developed and in production today employ

two peripheral rows. The primary challenges for the top

PoP are package thickness and controlling warpage. The

burden primarily falls on the top PoP to reduce thicknessin order to reduce the overall stacked PoP height. This

drives the top PoP to implement the thinnest substrate, die

attach, die, and mold cap before most other stacked-die

products. Commonplace are 0.13-mm-thick two-metal

layer substrates, 0.075 mm die thickness, and smaller die

top to mold cap gaps (requiring vacuum molding).

Some memory devices are sensitive to die thinning.

They can encounter memory refresh rate problems or otherfunctional problems due to the method used or residual

stress caused by die thinning [11]. Wafer polishing is

usually used to relieve stress on the wafer backside after

thinning and improve die strength and resistance to

cracking. Wafer thinning processes without this polishing

step have been developed and applied to memory devices to

eliminate any functional problems caused by polishing

while still maintaining adequate die strength. Top PoP with0.060-mm and 0.050-mm-thick memory devices stacked

within will be introduced soon. Less than 0.100 mm die

thickness requires the use of die attach films as opposed to

pastes. With paste, it is difficult to have uniform thickness

and to prevent the paste from contaminating the top

surface of the die at the edge. Such films are laminated to

the wafer backside after wafer thinning. The use of films

also helps control the thickness. Die attach materialthickness is 0.020 to 0.025 mm for the bottom die

(attached to the package substrate) and 0.020 to 0.010 mm

thick for die-to-die attach. If two devices of the same size

are stacked, then a space is required in between to allow for

the wire bond (Fig. 1). In order to create this gap, very thin

silicon die (blank Si) spacers are attached between the

functional die. These are called spacer die. To reduce this

gap and overall package height, 0.065 to 0.75 mm die attachfilms that flow around the wire during attach are used.

The top PoP is pushing the limits of material thickness

and package assembly technology, but the larger challenge

is meeting the package warpage requirements. Like the

bottom PoP, the larger the package is, the more difficult to

meet the warpage requirement. Unlike the bottom PoP,

the top PoP has multiple stacked-die configurations and

structures. Thus, the warpage is not as predictable and canbe positive or negative at RT and reflow temperature. This

unpredictability requires a thorough understanding of how

structure and materials impact the warpage in order to

meet customer expectations. A lot of work has been

focused in this area [12]. Table 3 summarizes the impact of

key variables on the top PoP warpage. The nature of the

warpage at reflow temperature, whether it is positive or

negative, will dictate which materials, specifically, theEMC and die attach materials, would be needed to

minimize the warpage. For the most part, EMCs with

high glass transition temperatures (Tg) and low coefficient

of thermal expansion (CTE) are well suited for the top PoP.

Of course, the identified EMC also has to have good gap

filling and flow characteristics to avoid voids and wire

sweep during the mold process. Materials with improved

properties, tailored to the needs of this top PoP, are beingdeveloped to meet more demanding warpage targets as the

top PoP gets thinner and finer pitched.

D. PoP ReliabilityThe package-level reliability of the 15 � 15 mm

bottom PoP is summarized in Table 4. All of the require-

ments could be met. The package-level reliability of the

Table 3 Factors Impact on Top PoP Warpage (14 mm and Above Size)



15 � 15 mm top PoP with a five-die stack configuration

is summarized in Table 5. Again, all the requirements

could be met. This was also proven for a two-die stack

configuration.

The board-level reliability of the 15 � 15 mm PoP was

also tested. Drop test was done to JEDEC standard JESD22-

B111. A drop-test evaluation in which different solder ball

alloys and ball pad finish were tested is summarized inTable 6. The result of this evaluation is shown in Fig. 7 in

the form of a Wiebull plot. This result showed that

regardless of alloy type and pad finish, acceptable drop-test

performance could be achieved. BLR temperature cycle

(�45 to þ125 �C, 15 min ramp, 15 min dwells) was also

performed on Leg 1 to Leg 4 using the same JEDEC drop

test board. The result was no failure after 2000 cycles,

which exceeds all mobile OEM requirements.

E. PoP TrendsThe demand for smaller, thinner, and lower cost PoP

solutions has already been noted. The package density is

increasing. The performance requirement is also increas-

ing. This is driving the need for a flip-chip logic device in

the bottom PoP. The majority of new bottom PoP products

being designed today are flip-chip type. The flip-chip

structure allows for a lower mounted device height, which

enables 0.5 mm top PoP ball pitch, and reduced overall

stacked height (Fig. 8). Per JEDEC guidelines, the mounted

height of the device (or mold cap) of the bottom PoP should

be less than 0.22 mm in order to accommodate the 0.5 mm

PoP interconnect pitch [3]. This requires that the flip-chip

device be thinned to less than 0.125 mm and collapsed

bump height be less than 0.080 mm. Such thickness isalready implemented in production for other packages

(PiP, for instance). Again, the challenge is in controlling

the warpage. In the case of flip-chip bottom PoP, there is no

mold cap, so the substrate warpage is even harder to

control. The die thickness, bump height, underfill material,

substrate thickness, and material all play important roles in

modulating the warpage. In general, thicker substrates are

required to achieve the warpage target. Flip-chip bottomPoP with 0.5 mm pitch top PoP will be in launched for

several new products the latter half of 2008.

Stacking of die in the bottom PoP to accommodate

logic/logic, logic/analog, or logic/RF, integration is also a

trend (Fig. 9). Such packages need thinner die and require

0.65 or 0.80 mm top PoP ball pitch in order to allow

enough vertical space for the thicker mold cap on the

bottom PoP. The stacked-die bottom PoP is limited to

Table 4 Package Level Reliability 15 � 15 mm Bottom PoP (No Failures Due to Opens/Shorts and Delamination, 3 Lots � 77 Units Each Test After MSL)

Table 5 Package Level Reliability 15 � 15 mm Five-Die Stack Top PoP (No Failures Due to Opens/Shorts or Delamination,

4 Lots � 77 Units Each Test After MSL)



two-die stack at the moment. Such packages are near

production stage.

To address the need for smaller, thinner, and lowercost PoP solutions, some variations of the conventional

PoP are being developed and will likely ramp into

production in the near future. One of these is a version

of the bottom PoP in which the mold cap extends to the

package periphery and the lands that interconnect to the

top PoP are exposed on the top periphery of the package

(Fig. 10). This type of bottom PoP does not require the

TCMG molding process, like the conventional PoP, whichallows for reduced tooling cost. The structure also will

result in less warpage and enable the use of thinner

substrates since the substrate is supported to the package

edge. This structure also enables 0.5 mm top PoP,

especially for wire-bond type devices, as the moldthickness in the center of the package can be increased

as long as the height above the interconnect lands is less

than 0.22 mm.

Another variation of the PoP solution are versions in

which the interconnect lands are exposed on the center of

the top surface. This solution is sometimes called a

Bfan-in[ type solution since the package to package inter-

connects fan-in instead of fan-out like a conventional PoP.Such fan-in approaches have already been implemented in

production, but more cost-effective solutions are being

Table 6 15 � 15 mm PoP Drop Test Matrix

Fig. 7. 15 � 15 mm PoP drop test result Wiebull plot.



introduced leveraging the existing assembly infrastructure.

Fig. 11 shows a fan-in package-on-package (FiPoP) utilizing

an interposer substrate with top package interconnectlands on its surface, which is stacked on top of the

packaged device, interconnected to the base package

substrate by means of wire-bonds, and then molded such

that the interconnect lands are exposed on the top surface.

Such a package fundamentally decouples the top and

bottom package size, allowing the top package to be

smaller. Warpage of the package can be well controlled

due to its structure, especially warpage in the area of thetop package interconnect [13]. High-pin-count high-

density package interconnect pitch can be supported.The interconnection of the interposer substrate by means

of wire-bonds instead of solder balls at the periphery

reduces the package size. Even large die (> 9� 9 mm) can

be accommodated in 12 � 12 mm package size using this

structure.

The trends for the top PoP are to support the overall

thickness of the PoP solution. Further reduction in

package thickness and ball pitch to 0.5 mm is required,as already discussed. Two-die stack NAND and DRAM

combinations are becoming more prevalent, which helps

to reduce the package thickness compared to more

complex three to five die-stack combinations. Higher

pin-count (> 200 pins) top PoP memory packages are on

the horizon to support more demanding memory types and

architectures. This will require even finer package

interconnect pitch or additional peripheral rows.Testing of the top interconnect lands during electrical

test of the bottom PoP is allowing the pin-count of the

bottom package to be reduced. This also helps to reduce

the routing and layer count of the PCB. Many OEMs have

highlighted this advantage of the PoP to decrease the

complexity and cost of their motherboards. The PoP

solution is being considered for solutions beyond integrat-

ing processor and memory, such as integrating logic, RF,memory, and combinations thereof. Also, PoP is being

used for applications beyond the mobile phone, where

stacking tested packages in small form factors is needed. In

such applications, reflowing the packages together and

shipping the combined tested PoP solution is advanta-

geous, as such nonmobile customers are not familiar with

PoP reflow to the PCB.

There is tremendous activity and growth in the PoParea. Coupled with this growth is the need for innovation

to address the needs of the handset makers. PoP is

addressing the need to integrate the digital section of the

mobile phone to common platforms or building blocks that

are interchangeable but seamlessly integrate together.

IV. PiP TECHNOLOGY AND TRENDS

A. General RequirementsThe PiP is a somewhat novel stacked package concept.

The finished package has the same form, fit, and function

as a conventional FBGA. Development of the PiP focused

Fig. 10. PoP with step mold (mold cap extends to package edge).

Fig. 9. Two-die stack bottom PoP.

Fig. 8. Flip-chip PoP.

Fig. 11. Fan-in PoP type.



on meeting the same package thickness and size, package-level reliability, and board-level reliability as current FBGA

product offerings. The initial PiP development focused on

a single mobile SDRAM memory die housed in the ISM

package. The ISM was stacked on top of a two-die

processor stack (digital and analog devices). The overall

package height requirement was 1.4 mm maximum. Ball

pitch was 0.5 mm. The developed PiP was 15 � 15 mm in

size with a 12 � 12 mm ISM package within. Logic die sizewas over 10� 10 mm. This PiP example shows some of the

advantages of the PiP to integrate a device stack in the base

package with fully tested memory in 1.4 mm height. Such

integration would have been impossible for a conventional

PoP solution in this case because of the logic device size

and the difficulty to stack die in the base package without

increasing package thickness and size.

The required package-level reliability is JEDEC pre-condition MSL 3 at 260 �C. Other package-level reliability

requirements are the same as in Table 1.

The BLR requirement is focused on meeting the drop-

test requirement for mobile applications. Drop-test and

board-level temperature cycle were performed, but since

the PiP is essentially an FBGA, and similar FBGAs have

been proven to pass such BLR tests, no problem was

anticipated or encountered.The PiP is less sensitive to SMT process as it reflows to

the PCB like any other FBGA. The PiP meets JEDEC

specified coplanarity based on ball size (0.080 mm for

0.3 mm ball size on 0.5 mm pitch) and because of the

package structure warpage during reflow (lead-free, 260 �Cpeak temperature) is not much of a concern, but needs to be

verified acceptable.

B. ISMThe ISM for this initial PiP is 0.38 mm thick (see

Fig. 4). The mold cap was 0.25 mm thick and the substrate

was 0.13 mm thick. The memory die within the ISM was

thinned to 0.075 mm thick, and 0.025-mm-thick die attach

film material was used. This ISM is array molded on matrix

strip during the assembly process and then saw singulated

like most FBGA/FLGA type packages; however it isextremely thin, and therefore controlling the warpage of

the ISM is a key concern. The ISM needs to stack within the

PiP like a die. Therefore, flatness needs to be controlled in

order to assure proper stackup within the package. Too

much warpage can result in mold voids or exposed wire-

bonds at the surface of the PiP (ISM interconnect wires).

To achieve acceptable flatness, the EMC was found to

be the critical element. Several EMCs were evaluated, andone of them was optimized for this application. High Tg,

low CTE, and low shrinkage EMC was needed. Good flow

during mold of the EMC was needed because the mold gap

between die top and top of mold was only 0.15 mm.

During electrical test, the test handler and socket used

for this very thin ISM had to be verified to not cause

any damage or additional warpage of the ISM. Less than

0.080 mm of warpage is allowed after test. Also, the testedISM needs to be stacked in the PiP; therefore it needs to be

free of any contamination, especially in the interconnect

wire-bond terminal area. Physical and visual criteria

needed to be developed and implemented in order to

assure ISM quality so it could be stacked in the PiP.

C. PiPThe PiP is a stacked-die package, with one of the de-

vices stacked being the ISM; therefore the stacked-die

assembly infrastructure is used. The stacking and wire-

bonding of the two devices below the ISM in this initial

case was done using mass production materials and pro-

cess. The bottom digital device was thinned to 0.100 mm,

and the analog device on top was thinned to 0.100 mm.

After stacking the die, wire-bond is performed, and then

the ISM is stacked on top of the die stack (Fig. 12). Epoxypaste is used for ISM attach. The paste used has small

spacer spheres of 0.075 mm diameter within the material

to create a gap between the analog die such that the wire-

bonds will not be damaged during ISM attach.

The ISM attach is the unique process to the PiP

package. The ISM is a fully tested LGA package and comes

in tray form, not wafer form like a typical device stacked in

the package. Existing die attach equipment was modifiedto handle a magazine of trays and to pick the ISM from the

tray rather than a sawn wafer on metal ring. Also, the

critical interface in the PiP package is the ISM mold cap to

ISM-attach material. The proper ISM-attach epoxy needed

to be selected to ensure the required package-level

reliability performance.

After the ISM is stacked, the interconnect wire-bond is

performed and the package is array molded in strip form.Again, the proper EMC selection is critical here. Warpage

is not so much of an issue due to the PiP structure, but the

EMC must have good adhesion to all the materials stacked

in the PiP in order to meet the reliability requirement.

D. PiP ReliabilityThe package-level reliability of the PiP is summarized

in Table 7. All the reliability requirements were met forthe developed 15 � 15 mm PiP. BLR test was also

performed. As expected, the PiP has similar BLR

performance to an equivalent FBGA package with the

Fig. 12. PiP showing wire-bonded two-die stack with ISM stacked

on top.



same die size mounted within. Acceptable drop test and

BLR temperature cycle result was achieved.

E. PiP TrendsThe PiP is well suited for high-performance applica-

tions. Whereas in the case of PoP, the top package is system

memory that is stacked on top instead of beside the logic

package on the mobile phone PCB, the memory ISM in the

PiP can be system memory or additional cache memory for

the logic processor. The development of flip-chip versionsof the PiP quickly followed the development of the wire-

bond version to increase the density and performance [14].

The PiP allows more device integration flexibility

below the memory ISM. The first PiPs had wire-bond die

stacks or flip-chip and wire-bond stacks. PiPs are currently

in development that will have multiple flip-chip die side by

side on the base substrate. PiP allows the highest level of

integration of probed-good die and tested good packages inthe smallest form factor.

PiP variations with two-die stacked in the ISM are

already in mass production. Thinner ISM (0.3 mm

thickness for single die package) has already been

developed. Also, the trend is to shrink the ISM, as the

memory die and logic die shrinks in order to minimize the

PiP size. A PiP of less than 1.2 mm thickness has been

developed using thinner ISM and die thickness.Several large IDMs have adopted the PiP solution for

3-D package integration. The benefits are higher perfor-

mance integration of known good packages in the

smallest form factor. As the memory performance

requirements increase for handheld device applications,

the PiP is well suited to handle this trend. The PiP is also

well suited to handle the complex integration schemes

envisioned for advanced applications.

V. SUMMARY AND CONCLUSION

The emergence of the 3-D package solution has been

driven by the need to integrate devices in the smallest form

factor and cost to support the feature-rich and memory-

hungry requirements of mobile phones. The die-stack

solution is well suited for memory stacking, but fell short

for logic and memory stacking due to yield- and business-related problems. Thus, 3-D package solutions combining

tested good packages were developed, namely, the PoP

and PiP.

The PoP and PiP have fundamentally different

structures and bring different advantages to the market.

The PoP is larger in size and is composed of two separate

packages. This is most desirable for business flow and

supplier flexibility, but requires the two packages to bereflowed simultaneously to the PCB. Development of the

PoP focused on optimizing the structure and materials to

avoid excessive warpage that could impact SMT yields and

BLR. Package-level and board-level reliability was

achieved. The trend for PoP is smaller size and lower

height, which in turn is driving finer ball pitch and flip-

chip device interconnect. Flip-chip is being driven by

performance as well. Variations upon the PoP theme arecoming to the market that allow for smaller package sizes

and denser interconnect. The PoP is poised for continuous

growth and innovation.

The PiP offers higher performance and more seamless

integration in that the final package is like a conventional

FBGA. Development focused on controlling the flatness of

the thin ISM package that is stacked in the PiP like a die.

Stacked-die assembly techniques were used to produce thispackage. Care had to be taken in material selection to meet

reliability and yield goals. All package-level reliability

requirements were met. The BLR of the PiP follows that of

an equivalent FBGA package. Wire-bond of the ISM to the

base package allows for a short electrical path. The PiP is

well suited for higher speed memory configurations. The

PiP has more flexibility to support different stacked or

side-by-side device configurations within. Flip-chip ver-sions of the PiP quickly followed initial wire-bond versions

to take advantage of the density and performance of the

PiP structure. Thinner, higher density versions of the PiP

are on the horizon. PiP currently has a smaller user base

than PoP, but as integration challenges and performance

demands increase, the PiP may experience increased

market share.

Table 7 Package Level Reliability 15 � 15 mm PiP (No Failures Due to Opens/Shorts and Delamination)



Both the PoP and PiP are packages that ten years agoperhaps very few people could have envisioned being

introduced into mass production. Such innovation is

required to meet the demands of the mobile market,

which continues to experience explosive growth with no

end in sight. As the future unfolds and the line between

handset and personal computer blurs, it will be interest-

ing to see how the packaging landscape will evolve.

Surely, PoP, PiP, and variations thereof will play animportant role and act as guideposts toward the future

packaging path. h

Acknowledgment

The authors thank the following members of STATS

ChipPAC Inc.: M. K. Lee and K. T. Kang, managers of thePiP and PoP package development teams, respectively; and

Dr. G. S. Kim and H. T. Lee, managers of the material

development teams. Dr. R. Pendse’s contributions to the

development of flip-chip variations are acknowledged. The

leadership of K. Lee and Dr. B. J. Han, as Vice President of

Worldwide R&D and CTO, respectively, should be duly

recognized.

REF ERENCE S

[1] The Week, vol. 8, no. 349, p. 38,Feb. 22, 2008.

[2] Package-on-Package (PoP) and InternalStacked Module (ISM). (Top Package12 � 12 mm, .65 mm Ball Pitch, �16F/NAdmux, �16 DRAM Option BA and�16NAND, �16 F/D DDR Option BBMultibus.), JESD21-C, MPC3_12_02, JEDEC,Nov. 2007.

[3] Fine-Pitch, Square Ball Grid Array (FBGA)Package-on-Package (PoP), JEDEC Pub. 95,Design Guide 4.22, JEDEC, Nov. 2007,Issue B.

[4] StandardVInternal Stacking Module,Land Grid Array Packages With ExternalInterconnect Terminals (ISM).Item 11.2-699(S), JEDEC Pub. 95, DesignGuide 4.21, JEDEC, Mar. 2007.

[5] K. Ishibashi, BPoP (package-on-package)stacked yield loss study,[ in Proc 57th IEEEECTC, Reno, NV, May 2007, pp. 1403–1408.

[6] IPC/JEDEC, ‘‘Moisture/reflow sensitivityclassification for nonhermetic solid statesurface mounted devices,[ J-STD-020D,Jun. 2007.

[7] JEDEC, ‘‘Board level drop test method ofcomponents for handheld electronicproducts,’’ JESD22-B111, Jul. 2003.

[8] F. Carson, BPOP developments and trends,[in Proc 2006 IMAPs Device Packag. Conf.,Scottsdale, AZ, Mar. 2006.

[9] N. Vijayaragavan, F. Carson, and A. Mistri,BPackage on package warpageVImpact onsurface mount yields and board levelreliability,[ in Proc. 58th IEEE ECTC.

[10] JEDEC, ‘‘High temperature package warpagemeasurement methodology,’’ JESD22-B112,May 2005.

[11] D. Sempek, BDesign feature: Packagingstacked memory,[ Electron. Design News,Feb. 3, 2005.

[12] F. Carson, S. M. Lee, and N. Vijayaragavan,BControlling top package warpage,[ in Proc.57th IEEE ECTC, Reno, NV, May 2007,pp. 737–742.

[13] F. Carson, BThe development of the fan-inpackage-on-package,[ in Proc. 58th IEEEECTC, submitted for publication.

[14] R. Pendse et al., BFlip chip package-in-package(fcPiP): A new 3D packaging solution formobile platforms,[ in Proc. 57th IEEE ECTC,Reno, NV, May 2007, pp. 1425–1430.

ABOUT THE AUT HORS

Flynn P. Carson received the B.S. degree in

mechanical engineering and material science

from the University of California, Davis.

He is Vice President of Emerging Technology

with STATS ChipPAC, Inc., responsible for new

product and technology introduction, especially in

the area of advanced 3-D packaging for mobile

and memory applications. He has more than

19 years’ experience in the semiconductor pack-

aging industry supporting production and devel-

oping new products.

Young Cheol Kim received the B.S. degree in

metallurgical engineering from Hanyang Univer-

sity, Seoul, Korea.

He is Deputy Director of R&D with STATS

ChipPAC, Inc., responsible for advanced 3-D pack-

aging technology development for mobile appli-

cations. He has 17 years’ experience in the

semiconductor packaging industry supporting

and developing new products.

In Sang Yoon received the B.S. degree in metal-

lurgical engineering from Chunnam University,

Korea.

He is Senior Director of R&D with STATS

ChipPAC, Inc., responsible for new package devel-

opment in the area of stacked die and stacked

package for memory applications. He has 21 years’

experience in the semiconductor packaging in-

dustry developing new products.



3-D Stacked Package Technology and Trends

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