2PARMA Project and P2012 Platform -...
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FP7-248716-2PARMA Project
2PARMA Projectand P2012 Platform
REFLECT and 2PARMA Fall 2012 School:Programming Paradigms for Multi--‐Core Embedded Systems
October 2, 2012
Prof. William FornaciariPolitecnico di Milano
[email protected]/fornacia
Project Technical Manager of 2PARMA
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List of Project Partners
FP7-248716-2PARMA Project 2
1. Politecnico di Milano (POLIMI) – Italy
(Coordinator)
2. STMicroelectronics (STM) – Italy
3. Fraunhofer Institut for Telecommunications /
Heinrich-Hertz Institut (HHI) – Germany
4. Interuniversitair Micro-Electronica Centrum
(IMEC) – Belgium
5. Institute of Communication and Computer
Systems (ICCS) - Greece
6. RHEINISCH-WESTFAELISCHE TECHNISCHE
HOCHSCHULE AACHEN (RWTH) - Germany
7. Synopsys (CoWare) [Y1-Y2]– Belgium
Start date: January 1st, 2010
Project duration: 3 years
(+ 3 months extension)
Total effort: 408 PM
EC Contribution: 2.74 M€
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Back-ground & side-ground projects
FP7-248716-2PARMA Project 3
PRO3DArtemis - SMECY
HiPEAC2ENIAC- TOISE
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Scientific and Technical Objectives
Main Goals
• Programmability of Many-core Computing Fabrics
• Virtualisation and Continuous Adaptation
• Design Space Exploration
• Runtime Adaptivity
Project Outcomes
• Integrated Compiler Toolchain and OS Layer
• DSE Toolchain
• Run-time Resource Manager
FP7-248716-2PARMA Project 4
The 2PARMA project focuses on the definition of suitable parallel programming models, instruction set virtualisation, run-time energy/power and resource management policies and mechanisms as well as design space exploration
methodologies for Many-core Computing Fabrics.
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Many-Core Computing Fabric Template
FP7-248716-2PARMA Project 6
The 2PARMA project focuses on the flexible family of parallel and scalable computing processors, which we call Many-core Computing Fabric Template, composed of many processing cores interconnected by an on-chip network.
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Platform 2012: Scalable Architecture Template
Source: STMicroelectronics
Platform 2012: A Many-core Programmable Accelerator for Ultra-Efficient
Embedded Computing in Nanometer Technology
The node:- From 8 to 16 cores
- Shared memory architecture- Floating point extension instead of vectorial extension- Capability to add HW blocks in the cluster
FP7-248716-2PARMA Project
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P2012 Cluster
Cluster Controller
Debug & Test Unit BOUTBIN
ENCore<N>
TMS TCK TDI TD0 BI BOTMS TCK TDI TD0 BI BO
HWPE-WPR
… x K …
CC InterfaceENCore Interface
N:1 Mux/Arbiter
DMAsub-system
CC interconnect, CCI
StreamingInterface,
SIF
CP Sub-System
CVP
STxP70-basedCluster
Processor, CP32K I$,16K TCDM,
32-entry ITC
CC-Peripherals
DMAChannel #0
BI
JTAG
BO
V0.2 Backbone
HardWare Synchronizer, HWS
Shared 256-KB, 2xN-bank TCDM
… x N…PE#0
I$
PE#1
PE#N-1
I$ I$
DMAChannel #1
DMAChannel #P-1
Asynchronous Local Interconnect, LIC (Configuration + Stream LIC, 32 bits)
…
NI64
ExtSIF
TMS TCK TDI TD0 BI BO
GIC
GALS I/F
GALS I/FSIF
NI3
2
HWPE-WPR
GALS I/FSIF
NI3
2
HWPE-WPR
GALS I/FSIF
NI3
2
M/S
GALS I/F
NI3
2
M
T3
HWPE #0 HWPE #1 HWPE #K-1
IT To CCIT To CC IT To CC
T3
Cluster Architecture evolutionssupporting many applications.
Heterogeneous Cluster RTL implementation(s): ENCore<N>, Cluster Controller,
Cluster Control, DMA Control,
Debug logic, Stream-flow logic, User-def. HWPEs.
Configurable(N, EFUs, banking factor, …)
“Computing Farm”
(supplied by “Computing”)
For SW PEs and/or intensive control
Debug Multicore Debug
Stream-flow logicInter-HWPE communication,
L3 or shared Memory HWPEs communication.
User-defined HWPEs
Source: STMicroelectronics
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FP7-248716-2PARMA Project
Platform 2012: Positioning
Source: STMicroelectronics
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FP7-248716-2PARMA Project
More on P2012 (now STHORM)
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IMEC COBRA Platform
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Synopsys Virtual Platforms [Y1 and Y2]
1. Abstract model mimicking P2012 in support of CBSE methodology
1. ARM based multi-core platform supporting Linux OS for design tool validation– Integration with DSE tools– Investigate RTRM support
FP7-248716-2PARMA Project 12
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Clustered General Purpose [Y3]• Reference multicore x86 architecture
• AMD NUMA machine with four nodes (clusters)
• Each node is a quad core Opteron 8378 processor • L1 cache is composed of 64KBytes data cache and 64KBytes
instruction cache• L2 cache is a 512KBytes unified cache • All cores within a node share unified 6144KBytes L3 cache • Inter-node communication is supported by a ring network
topology
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AMD x86 core Cluster (4 cores)
2GB DRAM
2GB DRAM 2GB DRAM
2GB DRAM HyperTransport Ring Network
FP7-248716-2PARMA Project
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2PARMA Target Applications
• Scalable Video Coding (SVC) – HHI
• Cognitive Radio– Physical Layer – RWTH-ISS– MAC Layer – RWTH-iNETs– Reconfigurable Radio – IMEC
• Multi-view Image Processing - IMEC
FP7-248716-2PARMA Project 14
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Applications/Architecture Integration
FP7-248716-2PARMA Project 15
OS Integration Layer
Run-time Management and Virtualisation
PHY
MAC
Cognitive Radio
ScalableVideo
Coding
Multi-view
REC
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Use Case UC1a UC3 UC4a UC5 UC6
Application
CR PHY Layer(CBSE Nuclei)
CR MAC(CBSE Nuclei)
SVC(CBSE MIND)
MultiVIEW(OpenCL)
MultiVIEW(OpenCL)
+SVC
(MIND)
PlatformSTM P2012 STM P2012 STM P2012 STM P2012 X86 Multi‐core
Objective
Performance evaluation of multi‐core
architectures
Performance evaluation of multi‐core
architectures
Integration&
Final Validation & Demonstration
OpenCL Toolchain Integration
& Validation
Broader Applicability
WP2 TaskOpenCL Toolchain T2.1 NA NA NA √ √ (Mul View)
LLVM Dynamic Compiler T2.2 NA NA NA √ √(Mul View)
CBSE toolchain T2.1 √(Nuclei)
√(Nuclei)
√(MIND) NA √ (SVC MIND)
CF device drivers T2.3 √ √ √ √ NA
WP3 Task
NoCTrace T3.1 & T3.2 √ √ √ √ √ 3
MOST ‐ DSE T3.3 √ No effort √ √ √
WP4 Task Dynamic Data MGT T4.1 NA 1 √ √ √ √
RuntimeTask Monitoring
T4.2 NA 1 √ 2 √ √ √
Runtime Resource MGR T4.3 NA 1 No effort 2 √ √ √
2PARMA Use cases [Y3]
Vertical Dimension: Tools Integration
Horizontal Dimension: Validation of the broad applicability of tools and techniques
LegendaNA = Not Applicable(1) Data and Resource Management are critical for keeping real-time constraints therefore data and task allocation should be managed statically.(2) CBSE Nuclei Toolchain includes runtime task monitoring and management. (3) Noc Trace with reduced functionalities due to the lack of SystemC simulator
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Partners role
WP2: Programmability of Parallel Computing Systems to Exploit Task/Data Parallelism
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Mapping OpenCL to Computing Fabrics
• Analysis of OpenCL programming model (strengths and weaknesses) vs P2012 Computing Fabric
• Specification of Computing Fabric-specific extensions to OpenCL• Proposed OpenCL extensions targeting Computing Fabrics• OpenCL front-end compilation toolchain for LLVM to be publicly
released soon• Dynamic compilation to adapt parallelism to system resources
18FP7-248716-2PARMA Project
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NI
PE 2(rASIP)
PE 3(DSP)
MEM
Comm. Arch.
PE 5(FPGA)
PE1(ASIP)
PE 4(GPP)
HWPlatform
PEs
Nuclei N 1 N 2 N 7 NNN 5
PE 2 PE 3 PE 4 PE 5PE 1
NI
Transceiver Description
Transceiver DescriptionN 1
N 7 N 5N 2 Non N Tasks
NucleusLibrary
Flavor
Nucleus Methodology
Nucleus Project within UMIC research cluster at RWTH Aachen University
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PE 2(rASIP)
PE 3(DSP)
MEM
Comm. Arch.
PE 5(FPGA)
PE1(ASIP)
PE 4(GPP)
HWPlatform
PEs
BoardSupportPackage
Nuclei
PE 2PE 1 PE 3 PE 4 PE 5
N 1 N 2 N 7 NNN 5
NINI
NI
NI NNI
Transceiver Description
Transceiver DescriptionN 1
N 7 N 5N 2 Non N Tasks
Mapping&
EvaluationCompile
Flavors
NucleusLibrary
NINI
Nucleus Methodology
Nucleus Project within UMIC research cluster at RWTH Aachen University
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Component-basedSoftware Engineering Toolchain
User inputs
N1 N2 NN1
N3
Waveform descriptionConfig & constraints
.xml .xml
Nucleus Mapper
Libraries
Nucleus Library
Board SupportPackage
FlavorLibrary
.xml
Platform Description
SynopsysVirtual Platform
STM P2012Platform
Code Generator
Synopsys IP requiredPA, VPU library, … STM P2012 SDK required
Nucleus IP required
Application domainspecific knowledge required
2PARMA IP – WP4
Application domainspecific knowledge required
Nucleus Project within UMIC research cluster at RWTH Aachen University
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Partners role
WP3: Co-exploration of Architectural Platforms and Programming Models
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HHI NoCTrace Architecture
• NoCTrace backend– collects data
• NoCTrace frontend– processes data– manages data
(persistency)– presents data
(GUI)
FP7-248716-2PARMA Project
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HHI NoCTrace Backend
• Extract/record program counter and transaction data in SystemC kernel
• Perform automatic design analysis to get to know where to place the probes
FP7-248716-2PARMA Project
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Automatic Multi-Objective Design Space Exploration
Source: Politecnico di Milano - MPEG2 decoder, generated with Multicube Explorer
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• Based on the design-time exploration, we derive a set of Pareto operating points corresponding to power, resources (number of cores) and QoS (average time per frame).
• The operating points will be used by the Run-time Resource Manager to achieve QoS requirements (average time per frame) while meeting overall resources (number of cores) and minimizing power consumption
Design-time Exploration to supportRun-time Resource Management
FP7-248716-2PARMA Project
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Partners role
WP4: Runtime Resource Management
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2PARMA RTRM – Different levels
System-level BBQApplication level
Application parameter monitoring and reconfigurationHeap management dmmlibPlatform Level
Run-time on the chip for thermal/power management, scheduling, …
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RTRM offers an integrated solutionand the mechanisms to performoptimal WM selection at run-time
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What is a working mode?
Application Parameters
Platform Parameters
Adaptive DMM Parameters(example)
Design Space Exploration
#CPUs $mem Size Instr. width ... Multiview SDR Heap arch Locking ... # Lists Fit policy
App. ParamsPlatform Params Adaptive DMM Params
FP7-248716-2PARMA Project
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Objectives of each RTRM level
BBQ objective to perform an efficient resource partitioning w.r.t run-time optimization goals
Application parameter monitoring and reconfiguration Continuously maximize output quality while meeting constraints
Heap management to accommodate the applications’ needs within the allocated memory space (from the OS/system-wide controller)
FP7-248716-2PARMA Project 30
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2PARMA RTRM control approach
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2PARMA RTRM control approach
Hierarchical controlSystem-wide level (e.g., resource partitioning)Application specific (tuning of application parameters, DMM)Firmware/OS level (frequency selection, thermal alarm, resource availability, adaptive
voltage scaling, …)Closed control loop enhanced with feed forward
OP and AWM increase convergence speedDistributed control
Several subsystems have their own control loop
OptimalUser defined goal functions
(including overheads)Robust
Can adapt to the model characteristicsAdaptive
The control algorithm is run-time computedEnforce observability and controllability
Rich set of sensing and control capabilities,both for applications and platforms
Bounded and measurable response time
FP7-248716-2PARMA Project 32
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The 2PARMA Run-Time Resource ManagerOverall view
System-Wide RTRM
Application-Specific RTRM
Dynamic CodeGeneration
Task Mapping
DDM
Appcr Appbe
RTLib
Res Accounting Res PartitioningResource Abstraction
MRAPI
Platform DRVPlatform DRVPlatform Driver
Platform Proxy
supported platforms
Kernel space
User space
Platform Firmware
X SW Interface (API)
SW/HW Meta-dataY
Legend
FP7-248716-2PARMA Project 33
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Project Promises1. Increased performance, power-efficiency and reliability of
Many-core Computing Fabrics by means of:– Fine grained platform configuration – Dynamic resource management techniques
2. Improved time to market for high-performance applications requiring hardware acceleration by means of:– ISA virtualisation on computing fabrics.– Supporting the full toolchain, including compilation and OS support
3. Reinforced European scientific and technological leadership in the multi-core computing architectures both at:– Industry side (STM as a large company) – Academic side (POLIMI, HHI, IMEC, ICCS and RWTH)
4. The project will contribute to Free and Open Source projects: – LLVM Static and Dynamic compiler– MULTICUBE Explorer framework– Runtime Resource Manager (BBQ) on top of Linux OS
5. The project will also spearhead the evolution of standards in the field of parallel programming models and languages (such as OpenCL)
FP7-248716-2PARMA Project
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January 14-15, 2010 FP7-248716-2PARMA Project
www.2parma.eu
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Thanks for your attentionAny question?
Prof. William FornaciariPolitecnico di Milano
[email protected]/fornacia
Project Technical Manager of 2PARMA