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I n t e l S t r a t a F l a s h S y n c h r o n o u s M e m o r y( K 3 / K 1 8 )2 8 F6 4 0K 3 , 2 8 F6 4 0K 1 8 , 2 8 F1 2 8K 3 , 2 8 F1 2 8K 1 8 , 2 8 F 25 6 K 3 ,

2 8 F 2 5 6 K 1 8 ( x 1 6 )

D a t a s h e e t

P r o d u c t F e a t u r e s

T h e I n t e l S tr a t a F l as h S y n c h ro n o u s M e m o r y ( K 3 / K 1 8) p r o d u ct l i n e a d d s a h i g h p er f o r m a nc eburst-mode interface and other additional features to the Intel StrataFlash memory family ofproducts. Just like its J3 counterpart, the K3/K18 device utilizes reliable and proven two-bit-per-c e l l t e c hn o l o g y t o d e l i ve r 2 x t h e m e m o r y i n 1 x t h e s p a c e, o f f e r i n g h i g h d e n s it y f l a s h a t l o w c o s t .This is Intels third generation MLC technology, manufactured on 0.18 m lithography, makingit the most widely used and proven MLC product family on the market.

K 3 / K 1 8 i s a 3 - v o l t d e vi c e ( c o re ) , b u t i t i s a v ai l a b l e w i t h 3 - v ol t ( K 3 ) o r 1 . 8 - vo l t ( K 1 8 ) I / Ov o l t a ge s . T h e s e d e vi c e s a r e i d e a l f o r m a i n s t r ea m a p p l i c a ti o n s r e q u i ri n g l a r g e s t o r a ge s p a c e f o r

both code and data storage. Advanced system designs will benefit from the high performancepage and burst modes for direct execution from the flash memory. Available in densities from 64Mbit to 256 Mbit (32 Mbyte), the K3/K18 device is the highest density NOR-based flash

c o m p on e n t a v a il a b l e t o da y, j u s t a s i t w a s w h e n I n t e l i n t r o du c e d t h e o r i g i n al d e v i c e i n 1 9 9 7.

Performance 110/115/120 ns Initial Access Speed for

64/128/256 Mbit Densities 25 ns Asynchronous Page-Mode Reads,

8 Words Wide 13 ns Synchronous Burst-Mode Reads,

8 or 16 Words Wide 32-Word Write Buffer Buffered Enhanced Factory

Programming

Software 25 s (typ.) Program and Erase Suspend

Latency Time Flash Data Integrator (FDI), Common

F l a s h I n t e r f a ce ( C F I ) C o m p a t ib l e Programmable WAIT Signal Polarity

Quality and Reliability Operating Temperature:

40 C to +85 C 100K Minimum Erase Cycles per Block

0.18 m ETOX VII Process

Architecture Multi-Level Cell Technology: High

D e n s it y a t L o w C o s t Symmetrical 64 K-Word Blocks 256 Mbit (256 Blocks) 128 Mbit (128 Blocks)

64 Mbit (64 Blocks) Ideal for CODE + DATA applications

Security 2-Kbit Protection Register Unique 64-bit Device Identifier Absolute Data Protection with VPEN and

WP# Individual and Instantaneous Block

L o c k in g , U n l o c k i n g a n d L o c k - D ow nCapability

Packaging and Voltage 64-Ball Intel Easy BGA Package 56-and 79-Ball Intel VF BGA Package VC C = 2 .7 0 V 3. 60 V

VC C Q = 1 .6 5 1 .9 5 V or 2 .3 75 3 .6 0 V

Order Number: 290737-006

June 2003

N o t i c e :This document contains information on new products in production. The specificationsare subject to change without notice. Verify with your local Intel sales office that you have the lat-est datasheet before finalizing a design.

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2 D a t a s h e e t

Information in this document is provided in connection with Intelproducts. No license, express or implied, by estoppel or otherwise, to any intellectualproperty rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liabilitywhatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating tofitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are notintended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined. Intel reserves these forfuture definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The 3 Volt Synchronous Intel StrataFlashMemory may contain design defects or errors known as errata which may cause the product to deviatefrom published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com.

Copyright Intel Corporation, 2003.

*Other names and brands may be claimed as the property of others.

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D a t a s h e e t 3

2 8 F 6 4 0K 3 , 2 8 F 6 40 K 1 8 , 2 8 F 1 2 8 K 3 , 2 8 F 1 2 8K 1 8 , 2 8 F 2 5 6 K 3 , 2 8 F 2 5 6K 1 8

C o n t e n t s

1.0 I n t r o d u c t i o n ..................................................................................................................7

1.1 Document Purpose................................................................................................7

1.2 Nomenclature........................................................................................................7

1.3 Conventions ..........................................................................................................8

2. 0 Dev i c e Des c r i p t i o n ....................................................................................................9

2.1 Product Overview ..................................................................................................9

2.1.1 High Performance Page/Burst Modes......................................................9

2.1.2 Single Chip Solution .................................................................................9

2.1.3 Packaging Options .................................................................................10

2.1.4 Product Highlights ..................................................................................10

2.2 Package Diagram................................................................................................11

2.3 Signal Descriptions..............................................................................................14

2.4 Block Diagram .....................................................................................................152.5 Memory Map .......................................................................................................16

3.0 D ev i c e O p e r a t i o n s ...................................................................................................17

3.1 Bus Operations....................................................................................................17

3.1.1 Read Mode.............................................................................................17

3.1.2 Write/Program ........................................................................................18

3.1.3 Output Disable........................................................................................18

3.1.4 Standby ..................................................................................................18

3.1.5 Reset ......................................................................................................18

3.2 Device Commands ..............................................................................................19

4.0 R e ad M o d e s ................................................................................................................21

4.1 Asynchronous Page-Mode Read ........................................................................214.2 Synchronous Burst-Mode Read ..........................................................................22

4.3 Read Configuration Register ...............................................................................22

4.3.1 Read Mode.............................................................................................23

4.3.2 Latency Count ........................................................................................23

4.3.3 WAIT Polarity .........................................................................................25

4.3.4 Data Hold ...............................................................................................25

4.3.5 WAIT Delay ............................................................................................26

4.3.6 Burst Sequence......................................................................................26

4.3.7 Clock Edge.............................................................................................26

4.3.8 Burst Length...........................................................................................26

5.0 P r o g r a m M o d e s .........................................................................................................27

5.1 Word Programming .............................................................................................275.2 Write-Buffer Programming...................................................................................27

5.3 Program Suspend ...............................................................................................28

5.4 Program Resume ................................................................................................29

5.5 Buffered Enhanced Factory Programming (Buffered-EFP).................................29

5.5.1 Buffered-EFP Requirements and Considerations ..................................29

5.5.2 Buffered-EFP Setup Phase....................................................................30

5.5.3 Buffered-EFP Program and Verify Phase ..............................................30

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4 D a t a s h e e t

5.5.4 Buffered-EFP Exit Phase .......................................................................31

6.0 E r a s e M o d e .................................................................................................................32

6.1 Block Erase.........................................................................................................32

6.2 Erase Suspend....................................................................................................326.3 Erase Resume ....................................................................................................33

7.0 Sec u r i t y Mo d e s .........................................................................................................34

7.1 Block Locking Operations ...................................................................................34

7.1.1 Block Lock..............................................................................................35

7.1.2 Block Unlock ..........................................................................................35

7.1.3 Block Lock-Down ................................................................................... 35

7.1.4 Block Lock During Erase Suspend.........................................................35

7.1.5 WP# Lock-Down Control........................................................................35

7.2 Protection Registers............................................................................................36

7.2.1 Reading the Protection Registers ..........................................................37

7.2.2 Programming the Protection Registers .................................................. 37

7.2.3 Locking the Protection Registers ...........................................................377.3 Array Protection ..................................................................................................37

8.0 S p e c i a l M o d e s ...........................................................................................................38

8.1 Read Status Register ..........................................................................................38

8.1.1 Clear Status Register .............................................................................39

8.2 Read Device Identifier.........................................................................................39

8.3 Read Query/CFI .................................................................................................. 40

8.4 STS Configuration (Easy BGA package ONLY) .................................................40

9.0 P o w e r a n d R es e t ......................................................................................................41

9.1 Power-Up/Down Characteristics ......................................................................... 41

9.2 Power Supply Decoupling...................................................................................41

9.3 Reset Characteristics ..........................................................................................4110.0 E l ec t r i c a l S p ec i f i c a t i o n s ........................................................................................42

10.1 Absolute Maximum Ratings ................................................................................42

10.2 Operating Conditions ..........................................................................................42

10.3 DC Current Characteristics .................................................................................43

10.4 Read Operations.................................................................................................45

10.5 Write Operation ................................................................................................... 50

10.6 Block Erase and Program Operation Performance.............................................52

10.7 Reset Operation ..................................................................................................53

10.8 AC Test Conditions .............................................................................................54

10.9 Capacitance ........................................................................................................54

Ap pen di x A Wr it e Sta te Mac hi n e (WSM)...............................................................................55

Ap pen di x B Com mo n Flas h In ter fa ce ....................................................................................60Ap pen di x C Flo wc har ts ...............................................................................................................66Ap pen di x D Mec han ic al Pac kag e Inf or mat io n ...................................................................74

Ap pen di x E Ad di ti on al In f or mat io n ........................................................................................77Ap pen di x F Ord er Inf or mat io n ..................................................................................................78

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2 8 F 6 4 0K 3 , 2 8 F 6 40 K 1 8 , 2 8 F 1 2 8 K 3 , 2 8 F 1 2 8K 1 8 , 2 8 F 2 5 6 K 3 , 2 8 F 2 5 6K 1 8

R e v i s i o n H i s t o r y

D a t e o fR e v i s i o n Re v i s i o n De s c r i p t i o n

08/22/01 -001 Original Version

09/24/01 -002 Corrected Typographical Errors in 11.0 AC Characteristics section.

09/27/01 -003 Change VFBGA Package from 64 to 56 ball package. Add ordering info inAppendix E.

02/22/02 -004 Changes to ballouts per engineering review and editing/formatting updates.

06/17/02 -005 Changes to Iccr, elimination of Speed Bin 2, expansion of Vccq range.

06/11/03 -006 Corrections to Ordering Information, typcs, added Next-State Table, Appendix Ainfo. Added table of Latency Count settings to Section 4.3.2.

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6 D a t a s h e e t

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2 8 F 6 4 0K 3 , 2 8 F 6 40 K 1 8 , 2 8 F 1 2 8 K 3 , 2 8 F 1 2 8K 1 8 , 2 8 F 2 5 6 K 3 , 2 8 F 2 5 6K 1 8

D a t a s h e e t 7

1.0 In t r o d u c t i o n

1. 1 Do c u m en t Pu r p o s e

T h i s d o c um e n t c o nt a i n s i n fo r m a t i o n p e r t a i ni n g t o t h e I n t e l S t r a ta F l a s h S y nc h r o n ou s M e m o r y( K 3 / K 1 8) d e v ic e . Th e p u r p o se o f t h i s d oc u m e nt i s to d e sc r i b e t h e f e a t u re s , o pe r a t i on s an ds p e c i fi c a t i o ns o f t h e s e d e v i c es .

1. 2 No m en c l at u r e

3 Volt core: VC C r an ge o f 2 .7 V 3. 6 V3 Volt I/O: VC C Q r a n g e of 2 . 3 7 5 V 3 . 6 V1.8 Volt I/O: VC C Q r a ng e of 1 . 65 V 1 . 9 5 VAMIN: F o r E a sy B G A p a ck a ge s : AMIN = A1

F o r V F B G A pa c k a ge s : AMIN = A0AMAX: F o r E a sy B G A p a ck a ge s :

64 Mbi t A MAX = A221 2 8 M b it A MAX = A23256 Mbit A MAX = A24F o r V F B G A p a c k ag e s :64 Mbi t A MAX = A211 2 8 M b it A MAX = A22256 Mbit A MAX = A23

Block: A g r o u p o f f l a s h c e l l s t ha t s h a r e c om m o n e r as e c i r c ui t r y a n d e r a se s i m u l t an e o u s l yProgram: To write data to the flash arrayVPEN: Refers to a signal or package connection nameVPEN: R e f e r s t o t i m i n g o r v o l t a ge l e v e l sCUI: C o m m a nd U s e r I n t e r f a ceOTP: O n e T im e P r og r am m a bl ePR: Protection RegisterPLR: Protection Lock RegisterRFU: R e s e r ve d f o r F ut u r e U s eSR: Status RegisterRCR: Read Configuration RegisterWSM: Write State MachineMLC: Multi-Level CellSet: I nd i ca te s a l og i c o n e ( 1 )Clear: I n di c at e s a l o g ic z e r o ( 0 )

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8 D a t a s h e e t

1.3 Co n v en t i o n s

0x: Hexadecimal prefix0b: B i n ar y p r ef i x

k (noun): 1,000M (noun): 1,000,000Byte: 8 bitsWord: 16 bitsKword: 1,024 wordsKb: 1,024 bitsKB: 1,024 bytesMb: 1,048,576 bitsMB: 1,048,576 bytesBrackets: S q u a r e b r a c k et s ( [ ] ) w i l l b e u s e d t o d e s i gn a t e g r o u p m e m b er s h i p o r t o d e f i n e a

g r o u p o f s i g n a l s w it h s i m i l a r f u n c t i on ( i . e . A [ 2 1 : 1 ], S R [ 4 , 1 ] a n d D [ 1 5: 0 ] ) .

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D a t a s h e e t 9

2.0 Dev i c e Des c r i p t i o n

This section provides an overview of the K3/K18 device features, packaging information, signal

n a m e s , a n d d e v i c e a r c h i t e ct u r e .

2. 1 Pr o d u c t Ov er v i ew

T h e K 3 / K 1 8 d e vi c e p r o d u ct l i n e a d d s a h i g h p e r fo r m a n ce b u r s t - m o de i n t e r f ac e a n d o t h er a d d i t i on a l f e a t ur e s t o t h e I n t e l S t r a ta F l a s h m e m o r y f a m i l y o f p r o d u ct s . J u s t l i k e i t s J 3 c ou n t e r pa r t ,t h e K 3 / K 1 8 ut i l i z e s r el i a b l e a n d p r o ve n t w o - b i t -p e r - ce l l t e c hn o l o g y t o d el i v e r 2 x t h e m e m or y i n 1 xt h e s p a ce , o f f e ri n g h i g h d en s i t y f l a sh a t l o w c o s t . T h is i s t h e t h i r d g en e r a t i on o f I n t e l ' s m ul t i - l e v elc e l l ( M L C ) t e c hn o l o g y, m a n u f ac t u r e d o n 0 .1 8 m l i t h o g r a p h y, m a k i n g i t t h e m o s t w i d e l y u se d a n d

proven MLC product family on the market.

K 3 / K 1 8 i s a 3 - v o lt d e v i c e ( c o r e ) , b u t i t i s a v a i l ab l e w i t h 3 - vo l t ( K 3) o r 1 . 8 - v ol t ( K 1 8 ) I / O v o l t ag e s .

T h e s e d e vi c e s a r e i d e al f o r m a i n s t r ea m a p p l i c at i o n s r e q ui r i n g l a r g e s t o r a g e s p a c e f o r b o t h c o d e a n dd a t a s t o r ag e . A d v a n ce d s y s t e m d es i g n s w i l l b e ne f i t f r o m t h e h i g h p e r fo r m a n ce p a g e a n d b u r s tmodes for direct execution from the flash memory. Available in densities from 64 Mb to 256 Mbit( 3 2 M b y t e ) , t h e K 3 / K 1 8 d e v ic e i s t h e h i g h e s t d e n s i t y N O R - ba s e d f l a s h c o m p on e n t a v a i l ab l e t o d a y,

just as it was when Intel introduced the original device in 1997.

2.1.1 Hi g h Per f o r m an c e Pag e/ Bu r s t Mo d es

NOR-based flash is generally preferred over other architectures for its reliability and fast reads p e e ds . F a s t r e a d s a l l o w t h e a p p li c a t i o n t o e x e cu t e c o d e d i r e c tl y o u t o f f l a s h , r a t h e r t h a nd o w n l oa d i n g t o R A M f o r e x e cu t i o n , s av i n g t h e c o s ts o f r e d u n da n t s y s t em m e m o r y a n d b o ar ds p a c e. T h e K 3 / K 1 8 d e v i c e s e t s t h e s t a n d ar d f o r f a s t r e a d s p e ed s b y a d d i n g b u r s t m o d e a n d u t i l i zi n ga n 8 w o r d p a g e m o de . B u r s t m o d e i n c r e as e s t h r o u gh p u t u p t o 7 6 M B / s , e f fe c t i v el y f i v e t i m e s f a st e r

t h a n a s y nc h r o n ou s r e a d s o n s t a n da r d f l a s h m e m o r y, a n d s u p p or t s p e r f o r m an c e u p t o 6 6 M h z w i t hz e r o w a i t s t a te s . B o t h p a g e an d b u r s t m o d es a l s o p r o v i de a h i g h p e r f o r ma n c e g l u e le s s i n t e r f ac e t othe Intel S t r o ng A R M* S A - 11 10 C P U ( a nd f u t ur e I n t el X S c a le p r o c es s o r s) a n d m a n y o t h e r microprocessors.

2. 1.2 S i ng l e Ch ip So l u ti o n

I n a d d i t i o n t o c o d e e x e cu t i o n , m a n y a p pl i c a t i on s a l s o h a v e d a t a s t o r a g e n e e d s. K 3 / K 1 8 m e m o r yprovides a single-chip solution for combined code execution and data storage. A single-chips o l u t i o n i s e a sy t o i m p l e m e n t b y u t i l i z i ng a u n i q u e h a rd w a r e a n d s o f t wa r e c o m b i n at i o n : t h e K 3 /K 1 8 d ev i c e a n d I nt e l Persistent Storage Manager (Intel PSM). Intel P S M i s r o ya l t y f r e e w h e nu s ed w i t h I n te l F l a s h , i s a n i ns t a l l a bl e f i l e s y s t em a n d b l o c k de v i c e dr i v e r f o r M i c r o s of tW i n do w s * C E O S v e r s io n 2 . 1 a n d l a t er .

T he I n te l P S M s o f t w a r e i s a p p r o p r i at e f o r a n y a p p l i c a t i on u s i n g t h e M i c r o s o ft W i n d o w s C Eoperating system, including PC Companions, Set-Top Boxes, and other connected appliances andh a n d - he l d d e vi c e s . O t h e r o p e r a ti n g s y st e m p o r ts a r e a l s o a v a i l ab l e . I n t el PSM is optimized for theIntel StrataFlash Memory product line.

For wireless applications, Intel Flash Data Integrator (Intel FDI) Version 4 software provides theability to manage data and files in Intel StrataFlash M e m o r y i n a n o p e n ar c h i t e ct u r e , i n cl u d i n gs u p p or t f o r d o w n l o ad e d J a v a* a p p l e t s , B l u et o o t h * f i l e t r a n s fe r s , a n d v o i c e r e c o g n it i o n t a g s .

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10 D a t a s h e e t

2.1.3 Pac kag in g Op ti o ns

T h e K3 / K 18 d ev i c e i s av a il a bl e i n m u l ti p l e p ac k ag e s: E a s y B G A a nd V F B G A , a n d St a c ke d C hi pS c a l e P a c k ag e ( S C SP, s t a ck i n g wi t h S R A M o r f l a sh + f l a s h ) . T h e 6 4- b a l l E as y B G A p a c ka g e

provides SOP reliability and long-term footprint compatibility and cost in a chip scale packages i z e . T h e V F B G A a n d S C S P o f f e r s m a l l f o o t pr i n t s f o r w i r e l e ss a p p l i c a t io n s .

Manufactured on Intel's 0.18-micron process technology, Intel StrataFlash Memory offersunprecedented value, performance and reliability, and is still the lowest cost-per-bit NOR flashm e m o r y i n t h e i n d u s t ry.

2.1.4 Pr o d uc t Hi g hl i gh ts

H i g h p e r f o rm a n c e r e a d m o de s : 8 o r 1 6 - w o rd s y n c h r o no u s b u r s t , 8 - w o r d p ag e :

64Mb: 110/25/13ns (async/page/burst)

128Mb: 115/25/13ns

256Mb:120/25/13ns

2 . 7 V 3. 6 V V c c o p er a ti o n

64-ball Easy BGA

V F B G A p a c k ag e s a n d St a c k e d Ch i p S c a l e P a c k ag e ( S C S P )

I / O V C C Q: 2 . 3 7 5 V 3 . 6 V ( K 3 ) ; 1 .6 5 V 1 . 9 5 V ( K 1 8 )

One-time-programmable protection registers (2Kbits)

Program and Erase suspend capability

C o s t - e ff e c t i v e m u l t i - l ev e l c e l l a r c h i t ec t u r e

R o y a l ty - f r e e s o f t w a re s up p o r t f o r m o s t a p p l i c at i o n s w i t h I n t e l PSM, Intel F D I Ve r s i on 4 , o r

VFM Full extended operating temperature: -40 C to +85 C

Pr oven reliability: 100,000 cycles, up to 20 years data retention

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D a t a s h e e t 11

2. 2 Pac k ag e Di ag r am

T h e K 3 /K 1 8 de v ic e i s a v ai l ab l e i n a 64 - b al l E a sy B G A p ac k ag e f or t h e 64 - , 1 28 - , a n d 2 5 6 M b i tdensities. (See Figure 1.)

T h i s de v i c e i s a l so a v ai l a b l e i n a 5 6 - b a ll V F BG A p a ck a g e f o r t h e 6 4 - an d 1 28 M b i t d e n s i t ie s a nd a7 9 - ba l l V F B G A p a ck a ge f o r t h e 2 5 6 M bi t d e ns i ty. ( S e e F i gu r e 3 o n p ag e 13 . )

F i g u r e 1 . 6 4- B a l l E as y B G A P a c k ag e , 1. 0 m m B a l l P i t c h

NO TES:1. Address A23 is valid only on 128-Mbit densities and above; otherwise, it is a no connect (NC).2. Address A24 is valid only on 256-Mbit density; otherwise, it is a no connect (NC).

1 82 3 4 5 6 7

A

A1 A6 A8 A13VPEN A18 A22Vcc

RFU Vssq Vcc D13Vss D7 A24

256M

Vssq

H

A23

128MRFU D2 D5Vccq D14 WE#D6

G

RFU D0 D10 D12D11 WAIT OE#ADV#

F

E

D8 D1 D9 D4D3 D15 STSCLK

D

A4 A5 A11 VccqRST# A16 A17Vccq

C

A3 A7 A10 A15A12 A20 A21WP#

B

A2 Vss A9 A14CE# A19 RFURFU

18 234567

RFUVssqVccD13 VssD7A24

256MVssq

H

WE#

G

RFUOE#

F

E

STS

D

A4A5A11Vccq RST#A16A17 Vccq

C

A3A7A10A15 A12A20A21 WP#

B

A2VssA9A14 CE#A19RFU RFU

A

A1A6A8A13 VPENA18A22 Vcc

T o p V i ew - B a l l S i d e D o w n B o t t o m V i e w - B a l l S i d e U p

V e r s i o n - E a s y B G A V e r s i o n - E a s y B G A

A23

128MRFUD2D5 VccqD14 D6

D0D10D12 D11WAITADV#

D8D1D9D4 D3D15 CLK

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NO TE: Address A22 is only valid on 128-Mbit density; otherwise, it is a no connect (NC).

F i g u r e 2. 5 6 B a l l V F B G A P a c k a g e 0. 7 5 B a l l P i t c h ( 6 4 - a n d 1 2 8M b D e n s i t i e s O N LY )

V F B G A 7 x 8

B o t t o m V i e w - B a l l Si d e U p V F B G A 7 x 8

T o p V i e w - B a l l S i d e D o w n

2 3 4 5 6 7 81

A8 VSS V CC VPEN A18 A6 A4

A9 A20 CLK RST# A17 A5 A3

A10 A21 WE# A19 A7 A2

A14 WAIT A16 D12 W P# A22

D15 D6 D4 D2 D1 CE# A0

D14 D13 D11 D10 D9 D0 OE#

ADV#

A1

VSSQ VCC D 3 VCCQ D8 VSSQ

A11

A12

A13

A15

VCCQ

VSS

D7 D5

A

B

C

D

E

F

G

2345678 1

A8VSSVCCVPENA18A6A4

A9A20CLKRST#A17A5A3

A10A21WE#A19A7A2

A14WAITA16D12WP#A22

D15D6D4D2D1CE#A0

D14D13D11D10D9D0OE#

ADV#

A1

VSSQVCCD3VCCQD8VSSQ

A11

A12

A13

A15

VCCQ

VSS

D7D5

A

B

C

D

E

F

G

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F i g u r e 3. 7 9 -b a l l V F B G A P ac k a g e ( 2 56 - M b i t D e n s i t y )

V F B G A

T o p V i e w - B a l l S i d e D o w n

A

B

C

D

E

2 3 4 5 6 7 81

A8 VSS VCC VPEN A18 A6 A4

A9 A20 CLK RST# A17 A5 A3

A10 A21 WE# A19 A7 A2

A14 WAIT A16 D12 WP# A22

D15 D6 D4 D2 D1 CE# A0

D14 D13 D11 D10 D9 D0 OE#

A1

VSSQ VCC D3 VCCQ D8 VSSQ

A11

A12

A13

A15

VCCQ

VSS

D7 D5

9

RFU

RFU

RFU

A23

RFU

RFU

RFU

10 11

DU DU

DU DU

DU DU

DU DU

DU DU

DU DU

F

G

DU DU

DU DU

12 13

ADV#

V F B G A

B o t t o m V i e w - B a l l S i d e U p

A

B

C

D

E

2345678 1

A8VSSVCCVPENA18A6A4

A9A20CLKRST#A17A5A3

A10A21WE#A19A7A2

A14WAITA16D12WP#A22

D15D6D4D2D1CE#A0

D14D13D11D10D9D0OE#

A1

VSSQVCCD3VCCQD8VSSQ

A11

A12

A13

A15

VCCQ

VSS

D7D5

9

RFU

RFU

RFU

A23

RFU

RFU

RFU

1011

DUDU

DUDU

DUDU

DUDU

DUDU

DUDU

F

G

DUDU

DUDU

1213

ADV#

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2.3 Si g n al De s c r i p t i o n s

Table 1 l i s t s t h e a c t i v e s i gn a l s u s e d a nd p r o v i d es a b r i e f d e s cr i p t i o n o f e a ch .

Ta b l e 1 . S i g n a l D e s c r i p t i o n s

Sy m Ty p e N am e a n d Fu n c t i o n

A[AMAX:AMIN] Input A D D R E S S :Device address. Address internally latched during read/write operations. See

nomenclature Section 1.2 for AMAXand AMINvalues.

D[15:0] Input/

Output

D A T A I / O : Inputs data and commands during write operations, outputs data during readoperations. Float when CE# or OE# are de-asserted. Data is internally latched during writeoperations.

CE# Input C H I P E N A B L E:Active-low; CE#-low selects the device. CE#-high deselects the device, places it

in standby mode, and places data and WAIT outputs in a High-Z state.

OE# Input OU T P U T E N A B L E :Active-low; OE#-low enables the devices output data drivers during read

cycles. OE#-high places the data outputs in a High-Z state.

WE# Input W R I TE E NA B L E :Active-low; WE# controls writes to the flash device. Address and data are

latched on the rising edge of WE#.

RST# InputRESET:Active-low; resets internal circuitry and inhibits write operations. This provides dataprotection during power transitions. RST#-high enables normal operation. Exit from reset placesthe device in asynchronous read-array mode.

WP# InputW R I T E P R O T E CT: Active-low; WP#-low enables the lock-down mechanism. Blocks lockeddown cannot be unlocked with the unlock command. WP#-high overrides the lock-down functionenabling blocks to be erased or programmed through software.

ADV# Input A D D R ES S VA L I D :Active-low; during synchronous read operations, addresses are latched on

the rising edge of ADV# or on the rising (or falling) edge of CLK, whichever occurs first.

VPEN Input E R A S E / P R O G R A M / B L O C K L O C K E N A B L E :Controls device protection. When VPEN

VPENLK, flash contents are protected against Program and Erase.

CLK Input

C L O C K : Synchronizes the device to the systems bus frequency in synchronous-read mode,and increments the internal address generator. During synchronous read operations, addressesare latched on ADV#s rising edge or CLKs rising (or falling) edge, whichever occurs first.Connect this signal to VCC if the device will not be used in synchronous-read mode.

STS Open Drain

Output

STATUS: Indicates the status of the internal state machine. When configured in level mode(default mode), it acts as a RY/BY# pin. When configured in one of its pulse modes, it canindicate program and/or erase completion. For alternate configurations of the STATUS pin, seethe configuration commands. STS is to be tied to VCCQwith a pull-up resistor.

WAIT Output WAIT: Indicates invalid data in synchronous-read (burst) modes. WAIT is High-Z whenever CE#

is de-asserted. WAIT is not gated by OE#.

VCC Power C O R E P O W E R S U P P L Y: Core (logic) source voltage. Writes to the flash array are inhibited

when VCCVLKO. Device operation at invalid VCCvoltages should not be attempted.

VCCQ Power I/O PO WER SUPPL Y: I/O Output-driver source voltage.

VSS Power G RO UND:Ground reference for device core power supply. Connect to system ground.

VSSQ Power I/O G RO UND: I/O Ground reference for device I/O power supply. Connect to system ground.

DU - D O N T U S E :Do not use this ball. This ball should not be connected to any power supplies,

signals or other balls and must be left floating.

NC - NO CO NNECT:No internal connection; can be driven or floated.

RFU - R E S ER V ED f o r F U T UR E U S E : Balls designated as RFU are reserved by Intel for future device

functionality and enhancement.

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2. 4 B l o c k Di ag r am

F i g u r e 4 . K 3 / K 18 D ev i c e M e m o r y B l o c k D i a g r a m

64-Mbit: Sixty-four128-Mbit: One-hundred

twenty-eight

256-Mbit Two-hundredfifty-six

64Kword Blocks

Input

Buffer

Output

Multiplexer

Y-Gating

Program/EraseVoltage Switch

Data

Comparator

StatusRegister

Identifier

RegisterData

Register

I/O Logic

Address

Latch

Address

Counter

X-Decoder

Y-DecoderInput

Buffer

OutputBuffer

GND

VCCQ

VPEN

CE#

WE#

OE#RST#

CommandUser

Interface

DQ0- DQ15

VCC

Write

Buffer

Write State

Machine

Input Multiplexer

Query

STS

VCCQ

Read StateMachine

VCCQ

CLK

ADV#

WAIT

AMAX : AMIN

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2.5 Mem o r y M ap

T h e K 3 /K 1 8 d e v i c e a r r a y i s di v i d e d in t o s y m me t r i c a l b l o c k s t h a t a re 6 4 - K w or d i n s i ze . A 6 4 M b i td e v i ce c o nt a i n s 6 4 b lo c k s , a 1 2 8 Mb i t d ev i c e c o n t ai n s 1 28 b l o c k s a n d a 2 5 6 M b i t d ev i c e c o n t ai n s

256 blocks. Flash cells within a block are organized by rows and columns. A block contains 512r o w s b y 1 28 w o r d s . Th e w o r d s on a r o w a r e d i v i de d i n t o 1 6 e i g h t - wo r d g r o u p s. ( R e f e r t o F ig ur e 5.)

F i g u r e 5 . K 3 / K 1 8 D e v i c e M e m o r y M ap

B l o c k 0

B l o c k 1

B l o c k 2

B l o c k 3

.

.

.

B l o c k 6 3

.

.

.

B l o c k 1 2 7

.

.

.

B l o c k 2 5 5

2 5 6 - M

b i t D e v i c e

1 2 8 - M

b i t D e v i c e

6 4 - M

b i t D e v i c e

0 x F F F F

0 x 3 F F F F F

0 x 1 F F F F

0 x 2 F F F F

0 x 3 F F F F

0 x 7 F F F F F

0 x F F F F F F

0

0x3F0000

0x7F0000

0xFF0000

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3.0 Dev i c e Op er at i o n s

This section provides an overview of device operations. The on-chip Write State Machine (WSM)

m a n a g es a l l b l o c k - e r a se a n d w o r d - p r og r a m a l g o r i t hm s . T h e s y s t e m C P U p r o v i de s c o n t r o l o f a l l i n -s y st e m r ea d , w r i te , a n d e r as e o p er a ti o n s o f t he d e vi c e v i a t h e s y st e m b u s.

D e v ic e c o m ma n ds a r e w r i tt e n t o t h e C o m ma n d U se r I n te r f ac e ( C U I) t o c o n tr o l a l l o f t h e f l a shm e m o r y d e vi c e s o p e r a t io n s . T h e C U I d o es n o t o c c u py a n a d d r e s sa b l e m e m o r y l o c a t io n ; i t i s t h em e c h an i s m t hr o u g h w h i c h t h e f l a s h d e v i ce i s c o n t r o l le d .

3. 1 B u s Op er at i o n s

B u s c y c l es t o a n d f r o m t h e d e v i ce c o n f o rm t o s t a n d a r d m i cr o p r o ce s s o r b u s o p e r at i o n s. Table 2s u m m a r i ze s t h e b u s o p e r a ti o n s a n d t h e v o l t a g e l e v e l s t h at m u s t b e a p p l i ed t o t h e d e v i c e c o n t r o ls i g n a ls w h e n o p e r at i n g w i t h i n e a ch d e v i c e m o d e . W h e ne v e r C E # i s a s s er t e d , t h e d e v i ce i s i n a n

a c t i v e s t at e ; i t i s s e l e c t ed a n d i t s i n t e r n a l c ir c u i t s a r e a c t i v e. O E # a n d W E # d e t e r mi n e w h e t he r D [ 1 5 : 0 ] a r e o u t p ut s o r i n p u t s, r e s p e c ti v e l y.

3.1 .1 Read Mo d e

To perform a bus read operation, CE# and OE# must be asserted. CE# is the device-select control;w h e n ac t i v e , i t e n ab l e s t he f l a s h m e m o r y d e v i ce . O E # i s t h e d a t a - ou t p u t co n t r o l ; w h e n a c t i v e, t h ea d d r e ss e d f l as h m e m o ry d a t a i s d r i ve n o n to t h e I / O b u s . F or a l l r e ad s t a t e s, W E # a n d R S T # m u s t bed e - a s se r t e d . S e e Section 10.4, Read Operations on page 45 . Refer to Section 4.0, Read Modes o n p a g e 2 1 f o r d e t a i ls o n r e a d i n g f r o m t h e f l a s h a r r a y, a nd r e f er t o S e c t i on 8 . 0 , S p e c i a l M o d e s o n

page 38 f o r d et a i l s r e g a r di n g a l l o th e r a v ai l a b l e r e a d s t a t e s.

Tab l e 2. B u s O per at i o ns

Mo d e RST# CE # O E # ( 1) WE# ( 1) ADV# WAIT VPEN D a t aSTS

( d e f a u l tm o d e )

N o t e s

Synch Array Read VIH Enabled VIL VIH X Valid X DOUT High-Z

Asynch. Reads andSynch. Status,Query and IdentifierReads

VIH Enabled VIL VIH X Driven X DOUT High-Z 2

Output Disable VIH Enabled VIH VIH X Driven X High-Z High-Z

Standby VIH Disabled X X X High-Z X High-Z High-Z

Reset VIL X X X X High-Z X High-Z High-Z

CUI CommandWrite

VIH Enabled VIH VIL X Driven X DIN High-Z

Array Writes VIH Enabled VIH VIL X Driven VPENH DIN VIL 3, 4

NO TES:1. OE# and WE# should never be asserted simultaneously, but if done, OE# overrides WE#.2. Refer to DC Characteristics. When VPENVPENLK, memory contents can be read but not altered.3. X should be VILor VIHfor the control pins and VPENLKor VPENHfor VPEN. For outputs, X should be VOLor VOH.4. Array writes are either program or erase operations.

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3.1.2 Wr it e/P r og ram

To p e r f or m a b u s w r i te o p e r at i o n , b o th C E # a nd W E # a r e a s s e r te d , a n d O E # i s d e - as s e r t ed . A l ld e v i ce w r i t e o p e r a t io n s ar e a s y n ch r o n o us , w i th C L K b e i n g i g n o r ed . D u r i ng a w r i t e o p e r a ti o n ,a d d r es s a n d d a t a ar e l a t c h ed o n t h e r i s i n g ed g e o f W E # o r C E # , w h i c h ev e r o c c u rs f i r s t . Se e T a b l e 3 ,Command Bus Definitions on page 19 for bus cycle commands. See S e c t io n 1 0 . 5 , Wr i t eOperation on page 50 .

W r i te o p e r a t i o ns w i t h i n v a l i d VC C and/or V PEN voltages can produce spurious results and shouldnot be attempted.

3.1.3 Ou t pu t Di s a b l e

W h e n O E # i s d e - as s e r t ed , d e v i ce o u t p u t s , D [ 15 : 0 ] , a r e d i s a b le d a n d p l a ce d i n a h i g h-impedancestate.

3.1.4 St an d b y

When CE# is de-asserted, the device is deselected and placed in standby, substantially reducingpower consumption. In standby, the data outputs are placed in a high-impedance state independento f t h e l ev e l p l ac e d on O E # . I f t h e d e v i c e i s d e -s e l e c te d ( C E# d e - as s e r t ed ) d u r in g a p r o g r am o r e r a s eo p e r a ti o n , i t w i l l c o nt i n u e t o c o n su m e a c ti v e p o w e r un t i l t h e pr o g r a m o r e r a se o p e r a ti o n i sc o m p l et e d . T he r e i s n o a d d i t i on a l l at e n c y f o r s u b s eq u e n t r e a d o p e r a ti o n s .

3.1.5 Res et

A f t e r i n i ti a l p o we r - u p or r e s e t , t h e d e vi c e d e f a u lt s t o R e ad A r r a y m o d e a nd t h e d e v ic e s t a t usregister is set to 0x80. If already in Read Array mode, asserting RST# de-energizes all internalcircuits, and places the output drivers in a high-i m p e d an c e s t a t e . A f t e r r e t u r ni n g f r o m r e s e t ( R S T #d e - a ss e r t e d) a m i n i m u m a m o u n t o f t i m e i s r e q u ir e d b e f o r e t h e i n i t i a l r e a d a c c es s o u t p u ts v a l i d d a t a.

A l s o , a m i n i m u m d e l a y i s r eq u i r ed a f t e r a r es e t be f o r e a w r i te c yc l e ca n b e i ni t i a t e d. A f t er t h i swake-up interval has passed, normal operation is restored. See S e c t i on 1 0 . 4 , R e a d O p e r at i o n s o n

page 45 f o r r e s e t t i mi n g d e t ai l s .

Note: I f R ST # i s a s s er t e d du r i n g a p ro g r a m o r er a s e o p e r a t io n , t h e o p e r at i o n w i l l be a bo r t e d a n d t h em e m o r y c o n t e nt s a t t he a b o r t ed l o c at i o n ( f or a p r o g r am ) o r b l o c k (f o r a n e r as e ) a r e n o l o n g e r va l i d ,s i n c e t he d a t a m a y h a v e b e en o n l y p a r t i al l y w r i t t e n o r e r a se d .

W h e n R ST # i s a s s er t e d , t h e d e v ic e s h u t s d ow n t h e o p e r at i o n i n p r o gr e s s , a p r o c e ss w h i c h t a k e s aminimum amount of time to complete. When RST# has been de-asserted, the device will be reset tor e a d a r r ay m o d e . I f t h e s y s t e m i s r e tu r n i n g f r o m a n a b o r t ed p r o g r a m o r e r a s e o pe r a t i on , a m i n i m u ma m o u nt o f t i m e m u s t b e s at i s f i e d b ef o r e a r e a d or w r i t e o p er a t i o n i s i n i t i a t ed .

A s w i t h a n y au t o m a t ed d e v i ce , i t i s i m po r t a n t to a s s e rt R S T # w h en t h e s y s t e m i s r e s e t. W h e n t h e

s y s t em c o m e s o u t o f r e s e t, t h e s ys t e m pr o c e ss o r w i l l a t t em p t t o r ea d f r o m t h e f l as h m e mo r y i f i t i st h e s y s t e m b o o t d e vi c e . A u t o m at e d f l a s h m e m o r i es p r o v i d e s t a t us i n f o r m a t i on w h e n r e a d d u r i n g

program or block erase operations. If a CPU reset occurs with no flash memory reset, improperC P U i n i t i al i z a t i on m a y o c c u r b e c a us e t h e f l a s h m e m o r y m ay b e p r o v i di n g s t a t u s in f o r m a t io n r a t h e r than array data. Intel F l a s h m e m o r y d e v ic e s a l l o w p r o p e r C P U i n i t i al i z a t i o n f o ll o w i n g a s y s t e mr e s e t t h r o u g h th e u s e of t h e R S T # i n pu t . R S T # sh o u l d be c o n t r ol l e d b y t h e s a m e l o w - t r ue r e s e tsignal that resets the system CPU.

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3. 2 Dev i c e Co m m an d s

D e v i c e o pe r a t i o ns a r e i n i t i a te d b y w r i t i n g s p e ci f i c d e v i c e c o m m an d s t o t h e C o m m an d U s e rInterface (CUI). (See Table 3. )

Ta b l e 3 . C o m m an d B u s De f i n i t i o n s (S h ee t 1 o f 2)

C o m m a n d B u s

C y c l e s

Fi r s t B u s Cy c l e Se c o n d B u s Cy c l e

Ty p e A d d r D a t a Ty p e A d d r Da t a

Re a d

Read Array 1 Write Any Address 0xFF ReadAddress of

memory to beread

Array Data

Read Identifier 2 Write Any Address 0x90 Read IdentifierCode Address

IdentifierCode Data

Read Query

(CFI)2 Write Any Address 0x98 Read

Query CodeAddress

Query CodeData

Read StatusRegister 2 Write

Address withinBlock 0x70 Read

Address withBlock

StatusRegister Data

Clear StatusRegister

1 Write Any Address 0x50

P r o g r a m

Program 2 WriteAddress of

memory locationto be programed

0x40

or

0x10

WriteAddress of

memory to beprogramed

Data to beprogramed

Write to Buffer4Numberof bufferwords +

3

Write Address within

Block 0xE8 Write

Addresswithin Block

Number ofwords to be

written tobuffer

Buffered EFP 2 WriteAddress of

memory locationto be programed

0x80 Write Address

within Block 0xD0

E r a s e Block Erase 2 Write

Address within

Block 0x20 Write

Address

within Block 0xD0

S u s p e n d Erase/Program

Suspend 1 Write Any Address 0xB0

R e s u m e Erase/Program

Resume 1 Write Any Address 0xD0

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R e g i s t e

r C o n f i g u r a t i o n

( B u r s t , L o c k ,

S T S

a n d

P r o t e c t i o n )

ReadConfigurationRegister

2 Write CD1 0x60 Write CD1 0x03

Lock Block 2 Write Address within

Block 0x60 Write

Addresswithin Block

0x01

Unlock Block 2 Write Address within

Block 0x60 Write

Addresswithin Block

0xD0

Lock-Down Block 2 Write Address within

Block 0x60 Write

Addresswithin Block

0x2F

STS 2 Write Any Address 0xB8 Write Any Address CC2

ProtectionProgram

2 Write PA5 0xC0 Write PA5

Data to beprogrammed

to theProtection

Register

Lock ProtectionProgram

2 WriteLock Protection

Address for 128-bit

0xC0 Write

LockProtection

Address for128-bit

0xFFFD

Lock 2K OTPProtection

2 Write Lock ProtectionAddress for 2K-bit

0xC0 Write LPA1 LPD3

NO TES:1. CD = Configuration register data presented on device addresses A[AMIN+15:AMIN]. A[AMAX:AMIN+16] address bits must be

cleared.SeeTable 4, Read Configuration Register on page 22for RCR bit descriptions.2. CC = STS Configuration code on D[7:0].3. LPD = Lock Protection Register1 Data. Valid values are between 0xFFFE and 0x0000.4. The second cycle of the Write-to-Buffer command is the count of words to load into the buffer, followed by data streaming up

to the count value. Then a Confirm command (0xD0) is issued to execute the program operation. Refer toFigure 22, Write toBuffer Flowchart on page 66.

5. PA = Valid Protection Register Address.

Ta b l e 3 . C o m m a n d B u s De f i n i t i o n s ( Sh e e t 2 o f 2)

C o m m a n d B u s

C y c l e s

F i r s t B u s Cy c l e S ec o n d B u s C y c l e

Ty p e A d d r D at a Ty p e A d d r D at a

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4.0 Read Mo d es

T h e d e v i c e s u p p or t s f o ur t y p es o f r ea d m o de s : r e a d a rr a y, r e a d i d e n ti f i e r, r e a d s t a t us o r r e a d q u e r y.

U p o n p o w e r- u p or r e t u r n f r o m r e s e t , t h e d e v i ce d ef a u l t s t o r ea d ar r a y m o d e . To c h a ng e th e d ev i c e sread mode, the appropriate Read command must be written to the device. (See Section 3.2, DeviceC o m ma n ds o n p a g e 1 9.) See S e c t i on 8 . 0 , S p e c i al M o d e s o n p a g e 3 8 f o r d e t a i ls r e g a r d i ng r e a ds t a t u s, r e a d I D , a n d CF I q u er y m o d e s .

T h e d e v i c e s up p o r t s t w o t y p e s o f a r r a y r e a d m od e s : a s y nc h r o n ou s p a g e m o d e a n d s y n c hr o n o u sburst mode. Asynchronous page mode is the default read mode after powered-up, or after a reset.T h e R C R m u st b e co n f i g u re d t o en a b l e S y n c hr o n o u s B u r s t r e a d s o f t h e f l as h m e m o r y a r r a y. ( S e eS e c t i on 4 . 3 , R e a d C o nf i g u r a ti o n R e g i s t er o n p a g e 2 2.)

T h e R e a d A r r ay c o m m a nd f u n c t i on s i n d ep e n d e nt o f V PEN. T h e f o l l o w i ng s e c t i on s d es c r i b es r e a d-a r r a y m o d e o pe r a t i o ns i n d e t a i l .

4. 1 A s y n c hr o n o u s Pag e-Mo d e Read

A s y n c hr o n o u s p a g e mo d e i s t h e d e f a ul t r e a d m o d e u p o n p o w e r- u p o r re t u r n f r om r e s e t . H o w e ve r ,t o p e r fo r m a rr a y r ea d s a ft e r a n y ot h er d e vi c e o p er a t io n ( e .g . , a w r i t e o pe r a ti o n) , t h e R e ad A r r a ycommand must be issued in order to read from the flash memory. Asynchronous page-mode readsare permitted in all blocks, and it is used to access device register information.

Note: A s yn c hr o n ou s p a ge m o d e r e ad s c an o n ly b e p e r fo r m ed w h e n R C R b i t 1 5 i s s et ( d e fa u lt ) . ( S eeS e c t i on 4 . 3 , R e a d C o n f i g u r a ti o n R e g i s t e r o n p a g e 2 2 .)

To p e r f o r m a n a s y n c hr o n o us p a g e - m o d e r e a d, a n a d d r e s s i s d r i v e n o n t o A [ AMAX:AMIN], and CE#a n d O E # a re a s s er t e d . W E # an d R S T # m u s t b e d e - a s se r t e d . A D V# m u s t b e he l d l o w t h r o u g ho u t t h er e a d c y c l e . C L K a n d WA I T a r e n ot u s e d f o r as y n c hr o n o u s p a g e - mo d e r e a d s. I f o n l y a s y n ch r o n o us

r e a d s a re t o b e p e r f o rm e d , i t i s r e c o m m en d e d t h at C L K b e t i e d t o a v a li d VIH l e v e l. A r r a y d a t a i sdriven out on D[15:0] after a minimum delay. (See Section 10.4, Read Operations on page 45.)

I n a s y nc h r o n ou s p a g e mo d e , o ne o f 1 6 e i gh t - w o r d g r o u p s a r e s e n s e d s i m ul t a n e ou s l y f r om t h eflash memory and loaded into an internal page buffer. After the initial access delay, the first wordo u t o f t h e d a t a b u f f er c or r e s p on d s t o th e i n i t i a l a d d r e ss , A[ AMAX:A MIN] . A d d r e ss b i t sA[A MAX:AMIN + 3 ] a r e l a t c h ed b y t h e de v i c e. H o w ev e r , t h e l ow e r a d d r e ss b i t s, A [ AMIN+ 2 : AMIN] , a r e n ot l a t ch e d .

Address bits A[AMIN+ 2 : AMIN] d e t er m i n e w h i c h w o r d of t h e e i g h t - wo r d g r o u p i s o ut p u t f r o m th ed a t a b u f f er a t a n y g i v e n t i m e . S u b s eq u e n t r e a ds f r o m t h e d e v i c e c o m e f r o m t h e p a g e b u f f er , a n d a r eo u t p u t o n D [ 1 5: 0 ] a f t e r a m i n i m u m d e l ay, a s l o n g a s a d d r e ss b i t s A [ AMIN+2:A MIN] a r e t he o n lya d d r e ss b i t s t ha t c h a ng e . D a t a c an b e r e ad f r o m t h e p a g e bu f f e r mu l t i p l e t i m e s , a nd i n a n y o r d e r. I f address bits A[AMAX:AMIN+ 3 ] c ha n g e a t a ny t i m e, o r if C E # i s t o g g l ed , t he d e vi c e w i l l s en s e a n d

l o a d a n e w e i g h t - w or d g r o u p f r o m t he f l a s h m e m o r y i n to t h e p a g e b u f f er .

B y c o n t r o ll i n g c e r t a i n si g n a l s, s u c h a s C E # a n d /o r O E # , t h e d e v i c e c a n b e m a d e t o o u t p ut l e s s t h a ne i g h t - wo r d s o f d a t a . A s y nc h r o n ou s p a g e -m o d e r e a d i s u s ed t o a c c e s s r e g i st e r i n f o r m at i o n , b u t o n l yo n e w o r d i s l oa d e d i nt o t h e p ag e b u f f er .

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4.2 Sy nc h ro n o u s B u rs t-M o de Read

S i n c e as y n c hr o n o u s p a g e m od e i s t h e d e f au l t r e a d m od e f o l l o wi n g a d e v i c e po w e r- u p o r r e s e t , t hea p p r op r i a t e b i t s i n t h e R C R m u st b e s e t be f o r e sy n c h r on o u s bu r s t m od e r e ad s o f t h e f l a s h m e m o r y

c a n o c c u r. S e e S e c t i on 4 . 3 , R e a d C o n f i gu r a t i o n R e g i st e r o n p a g e 2 2 for details. Immediatelya f t e r co n f i g u r in g t h e R C R , i t i s n ot n e c e ss a r y t o i s s u e t h e R e ad A r r a y c o m m a nd ( 0 x F F ) b e f o r e

performing a synchronous burst-mode read. However, to perform a synchronous burst-mode reada f t e r e x e c u ti n g a n y o t h e r d e v i c e o p e r a ti o n ( e . g . , a wr i t e o p e r at i o n ) , i t i s ne c e s sa r y t o i s s u e t h e R e a dA r r a y c o m m a nd b ef o r e p e r f o r mi n g a s y n c hr o n o u s b u r s t -m o d e re a d o f t h e fl a s h m e m o r y.

To p e r f o r m a s y n c h r on o u s b u r st - m o d e r e a d , a n a d d r es s i s d r i v e n o n t o A [ AMAX:AMIN], and CE#and OE# are asserted. WE# and RST# must be de-asserted. ADV# is asserted, then de-asserted tol a t c h t h e ad d r e s s. A l t er n a t i ve l y, A D V # c a n r e m a i n a s s e rt e d t h r o u gh o u t t h e b u r s t a c c e ss , i n w h i c hc a s e , t h e a d d r e ss i s l at c h e d o n t h e n e x t v al i d C L K e d g e .

I n s y n c h ro n o u s b u r s t mo d e , o n e o r t w o o f t he 1 6 e i gh t - w o rd g r o u ps a r e s en s e d s i m u lt a n e o us l yf r o m t h e f l a s h m e m o r y a nd l o a d e d in t o a n i n t er n a l p a ge b u f f er . A f te r t h e i n i t i a l a cc e s s d el a y, t h ef i r s t w o r d i s o u t p u t f r o m t h e d at a b u f f e r o n t h e n e x t va l i d C LK e d g e. S u b s eq u e n t b u f f er d a t a i s

output on valid CLK edges. Synchronous burst-mode reads can only step through the data buffero n c e, a n d c a n o n l y d o s o i n a s e q u en t i a l m a nn e r ; s t a r t in g f r o m t h e a d d r es s l a t c he d a t t h e b e g i nn i n go f t h e b u r st c yc l e ( s ee Section 10.4, Read Operations on page 45).

T h e d e v ic e s u p p or t s 8 - o r 1 6 - w o r d b u r s t s. H o w e v e r, b y c o n t r o l li n g c e r t ai n c o n t r o l s i gn a l s , s u ch a sC E # a n d / o r O E # , t h e d e v i c e c a n o u t p u t l e s s t h a n 8 / 1 6 - wo r d s o f s y n c hr o n o u s d a t a . A b u r s t - m od er e a d c a n be u s e d t o a c c es s r e g i s t er i n f o r m a t i on . W h e n a b u r s t- m o d e r e a d i s p e r f o r me d o n a r e g i s t er ,o n l y o n e w o r d i s l o a d ed i n t o t h e d a t a b u f f er . I n b u r s t m od e , t h e a d d r es s i s l a t c h e d b y e it h e r t h er i s i n g ed g e o f A D V # or t h e n e x t v al i d e d g e o f C L K w i t h A D V # l o w, w h i c he v e r o c c u r s f i r s t .

4.3 Read Co n f i g u r at i o n R eg i s t er

T h e R e a d C on f i g u r at i o n R e g i st e r ( R C R ) i s u s e d t o s e l ec t t h e r e a d m o d e ( s y nc h r o no u s o ra s y n ch r o n o us ) , a n d i t d e f i n e s t h e s y n c h ro n o u s b u r s t c h a r a ct e r i s t i cs o f t h e d e v i c e. To m o di f y t heRCR settings, write the RCR command to the device (see S e c t i on 3 . 0 , D e v i c e O p e r a t i on s o n

page 17).

RCR contents can be examined by writing the Read Identifier command to the device. See Section8 . 2 , R e a d D e vi c e I d e n t if i e r o n p a g e 3 9). The RCR Register is shown in Ta bl e 4. The followingsections describe each RCR bit in detail.

il.

Ta b l e 4 . R ea d C o n f i g u r a t i o n Re g i s t e r ( Sh e e t 1 o f 2)

R e a d C o n f i g u r a t i o n R e g i s t e r ( R C R ) D e f au l t Va l u e = 0 x F F C 7

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R eadM o d e L a t e n c y C o u n t WAITP o l a r i t y D ataH o l dWAIT

D el ayB u r s tSeq C L KE d g e RES RES R ES B u r s t L en g t h

RM L C [ 3: 0] WP D H WD B S CE R R R B L [ 2: 0]

B i t N am e D e s c r i p t i o n

15 Read Mode (RM) 0 = Synchronous burst-mode read1 = Asynchronous page-mode read (default)

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4.3 .1 Read Mo d e

T h e r e a d m o d e (R M ) b i t s e l ec t s s y n ch r o n ou s b u r s t m od e o r a s y n c hr o n o u s pa g e m o d e o p e ra t i o n o f

t h e d e v i c e. W h e n t h e R M b i t i s s e t , a s y n c hr o n o u s p ag e m o d e i s s e l e c t ed ( d e f a u l t ) . W h e n R M i sc l e a r e d, s y n c h ro n o u s bu r s t m o d e i s s e l e ct e d .

S y n c hr o n o u s b ur s t m o d e i s u s e d f o r a r r a y r e a d s, w h e r e a s a sy n c h ro n o u s p a g e m o de i s u s e d f o r r e a d i ng a r r a y d a t a , S t a t u s R e g i s te r i n f o r m at i o n , De v i c e I D i n f o r m at i o n , an d C F I i n f o r m a ti o n . N ot et h a t w h en o p e r a ti n g i n sy n c h r on o u s bu r s t m o de , S t at u s , I D , a n d C F I i n f o r m at i o n w i l l be d r i v e no n t o t h e b us o n t h e n e x t v a l i d c l oc k e d g e f ol l o w i n g t h e i n i t i a l s yn c h r o no u s a c c e ss d e l a y, a n d w i l lr e m ai n o n t h e b u s f or t h e d ur a ti o n o f t h e a c ce s s c yc l e.

4. 3.2 L at en c y Co u n t

T h e L a t e n cy C o u n t bi t s , L C [ 3: 0 ] , t e l l t he d e v i ce h o w m a n y c lo c k c y c l es m u s t e la p s e f r o m t h er i s i n g e dg e o f A D V # ( o r f r o m t h e fi r s t v a l i d c l o c k e dg e a f t er A D V # i s as s e r t ed ) u n t i l t he f i r s t d at a

word is to be driven onto D[15:0]. Ta bl e 6 o n p ag e 2 4 s h o w s t h e d a t a o u tp u t l a t e n cy f o r t h e v a l i dsettings of LC[3:0]. See Table 5 on page 24 f o r l a t e n cy s e t t i n g v al u e s m a t ch e d f o r i n p u t c l oc kfrequencies.

14:11 Latency Count (LC[3:0]) 0000 = Code 0. RFU0001 = Code 1. RFU0010 =Code 20011 =Code 3

0100 =Code 40101 =Code 50110 = Code 60111 = Code 71000 = Code 81001 = Code 91010 = Code 101011 - 1111 = Code 11 - Code 15. All these codes are RFU

10 Wait Polarity (WP) 0 = WAIT signal is active low1 = WAIT signal is active high (default)

9 Data Hold (DH) 0 = Hold data for one clock1 = Hold data for two clocks (default)

8 Wait Delay (WD) 0 = WAIT de-asserted with valid data1 = WAIT de-asserted one clock before valid data (default)

7 Burst Sequence (BS) 0 = Reserved1 = Linear (default)

6 Clock Edge (CE) 0 = falling edge1 = rising edge (default)

5:3 Reserved (R) 000 - Cannot be changed

2:0 Burst Length (BL[2:0]) 001 = RFU010 = 8-word burst011 = 16-word burst111 = RFU (default)

Ta b l e 4 . R ea d Co n f i g u r a t i o n R eg i s t e r ( Sh e et 2 o f 2)

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F i g u r e 6. F i r s t - A c c e s s L a t e n c y C o u n t

Code 1(Reserved

Code 6

Code 5

Code 4

Code 3

Co d e 2

Code 0 ( Reser ved)

Code 7

Va l i d

Ad d re ss

Va l i d

O u t p u t

Va l i d

O u t p u t

Va l i d

O u t p u t

V a l i d

Ou tp u t

Va l i d

O u t p u t

V a l i d

Ou tp u t

Va l i d

O u t p u t

Va l i d

O u t p u t

Va l i d

O u t p u t

Va l i d

O u t p u t

V a l i d

Ou tp u t

Va l i d

O u t p u t

V a l i d

Ou tp u t

Va l i d

O u t p u t

Va l i d

O u t p u t

Va l i d

O u t p u t

V a l i d

Ou tp u t

Va l i d

O u t p u t

V a l i d

Ou tp u t

Va l i d

O u t p u t

Va l i d

O u t p u t

V a l i d

Ou tp u t

Va l i d

O u t p u t

V a l i d

Ou tp u t

Va l i d

O u t p u t

Va l i d

O u t p u t

Va l i d

O u t p u t

V a l i d

Ou tp u t

Va l i d

O u t p u t

Va l i d

O u t p u t

V a l i d

Ou tp u t

Va l i d

O u t p u t

Va l i d

O u t p u t

Va l i d

O u t p u t

Va l i d

O u t p u t

Va l i d

O u t p u t

Address [A]

ADV# [V]

DQ15-0

[D/Q]

CLK [C]

DQ15-0

[D/Q]

DQ15-0

[D/Q]

DQ15-0

[D/Q]

DQ15-0

[D/Q]

DQ15-0

[D/Q]

DQ15-0

[D/Q]

DQ15-0

[D/Q]

Ta b l e 5 . L a t e n c y C o u n t Ta b l e

L CS e t t i n g

6 4 Mb 12 8 Mb 2 5 6 Mb

K 1 8 K 3 K 1 8 K 3 K 1 8 K 3

2 1 to 21 MHz 1 to 20 MHz 1 to 20 MHz 1 to 19 MHz 1 to 19 MHz 1 to 18 MHz




6 na 51 to 61 MHz na 50 to 59 MHz 48 to 50 MHz 47 to 56 MHz

7 na 62 to 66 MHz na 59 to 66 MHz na 57 to 66 MHz

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F i gu r e 7 shows an example of a LC setting of Code 3.

4. 3.3 WA IT Po lar i t y

T h e WA I T P o la r i ty ( W P ) b i t s el e c ts t h e a s se r t ed , o r t r u e, s t at e o f WA I T. W h e n W P i s s e t, WA I T i san active-high signal (default). When WP is cleared, WAIT is an active-low signal.

4. 3.4 Dat a Ho l d

For burst read operations, the Data Hold (DH) bit determines whether the data output remains valid

o n D [ 1 5 : 0 ] f o r o n e o r t w o c l oc k c y c l es . W h e n D H i s s e t , o u t p u t d a ta i s h e l d f o r t w o c l o c ks( d e f a u lt ) . W h e n D H i s c l e a r ed , o u t p u t d a t a i s h el d f o r o n e c l o c k c y cl e . ( S e e F ig ur e 8. ) T he

processors data setup time and the flash memorys clock-to-data output delay should bec o n s i de r e d i n d e t e r mi n i n g w h e th e r t o h o l d o u t p ut d a t a f o r o n e o r t w o c l o c ks .

F i g u r e 7 . E x a m p l e L at e n c y C o u n t S et t i n g

CLK

CE#

ADV#

A[MAX:0]

D[15:0]

tData

C o d e 3

A d dr es s

D a t a

0 1 2 3 4

R103

H i g h - Z

F i g u r e 8 . D a t a H o l d T i m i n g

DQ15-0

[D/Q]

CLK [C]

V a l i d

O u t p u t

V a l i d

O u t p u t

V a l i d

O u t p u t

DQ15-0

[D/Q] V a l i d

O u t p u t

V a l i d

O u t p u t

1 CLK

Data Hold

2 CLKData Hold

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4.3.5 WA I T De l ay

The WAIT Delay (WD) bit controls the WAIT signals delay behavior during synchronous burstr e a d s. WA I T c a n b e a s s e r t ed e i t he r d u r i n g, o r o ne c l o ck c y c l e b e f o r e , v a l i d d a t a i s o u t pu t o n

D[15:0].When WD is set, WAIT is de-asserted one clock before valid data (default). When WD isc l e a r ed , WA I T i s d e - a s se r t e d w i t h v al i d d a t a . T h e s e tt i n g o f W D i s d e p e nd e n t o n t h e s y s t em a n dC P U d a t a s a m p l in g r e q u i r e m e nt s .

4.3.6 B u rs t Seq u en c e

T h e B u r s t S eq u e n ce ( B R ) b i t s e l e ct s l i n e a r- b u r s t s e qu e n c e ( d e f a u l t) . O n l y l i n e ar - b u r s t s eq u e n ce i ssupported. Table 6 s h o w s t he s y n c hr o n o u s b u r s t se q u e nc e f o r a l l b u r st l e n g t hs .

4.3.7 Cl o c k Ed g e

T h e C l o c k E d g e ( C E ) bi t s el e c t s e i t h e r a r i s in g ( de f a u l t) o r f a l l i n g c l o c k e d g e f o r C L K . T h i s i s t hec l o c k ed g e t h a t i s us e d a t t h e s t a r t o f a b u r s t c y cl e t o o u t p ut s y n c hr o n o u s d a t a a n d t o as s e r t / de -assert WAIT.

4.3.8 B u r s t L en g t h

B L [ 2 : 0 ] s e l e ct s t h e l i n e a r b u r st l e n g t h f o r a l l s y nc h r o n ou s b u r s t r e a ds o f t h e f l a s h m e m o r y. T h eburst length can be configured to be an 8-word or a 16-word burst. Once a burst cycle begins, thedevice will output synchronous burst data until it reaches the end of the burstable address space.

Ta b l e 6 . B u r s t S e q u e n c e W o r d O r d e r i n g

S t a r t Add r.

(D EC )

B u r s t A d d r e s s i n g S e q u e n c e ( DE C )

8 - W o r d B u r s t( B L [ 2 : 0 ] = 0 1 0) 1 6 - W o r d B u r s t( B L [ 2 : 0 ] = 0 1 1 )

0 0-1-2-3-4-5-6-7 0-1-2-3-414-15

1 1-2-3-4-5-6-7-0 1-2-3-4-515-0

2 2-3-4-5-6-7-0-1 2-3-4-5-60-1

3 3-4-5-6-7-0-1-2 3-4-5-6-71-2

4 4-5-6-7-0-1-2-3 4-5-6-7-82-3

5 5-6-7-0-1-2-3-4 5-6-7-8-93-4

6 6-7-0-1-2-3-4-5 6-7-8-9-104-5

7 7-0-1-2-3-4-5-6 7-8-9-10-115-6

14 14-15-0-1-212-13

15 15-0-1-2-313-14

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5.0 Pr o g r am Mo d e s

The device supports three different programming methods: Word Programming, Write-Buffer

Programming, and Buffered Enhanced Factory Programming or Buffered-EFP. Successfulprogramming requires the addressed block to be unlocked. If the block is locked down, WP# mustbe de-asserted and the block unlocked before attempting to program the array. An attempt toprogram a locked block will result in the operation aborting, and SR[1] and SR[4] being set,i n d i c a ti n g a p r o g r am m i n g e r r o r. T h e f o l l o w i ng s e c t i on s d e s cr i b e d e v i c e pr o g r a m mi n g i n d e t a i l .

5. 1 Wo r d Pr o g r am m i n g

Wo r d P r o g r a m m in g i s p e r f o r m e d b y e x e c u t i ng t h e Wo r d P r o g r a m c o m ma n d . Wo r d P r o g r a mm i n gi s a n on - b u f fe r e d o p e r a ti o n a nd p r o g r am s o n e w or d t o t he f l a s h a r r a y b a s e d o n t h e i n i t i a l pr o g r a maddress A[A MAX:A MIN] . To d e te r mi n e t h e s t at u s o f a w o r d- p r og r am o p e r at i o n, p o ll t h e s t a t usr e gi s t er a n d a na l y ze t h e b i t s. I f t h e f l a sh d e v ic e i s p u t i n s t an d by m o d e d u r in g a p r o g ra m o p er a t io n ,

t h e d ev i ce w i l l c o nt i n ue t o p r og r am t h e w or d u n t il t h e o p er a t io n i s c om p l et e ; t h en t h e d ev i ce w i l le n t er s t an d by m o d e . R e fe r t o F i g u r e 2 3 , W or d P r o g r a m m i n g F l o w ch a r t o n p a g e 6 7 for a detailedf l o w o n ho w t o im p l e m e nt a w o r d p r o g r a m o p e r at i o n .

During programming, the Write State Machine executes a sequence of internally-timed events thatprogram the desired data bits and verifies that the bits are sufficiently programmed. Programmingt h e f l as h m e m o r y a r r a y ch a n g es on e s t o z er o s . M e m o r y a r r a y b i t s t ha t a re z e r os c an b ec h a n ge d t o o n e s o n l y b y e r a s i n g t h e b l o c k .

W h e n p r o g r a mm i n g h a s f i n i s h e d, S t a t u s R e g i s t er b i t S R 4 s e t i n d i c a t es a p r o g r a mm i n g f a i l u r e. I f S R 3 i s s e t , t hi s i n d i c at e s t h a t t he W r i t e St a t e M a ch i n e c o u l d n ot p e r f o r m t h e W or d P r o g r a mm i n go p e r a ti o n b ec a u s e VPEN w a s o u t s i de o f i t s a c c ep t a b l e l im i t s . I f S R 1 i s s et , t h e Wo r d P r o g r a mm i n goperation had attempted to program a locked block, causing the operation to abort.

A f t e r e x a m i ni n g t h e s t a t u s r e g i st e r , i t s h o u l d b e c l e a r ed u s i n g t h e C l e a r S t a t us R e g i s t e r c o m ma n dbefore issuing a new command. Any valid command can follow, after Word Programming hascompleted.

5. 2 Wr i t e-B uf fer Pr o g r am m i n g

T h e d e v i c e f e at u r e s a 3 2 - w o r d Wr i t e B u f f er t o a l l o w o p t i m u m p r o gr a m m i n g p e rf o r m a nc e . F o r Write-Buffer Programming, data is first written to an on-chip write buffer, then programmed intot h e f l a sh m e m o r y ar r a y i n b uf f e r -s i z e i n c r e m en t s . O p t i m a l pe r f o r m a nc e i s r ea l i z e d w h e n

programming is buffer-size aligned to the 32-word write-buffer boundary. The write-buffer isd i r e c t l y m a pp e d t o t h e f l a s h a r r a y t h r o ug h A [ AMIN+4:A MIN]. Unaligned buffered writes willdecrease program performance. Buffered writes can improve system programming performance

m o r e t h an 2 0 X o ve r n o n w r i t e- b u f fe r p r o g r am m i n g .

To p e r f o r m W r i t e - B u ff e r P r o g r am m i n g , t h e W r i t e - t o -B u f f e r S e t u p c o m m a nd , 0 x E 8 , i s i s s u e d a l o n gwith the block address (see S e c t i on 3 . 2 , D e v i c e C o m m a nd s o n p a g e 1 9 ) . S t a t us R eg i s t e ri n f o r m at i o n i s u p d a te d , a n d a read from the block address w i l l r e t u rn S t a tu s R e gi s t e r d a t a s h o w i ngt h e w r i t e b u f f er s a v a i l a b i li t y.Note: Do not issue the Read Status Register command during thissequence. S R 7 i n d i c at e s th e a v a i l ab i l i t y of t h e wr i t e b u f f er f o r l o a d i ng d a ta . I f S R 7 i s s e t , th e w r i te

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buffer is available; if not set, the write buffer is not available. To retry, issue the Write-to-BufferS e t u p co m m a n d a g a i n, a n d r e - ch e c k S R 7 . W h en S R 7 i s se t , t h e w r i t e b u f f er i s a v a i la b l e . S ee Figure 2 2 , Wr i t e t o B uf f e r F l o w c h ar t o n p a g e 6 6.

Next, a word count (actual word count - 1) is written to the device at the buffer address. This tellst h e d e vi c e h o w m a ny d a ta w o r ds w i l l be w r i tt e n to t h e wr i t e b u ff e r, u p t o t h e ma x i mu m s iz e o f t h ew r i t e b u f f er . T h e v a l i d r a n g e o f v a l u e s f o r wo r d c o u n t i s 0x 0 0 t o 0 x1 F.

O n t h e n e x t w ri t e , a d e v i ce s t a r t a d d r e ss i s gi v e n al o n g w it h t h e f ir s t d a t a t o b e w r i t t e n t o t h e f la s hmemory array. Subsequent writes provide additional device addresses and data. All data addressesm u s t l i e w i t h i n t h e s t a r t a d dr e s s p l u s t h e w o r d c o u nt . M a x i m u m p r o g r am m i n g p e r f o rm a n c e a n dl o w e r p o w e r a r e o b t a i ne d b y al i g n i n g t h e s ta r t i n g a d d r e ss a t t he b e g i nn i n g o f a 3 2 w o r d bo u n d ar y.A m i s a l i gn e d st a r t i n g a d d r es s w i l l r e s u l t i n a d o ub l i n g o f t h e t o t al p r o g r am t i m e .

A f t e r t he l a s t d at a i s w r i t t en t o t he w r i t e bu f f e r, t h e W r i t e- t o - B u f fe r C o n f i r m co m m a n d i s i s su e d .T h e Wr i t e S t at e M a c h i ne b e g i ns t o c o p y t h e w ri t e b u f f er c o n t e nt s t o t h e f l a s h m e m o r y ar r a y. I f ac o m m an d o t h er t h a n t he W r i t e- t o - B u ff e r C o n f i r m co m m a n d is w r i t t en t o t h e d e v i c e, a c o m m an ds e q u en c e e rr o r w i l l o c cu r a n d St a t u s Re g i s t er b i t s S R4 , S R 5 a n d S R 7 w i l l b e s e t . If a n e r r o r o c c ur sw h i l e w r i t i n g t o t he a r r ay, t h e d e v i c e w i l l st o p p r o g r am m i n g , a n d S t a t u s R e g i st e r b i t S R 4 a n d S R 7

will be set, indicating a programming failure.

A d d i t io n a l b u f f er w r i t e s c a n b e i n i t i a te d b y i s s u i n g a n ot h e r W r i t e- t o - B u ff e r S e t u p c o m m an d a n dr e p e at i n g t h e w r i t e - t o- b u f f er s e q ue n c e .

A n y t i m e S R 4 a nd S R 5 a r e s et , t h e d e v i ce w i l l n o t a cc e p t W ri t e - t o -B u f f e r c o m m a nd s . I f a n a t t e m p ti s m a d e t o p r o g r a m p a s t a b l o c k b o un d a r y u si n g t h e W r it e - t o - B uf f e r c o m ma n d , t h e de v i c e w il la b o r t t h e o p e r a ti o n . T h i s w i l l g e n e r a te a c o m m an d s e q u e nc e e r r o r , a n d S t a t u s R e gi s t e r b i t s S R 4 a n dSR5 will be set.

I f W r i t e - B uf f e r P r o g r a mm i n g i s a t t e m p t e d w h i l e VPEN i s be l ow VPENLK, S t a t u s R e g i st e r b i t s S R 3and SR4 will be set. If any errors are detected that have set Status Register bits, the Status Registershould be cleared using the Clear Status Register command.

5.3 Pr o g r am Su s p en d

To e x e c u t e a p r o g r a m s u s p en d , e x e c u t e t h e P r o g r a m S u s pe n d c o m m a nd . A s u s pe n d o p e r a t io n h a l t sany in-progress programming operation. The Suspend command can be written to any deviceaddress. A Suspend command allows data to be accessed from any memory location other thanthose suspended.

A p r o g r am o p e ra t i o n c a n b e s u s p en d e d t o p er f o r m a d e v i c e r e a d . A p r o g r am o p e ra t i o n n e s t edw i t h i n a n e r as e s u s pe n d o p e r at i o n c a n b e s u sp e n d ed t o r e a d t h e f l a s h d e v i ce . O n c e t h e p r o g r am

process starts, a suspend operation can only occur at certain points in the program algorithm. Erasesuspend operations cannot resume until program operations initiated during the erase suspend arec o m p l et e . A l l d e v i c e r e a d f u n c t i on s a r e p e r m i t t e d d u r i n g a s u s p e n d o p e r at i o n .

D u r i n g a s u sp e n d , VPEN m u s t r e ma i n a t a v a l i d pr o g r a m l ev e l a n d W P # m u st n o t c h an g e . A l s o , am i n i m u m am o u n t o f t i m e i s r e q u ir e d b e t w e en i s s u i ng a P r o g r a m or E r a s e c o mm a n d a n d t h e nissuing a Suspend command.

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5. 4 Pr o g r am Res u m e

To r e s u me ( i . e . , c o n t i nu e ) a p r o gr a m s u sp e n d o p e r a t io n , e x e c u te t h e P ro g r a m Re s u m e c o m m a nd .T h e R e s u m e co m m a n d ca n b e w r i t te n t o a n y d e v i ce a d d r e ss . W h e n a p r o g r a m o p e r at i o n i s n e st e d

w i t h i n a n e r a se s u s p en d o p e r a t io n a n d t h e P r o g r a m S us p e n d c om m a n d i s i s s ue d , t h e d e v i ce w i l ls u s p en d t h e p r o g r am o p e r at i o n . W h e n t h e R e s u m e c o m m an d i s i s su e d , t he d e v i ce w i l l r e s um e a n dc o m p l e te t h e p r o g r am o p e ra t i o n . O n c e t h e ne s t e d p r o g r am o p e r a ti o n i s c o mp l e t e d, a n a d d i t i on a lR e s u m e co m m a n d i s r e qu i r e d t o c o m p le t e t h e b l o c k e r as e o p e r a ti o n . T h e d e v i c e s up p o r t s amaximum suspend/resume of two nested routines. See F i g u r e 2 4 , P r o g r a m S u s p e n d /R e s u m eF l o w c h a r t o n p a g e 6 8 .

5. 5 B u f f er ed En h an c ed Fac t o r y Pr o g r am m i n g (B u f fe red -EFP)

B u f f e re d - E F P s p e e ds u p M L C f l a s h p r o g r a mm i n g f o r t o d a y s b e a t - r a t e - se n s i t iv e m a n u f ac t u r i n genvironments. This enhanced algorithm eliminates traditional elements that drive up overhead ino f f - b oa r d o r o n - b oa r d , o f f - l i ne o r i n - l i n e , m a n u a l o r a u t o m a te d p r o g r a mm e r s y s t e ms . B u f f e r ed - E F P

i s d i f f e r e nt t h a n n o n - bu f f e r ed E F P m o d e ; i t i n c or p o r a t e s a w r i t e b u ff e r t o s p r e a d M L C p r og r a mperformance across 32 data words. Additionally, verification occurs in the same phase asprogramming, an inherent requirement of two-bit-per-cell technology to accurately program thecorrect state.

A s i n g l e tw o - c y cl e c o m m an d s e qu e n c e p r o g r am s a n e n t i r e b l o c k of d a t a . T hi s e n h an c e m en te l i m i n at e s t h r ee w r i t e c y c l e s p e r b u f f e r p a g e , tw o c o m m an d s a n d t h e w or d c o u nt p e r e a c h se t o f 3 2d a t a w o r d s. H o s t p r o g r am m e r b u s c y c le s f i l l t h e d e v i c e w r i t e b u f fe r , f o l lo w e d b y a s t a t u s c he c k o fSR.0 to determine when the data from that page has completed programming into sequential flashm e m o r y l o c a t i on s . F o l l o w i n g t h e b u f f er - t o - f l as h p r o g r a m m i n g s e q u en c e , t h e W S M i n c r e m e n t sinternal addressing to automatically select the next 32-word array boundary. This aspect ofBuffered-EFP saves programming equipment address-bus setup overhead. In combination, theseenhancements allow programming equipment to stream data to the device.

With proper continuity testing, programming equipment can rely on the WSM internal verificationto assure the device has programmed properly. This capability eliminates the external post-programverification and its associated overhead. Buffered-EFP consists of three phases: setup, program/v e ri f y, a n d e xi t . R e fe r t o Figure 25, Buffered Enhanced Factory Programming ProcedureF l o w c h a r t o n p a g e 6 9 f o r a g r ap h ic a l r e pr e s en t at i on o f B u ff e re d - EF P.

5. 5.1 B u f fer ed -EF P Re q u i r em en t s an d Co n si d er at i o ns

B u f f e re d - E F P r e q u i r em e n t s:

Ambient temperature: TA = 2 5 C 5 C

V C C w i t h i n s p e c i f ie d o p e r a t in g r a n g e

V PEN driven to V PENH Target block unlocked before issuing the Setup and Confirm commands

WA0 ( f i r s t w o r d a d d r es s i n b l o c k t o b e p r o g r a m m e d) m u s t b e h e l d c o n s t a n t f r o m s e t u p p h a sethrough all data streaming in the target block, until transition to the exit phase is desired

WA0 must align with the start of an array buffer boundary1

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Buffered-EFP considerations:

F o r o p t i m u m p e r f o r ma n c e , l i m i t c y c l i ng b el o w 10 0 e r a s e c y c l e s p e r b l o c k 2

B u f f er e d - E F P pr o g r a m s o n e b l o c k a t a t i m e, a l l b u f fe r d a t a m us t f a l l w i t h i n a si n g l e b l oc k 3

Buffered-EFP cannot be suspended P r o g r am m i n g to f l a sh c a n o n l y oc c u r w h e n t h e b u f f er i s f ul l4

1Buffer boundary in array is determined by A[A MIN+4:A MIN] ( 0 0h t hr o ug h 1 F h) . A l ig n me n t s t ar t p o in t i sA[AMIN+4:A MIN]=0.

2S o m e d e g r ad a t i on in p e r f o r ma n c e m a y o c c u r i f t h i s l i m it i s e x c e ed e d , b u t t h e i n t er n a l a l g o ri t h m w i l l c o n t in u et o w o r k p r o p e rl y.

3I f t h e i n t e rn a l a d d r e

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