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Multi-scale Systems Design andManufacturing

Characteristics of CommonMicrofabrication Processes

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Content

General ideas about MEMS and m-FAB Fundamental issues

Case Studies

Microengine, accelerometeretc

Micro-Fabrication

CVD/PVD

Oxidation/Deposition

Etching

Lithography Shih -Chi Chen

Nov 6, 2006

http://mems.sandia.gov/scripts/images.asp

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In the micro-scale

Modeling

Dominant

Application

Fysics

Limiting

Momentum

Information

Mass

Flows

Energy

Motion

Constraints

Geometry

Form

Interfaces

Performance

Cost

Processes

Fabrication

Rate

Who?

Where?

What?

Function

Why?

Machine

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Design & manufacture of machines

Marketresearch

Conceptualdesign

Design formanufacture

Fabricationprocesses

Assemblyprocesses

Factory andmfg. systems

Mil l

In ject ion mold ing

Photol i thography

DRIE

Forging

Bol t ing

Riveting

Solder ing

Welding

OthersItems in dotted lines adaptedFrom 2.008 (Prof. JH Chun)

Consumer

Grinding

Lathe

Function Form Flows Physics

1 2 3

4

5

6

Waterjet, Others

)(InputfOutput

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Fundamental IssuesFundamental reasons fabrication must be different

at microscale Material properties, size vs. tool, tools

Lithographic vs. Non-lithographic/ Macro vs. Micro

Quality: resolution: optical vs. mechanical

Rayleighs criterion: Resolution~1.2* / NA

Rate & cost: batch vs. individual

Flexibility: 2D based vs. 3D (need assembly/ material..etc)

Metrology

You cant make it if you cant measure it.

Grain boundary

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MICRO-ELECTRO-MECHANICAL-SYSTEM

MICRO- 10-6 m scale

ELECTRO- Electrical circuits/device

MECHANICAL- Mechanical structures/device

Parasite on matured IC fabrication processes

Miniaturization Engineering

Different Manufacturing Methods

Material

By the end of this lecture, you will be able to

Design basic m-FAB processes

Select proper materials

MEMS overview

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What you need to know?

MEMS Analysis

Chemistry

Micro-fluidic

Electronics

Optics

Thermal Science

Solid Mechanics

Course 2 material

Micro-Fab

PDMS Cell Sorter Micro Mirror

Micro-thermal actuator

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A nm 0.1mm 10mm 1mm 100mm 10 m

atomDNA

virus bacteriadust

hair

MEMS

People

nanotechnology microsystems meso macrosystems

Size matters: scales, miniaturizationhttp://w

ww.icknowledge.com/

1947~1999

1 transistor42 x 106 transistors

Courtesy:Sang-

gookKim,

MIT

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Chronicles about MEMS

1959: Richard Feyman says, There is plenty of room at the

bottom.

1969: Westinghouse creates the Resonant Gate FET.

1970s:Bulk-etched silicon wafers used as pressure sensors.

1982: Kurt Petersen published Silicon as a Structuralmaterial.

1980s: Early experiments in surface- micromachinedpolysilicon. Micromachining leverages the micro-electronic industry in late 80s.

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Why do we make things small?

Cost Reduced

Batch Fabrication

Larger wafer in diameter

Speed Increased

Shorter distance between elements

Reduce RC delay

Rigidity Enhanced

Very High Resonant Frequency

Mostly Single Crystal Silicon. No Fatigue!

Compatibility

Integration with IC/electronics

Capability of Arrays

Avoidable Drawbacks

Noise Amplification

High Developing Cost

Fundamental

Limitations

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Moores law (1964)Number of transistors per chip doubles every 1.5-2 years

Information store on Si = 2^(Time-1962)

Case Study: Accelerometers

6.152J class note

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Market for small-scale devices

http://www.aero.org/publications/helvajian/helvajian-4.html

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Integrated circuits (ICs)

This picture comes from an excellent introductory discussion about IC fabrication at: icknowledge.com

Start Finish

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Integrated circuits: Example-Pentium 4TM

Device characteristics

# of transistors 42 000 000

Line width: 0.18 m=>( 0.13 m)

P4 die size: 224 mm2

US dime size 248 mm2

Source: icknowledge.com

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Case Study: Thermal ink jetSuperheat ink 250oC

Peak pressure 1.4 MPa

Refills in 50ms

San

g-gookKim,

MIT

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Case Study: Accelerometers

San

g-gookKim,

MIT

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Case Study: Pressure sensors

www.evgroup.com

San

g-gookKim,

MIT

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Case Study: Digital Micro Mirrors

www.ti.com

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Case Study: MIT Micro-turbine engine

Great power-to-weight ratioGenerates power or thrust

Real Gas Turbine Engine

http://travel.howstuffworks.com/turbine.htm

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Mehra, A, etc.,A six-wafer combustion system for a silicon microgas turbine engine, Microelectromechanical Systems, Journal

of , Volume: 9 , Issue: 4 , Dec. 2000

Mehra, A, etc.,Microfabrication of high-temperature silicon devicesusing wafer bonding and deep reactive ion etching,

Microelectromechanical Systems, Journal of , Volume: 8 , Issue: 2 , June

1999

Case Study: MIT Micro-turbine engine

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Micro-manufacturing

Surface/bulk micro-machining

Materials: Silicon

Oxidation

Thin film deposition

Photolithography

Etching

Lift-off

Wafer Bonding

K. Pister, Berkeley

Sandia National Lab

DispenserPR

Wafer

Chuck

Spin

ICL, MITMIT MTL

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MIT Microsystems Technology Lab

MIT microfab facility (Building 39)

ICL IC Fab Class 10

TRL MEMS Class 100

EMLmFluidics Class 1000

Acid hood Wafer Stepper Coater

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Clean rooms

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Process matrix

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Typical Materials

Silicon (Si)

Doped Si

Poly silicon

Silicon oxide

Silicon nitride

Glass, quartz

Metals

Al, Au, Ag, Ti, Pt,

Polymers

Photoresist

Polyimide

PDMS

Ceramics

PZT

Polycrystalline Al

(C. V. Thompson)

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MEMS Fab Overview

How do you make this?

Using only 2D layer addition

and removal

With available processes

Micron-level size

Silicon

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MEMS Fab Overview

W. Tang - Darpa

Material system:

Poly/ SiO2/ HF

SiO2 / Poly/ XeF2

SiO2/ SCS/ XeF2

Al/ SCS/ SF6

PR/ SiO2/ HF

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Micro-Fabrication Overview

DepositionOxidation or

Deposition

LithographyAdd resist

Transfer pattern

Remove resist

EtchWet isotropic or

Wet anisotropic or

RIE

Sacrificial Etch

Wafers

2D

Devices

Repeat as Necessary

For typical processes

Needed for previous

example

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Silicon Wafers

http://www.msil.ab.psiweb.com/english/msilhist4-e.html

Czochrolski method

Molten Si bath

Seed pulled at 2-5 cm/hr

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Silicon Crystal Structure

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Silicon Wafers

Structural properties compared to Steel /

Aluminum:Density sut E CTE

Material g/cc Mpa GPa x 10-6

Silicon 2.33 4000 130 4.2

Steel [1020] 7.87 420 205 12

Aluminum [6061 T6] 2.7 310 69 24

Make Si into a conductor or insulator by doping

Boron, phosphorous, arsenic, antimony

Conductors Semi-conductors Insulators

10-3W-cm 102W-cmResistance

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Silicon-On-Insulator (SOI) Wafers

Multi-layered Si / Oxide1. Start with Si wafer

2. Grow oxide

3. Bond 2nd Si wafer to oxide

4. Grind top wafer to size

5. Repeat if necessary

Expensive~ $400 vs. $30

Reduces process time

Si Base Wafer

Si Base Wafer

Si Base Wafer

2nd Si Wafer

Si Base Wafer

Oxide

SOI

/

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Material Addition / Removal

Additive Casting

Molding

Oxidation

Deposition

Physical

EvaporationSputtering

Chemical

CVD Spin-on

Subtractive

Machining

Grinding

EtchingWet

Dry

MEMSwww.memspi.com

O id i

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Oxidation

Forming Silicon Dioxide by oxidation

O2 chamber @ 800-1200 oC (steam optional)

Silicon reacts with O2 to grow oxide

2 micron max film thickness

Si Wafer

O2 chamber

Si Wafer

O2 chamber

Oxide

3hr, 1000 C1m

O id ti

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Oxidation

Forming Silicon Dioxide by oxidation

Uses: insulation, masking, sacrificial layer

Easy to grow and etch (HF)

Good insulator/ diffusion barrier (Ex. B, P, As)

High dielecytic breakdown field (500 V/mm); = 1016 ohm-cm Good Ge/ GaAs => higher mobility/direct bandgap, but no stable oxide

=> Cant make MOS device

Si Wafer

O2 chamber

Si Wafer

O2 chamber

Oxide

3hr, 1000 C 1m

Ch i l V D iti

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Chemical Vapor Deposition

Gases react to deposit film on surfaces

Example: Polysilicon at 580-650C

24 2HSiHSi

ICL, MIT

Typical CVD Furnace:

E ti

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Evaporation

Metal evaporated w/ electron beam

Vacuum environment prevent oxidation, directionalvapor travel

Can get shadowing:

S. G. Kim, MIT

S tt i

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Sputtering

Materials: Metals and dielectrics

Requires high vaccuum

Argon ions bombard material target

Ejected material - ballistic path to wafers

S. G. Kim, MIT

D iti I

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Deposition Issues

Thermal compatibility

Topographic compatibility

Residual stresses

Deposition over features

Conformality:

Conformal Non-conformal

Non-conformal

Ph t lith h

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PhotolithographyPhotoresist (PR) used to transfer patterns

Viscous PR spun onto wafer Dispense, then spin

Speed controls thickness

Thickness: 1 10mmRequires baking (~100C)

DispenserPR

Wafer

Chuck

Spin Xrpm

7mm Positive Thick Resist1. Dispense, Spin 3500rpm

2. Pre-bake 90C 60min

3. UV mask expose 15 sec

4. Develop in aqueous

solution

5. Post-bake 90C 30min

Ph t lith h

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PhotolithographyExpose PR to UV light thru mask

Properties change in exposed regions

Masks: laser etched or print-transferred chrome

Positive resist destroy bonds, soluble

Negative resist crosslinking, less soluble

PositiveMask

PRSubstrate

UV light

SubstrateExpose

PR Reaction

Develop

NegativeWe use:

M t i l R l Et hi

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Material Removal - Etching

Bulk micromachining remove Si substrate

Surface micromachining add / remove films

Masks for etch surface:

Photoresist

oxide, nitride

Isotropic vs. anisotropic

Wet vs. dry etch

Deep Reactive Ion Etching

http://www.ti.

com/dlp/resources/library

K. Pister,

Berkeley

M t i l R l Et hi

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Material Removal - Etching

Williams, et al., J. MEMS Vol 5, no 4 1996

W t D Et hi

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Wet vs. Dry Etching

Wet etch

Chemical reaction

Low res

Low cost

Hard to control direction

Limited 2D geometries

1 10s of microns/min

Dry etch

Reactive ion etching (RIE)

High res

High cost

Very directional

Unlimited 2D geometries

0.1 10 microns/min

I t i A i t i Et hi

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Isotropic vs. Anisotropic EtchingIsotropic same etch rate in all directions

Etch depth / surface uniformity problems

Diffusion dependent

Etch silicon wafer and deposited films

Anisotropic crystal plane dependent

Etch ratios more than 100:1

silicon wafers only

Crystal planes:

54.7 Si

Adapted from: S.M. Sze, Semiconductor Devices S. G. Kim, MIT

Deep Reactive Ion Etching

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Deep Reactive Ion Etching

Alternating RIE - polymer deposition

Protection of side walls during material removal

CHF3/Ar forms Teflon-like layer

Issues: Scalloping and tapering

Milanovic et al, IEEE TED,

Jan. 2001.

Reverse Resist and Lift Off

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Reverse Resist and Lift-Off

Limited thickness need non-conformal film

Limited deposition methods PR compatibility

Not typically used in semiconductor industry

Substrate

PR1. Apply and pattern reverse resist

Need negative sidewalls

Positive resist negative image

2. Deposit desired film

Evaporation

Typically metal

3. Dissolve photoresist, lift-off film

Process:

Wafer Bonding

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Wafer Bonding

Combine complexshapes from multiplewafers

Si-Si wafers Low temp (450C) Fusion high temp (1000C) Adhesive epoxy, PR

Si-Glass wafers Anodic low temp, high voltage(700V)

M. Schmidt, 2000

MIT

Microengine

Project

Fusion bonded

wafer stack

Exercise 1: Design a micro structure

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Exercise 1: Design a micro-structure

Reverse engineer the m-FAB processes for thestructure shown below.

Hint:

Start with SOI wafers

Thickness=100mm Thickness=1mm

Exercise 2: Design a Micromotor

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Exercise 2: Design a Micromotor

Design the m-FAB processes & Select the materialsfor a micro-motor with cross-section view below

Beerschwingert et al. 1994

Conclusion

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Conclusion

Micro-fabrication is DIFFICULT: Many of themare still vibrant fields of research

Micro-fabrication is EXPENSIVE at developingstage: ~18k/ year @MIT

NEXT:

Micro-actuation/sensing/metrology