2758 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 49, NO. …circuits replace the OTAs in pipeline...

2758 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 49, NO. 12, DECEMBER 2014

Switched-Mode Operational Amplifiers andTheir Application to Continuous-Time Filters

in Nanoscale CMOSBaradwaj Vigraham, Member, IEEE, Jayanth Kuppambatti, and Peter R. Kinget, Fellow, IEEE

Abstract—We introduce a new class of feedback amplifiers,called switched-mode operational amplifiers (SMOAs) that ad-dress voltage-swing limitations of classical feedback amplifiers inscaled CMOS technologies. By exploiting the increased timing res-olution available in scaled CMOS, SMOAs encode analog signalinformation in the time domain and provide near-rail-to-railoutput-signal swing, high output-stage efficiency and betterlinearity. A 4th-order, 70 MHz continuous-time active-RC But-terworth filter is presented in 65 nm CMOS to demonstrate theadvantages of SMOAs. The filter consumes 25.4 mW from a0.6 V supply and achieves 55.8 dB peak SNDR while operatingat a full-scale of 873 mV . Thanks to SMOAs, the full-scale(73% of the 0.6 V supply voltage) and the bandwidth are respec-tively, a 2.5 and 6.2 improvement over other state-of-the-artlow-voltage filters.

Index Terms—Feedback amplifiers, filters, low supply voltages,pulse-width modulation, scaling, switched mode.

I. INTRODUCTION

F EEDBACK amplifiers are critical for the design of high-linearity active circuits and are extensively used in analog

and mixed signal applications like programmable gain ampli-fiers (PGAs), sensor amplifiers, anti-aliasing filters and ADCs.Continuous CMOS technology scaling has led to greatly re-duced supply voltages and transistors with poor intrinsic gain( ) [1] and calls for fundamentally different approaches toanalog design. Conventional design techniques that use opera-tional transconductance amplifiers (OTAs) at low supply volt-ages ( V) suffer from reduced signal swings and poordistortion. In such designs, the headroom required to maintainthe output devices in saturation increases the power dissipationto maintain the same signal-to-noise ratio [2]–[4].

Manuscript received April 23, 2014; revised July 08, 2014; accepted Au-gust 25, 2014. Date of publication September 23, 2014; date of current versionNovember 20, 2014. This paper was approved by Guest Editor Makoto Nagata.This work was supported in part by the National Science Foundation (NFS)Grant EECS 1309721.B. Vigraham was with the Department of Electrical Engineering, Columbia

University, New York, NY 10027 USA, and is now with MaxLinear Inc., SanJose, CA 95134 USA (e-mail: [email protected]).J. Kuppambatti was with the Department of Electrical Engineering, Columbia

University, New York, NY 10027 USA, and is now with Seamless Semiconduc-tors Inc., New York, NY USA (e-mail: [email protected]).P. R. Kinget is with the Department of Electrical Engineering, Columbia Uni-

versity, New York, NY 10027 USA (e-mail: [email protected]).Color versions of one or more of the figures in this paper are available online

at http://ieeexplore.ieee.org.Digital Object Identifier 10.1109/JSSC.2014.2354641

Fig. 1. Circuit architectures used in the design of continuous-time filters; per-formance critical blocks in nanoscale CMOS are highlighted.

Alternatives to classical feedback amplifiers (OTA-based cir-cuits) have been proposed in the literature but are largely lim-ited to discrete-time applications [5]–[8]. Zero-crossing-basedcircuits replace the OTAs in pipeline ADCs with power-effi-cient continuous-time slicers and current sources [5], [6], butsuffer from reduced signal swings similar to OTAs. VCO-basedquantizers [8]–[10] use ring-oscillators to minimize analog pro-cessing, but are limited to ADC applications and also have lim-ited linearity.Filters serve as a representative example for the various

continuous-time circuit architectures (Fig. 1) in the literature,both with and without the use of negative feedback. Active-RCarchitectures [11]–[13] use OTAs in feedback to realize highlylinear integrators at the cost of signal bandwidth. Transcon-ductor-based ( ) architectures, on the other hand, areopen-loop and offer wider bandwidth but are more nonlinear.Techniques attempting to combine the advantages of bothhave also been proposed [14], but still suffer from the signalswing limitations in nanoscale CMOS. Ring-oscillator-basedintegrators [15] address the DC gain limitations by leveragingthe increased of the transistors. However, they inherit thelinearity limitations of both VCO-based circuits and classicalopen-loop (e.g., ) architectures. The implementation ofhighly linear, near-rail-to-rail feedback amplifiers that exploitthe faster switching speeds of scaled CMOS processes remainschallenging.The rest of this paper is organized as follows. The chal-

lenges associated with classical feedback amplifiers in

0018-9200 © 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

VIGRAHAM et al.: SWITCHED-MODE OPERATIONAL AMPLIFIERS AND THEIR APPLICATION TO CONTINUOUS-TIME FILTERS IN NANOSCALE CMOS 2759

Fig. 2. (a) A typical class-A output stage OTA configured as a resistive feedback amplifier; voltage gain of the first and second stages are andrespectively. (b) Simplified distortion model for the OTA using for the transconductors and a single tone sinusoidal input, ;magnitude of the input-referred distortion due to first stage nonlinearity is times weaker than that from the output stage.

nanoscale CMOS are presented in Section II. In Section III,switched-mode operational amplifiers (SMOAs) that overcomethese challenges are introduced. A continuous-time filter ar-chitecture [16] that demonstrates the advantages of SMOAsis presented in Section IV. The measurement results of thefilter are presented in Section V, followed by conclusions inSection VI.

II. CHALLENGES FOR CLASSICAL AMPLIFIER TOPOLOGIES ATLOW SUPPLY VOLTAGES

Classical analog techniques represent information in thevoltage domain and require efficient use of the available signalswing tominimize power dissipation, for a given signal-to-noiseratio (SNR). The total power required is bounded by the powerneeded to drive the impedances in the circuit which are setby the required system SNR. E.g., this is the power drawn byan OTA output stage and can be shown to be independent ofthe supply voltage ( ) if the signal swing is maximized to

[17]. However, as supply voltages continue to scale, thepeak available swing rapidly drops due to overdrive ( )voltages needed to maintain the output transistors in saturation.This increases the power dissipation of the first stage and alsothe output stage, which now needs to drive lower impedances.The distortion performance of analog circuits is often limitedby the output stage in OTAs [14] or the transconductor in

architectures. Negative feedback is often employed inboth architectures to improve linearity, but at the expense ofbandwidth. An inherently more linear output stage is criticalsince it allows for the design of active-RC filters with lessfeedback and thus a wider bandwidth.This section analyzes in detail, the effect of these limitations

on classical feedback amplifier design. A 2-stage-OTA with re-sistive feedback (Fig. 2(a)) and a sinusoidal excitation is usedto illustrate the analysis. The conclusions do not significantlychange for a more complex circuit, such as the filter presentedin this work.

A. Reduced Supply Voltages

The single-ended peak output swing for the amplifier inFig. 2(a) is , where mVis the minimum headroom required to maintain the outputdevices in saturation [18]. The signal-to-noise ratio (SNR)at the amplifier’s output is calculated as follows: For a sinu-soidal input/output, the maximum RMS output voltage that

the amplifier supports is . The resistors ( , )and the transconductance in the OTA’s first stage ( ) con-tribute to the total noise at the output of the amplifier.1 Theoutput RMS noise voltage in a bandwidth B can be writtenas , where and arefeedback circuit topology-specific proportionality constants.E.g., in the circuit shown in Fig. 2(a), it can be shown that

and . The noise from the re-sistors ( ) and the OTA’s first stage ( )are assumed to contribute equally to the output noise, for abalanced design. The output SNR is therefore given by

(1)

The class-A output stage supports a current swing ofinto the load and requires a minimum bias current of .Using (1), the output stage power, can be expressed as afunction of the SNR as

(2)

As the and hence the maximum signal power reduces, thefirst stage transconductance increases to meet the SNR re-quirements according to (1). The desired in turn, sets thebias current in the first stage and its power dissipation,

. Using (1), can be rewritten as

(3)It should be noted that is only influenced by throughthe bias current and is dependent on the input stage’s operatingpoint. This is captured in its dependence on the of thefirst stage in (3). The expression , couldbe used in strong inversion, assuming ,

1The OTA’s input-referred noise is modeled as for illustration pur-poses, based on the following assumptions: (a) the output stage noise contribu-tion is small compared to that of the first stage and is neglected; (b) flicker noiseof the OTA is also ignored, i.e., the bandwidth B is much larger than the flickernoise corner; (c) an excess noise factor [19] is assumed for a transistorin saturation.


Fig. 3. Normalized power consumed by the amplifier in Fig. 2(a) with, V showing a large increase at low supplies;

the power consumed by the proposed SMOAs with showsmarginal increase.

while in weak inversion[19]. Assumingsquare-law transistors in strong inversion the total amplifierpower dissipation, from (2) and (3), is

(4)

For the amplifier in Fig. 2(a), with andmV, the total normalized power consumed by

the amplifier is plotted in Fig. 3 and rapidly increases withshrinking supply voltage. in (4) represents only the noiseconstrained power dissipation of a linear amplifier. In practice,the linearity requirements require (a) reducing the peak-to-peakswing to relax the output-stage drain nonlinearities and(b) increasing the output stage bias current to relax its gatenonlinearities. Fig. 3 shows the total normalized power when

is reduced to . Note that is doubledto meet the distortion requirements. The increase in powerdissipation is attributed to the reduced signal swing fromheadroom limitations and can be minimized by near-rail-to-railoperation. The proposed SMOAs, as we show later, achieve

, even at low supplies and hence their powerconsumption shows marginal increase with shrinking supplyvoltages as shown in Fig. 3.

B. Poor Output Stage Power Efficiency and Distortion

The output stage power in (2) is marginally influencedby supply scaling but strongly by its class of operation e.g.,class-A, AB or B. For an output stage with efficiency , (4)becomes

(5)

Class-A operation limits the efficiency to 25% (Fig. 4(a))in the absence of distortion and even lower in practice. TheOTA power can be reduced by going to other classes of op-eration, i.e., class-AB or B with ,but at the cost of distortion since the amplifier’s distortionis often output-stage-limited. In Fig. 2(b), the first stage ex-periences a smaller input swing than the output stage dueto its gain. Without loss of generality, the transconductorsin the OTA are assumed to be biased at the sameand are modeled as with the same. For a sinusoidal input, , the distortion terms

referred to the OTA’s input (VG in Fig. 2(b)) from the firstand the output stages are and

, respectively. Intuitively,the output stage experiences a larger swing and hence adds

times more distortion, limiting the overall linearity.Fig. 5 shows the OTA power consumption as the output

stage efficiency is varied up to 39% (class-B operation), notaccounting for distortion. However, the higher distortion fromthe class-AB or B stage increases the total power to meetthe linearity specifications. In contrast, the efficiency of theproposed SMOAs will be shown to be close to 50% with littledistortion, thanks to their class-D output stages.It is also critical that the OTA output stage gain,

be 1, in the absence of which, the output of the firststage needs to swing as much as the amplifier output,adding additional distortion through drain nonlineari-ties. Moreover, the output stage distortion (referred toVG in Fig. 2(b)) is

, whereis the open loop gain of the OTA. For a given unity-gainbandwidth (UGB), this is proportional to and hence,

is key to lowering distortion from output-stage gate non-linearities. As we will show later, SMOAs are inherently morelinear (i.e., lower ) and support up to dB,even while driving low-impedance loads.

C. Reduced Intrinsic Gain and Stability

The digital-oriented CMOS scaling has resulted in switch-like transistor operation and reduced DC gain. Analog applica-tions require large DC gains, often achieved using cascoded andmulti-stage OTAs [20]. Cascoding in single-stage OTAs leadsto higher power dissipation from further reduced signal swingsdue to headroom limitations. Also, they cannot drive resistiveloads, inevitably leading to multi-stage OTAs. The analysis sofar has been limited to resistive-feedback amplifiers to keep thecalculations manageable. In systems like filters, the OTAs arealso loaded by capacitors that are sized based on noise require-ments. Multi-stage OTAs pose stability challenges with capac-itive loads, require frequency compensation and compensationcapacitors comparable to the load capacitors. This places a min-imum transconductance requirement on both stages of the OTA,increasing power dissipation.To overcome the shortcomings of classical OTAs, an oper-

ational amplifier with the following key properties is desired:the output stage needs to (a) support rail-to-rail output signalswings and have voltage gain; (b) exhibit a higher power ef-ficiency compared to class-A stages with low-distortion and


Fig. 4. A comparison of loading networks to calculate power efficiency of (a) class-A output stage in a classical OTA, (b) class-D output stage in an SMOA and(c) N-signal class-D output stages in a multi-phase SMOA.

Fig. 5. Comparison of power consumed by OTA-based and the proposedSMOA-based feedback amplifiers for varying output stage efficiencies at

V. , V for OTA operation andfor SM operation. Distortion (ignored in the power consump-

tion shown) increases as in OTA operation and is intrinsically lowerin SMOA operation ( ).

(c) have a pole that does not significantly influence the sta-bility of the feedback loop. In the following section, switched-mode operational amplifiers (SMOAs) that overcome these lim-itations of OTAs by exploiting the faster switching speeds ofscaled CMOS processes are presented.

III. SWITCHED-MODE OPERATIONAL AMPLIFIERS (SMOAS)

Fig. 6(a) shows a simplified representation of the proposedSMOA. The first stage is identical to that of a typical OTA(Fig. 2(a)). The output stage is a pulse-width modulator whichdrives the feedback network through a series of CMOS inverter-buffers. It transforms the input voltage signal information to

Fig. 6. (a) Resistve feedback amplifier using proposed SMOAs showingswitched output signals, single-phase differential-input PWM modulatorresults in 2-level representation of signals; the signal component is shown as ablack dashed line. (b) Linear model of an ideal natural sampling PWM mod-ulator. (c) Output spectrum of an ideal PWM modulator with MHzand MHz; out-of-band spurs are modeled as an additive source

in Fig. 6(b).

the pulse-width domain by using natural sampling pulse-widthmodulation (PWM) [21].The PWM modulator is implemented as a continuous-time

slicer which compares the input signal to an ideal triangularwave (or sawtooth wave) and outputs a binary level signal.


The output consists of pulses with continuously varying widths(i.e., no time quantization) repeating at the PWM referencefrequency . The PWM modulator can be modeled as again block ( ) with a propagation delay (Fig. 6(b)).The gain is set by the peak-to-peak voltage of thePWM reference, to that of the PWM output, . Thepropagation delay includes the delay of the continuous-timeslicer, which is dominant and the CMOS inverter buffers thatdrive the output load. The output spectrum [22], [23] consistsof: 1) a tone at the fundamental amplified by ;2) No distortion components; and 3) modulation componentsaround the PWM carrier frequency and its har-monics ( ), denoted by in Fig. 6(b).The output of an SMOA is corrupted only by the presenceof spurious frequency components around the harmonics ofthe modulation frequency, unlike that of an OTA which hasharmonics of the signal frequency. If the out-of-band spurs canbe ignored, SMOAs are highly linear feedback amplifiers; thesuppression of these spurs is discussed later.Feedback-based class-D audio driver-amplifiers [24], [25]

also use PWM-modulated output stages like SMOAs. Theydrive low-impedance resistive loads and have stringent linearityrequirements ( 90 dB) and require a highly-linear first stage(in Fig. 6(a)), often OTA-RC integrators, to handle the fed backrail-to-rail PWM signal. Feedback-based class-D amplifiersare typically limited to audio frequencies ( 100 kHz) and useoff-chip loss-less passives for filtering.SMOAs are geared towards analog/mixed signal processing

applications which require driving higher resistive impedancesin addition to capacitive loads. In this work, we present de-sign techniques for SMOAs that overcome the lack of induc-tive elements for analog/mixed signal applications, relax thefirst stage linearity requirements and support higher bandwidths( MHz). SMOA-based designs, like class-D ampli-fiers, can be impacted by power supply noise and mitigationtechniques developed for class-D amplifiers like [26]–[28] canbe used as a starting point in future investigations. In the fol-lowing sections, we compare SMOAs to OTAs and present theiradvantages in scaled CMOS processes.

A. Rail-to-Rail Operation

The output of SMOAs are switched signals (0 or ) withthe signal information encoded in pulse widths. The signalcomponent swing is limited only by the minimum pulse-width

that the circuit can handle and the signal component in theoutput can vary from toi.e., , peak-to-peak. E.g., in 1.0 V 65nmGP CMOS, ps and with an of 300 MHz, thepeak output signal swing of the SMOA is as high as .At a 0.6 V supply, though increases to 200 ps, the peakswing is still . This is well beyond that of an OTAthat can be as low as , predicting power savingsfrom the analysis presented earlier, even ignoring any outputstage efficiency improvement (Fig. 3). Furthermore, the peaksignal swing of SMOAs is expected to improve as reduceswith scaling, a key advantage.

B. Improved Power Efficiency and Linearity

The maximum theoretical power efficiency is limited to 25%in class-A OTAs (Section II-B). Consider the OTA and SMOAoutput stages in Fig. 4(a) and (b). Since the SMOA is placedin feedback, the output/feedback resistor terminates in a vir-tual ground which is nominally maintained at by feed-back. As a result, the drop across the resistor is alwaysand the power dissipated in the resistor is . This equalsthe total power consumed by the output stage, assuming idealclass-D operation.2 The signal power is and

yielding . Thepower dissipated to represent information at the input frequency,is at best half the power delivered to the load. The remainingpower is dissipated in the frequency components at the modula-tion spurs. This loss is eliminated in conventional class-D ampli-fiers by the use of off-chip lossless passives between the outputstage and the load. Since this is not practical in SMOAs, the peakefficiency of an SMOA output stage is limited to 50%. Fig. 5compares the power consumed in OTAs and SMOAs using (5)as a function of the output stage efficiency , predicting over8 reduction in power consumption in SMOAs compared toOTAs, neglecting the power consumed for PWM modulation.Pulse width modulation does not result in distortion [29] and

hence the output stage of an SMOA is theoretically linear. Inpractical implementations however, there are two main sourcesof distortion: (a) finite rise and fall-times of the switching wave-forms at very narrow pulse widths i.e., high signal swings; thisimproves with technology scaling and (b) imperfect generationof the triangular wave reference for PWM, which is more dom-inant. E.g., in a simulation experiment in a 65 nm GP CMOStechnology at 0.6 V, a 2-stage class-A OTA achieves an openloop HD3 of 40 dB while operating at a full scale of ,but an SMOA for the same distortion performance and powerconsumption, including the power expended in the PWM mod-ulators, can operate at a full scale of . Note that, in ad-dition, the PWM modulator power consumption is expected tofurther reduce with scaling. The intrinsically better linearity ofSMOAs allows the use of lower loop gain in the feedback am-plifier to meet the distortion requirements, and hence a widerbandwidth.

C. Load-Independent Bandwidths in SMOAs

The stability of OTA-based feedback systems is stronglyload-dependent since the transconductance nature of OTAoutput stages leads to an output pole. This places an upper limiton the stable unity-gain bandwidth (UGB) which can be in-creased only by a higher power dissipation in both stages of theOTA. In contrast, an SMOA output stage has a low open-loopoutput impedance and the transfer function is ,where is the total propagation delay of the PWM modulator.Since is dominated by the delay of the slicer, SMOA stabilityand bandwidth is almost load independent.

2The power consumed by the PWMmodulator and the power dissipated in theoutput stage switches are assumed to be negligible, as in the case with thermalnoise limited systems. It should be noted that feedback amplifier applicationsoperate at much higher impedance levels compared to class-D power amplifierapplications. Consequently, the output stage switches are much smaller in sizeand do not significantly contribute to the output stage power dissipation.


Fig. 7. Linear models used for stability analysis for (a) OTA, (b) SMOA and(c) RC-compensated SMOA with FIR filtering; UGB limiting factors in the re-spective feedback amplifiers are highlighted.

To compare the bandwidths achievable using OTAs andSMOAs, consider Fig. 7. If is the transconductance ofthe first (noise-limited) stage of an OTA, that of theoutput stage and and are the load and compensationcapacitors respectively, the transfer function of the OTA is

. The output stagepole limits the UGB as follows:

where is a proportionality constant setby the phase margin (PM) and the feedback factor. E.g.,

for 65 PM in Fig. 2. An SMOA with anidentical first stage as the OTA has the transfer function

.The output stage adds a linear phase lag tothe lag from the first stage. The UGB is limited bythe PWM modulator’s propagation delay and is given by

whereis a proportionality constant set by the PM and the

feedback factor. E.g., for 65 PM in Fig. 6(a).However, unlike OTAs, the maximum stable UGB is load-inde-pendent and depends only on which improves with scaling.

D. Suppressing Modulation Spurs and Driving CapacitiveLoads

The output of an SMOA contains undesired modulation spursat integral multiples of that need to be pushed away fromthe signal band. As discussed earlier, these modulation spurslimit the efficiency of SMOAoutput stages to 50%while drivingresistive loads. If the load is a capacitor , the switching natureof the SMOA output leads to a power dissipation .In comparison, the power dissipation of a class-A output stagewith signal swing3 and a bandwidth ofis , which could be much smaller than that of

3We assume signal swing for a class-A stage only to estimate the biascurrent required, all other parameters being the same.

an SMOA if . In practice, the distortion of aclass-A stage requires a higher bias current ( ) to meet thelinearity specifications, relaxing the minimum needed toefficiently drive capacitors.Additionally, since the input is analog while the SMOA

output is switched, the virtual ground node in a single-phaseSMOA (Fig. 6(a)) experiences large jumps. These are filteredby the first stage and do not affect loop operation, if the firststage is perfectly linear. However, the differential peak-to-peakvariation on the virtual ground node of a single-phase SMOA(Fig. 6(a)) is which imposes very stringent linearityspecifications on the first stage. To address this and improvethe SMOA efficiency while driving capacitive loads, we nowpresent techniques to suppress the spurs from PWM modula-tion.1) Multi-Phase Operation: In single-phase PWM, the modu-

lation spurs occur aroundmultiples of . In a fully differen-tial implementation, by operating two modulators that comparethe input with differential reference waveforms, i.e.,(phase 1) and (phase 2), the spurs around odd mul-tiples of are canceled, realizing an effective modulationfrequency of . In general, -phase PWMwith referencesstaggered by results in an effective modulation frequencyof [15], [30] and an -level time-domain signal(see Fig. 8). The variation on the virtual ground node of theSMOA is now reduced to , relaxing the first stage’s lin-earity requirements.In a multi-phase SMOA, each phase is an impedance-scaled

version of the desired circuit. E.g., in Fig. 8, the load isdivided amongst the eight phases, loading each phase with .The efficiency of SMOAs when driving resistive loads remains50% (Fig. 4(c)), identical to single-phase SMOAs. When theload is capacitive ( ), each phase is loaded with . TheSMOA’s output stage dissipates i.e.,

. Since multi-phase SMOAs allow the use oflower to push the spurs to a given frequency, this leadsto lower power dissipation for capacitive loads.2) Continuous-Time (CT) FIR Filtering: The switched na-

ture of SMOA outputs uniquely enables CT-FIR (finite impulseresponse) filtering [31]–[34] using simple digital delay cells.CT-FIR filtering can be used to produce notches in the fre-quency domain at the SMOA output, increasing the number ofeffective levels used for signal representation. E.g., consider an8-phase SMOA ( ) as shown in Fig. 9. Noting that thespurs occur at the multiples of and that an FIR filterof the form (where ) pro-duces notches at odd multiples of , thestrongest modulation components are now at . In thetime domain, this is equivalent to a 17-level representation forslow-varying signals (see Fig. 9), further relaxing the linearityrequirements of the first stage of the SMOA. However, suchnotches have a finite bandwidth and add more phase shift inthe transfer function. This introduces a trade off to realize agiven number of signal levels, since delay cells for the FIR con-sume little power compared to the slicers required for PWMmodulation.


Fig. 8. Proposed 8-phase SMOAs use a 9-level signal representation. In multi-phase implementations, resistors of the various phases are tied together to interfacewith the following stage. Open termination yields a voltage output as shown in the figure and termination to virtual ground yields a current output.

Fig. 9. SMOA used in this work with 8-phase PWMmodulators and a 2-tap FIR showing the 17-level output waveform for slow-varying signals. Interfacing withneighboring stages is similar to the multi-phase approach in Fig. 8.

In the SMOAs used in this work (Fig. 9), RC-compensationtechniques which introduce a phase lead using a zero are used toincrease the bandwidth. However, due to the faster phase roll-offwith frequency in SMOAs (linear vs. arctan in OTAs), the gainmargin requirements place the zero slightly beyond the UGB.Continuous-time FIR filtering introduces additional phase shiftto the SMOA’s transfer function and the complete transfer func-tion of the RC-compensated SMOA with FIR is

(6)

where and.

IV. CONTINUOUS-TIME FILTER ARCHITECTURE USING SMOAS

Feedback-based filter architectures like OTA-RC fil-ters deliver better linearity due to the OTA loop gain,compared to their open loop counterparts. But,the large capacitance values set by filter noise require-ments in wideband ( 50 MHz) and medium resolution( 55 dB) applications lead to high power dissipation dueto fundamental OTA limitations discussed in Section II.The proposed SMOAs offer a solution that address thesechallenges while improving with technology scaling. Inthis work, we demonstrate this using a 4th-order con-tinuous-time SMOA-RC, 70 MHz Butterworth filter thatoffers a 6.2 improvement in bandwidth compared tostate-of-the-art low-voltage filters.The prototype filter is built using Tow-Thomas biquads

(Fig. 10(a)) which are less sensitive to filter parameter varia-tions compared to other implementations (e.g., Sallen-Key).


Fig. 10. Biquad architecture using 8-phase SMOAs with FIR filtering. (a) Tow-Thomas realization of the biquads using SMOAs, impedance-scaled R and Ccomponent values used for the each phase of the two biquads are given. (b) Inter-connection of various input/output signals of the second integrator (shadedsection in (a)).

Fig. 11. (a) SMOA unit cell; the complete SMOA consists of 8 identical units in parallel. Values of and for each of the 8 UGB-limiting RCs are given.(b) Time domain waveforms of first stage output, and the SMOA output, . is a sum of an amplified sinusoidal signal (from the input) and thetriangular PWM reference (integral of a square wave reference current). is obtained by differentially slicing .

Fig. 10(b) shows the implementation of the biquad’s second in-tegrator, built around the SMOAs in Fig. 9. The following sec-tions describe the circuit implementation of the filter in a 65 nmGP CMOS process.

A. Switched-Mode Operational Amplifier (SMOA) ArchitectureThe SMOA (Fig. 9) uses a 16-signal architecture with 8-phase

PWM and 2-tap FIR. The PWM reference frequency is chosenbased on the signal bandwidth as follows: the spurs are designed


Fig. 12. Continuous-time slicer used for pulse-width modulation in Fig. 11(a).

to be filtered by two RC filter sections (with anMHz) at the SMOA output. This requires the spurs to be

beyond 2 GHz for dB rejection. A single-phase imple-mentation with GHz has several disadvantages asdiscussed in the previous section. In this work, MHzand hence 8 phases with MHz is chosen toachieve a 2.4 GHz effective modulation frequency. Further,CT-FIR filtering with 2 taps ideally suppresses some of thespurs at 2.4 GHz leading to dominant spurs at 4.8 GHz and a17-level signal representation. Since each SMOA phase hastwo outputs (un-delayed and delayed for FIR), the feedbackand feedforward networks are split into 16 parallel paths.

B. Circuit Implementation of the SMOA Unit

The multi-phase SMOA is implemented as a composite ofeight parallel single-phase units (Fig. 11(a)). The unit SMOA’sfirst stage consists of a transconductor while the outputstage is a single-phase PWM modulator. The filter capacitorsdo not set the SMOA bandwidth (due to load-independent op-eration) and is solely set by the filter’s noise requirements,after appropriate impedance scaling for the eight parallel paths.The following sections present the implementation of the keycircuit blocks.1) First Stage Transconductor: The transconductor

(Fig. 11(a)) is implemented as a pseudo-differential telescopiccascode amplifier without a tail current source to enable 0.6 Voperation and has a DC gain of 40 dB in simulation. The biascurrent is set by controlling the body ( ) of the transistors

through a body mirror circuit [2]. Their gates are biased atwhen placed in feedback, through a slow common-mode

feedback (CMFB) loop at the composite SMOA’s output. Adedicated common-mode loop for the first stage providescommon-mode rejection. Resistors are chosen to belarge enough not to load the first stage output.2) Pulse-Width Modulator Design: Converting an analog

signal into a pulse-width modulated stream entails two opera-tions: (a) generation of the reference ramp, against which the

Fig. 13. Implementation of the continuous-time FIR delay cell and the inverterbuffers used to drive the load network.

Fig. 14. Die photo of the 65 nm CMOS filter prototype.

input signal is compared and (b) the continuous-time compar-ison that produces the PWM signal. The input-reference sub-traction is performed as follows: the signal current ( )and a square-wave current ( ) areadded on a capacitor ( in Fig. 11(a)). The capacitor4 in-

4In practice, is a parasitic capacitor at the output of and is dom-inated by the bottom plate capacitance from .


Fig. 15. Filter measurement setup.

Fig. 16. Measured filter transfer function and a superimposed ideal fourth-order Butterworth transfer function for comparison.

tegrates the square-wave current to generate the reference ramp(see Fig. 11(b)). This elegantly accomplishes both the genera-tion of the PWM reference and its subtraction from the analoginput. The amplitude of the reference is chosen to provide a gainof for the PWM modulator by adjusting .The propagation delay ( ) of the continuous-time slicer (

in Fig. 11(a)) sets the maximum UGB of the SMOA. The slicer(Fig. 12) is a cascade of 3 differential pairs followed by staticinverters to drive the output load. The delay of the slicer islargely set by the gain-bandwidth of its first stage. Also, sinceeach SMOA requires 8 PWM modulators, achieving this largegain-bandwidth in a power-efficient manner is critical to min-imize the SMOA power. The slicer’s first stage is a CMOS(NMOS and PMOS) differential pair, interfaced to the output of

through aDC level-shifting network. A dedicated common-mode feedback network sets the SMOA output common-modeto . Simulations indicate a PWM modulator delay of 200ps while dissipating W.3) Unity-Gain Bandwidth (UGB) Limiting Capacitors: The

large transistor -s in nanoscale CMOS necessitate limitingthe bandwidth of the first stage for stability in the presence ofphase shifts due to the PWM modulator and FIR delays. How-ever, the bias current of is set by the noise specifications andits bandwidth is controlled by changing the capacitance .

Fig. 17. Filter performance as a function of the input signal amplitude at200 kHz showing a full-scale of dBm or 873 mV .

TABLE IFILTER PERFORMANCE SUMMARY

1. Includes transconductor .2. Includes pulse-width modulator, 8-phase clockgenerator and output drivers.3. From 2.5 V supply which includes clock-chipinterface; all internal clock distribution is done at0.6 V.

The RC-compensated SMOA (Section III-C) can be realized byconnecting an RC network to the output of the 8 s between

and , and etc. But


Fig. 18. Filter output spectrum for a 200 kHz input signal: (a) in-band (0 – 4 MHz) showing an inband SFDR of 65 dB and (b) complete spectrum (0 – 2 GHz)showing incomplete cancellation of multi-phase modulation spurs.

Fig. 19. Two-tone linearity performance: (a) in-bandmeasurement with tones at 1.95MHz and 2.05MHz and (b) out-of-band measurement with tones at 75.5MHzand 150 MHz. The solid lines represent the fundamental tone’s power while the dashed lines represent that of the third order intermodulation product, as predictedby the IIP3 values (markers) reported in the respective papers.

such an arrangement would capacitively load the PWM currentsource in Fig. 11(a) requiring a higher to maintain thesame modulator gain. This increases the noise added to the firststage and the power dissipation. This is resolved by connectingthe capacitors such that the ramps appear in common-modewhile the signal current is loaded by these capacitors. Notingthat the PWMphases , etc. are 180 out-of-phase,the UGB-limiting RC network is connected between the nodes

and , and , etc. Thisenables the use of a smaller, lower noise for a given mod-ulator gain. is tunable and set to achieve a nominal UGBof 450 MHz while is chosen for a zero around 600 MHz.

4) CT-FIR Delay Cells: CT-FIR filtering is used to provide anotch at 2.4 GHz, with dominant spurs at 4.8 GHz. This requiresan FIR delay GHz ps, achieved usingon-chip delay cells. The delay cells are tunable with 10 ps reso-lution, through a serial interface and an on-chip DAC. A 4-phaseSMOA, with an of 300 MHz, and a 4-tap FIR filter using3 delay cells (each GHz ) also achieves the samedominant spur frequency (4.8 GHz). But, this would increase thephase shift in the signal path (tousing Fig. 7(c)) and reduce the maximum UGB. An 8-phase,2-tap FIR SMOA is therefore preferred. To propagate pulsesdown to 150 ps widths to maximize the output signal swing,


TABLE IICOMPARISON TO STATE-OF-THE-ART FILTER IMPLEMENTATIONS

the delay cell (208.33 ps) requires at least two stages (Fig. 13).5

This is implemented as a cascade of inverters with a MOS-tun-able delay.

V. MEASUREMENT RESULTS

The filter was fabricated in 65 nm GP CMOS (Fig. 14) andoccupies an active area of 0.38 mm . The filter’s output fromeach biquad directly drives the off-chip load as shown in Fig. 15.An externally fed 2.4 GHz clock is used to generate the 8-phasePWM reference clocks, which drive the SMOAs through tun-able delay cells to correct for timing mismatches. The filter ca-pacitors are tunable to compensate for process variations. Onpower up, the output of each biquad is observed on the spec-trum analyzer (SA) and a sweep of delay settings of the clockphases of both the SMOAs ( ) is performed, followedby FIR delay tuning to minimize the spurs at multiples of thePWM frequency, MHz.

A. Frequency Response, Dynamic Performance and Linearity

Fig. 16 shows the measured filter transfer function, whichclosely matches that of an ideal 4th-order Butterworth filter. Thesmall peaking observed out-of-band at 400 MHz is due to re-duced gain margin and can be easily resolved in future work bymarginally reducing the UGB of the SMOA.To demonstrate the near-rail-to-rail swing capabilities of

SMOAs, Fig. 17 shows the filter’s dynamic performance as afunction of the input signal amplitude at 200 kHz. The peaksignal-to-noise ratio (SNR), total harmonic distortion (THD)and the spurious-free dynamic range (SFDR) are 55.8 dB,60 dB, and 65 dB, respectively, for a full-scale input of2.8 dBm or 873 mV . This is 73% of the 0.6 V supply and

a improvement over other low-voltage, state-of-the-artfilters [2], [3], [15].The largest in-band spur (0–4 MHz) for a 200 kHz full-scale

input (Fig. 18) is 65 dB below the fundamental, thanks to thehighly linear operation of SMOAs at large signal swings. In an

5Since delays are generated by slowing the rise/fall time of the pulses, de-laying a 150 ps wide pulse by 208.33 ps using a single-stage would reduce thepulse-width, leading to distortion.

Fig. 20. Filter THD for a 200 kHz input signal at dBm as a function ofvarying blocker tone power at 75 MHz. The time domain waveforms add involtage at these frequencies and the input is backed off to remain within thevoltage full-scale dBm mV .

ideal gain and phase matched system, the 8-phase SMOA im-plementation along with the CT-FIR filtering leads to dominantmodulation spurs at 4.8 GHz. However, the complete outputspectrum (0–2 GHz) shows spurs at multiples of the PWMreference frequency (300 MHz) at 32.8 dB or more, below thesignal. These spurs stem frommismatches between the SMOA’s8-phases. While timing mismatches in PWM reference clockdistribution have been addressed by the use of retiming in thepresented design, the offsets in the transconductors ( inFig. 11(a)) are found to be the dominant source of these spurs.They can be eliminated by use of auto-zeroing or other offsetcancellation techniques in future work.The inherently linear operation of SMOAs allows for a lower

loop gain for the same linearity and enables a wider bandwidththan conventional architectures. The in-band IM3 (Fig. 19(a))shows superior performance (at dBm) compared toother 0.6 V designs and even some higher supply voltage de-signs. The out-of-band IM3 is closely competitive (Fig. 19(b))at dBm, a distinct feature of feedback-based fil-ters. In both the in-band and out-of-band two-tone IM3 tests,


Fig. 21. Effect of clock jitter: (a) out-of-band modulation spur at 600 MHz and (b) in-band integrated noise, showing robustness to jitter.

the 3rd order distortion terms do not increase at 3 dB/dB withinput signal power as expected from systems with soft nonlin-earities. In this prototype, the distortion is limited by folding ofthe modulation spurs caused by mismatch and not by the firststage ( ). This is also evident from the output spectrum inFig. 18 where the largest distortion term is the 4th harmonic at800 kHz.The active-RC nature of the filter enables robust operation in

the presence of out-of-band blockers. To evaluate this, signal(200 kHz, dBm) and blocker (75 MHz, swept power) tonesare fed to the filter and the THD for the signal is measured as afunction of the blocker power (Fig. 20). The THD is largely un-affected even with a high (0 dBm) blocker power, unlikearchitectures.

B. Effect of PWM Clock Jitter

Since the SMOA encodes information in pulse widths, jitteron the PWM reference can be translated to a voltage noise6 atthe input of the SMOA output stage. The jitter on the PWMreference is therefore equivalent to output stage noise in theSMOA and is suppressed in feedback. To demonstrate this, ajittery clock source was emulated by phase modulating the 2.4GHz clock with a white noise source. This is seen as a rise inthe out-of-band noise-floor around 600 MHz (Fig. 21(a)). Thein-band integrated noise only changes negligibly with the addedjitter (Fig. 21(b)). This enables the use of low-power compactring oscillator clock sources in future implementations.

C. Performance Summary and Comparison to State of the Art

The filter draws 25.4 mW (Table I) from a 0.6 V supply:12.6 mW for the first stage transconductors in the SMOAs and12.8 mW for the switching sections including clock generationand distribution, PWMmodulators and signal buffering to drivethe off-chip load. The filter peak SNR is 55.8 dB which is 2.2 dBless than the dynamic range of 58 dB. This is attributed to noisefolding back into the pass-band due to incomplete multi-phasespur cancellation in the SMOAs. The performance of the filter

6Using the slope of the PWM ramp signal.

Fig. 22. Comparison to state-of-the-art filters.

is compared to others using [14], [36]:where dBm dBm ,

is the filter 3 dB bandwidth, is the order and isthe in-band integrated noise power (Table II). The filter’s FoMof 0.07 fJ, is next only to a 1.8 V design [14]. The power perpole normalized to SFDR plotted as a function of the bandwidth(Fig. 22) shows that the filter has the largest bandwidth amonglow-voltage implementations, with the largest full-scale output(73% of ).

VI. CONCLUSIONS

CMOS technology scaling has led to several challengesin the design of amplifiers using conventional techniques.Switched-mode operational amplifiers (SMOAs) that leveragethe faster switching speeds of nanoscale CMOS to realizehigh-linearity feedback amplifiers are introduced. PWMmodulation with multi-phase operation and continuous-timeFIR filtering techniques that improve the performance of


SMOAs are also presented. A continuous-time filter prototypethat uses SMOAs to achieve near-rail-to-rail operation andstate-of-the-art linearity at 0.6 V is demonstrated. The filterachieves the best FoM among low voltage designs whileachieving the highest bandwidth and the largest full-scale.

ACKNOWLEDGMENT

The authors thank D. Belot and ST Microelectronics for sil-icon donation,Marianne Santangelo (Electrorent) for test equip-ment, and Mentor Graphics for AFS.

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Baradwaj Vigraham (S’12–M’14) received theBachelors degree in electrical engineering fromthe Indian Institute of Technology, Madras, India,in 2008, and the Masters and Ph.D. degrees fromColumbia University, New York, NY, USA, in 2010and 2014, respectively.He is currently with MaxLinear, Inc., San

Jose, CA, USA, and his research interests includeultra-low power receivers, and high-performancedata converters. He has worked at Silicon Laborato-ries, Austin, TX, and Texas Instruments, Dallas, TX,

over the summers of 2009–2011 as an intern.Dr. Vigraham was the recipient of the Armstrong Memorial Award from the

Department of Electrical Engineering at Columbia University, Analog Devices’Outstanding Student Designer Award and the Columbia University ElectricalEngineering Outstanding Collaborative Research Award.

Jayanth Kuppambatti received the Bachelor ofEngineering degree in electronics and communica-tions engineering from the College of Engineering,Guindy (CEG), Anna University, India, in 2008, andthe Master of Science and Ph.D. degrees in electricalengineering from Columbia University, New York,NY, USA, in 2010 and 2014, respectively.He was jointly responsible for the develop-

ment of multi-channel radiation-hard PipelineADCs intended for the upgraded electronics inthe ATLAS Liquid Argon Calorimeter readout at

the CERN Large Hadron Collider (LHC). He is the co-founder of SeamlessSemiconductors, a semi-conductor start-up focusing on high performancemixed-signal design solutions in scaled CMOS technologies. His interestsinclude mixed-signal design and high performance data converters.Dr. Kuppambatti was the recipient of Analog Devices’ 2012 Outstanding Stu-

dent Designer award and the 2014 Columbia University Electrical EngineeringOutstanding Collaborative Research Award.

Peter R. Kinget (M’90–SM’02–F’11) received theengineering degree (summa cum laude) in electricaland mechanical engineering and the Ph.D. (summacum laude with Congratulations of the Jury) in elec-trical engineering from the Katholieke UniversiteitLeuven, Belgium, in 1990 and 1996, respectively.From 1991 to 1995, he received a graduate fellow-

ship from the Belgian National Fund for ScientificResearch (NFWO) and was a Research Assistant atthe ESAT-MICAS Laboratory of the Katholieke Uni-versiteit Leuven. From 1996 to 1999 he was at Bell

Laboratories, Lucent Technologies, in Murray Hill, NJ, as a Member of Tech-nical Staff in the Design Principles Department. From 1999 to 2002 he heldvarious technical and management positions in IC design and development atBroadcom, CeLight and MultiLink. In 2002 he joined the faculty of the Depart-ment of Electrical Engineering, Columbia University, NY. During 2010–2011,he was at the Université catholique de Louvain, Belgium, on sabbatical leave.He also serves as an expert on patent litigation and a technical consultant toindustry.His research interests are in analog, RF and power integrated circuits and

the applications they enable in communications, sensing, and power manage-ment. He is widely published in circuits and systems journals and conferences,has co-authored 3 books and holds 16 US patents with several applicationsunder review. His research group has received funding from the National Sci-ence Foundation, the Semiconductor Research Corporation, the Department ofEnergy (ARPA-E), the Department of Defense (DARPA), and an IBM FacultyAward. It has further received in-kind and grant support from several of themajor semiconductor companies.Dr. Kinget is a Fellow of the IEEE. He is an elected member of the IEEE

Solid-State Circuits Adcom (2011–2013 and 2014–2017). He has been an IEEEDistinguished Lecturer of the Solid-State Circuits Society (2009–2010) and anAssociate Editor of the IEEE Journal of Solid State Circuits (2003–2007) andthe IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II (2008–2009). He hasserved as a member of the Technical Program Committee of the IEEE CustomIntegrated Circuits Conference (2000–2005), the Symposium on VLSI Circuits(2003–2006), the European Solid-State Circuits Conference (2005–2010) andthe International Solid-State Circuits Conference (2005–2012). He was a co-re-cipient of several awards including the Best Student Paper Award – 1st Placeat the 2008 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium,the First Prize in the 2009 Vodafone Americas Foundation Wireless Innova-tion Challenge, the Best Student Demo Award at the 2011 ACM Conference onEmbedded Networked Sensor Systems (ACM SenSys), the 2011 IEEE Commu-nications Society Award for Advances in Communications, and the First Prize($100 K) in the 2012 Interdigital Wireless Innovation Challenge (I2C).

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Transcript of 2758 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 49, NO. …circuits replace the OTAs in pipeline...