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APPENDIX B-2

Farmwald/Horowitz Patents

No. Claim Term, Phrase,

or Clause

Claims NVIDIA’S Preliminary Proposed

Construction

NVIDIA’S Evidence

1. access time

information

937/4(1), 5(1)

097/6(1)

information that specifies a

predetermined non-zero amount of time

that a device must wait from receivinga transaction request to responding to a

transaction request

‘097 patent, 7:1-4, 9:58-64, 10:26-38;

15:64-16:11, 16:44-67, 20:17-31; ‘937

patent, 7:1-4, 9:59-65, 10:27-39; 15:63-16:9, 16:45-65, 20:14-28.

2. delay time 937/31(30)

696/27(26),

29(26)

a predetermined non-zero amount of

time that must transpire before

commencing an action.

‘696 patent, 6:34-39, 7:1-8, 9:57-63,

10:8-12, 36-39, 11:19-31, 15:60-16:10,

16:45-65, 20:14-28; See also citationsto same or substantially similar content

in ‘937 patent.

3. read delay 997/1, 19, 32, 35,

38


time that must transpire before data isread from a memory device.

‘997 patent, 6:34-39, 7:11-18, 10:3-8,

20-26, 48-51, 11:19-31, 16:18-32,16:66-17:23, 20:43-57.

4. in response to 997/1, 19, 32, 38

696/26, 29(26),

30(26)

281/36, 42(36),

43(36)

097/1, 5(1), 26

937/1, 3(1), 4(1),5(1), 18, 23(18),

24(18), 37(30)

020/2(1), 32(28),

34(28), 37(28), 38

plain meaning. ‘020 patent, 6:62-66, 8:42-57, 9:46-64;

See also citations to same or

substantially similar content in ‘937,

‘281, ‘097, ‘696, ‘997 patents.

Case3:08-cv-03343-SI Document272-3 Filed12/02/11 Page1 of 9

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or Clause


Construction

NVIDIA’S Evidence

5. information thatrepresents an amountof time which lapses

937/32(30) information that indicates apredetermined non-zero amount of timethat must lapse.

‘937 patent, , 6:34-39, 7:1-8, 9:57-63,10:8-12, 36-39, 11:19-31, 15:60-16:10,16:45-65, 20:14-28

6. latch circuitry 937/19(18) circuitry for maintaining a particular

state of a signal until being reset.

‘937 patent,10:15-27, 49-60, 12:12-16,

23:43-52; 25:60-26:9; The Computer

Glossary – Fourth Edition – 1989 –same for Fifth Edition from 1991 (A

latch is an electronic circuit, such as a

flip-flop, that maintains one of twostates. It is set and then reset.); IBM

Dictionary of Computing – 1994 (latch– (1) a bistable circuit that is set and

reset by appropriate input signals; …

(3) an electronic circuit that records thestatus of a signal until it is reset);

Microsoft Computer Dictionary – 1991

(latch – a circuit or circuit element usedto maintain a particular state, such as

on or off, or logical true or false. A

latch changes state only in response to

a particular input. A flip-flop is onekind of circuit.); The Illustrated

Dictionary of Microcomputers – Third

Edition – 1990 (latch – an arrangementor circuit used to hold data in a ready

position until required, usually

controlled by another condition orcircuit. Also called lock . latching – a

technique in which data is held in a

circuit until other circuits are ready tochange this circuit)


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or Clause


Construction

NVIDIA’S Evidence

7. latch 937/19(18) maintaining a particular state of asignal until being reset, asdistinguished from sampling

‘937 patent,10:15-27, 49-60, 12:12-16,23:43-52; 25:60-26:9; The ComputerGlossary – Fourth Edition – 1989 –

same for Fifth Edition from 1991 (A

latch is an electronic circuit, such as a

flip-flop, that maintains one of twostates. It is set and then reset.); IBM

Dictionary of Computing – 1994 (latch

– (1) a bistable circuit that is set andreset by appropriate input signals; …

(3) an electronic circuit that records the

status of a signal until it is reset);Microsoft Computer Dictionary – 1991

(latch – a circuit or circuit element used

to maintain a particular state, such as

on or off, or logical true or false. Alatch changes state only in response to

a particular input. A flip-flop is one

kind of circuit.); The IllustratedDictionary of Microcomputers – Third

Edition – 1990 (latch – an arrangement

or circuit used to hold data in a readyposition until required, usually

controlled by another condition orcircuit. Also called lock . latching – atechnique in which data is held in a

circuit until other circuits are ready to

change this circuit); See also citations

for sample / samples / sampling.

8. memory controller / controller device /

997/1, 3(1), 19,26(19), 31(19),

a device that includes circuitry to directthe actions of one or more memory

‘020 patent, 6:12-26, 20:45-60; ‘937patent, 6:14-25, 20:45-60; ‘997 patent,


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or Clause


Construction

NVIDIA’S Evidence

memory controllerdevice

32, 38

696/26

937/18, 19(18),

22(18), 23(18),24(18), 26(18),

29(18), 30, 31(30)

020/1, 2(1), 10(1),

11(1), 12(1),13(1), 14(1), 38,

47(38), 49(38)

devices 6:24-35, 21:7-19; ‘696 patent, 6:13-27,20:45-60; ‘020 patent, claims 1, 17, 28,38.

‘937 Reexam, 12/18/2009 OA,

8/6/2010 OA, 11/24/2010 ACP,

4/4/2011 ACP (and citations therein).

9. integrated circuit

controller device

020/38 A controller device constructed on a

single monolithic substrate, commonly

called a “chip.”

Rambus v. Infineon, 318 F.3d 1081,

1091 (Fed. Cir. 2003); Rambus v.

Hynix II , 05-00334, 7/10/2008 Claim

Construction Order at 21; The New

IEEE Standard Dictionary of Electricaland Electronic Terms 662 (5th ed.

1993); IBM Dictionary of Computing 347 (10th ed. 1994). See also citations

for controller device; ’937 Reexam,

PO’s 12-18-09 Response.

10. memory device 937/2(1), 4(1),

5(1), 8(1), 18,

23(18), 24(18),30, 32(30), 36(30)

37(30), 38(30),

097/1, 5(1), 6(1),26

281/36, 38(36),

39(36), 40(36),

A device in which data can be stored

and retrieved electronically.

‘020 patent, 1:20-27, 3:23-28, 31-32,

50-55, 4:10-14, 5:29-32, 58-63, 7:18-

30, 19:63-20:13. See also citations tosame or substantially similar content in

‘937, ‘097, ‘281, ‘696, ‘997 patents;

Rambus v. Hynix II , 05-00334,

7/10/2008 Claim Construction Order at

32-35.’937 patent, 3:63-4:2.


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or Clause


Construction

NVIDIA’S Evidence

42(36), 43(36),44(36), 45(36),46(36)

696/26, 27(26),

28(26), 29(26),

30(26), 31(26),

997/1, 19,26(19),

32, 38

020/1, 2(1), 28,

29(28), 32(28),

34(28), 35(28),37(28), 38, 49(38)

95/001,134, 2010-03-29 PO’sComments at 3.‘937 Reexam, 12/18/2009 OA,

8/6/2010 OA, 11/24/2010 ACP,

4/4/2011 ACP, NVIDIA’s 11/23/2011

Cross-Appeal Brief (and citationstherein).

U.S. Patent No. 5,841,715, claims 1

and 3.U.S. Patent No. 5,657,481, claim 1.

11. operation code 937/1, 3(1), 4(1),

5(1), 14(1), 15(1),

17(1), 18, 23(18),24(18), 29(18),

30, 37(30)

020/2(1), 32(28),34(28), 37(28), 38

696/26, 29(26),

30(26), 35(26)

997/1, 2(1), 3(1),19, 26(19),

31(19), 32(19), 38

One or more control bits specifying a

type of action to be performed by a

memory device.

‘020 patent, 3:50-60, 4:1-5, 10:12,

5:29-50, 6:16-17, 53-60, 8:58-63, 9:24-

64. See also citations to same orsubstantially similar content in ‘937,

‘281, ‘696, ‘997 patents; The

Authoritative Dictionary of IEEE

Standard Terms 769 (2001 ed.)

12. precharge information 937/17(1)

696/35(26),

Information denoting whether senseamplifiers and/or bit lines (or a portion

of the sense amplifiers and/or bit lines)

should be precharged.

‘696 patent, 10:52-60, 32-44; See also citations to same or substantially

similar content in ‘937, ‘997 patents;

Rambus v. Hynix I , 00-20905,


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or Clause


Construction

NVIDIA’S Evidence

997/19, 32(30) 11/15/2004, Claim Construction Orderat 22-23.

Rambus v. Hynix II , 05-00334, Dkt.

No. 312, Rambus’s Opening Markman

Brief at 18; Murphy Decl. ¶¶ 188-95.

Rambus v. Hynix I , 00-20905, Dkt. No.328, Rambus’s Opening Claim

Construction Brief at 19.

13. programmableregister

696/26 A register within a memory device thatis permanently or semi-permanently

loaded with a fixed value.

‘696 patent, 6:28-54, 10:8-14; 16:45-52; Fig. 16.

14. representative of a

number of clock

cycles of the externalclock signal to

transpire

696/28(26)

937/5(1)

indicates a number of clock cycles of

the external clock signal that must

transpire before commencing an action.

‘696 patent, 6:34-39, 7:1-8, 9:57-63,

10:8-12, 36-39, 11:19-31, 15:60-16:10,

16:45-65, 20:14-28; See also citationsto same or substantially similar content

in ‘937, ‘097 patents.

15. sample / samples /

sampling

997/1, 19, 32, 38

696/27(26),

28(26)

097/1, 26

937/1, 18, 23(18),26(18)

020/14(1), 17,

25(17), 29(28),

30(28), 34(28),49(38)

obtain/ obtains/ obtaining at one or

more discrete points in time, as

distinguished from latch/ latches/ latching.

‘020 patent, 21:50-55, 22:21-56, 23:26-

41; ‘937 patent, 25:60-26:9; See also

citations to same or substantiallysimilar content in ‘937, ‘097, ‘696,

‘997 patents;

Przybylski Depo Testimony, 8/18/2011at p. 86:12–19, 8/19/2011 at pp.

314:12-315:16Przybylski Hearing Testimony,

10/13/2011 at pp. 831:18–832:18,833:17-834:15.

Rambus v. Hynix II , 05-00334, Dkt.

No. 312, Rambus’s Opening MarkmanBrief at 15; Dkt. No. 313, Murphy

Decl., ¶ 156.


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or Clause


Construction

NVIDIA’S Evidence

‘937 Reexam, 12/18/2009 OA,8/6/2010 OA, 11/24/2010 ACP,4/4/2011 ACP (and citations therein).

16. value is representative

of a delay time to

transpire

696/27(26),

29(26)

information that indicates a

predetermined non-zero amount of time

that must transpire before commencingan action.

‘696 patent, 6:44-49, 7:1-8, 9:57-63,

10:8-12, 36-39, 11:32-45, 15:60-16:10,

16:45-65, 20:14-28.

17. variable delay line 020/11(1), 12(1) a delay line that uses feedback to

provide a varying amount of the delay.

‘020 patent, 22:57-23:13, Fig. 12.


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Barth II Patents

No. Claim Term, Phrase,or Clause

Claims NVIDIA’s Preliminary ProposedConstruction

NVIDIA’S Evidence

1. after a second/third

delay time has

transpired

119/21

952/21

953/25

After an additional second/third

predetermined non-zero amount of

time has transpired.

‘119 patent, 10:7-10, 11:18-22, 3:3-

13, Fig. 3; See also citations to same

or substantially similar content in ‘952

and ‘953 patents.

2. memory device 050/29

119/21

952/21, 22(21)

953/25

A device in which data can be stored

and retrieved electronically.

‘119 patent, 1:19-44, 7:10-18, 19:30-

22:57; ‘953 patent, 19:60-26:11; ‘952patent, 19:59-24:35; ‘050 patent,

19:53-22:67.

3. integrated circuit

memory device

050/29

119/21

952/21, 22(21)

A memory device constructed on a

single monolithic substrate, commonly

called a “chip.”

Rambus v. Infineon, 318 F.3d 1081,

1091 (Fed. Cir. 2003); Rambus v.

Hynix II , 05-00334, 7/10/2008 ClaimConstruction Order at 21; The New

IEEE Standard Dictionary of

Electrical and Electronic Terms 662

(5th ed. 1993); IBM Dictionary of

Computing 347 (10th ed. 1994). See

also citations for memory device.

4. sense command 050/29

119/21

952/21

953/25

Signals provided to a memory device

for initiating a sense operation within

the memory device.

’119 patent, Fig. 10; 5:61-63, 1:37-39;

9:56-59; 1:40-44; 11:40-42; See also

citations to same or substantiallysimilar content in ‘050, ‘952 and ‘953

patents.

5. the memory device

initiates a write

operation after a firstdelay time transpires

953/25 The memory device begins to perform

a write operation only after a first

predetermined non-zero amount of time transpires.

’119 patent, 12:18-25; 2:18-19; See

also citations to same or substantially

similar content in ‘050, ‘952 and ‘953patents.


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6. the write command is

presented/posted

internally to/within thememory device after a

first/second delay

[time] has transpiredfrom when the write

command is received

119/21

952/21

The write command is provided to a

memory core of a memory device only

after a first/second predetermined non-zero amount of time has transpired

from when the write command is

received by the memory device.

‘119 patent, 1:37-39, 2:21-25, 10:24-

66, 11:1-6, Figs. 1, 16-21, 48; See also

citations to same or substantiallysimilar content in ‘050, ‘952 and ‘953

patents; File History of patent #

7,197,611, 8/21/2006 Amendment toFinal Office Action. 2/17/06.

Amendment, at 9 (pointing to support

in 1J[102 of specification [equivalentto ' 119 patent, col. 10, 11.48-57])

7. write command 050/29

119/21

952/21

953/25

Signals provided to a memory devicefor initiating a write operation within a

memory device.

’119 patent, 12:18-25; 2:18-19; Seealso citations to same or substantially

similar content in ‘050, ‘952 and ‘953

patents.

8. delay time 119/21

952/21

953/25


time that must transpire before

commencing an action.

‘119 patent, 10:24-66, 11:1-6, Figs.

17-21. See also citations to same or

substantially similar content in ‘’050,‘952 and ‘953 patents. 2/17/06

Amendment, at 9 (pointing to supportin 1J[102 of specification [equivalent

to ' 119 patent, col. 10, 11.48-57])


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