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Appendix B-1

Farmwald/Horowitz Patents

No. Claim Term, Phrase, or

Clause

Rambuss Proposed Construction Supporting Evidence

1. access time information information that indicates a time adevice must wait from receiving a

transaction request to responding to atransaction request

Specification(s)

and all original claims; e.g.,

0971

patent, 6:34-36; 7:1-6; 8:47-51; 9:15-17;9:56-58; 10:14-15; 11:61-63; 15:64-16:11;

16:47-64; 24:57-59

Hynix I2Evidence for access time register

Definitions for access time andinformation in IEEE Standard Dictionary of

Electrica1 and Electronics Terms, Fourth

Edition, 1988 (hereinafter referred to as 1988IEEE Dictionary), pp. 17, 473.

Definitions for access time in The NewIEEE Standard Dictionary of Electrical andElectronic Terms, Fifth Edition, 1993

(hereinafter referred to as 1993 IEEE

Dictionary), pp. 7, 642.

Expert testimony by Robert Murphy may beprovided as referenced and provided herein, as

set forth in the cover pleading to this exhibit,

and/or as set forth in footnote 4.3

1Cites to the Farmwald/Horowitz patent specifications are to U.S. Patent Nos. 6,260,097 (097 patent) and 7,209,997 (997 patent).

2 As used herein,Hynix Irefers toHynix Semiconductor Inc. et al. v. Rambus Inc., No. CV-00-20905 RMW (N.D. Cal.). Becausemany of the terms were construed previously by the Court inHynix I, Rambus may rely on the supporting intrinsic and extrinsic evidence offeredby Rambus in that case relating to the terms in support of its proposed constructions. ThisHynix I Evidence is available to at the belowlisted

Hynix Idocket numbers. As used in these tables, Hynix IEvidence relating to a particular term should be understood to include Rambus

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6:64-7:10; 8:47-57;9:12-19; 9:56 62; 10:3-15; 10:35-47; 11:19-35; 11:59-60; 11:61-63;14:60 15:63;15:64-16:11; 16:47 16:64;

20:19-23; 20:28 31; 23:13-16; 24:57-59;

997 patent, Fig. 16.

Hynix Iand Consolidated Actions Evidencefor delay time, and read operation. See

also intrinsic and extrinsic evidence cited for

the term delay time.Expert testimony by Robert Murphy may be

provided as referenced and provided herein, as

set forth in the cover pleading to this exhibit,and/or as set forth in footnote 4.

4. in response to as a result of Specification(s)and all original claims; e.g.,

097 patent, 5:13-14; 6:8-11; 8:29-40; 15:23-

27; 16:3-11; 18:3-4, 12; 18:64-19:1; 16:15,16:35-47; 21:36-38, 21:56-58; -21:53-22:3;

22:18-23, 53-59; 23:35-45; 24:23-24, 39-41;

Figs. 10, 12, 13.

Hynix Iand Consolidated Actions Agreedconstructions, and Evidence for in response

to rising/falling.



and/or as set forth in footnote 4.

5. information that represents anamount of time which lapses

information that indicates an amount

of time which lapses

Specification(s)

and all original claims; e.g.,097 patent, 4:23-27; 6:32-37; 6:42-50, 55-60;

6:64-7:10; 8:47-57;9:12-19; 9:56 62; 10:3-


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15; 10:35-47; 11:19-35; 11:59-60; 11:61-63;14:60 15:63;15:64-16:11; 16:47 16:64;20:19-23; 20:28 31; 23:13-16; 24:57-59;

997 patent, Fig. 16.

Hynix Iand Consolidated Actions Evidence

for delay time and value that isrepresentative of an amount of time to

transpire




6. latch circuitry a circuit or circuit element to captureand maintain a signal value

Specification(s)

and all original claims; e.g.,097 patent, 9:19-22; 10:17-26; 12:13-16;

15:23-27; 15:42-63; 18:12-13; 21:26-24:59;

Figs. 10, 11.Hynix Iand Consolidated ActionsEvidence for output driver circuitry, output

driver, input receiver circuitry, input

receiver

Definition for latch in IEEE StandardDictionary of Electrical and Electronics

Terms, Sixth Edition, 1996, p. 572.

Definition for latch in Websters Ninth NewCollegiate Dictionary, 1990, p. 675.

Expert testimony by Robert Murphy may be

provided as referenced and provided herein, asset forth in the cover pleading to this exhibit,

and/or as set forth in footnote 4. Mr. Murphy

may testify as to how one of skill in the art atthe time of the inventions would interpret the


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terms latch and latch circuitry in thecontext of the patents-in-suit. Mr. Murphymay testify as to any differences, similarities,

and relationship between latch and latch

circuitry and sampling in the context of the

claims of the patents-in-suit, in conjunctionwith why it is improper and ambiguous to

incorporate a negative limitation into the term

sample distinguish[ing] it from latching,and vice versa. Mr. Murphy may also testify

as to why it is improper to incorporate an

extraneous reset limitation into the termslatch and latch circuitry.

7. latch to capture and maintain a signalvalue

Specification(s)and all original claims; e.g.,

097 patent, 9:19-22; 10:17-26; 12:13-16;

15:23-27; 15:42-63; 18:12-13; 21:26-24:59;Figs. 10, 11.Hynix Iand Consolidated Actions

Evidence for output driver circuitry, output

driver, input receiver circuitry, input

receiverDefinition for latch in IEEE Standard

Dictionary of Electrical and Electronics

Terms, Sixth Edition, 1996, p. 572.Definition for latch in Websters Ninth New

Collegiate Dictionary, 1990, p. 675.



and/or as set forth in footnote 4. Mr. Murphymay testify as to how one of skill in the art at


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the time of the inventions would interpret theterms latch and latch circuitry in thecontext of the patents-in-suit. Mr. Murphy

may testify as to any differences, similarities,

and relationship between latch and latch

circuitry and sampling in the context of theclaims of the patents-in-suit, in conjunction

with why it is improper and ambiguous to

incorporate a negative limitation into the termsample distinguish[ing] it from latching,

and vice versa. Mr. Murphy may also testify

as to why it is improper to incorporate anextraneous reset limitation into the terms

latch and latch circuitry.

8. memory controller /controller device / memory

controller device / integratedcircuit controller device

an integrated circuit device that

includes circuitry to direct the actions

of one or more memory devices

Specification(s)


097 patent, 6:12-8:14; 8:41-11:60; 14:46 -16:22.


for memory controller.

See also intrinsic and extrinsic evidence formemory device.




9. memory device an integrated circuit device in whichinformation can be stored and

retrieved electronically, not includinga memory controller

Specification(s)


097 patent, 1:32-61; 3:23-27; 3:32-48; 3:52-54; 4:27-35; 4:60-61; 4:65 5:1; 5:8-9; 6:6-

15; 7:17-36, 52-55; 8:28-29, 34-40; 16:3-6,


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35-36; 17:36-42; 19:16, 35-38, 42-46; 21:34-36, 53-58; 22:60-23:29; 23:17-19, 35-40;24:57-59;

Figs. 1, 2, 3, 4, 8a, 10, 13, 15,

and 997 patent, Fig. 16.

Hynix Iand Consolidated Actions Evidencefor memory device.




10. operation code one or more bits to specify a type ofaction

Specification(s)


097 patent, 9:23-42, 46-64; 10:14-56; 11:25-67; 24:57-59; Fig. 4.


for operation code.Expert testimony by Robert Murphy may be




11. precharge information one or more bits indicating whetherthe sense amplifiers and/or bit

lines(or a portion of the senseamplifiers and/or bit lines) should be

precharged

Specification(s)


097 patent, 10:17-20, 39-47, 52-56; 11:29-36;24:57-59.

Hynix Iand Consolidated Actions Evidencefor precharge information.

Definition for precharge from A 4096-b

One Transistor per Bit Random AccessMemory with Internal Timing and Low

Dissipation, L. Boonstra et al., IEEE Journal


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of Solid State Circuits, Vol. SC-8, No. 5,October 1973, pp. 306-308.Definition of precharge from CMOS

Devices and Technology for VLSI, John Y.

Chen, 1990, pp. 106-110, 115- 116.



and/or as set forth in footnote 4.12. programmable register a register whose contents can be

modified based on informationreceived from an external source

Specification(s)

and all original claims; e.g.,097 patent, 4:23-27; 6:27-52; 9:7-9; 9:15-17;

9:46-10:13; 14:50-65; 15:64-16:11; and 997

patent, Fig. 16.Expert testimony by Robert Murphy may be



13. representative of a number ofclock cycles of the external

clock signal to transpire

indicates a number of clock cycles of

the external clock to occur

Specification(s) and

all original claims; e.g., 097

patent, 4:23-27; 6:32-37; 6:42-50, 55-60; 6:64-7:10; 8:47-57;

9:12-19; 9:56 62; 10:3-

15; 10:35-47; 11:19-35; 11:59-60;11:61-63; 14:60 15:63;

15:64-16:11; 16:47 16:64; 20:19-23; 20:28 31; 23:13-16; 24:57-59; 997 patent, Fig. 16.


for value that is representative of anamount of time to transpire and value which

is representative of a delay time


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Definitions for represent andtranspire in Websters New WorldDictionary, Third College Edition, 1988

(herein referred to as 1988 Websters

Dictionary), pp. 1139, 1422.



and/or as set forth in footnote 4.14. sample / samples / sampling to obtain at a discrete point in time /

obtains at discrete points in time /obtaining at discrete points in time


all original claims; e.g., 097patent, 19:32-34; 21:45-23:45; Fig. 11.

Consolidated Actions Evidence

for samples/samplingDefinitions for sampled data and sampled

signal in 1988 IEEE Dictionary, p. 855.

Definitions for sampled data and sampledsignal in 1993 IEEE Dictionary, p.

1164.

See operation code, block

size information, inputreceiver circuitry.



and/or as set forth in footnote 4. See also

Supporting Evidence for latch / latchcircuitry.

15. value is representative of adelay time to transpire

information that indicates a delaytime to occur

Specification(s) andall original claims; e.g., 097

patent, 4:23-27; 6:32-37; 6:42-


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50, 55-60; 6:64-7:10; 8:47-57;9:12-19; 9:56 62; 10:3-15; 10:35-47; 11:19-35; 11:59-

60; 11:61-63; 14:60 15:63;

15:64-16:11; 16:47 16:64; 20:19-23; 20:28

31; 23:13-16; 24:57-59; 997 patent, Fig. 16.


for value that is representative of an

amount of time to transpire and value whichis representative of a delay time

Definitions for represent and

transpire in 1988 WebstersDictionary, pp. 1139, 1422.

See delay time




16. variable delay line a circuit or circuit element to providea variable amount of delay

Specification(s)


097 patent, 5:17-19; 18:66; 22:60 23:29;23:40-45; Figs. 12, 13.


for delay locked loop.Expert testimony by Robert Murphy may be




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Barth II Patents

No. Claim Term, Phrase, orClause

Rambuss Preliminary ProposedConstruction

Supporting Evidence

1. after a second/third delaytime has transpired

after a second/third amount of time

has elapsed

Specification(s)


1195 patent, Figs. 1, 9, 16, 20, 21, and 46;

Abstract; 1:31-44; 2:42-45; 9:60-11:28; 10:7-10; 10:48-11:12; 14:34-35

See also evidence related to this term cited by

Rambus in reexaminations familiar to andbrought by or involving NVIDIA related to

the asserted claims of the Barth II patents in

which this term occurs. R20573335-R20744264; R20521849-R20559808.




and/or as set forth in footnote 4.2. memory device / integrated

circuit memory device

a integrated circuit device in which

information can be stored and

retrieved electronically, not including

a memory controller

Specification(s)


119 patent, Abstract; 1:24-2:13; Figs. 1, 2,

10, 16, 20.

Hynix Iand Consolidated Actions Extrinsic

Evidence for memory device.

See also evidence related to this term cited byRambus in reexaminations familiar to and

brought by or involving NVIDIA related to

the asserted claims of the Barth II patents inwhich this term occurs. R20573335-

5 Note: all cites to the Barth II patent specifications are to U.S. Patent No. 7,287,119 (119 patent).


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R20744264; R20521849-R20559808.




3. sense command one or more bits that specify that arow of memory cells be activated

Specification(s)


119 Patent, Figs. 3, 4, 5, 6, and 7; Abstract;2:14-20; 2:49-62; 3:16-18; 12:18-25; 119

patent claim 23; 952 patent claim 25; 953

patent claim 26; 050 patent claim 30; see alsoevidence related to this term cited by Rambus

in reexaminations familiar to and brought by

or involving NVIDIA related to the assertedclaims of the Barth II patents in which this

term occurs. R20573335-R20744264;

R20521849-R20559808.




4. the memory device initiates awrite operation after a firstdelay time transpires

the writing of data is initiated after a

first delay time


all original claims; e.g., 119 Patent, Figs. 1, 9,16, 20, 21, and 46; Abstract; 1:31-44; 2:42-45;

9:60-11:28; 10:7-10; 10:48-11:12; 14:34-35

Definition for delay in American HeritageCollege Dictionary, p.377 (2d ed. 1985); see

also p.366 (3d ed. 2000); see also evidence

related to this term cited by Rambus inreexaminations familiar to and brought by or

involving NVIDIA related to the asserted

claims of the Barth II patents in which thisterm occurs. R20573335-R20744264;


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R20521849-R20559808.




5. the write command ispresented/posted internally

to/within the memory deviceafter a first/second delay

[time] has transpired from

when the write command isreceived

the write command is held and issued

internally after a first/second delay

[time] has transpired from when thewrite command is received


all original claims; e.g., 119 patent, Figs. 1, 9,

16, 20, 21, and 46; Abstract; 1:31-44; 2:42-45;9:60-11:28; 10:7-10; 10:48-11:12; 14:34-35

Definition for delay in American Heritage

College Dictionary, p. 377 (2d ed. 1985); seealso p.366 (3d ed. 2000); see also evidence

related to this term cited by Rambus in

reexaminations familiar to and brought by orinvolving NVIDIA related to the asserted

claims of the Barth II patents in which this

term occurs. R20573335-R20744264;

R20521849-R20559808.



6. write command one or more bits that specify that thememory device receive and store

data

Specification(s) and all original claims; e.g.,119 patent, Figs. 6 and 20; Abstract; 10:58-

66; 9:51-11:53; see also evidence related to

this term cited by Rambus in reexaminationsfamiliar to and brought by or involving

NVIDIA related to the asserted claims of the

Barth II patents in which this term occurs.R20573335-R20744264; R20521849-

R20559808.



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7. delay time an amount of time that must transpirebefore commencing an action Specification(s) and all original claims; e.g.,119 patent, Figs. 1, 9, 16, 20, 21, and 46;Abstract; 1:31-44; 2:42-45; 9:60-11:28; 10:7-

10; 10:48-11:12; 14:34-35; see also evidence

related to this term cited by Rambus in

reexaminations familiar to and brought by orinvolving NVIDIA related to the asserted

claims of the Barth II patents in which this

term occurs. R20573335-R20744264;R20521849-R20559808.





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