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APPENDIX A

Farmwald/Horowitz Patents

No. Claim Term, Phrase,

or Clause

Claims Rambuss Preliminary Proposed

Construction

nVidias Preliminary Proposed

Construction

1. access timeinformation

937/4(1), 5(1)

097/6(1)

information that indicates a time a

device must wait from receiving a

transaction request to responding to atransaction request

information that specifies a

predetermined non-zero amount of time

that a device must wait from receivinga transaction request to responding to a

transaction request

2. delay time 937/31(30)696/27(26),

29(26)

an amount of time that must transpire

before commencing an action

a predetermined non-zero amount of

time that must transpire before

commencing an action.

3. read delay 997/1, 19, 32, 35,38

an amount of time associated with a

read


time that must transpire before data is

read from a memory device.

4. in response to 997/1, 19, 32, 38696/26, 29(26),

30(26)

281/36, 42(36),

43(36)

097/1, 5(1), 26

937/1, 3(1), 4(1),5(1), 18, 23(18),

24(18), 37(30)

020/2(1), 32(28),

34(28), 37(28), 38

as a result of plain meaning.

5. information thatrepresents an amount

937/32(30) information that indicates an amount of

time which lapses

information that indicates a


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or Clause


Construction


Construction

of time which lapses that must lapse.6. latch circuitry 937/19(18) a circuit or circuit element to capture

and maintain a signal valuecircuitry for maintaining a particularstate of a signal until being reset.

7. latch 937/19(18) to capture and maintain a signal value maintaining a particular state of asignal until being reset as distinguished

from sampling

8. memory controller /controller device /

memory controllerdevice

997/1, 3(1), 19,

26(19), 31(19),

32, 38

696/26

937/18, 19(18),22(18), 23(18),

24(18), 26(18),

29(18), 30, 31(30)

020/1, 2(1), 10(1),11(1), 12(1),

13(1), 14(1), 38,

47(38), 49(38)

an integrated circuit device that

includes circuitry to direct the actions

of one or more memory devices

a device that includes circuitry to direct

the actions of one or more memory

devices

9. integrated circuitcontroller device

020/38 no separate construction required a controller device constructed on a

single monolithic substrate, commonlycalled a chip

10.

memory device 937/2(1), 4(1),5(1), 8(1), 18,

23(18), 24(18),30, 32(30), 36(30)37(30), 38(30),

097/1, 5(1), 6(1),

26

281/36, 38(36),

an integrated circuit device in whichinformation can be stored and retrieved

electronically, not including a memorycontroller

A device in which data can be storedand retrieved electronically.


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or Clause


Construction


Construction

39(36), 40(36),42(36), 43(36),44(36), 45(36),

46(36)

696/26, 27(26),

28(26), 29(26),30(26), 31(26),

997/1, 19,26(19),32, 38

020/1, 2(1), 28,

29(28), 32(28),34(28), 35(28),

37(28), 38, 49(38)

11. operation code 937/1, 3(1), 4(1),5(1), 14(1), 15(1),17(1), 18, 23(18),

24(18), 29(18),30, 37(30)

020/2(1), 32(28),

34(28), 37(28), 38

696/26, 29(26),

30(26), 35(26)

997/1, 2(1), 3(1),

19, 26(19),

31(19), 32(19), 38

one or more bits to specify a type of

action

One or more control bits specifying a

type of action to be performed by amemory device.

12. precharge information 937/17(1)696/35(26),

one or more bits indicating whether the

sense amplifiers and/or bit lines(or a

portion of the sense amplifiers and/or

Information denoting whether sense

amplifiers and/or bit lines (or a portion

of the sense amplifiers and/or bit lines)


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or Clause


Construction


Construction

997/19, 32(30) bit lines) should be precharged should be precharged.

13. programmableregister

696/26 a register whose contents can be

modified based on informationreceived from an external source

A register within a memory device that

is permanently or semi-permanentlyloaded with a fixed value.

14. representative of anumber of clock

cycles of the external

clock signal totranspire

696/28(26)

937/5(1)

indicates a number of clock cycles ofthe external clock to occur

indicates a number of clock cycles ofthe external clock signal that must

transpire before commencing an action.

15. sample / samples /sampling

997/1, 19, 32, 38

696/27(26),28(26)

097/1, 26

937/1, 18, 23(18),

26(18)

020/14(1), 17,25(17), 29(28),

30(28), 34(28),

49(38)

to obtain at a discrete point in time /obtains at discrete points in time /

obtaining at discrete points in time

obtain/ obtains/ obtaining at one ormore discrete points in time, as

distinguished from latch/ latches/

latching.

16. value is representativeof a delay time to

transpire

696/27(26),

29(26)

information that indicates a delay time

to occur

information that indicates a


that must transpire before commencingan action.

17. variable delay line 020/11(1), 12(1) a circuit or circuit element to provide avariable amount of delay

a delay line that uses feedback toprovide a varying amount of the delay.


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Barth II Patents

No. Claim Term, Phrase,or Clause

Claims Rambuss Preliminary ProposedConstruction

nVidias Preliminary ProposedConstruction

1. after a second/thirddelay time has

transpired

119/21

952/21

953/25

after a second/third amount of time

has elapsed

After an additional second/third

predetermined non-zero amount of

time has transpired.

2. memory device 050/29119/21

952/21, 22(21)

953/25

a integrated circuit device in which

information can be stored andretrieved electronically, not including

a memory controller

A device in which data can be stored

and retrieved electronically.

3. integrated circuitmemory device

050/29

119/21

952/21, 22(21)

no separate construction required a memory device constructed on a

single, monolithic substrate,

commonly called a chip

4. sense command 050/29119/21

952/21

953/25

one or more bits that specify that arow of memory cells be activated

Signals provided to a memory devicefor initiating a sense operation within

the memory device.

5. the memory deviceinitiates a writeoperation after a first

delay time transpires

953/25 the writing of data is initiated after a

first delay time

The memory device begins to perform

a write operation only after a firstpredetermined non-zero amount of

time transpires.


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6. the write command ispresented/posted

internally to/within thememory device after a

first/second delay

[time] has transpiredfrom when the write

command is received

050/29

119/21

952/21

the write command is held and issued

internally after a first/second delay

[time] has transpired from when thewrite command is received

The write command is provided to a

memory core of a memory device only

after a first/second predetermined non-zero amount of time has transpired

from when the write command is

received by the memory device.

7. write command 050/29119/21952/21

953/25

one or more bits that specify that the

memory device receive and store data

Signals provided to a memory device

for initiating a write operation within a

memory device.

8. delay time 119/21952/21

953/25

an amount of time that must transpire

before commencing an action


time that must transpire before

commencing an action.


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