26.8: A 1.9GHz Single-Chip CMOS PHS Cellphone

William W. Si, Srenik Mehta, Hirad Samavati, Manolis Terrovitis, Michael Mack, Keith Onodera,

Steve Jen, Susan Luschas, Justin Hwang, Suni Mendis, David Su, Bruce Wooley1

Atheros Communications, Santa Clara, California1 Stanford University, Stanford, California

n Introduction

n Overall Architecture

n RF Transceiver

• Synthesizer

• Receiver

• Transmitter

n Calibration

n Measurement Results

Outline

Integrated PHS SoC Solution

n Personal Handy-Phone System (PHS)

• Commercially launched in 1995• Resurgence in China (> 50M subscribers in 2004)

n Single-Chip PHS Solution in 0.18µm CMOS

• RF/Analog: RF transceiver, audio/voiceband data converters and audio amplifiers

• Digital: PHS MODEM, TDMA, CPU, Voice subsystem, Interfaces

n PHS System• TDMA/TDD - Time Domain Multiple Access / Duplexing• π/4 QPSK modulation with 192kHz channel bandwidth• 1.9GHz frequency band, 300kHz channel spacing• Support seamless handover → fast channel switching

Advantages of System-on-Chip

n Low cost, small form factor with fewer external components

n Digital calibration

• Wide digital-analog interface without package pins and associated power for I/Os

• Digital calibration to repair analog impairments, eases requirements of analog RF circuits

SoC

Block Diagram of Single-Chip PHS Cellphone

PHS RFTransceiver

PHSMODEM

PHSTDMA

MicrophoneEarpieceSpeaker

LCD

LED

Keypad

WLAN

SRAM

Flash

Display

VoiceSubsystemCPU

Interfaces

PowerMgmt

AudioAmplifiers

Data-Converters

Receiver

Synthesizer

Channel FrequencyDAC

LO

PAXPA

÷2

RF Transceiver Block Diagram

I

Q

DAC

÷2LO

ADC

ADC

I

Q

3.8GHz Fractional-NSigma Delta

Transmitter

RF Loop back fvco = 2 x frfn weaker PA pullingn smaller inductorn easy quad. LO gen

Sigma-Delta Fractional-N Synthesizer

2×fRF

38.4MHz crystal / TCXO

P/SCounter Prescaler

8/9

Channel Frequency

VCODetectorPhase

PumpCharge

FilterLoop

Retiming

Σ∆ Modulator

3.8GHz

Total current = 25mA

3

Voltage Controlled Oscillator

Vc

Regulated VDD (1.8V)

CMetal

7-bitcontrol

CMetal

Fast Synthesizer Settling (I)n Seamless handover support → requires fast

channel switching

n Traditional approach: Use two interleaving synthesizers → power and area penalty

nWe use only one synthesizer with fast settling

time slot 1 time slot 2 time slot 3

Ch. 1 Ch. 2

Time for synthesizer settling

Talking Scan other cell station channels ...

Ch. 3

Synth 2LO

output slot 1

Synth 1 Synth 2 Synth 1

slot 2 slot 3Ch. 1 Ch. 2 Ch. 3

Synth 1

...

n Tradeoff between settling time and phase noise: Loop bandwidth optimization• Wide loop BW for fast settling• Low loop BW to suppress Σ∆ quantization noise• Optimized loop BW = 120kHz

n Avoid over-design → Minimizing loop BW variation• BW = (Kvco Icp Rs) / (2πN)• Vctrl within 200mV → Kvco is roughly constant • Icp tracks process variation of Rs → IcpRs constant

n Loop BW dynamically adjusted during switching to speed up frequency transient response

n Resulting settling time = 15µs

Fast Synthesizer Settling (II)

ADC

ADC

LNA RFVGA1 Q

DAC

Q Offset

Control

DAC Control

I Offset

I

2×LORF

1

RFVGA2

Envelope Detection for AGC

RF in1

÷ 2

LORF (I)

LORF (Q)

Direct Conversion Receiver

RF loopback from TX

Total current = 32mA

LOin+

LORF-

Common-ModeFeedback and

+

-

+

_ LOin-

LORF+

BB-Replica Bias

Two-StageInductorlessLO Buffer

Passive I/Q MixerUsing NMOS Native Devices

RF-

RF+ BB+

VDD/2

_

+

VDD/2

Receive Mixer and LO Buffers

M0

M1

M2

M3

M4OP1

OP0

Direct Conversion Transmitter

DAC

DAC

9

9

RFVGA PA XPA

RF Loopback

2×LORF ÷ 2

LORF(I)

LORF(Q)

RF out

Q

I

to RX

Total current = 29mA

PGA

Vin+ Vin-

Vdd

Vin+ Vin-

Vout-Vout+

b1 b4

Segmented Power Amplifier

...

M1 M2 M3 M4

M5 M6 M7 M8

SW1 SW4

...

Vdd

Digital Calibration and RF Loopback

DAC

LORF

ADC1

LORF DAC

9MODEM

SW0

RF in

RF outTXBB

RXBB

n Calibration of Analog Imperfections• Receiver filter bandwidth• Receiver DC offset• I/Q mismatch• Transmitter carrier leak

-120

-115

-110

-105

-100

-95

-90

-85

-80

1895 1898 1901 1904 1907 1910 1913 1916 1919

Channel Frequency (MHz)

Sen

siti

vity

(dB

m)

Receiver Noise Figure = 3.5dB

Sensitivity = -106dBm9dB

PHS Sensitivity Standard

Receiver Sensitivity

35

40

45

50

55

1895 1898 1901 1904 1907 1910 1913 1916 1919

Ad

jace

nt

Ch

ann

el S

elec

tivi

ty (

dB

c) Receiver Adjacent Channel Selectivity (ACS)

600kHz

PHS Signal-94dBm

PHS Blocker

ACS

PHS modulated blocker at 600kHzoffset

Channel Frequency (MHz)

ACS Spec = 50dBc

Adj. Ch. Selectivity (PHS modulated blocker at 600kHz offset)

35

40

45

50

55

1895 1898 1901 1904 1907 1910 1913 1916 1919

Inte

rmo

du

latio

n (

dB

c)

Receiver 2-Tone Intermodulation

600kHz

PHS Signal-94dBm

Blockers

1200kHz

Intermod

2 equal sizedsingle-tone blockersat 600kHz &1.2MHz

Channel Frequency (MHz)

Intermod Spec = 47dBc

offset

Transmit Spectrum

Log10dB/

Center 1.907GHzRes BW 10kHz

Span 2MHz

Measured OBW < 250kHz for all channels

PHS standard requires OBW < 288kHzOBW = Occupied BW containing 99% signal power

Ref -10dBm

Transmitter Modulation Accuracy

II

Q Q

Frequency: 1 906.847 373 1 MHzFrequency Error: -2.626 9 kHzRMS Vector Error: 3.80%Peak Vector Error: 7.82%Output Power: 0dBm

Frequency: 1 906.847 366 4 MHzFrequency Error: -2.633 6 kHzRMS Vector Error: 1.03%Peak Vector Error: 2.50%Output Power: -10dBm

PHS Standard requires EVM less than 12.5%

Transmit Adjacent Channel Power (ACP)

-48

-46

-44

-42

-40

-38

-36

-34

-32

-30

-28

1895 1898 1901 1904 1907 1910 1913 1916 1919

Channel Frequency (MHz)

Ad

jace

nt

Ch

ann

el P

ow

er (

dB

m)

Spec

600kHz ACP

Spec

900kHz ACP

600kHz

ACP

PHS signal 18.5dBm with xPA

>8dB Margin

8dB Margin

-140

-130

-120

-110

-100

-90

-80

0.01 0.1 1 10

Frequency Offset (MHz)

Pha

se N

oise

(dB

c/H

z)Synthesizer Phase Noise at 1895.15MHz

Phase Noise @ 600kHz = -118dBc/Hz

1.0E+00

1.0E+01

1.0E+02

1.0E+03

1.0E+04

1.0E+05

1.0E+06

1.0E+07

0 5 10 15 20 25 30 35 40

Time (us)

Fre

qu

ency

Off

set

(Hz)

Measured Synthesizer Settling Time

Settling Time to 1 kHz = 15µs

1k

10k

100k

1M

10M

100

10

1

Time (µs)

Die Micrograph

TX

RXSYNTH

BIAS

AUDIO

Performance SummaryPower Dissipation

RF TransmitterRF Receiver

RF Synthesizer Talk Mode (1/8 duty cycle Tx & Rx) Standby Mode

29mA32mA25mA81mA (including audio and digital) 1mA (including audio and digital)

Phase Noise @ 1.9GHz -118dBc/Hz @ 600kHz offset

Settling time to +/- 1kHz 15µs

Receive Sensitivity -106dBm

Receiver Noise Figure 3.5dB

Transmit Power (EVM compliant) +4 dBm

Transmit EVM 4% rms @ 1dBm1% rms @ -10dBm

Technology Standard 0.18µm CMOS

Supply Voltage 3.0V with internally regulated 1.8V

Die Size: Total

RF and Analog33 mm2

12 mm2

Package 276-pin BGA

n Demonstrated single-chip PHS cellphone in 0.18 µm standard digital CMOS

n SoC performance meets or exceeds all PHS specifications

n System on a single chip allows for digital calibration to ease requirements of analog circuits

Conclusions

The authors wish to acknowledge the

contributions from the entire PHS team at

Atheros, especially their efforts in algorithm

development, digital design, and system

design and verification

Acknowledgments