PIC16F87XA Data Sheet 28/40/44-Pin Enhanced Flash Microcontrollers 2003 Microchip Technology Inc. DS39582B

Note the following details of the code protection feature on Microchip devices: Microchip products meet the specification contained in their particular Micr ochip Data Sheet. Microchip believes that its family of products is one of the m ost secure families of its kind on the market today, when used in the intended m anner and under normal conditions. There are dishonest and possibly illegal meth ods used to breach the code protection feature. All of these methods, to our kno wledge, require using the Microchip products in a manner outside the operating s pecifications contained in Microchip's Data Sheets. Most likely, the person doin g so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Mi crochip nor any other semiconductor manufacturer can guarantee the security of t heir code. Code protection does not mean that we are guaranteeing the product as unbreakable. Code protection is constantly evolving. We at Microchip are committed to continu ously improving the code protection features of our products. Attempts to break microchips code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specificati ons. No representation or warranty is given and no liability is assumed by Micro chip Technology Incorporated with respect to the accuracy or use of such informa tion, or infringement of patents or other intellectual property rights arising f rom such use or otherwise. Use of Microchips products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellec tual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEEL OQ, MPLAB, PIC, PICmicro, PICSTART, PRO MATE and PowerSmart are registered trade marks of Microchip Technology Incorporated in the U.S.A. and other countries. Am pLab, FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL and The Embedded Contr ol Solutions Company are registered trademarks of Microchip Technology Incorpora ted in the U.S.A. Application Maestro, dsPICDEM, dsPICDEM.net, ECAN, ECONOMONITO R, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, mic roPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.n et, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPIC, Select Mode, SmartS ensor, SmartShunt, SmartTel and Total Endurance are trademarks of Microchip Tech nology Incorporated in the U.S.A. and other countries. Serialized Quick Turn Pro gramming (SQTP) is a service mark of Microchip Technology Incorporated in the U. S.A. All other trademarks mentioned herein are property of their respective comp anies. 2003, Microchip Technology Incorporated, Printed in the U.S.A., All Rig hts Reserved. Printed on recycled paper. Microchip received QS-9000 quality system certification for its worldwide headqu arters, design and wafer fabrication facilities in Chandler and Tempe, Arizona i n July 1999 and Mountain View, California in March 2002. The Companys quality s ystem processes and procedures are QS-9000 compliant for its PICmicro 8-bit MCU s, KEELOQ code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchips quality system for the desi gn and manufacture of development systems is ISO 9001 certified. DS39582B-page ii

2003 Microchip Technology Inc.

PIC16F87XA 28/40/44-Pin Enhanced Flash Microcontrollers Devices Included in this Data Sheet: PIC16F873A PIC16F874A PIC16F876A PIC16F877A Analog Features: 10-bit, up to 8-channel Analog-to-Digital Converter (A/D) Brown-out Reset (B OR) Analog Comparator module with: - Two analog comparators - Programmable onchip voltage reference (VREF) module - Programmable input multiplexing from devi ce inputs and internal voltage reference - Comparator outputs are externally acc essible High-Performance RISC CPU: Only 35 single-word instructions to learn All single-cycle instructions exce pt for program branches, which are two-cycle Operating speed: DC 20 MHz cloc k input DC 200 ns instruction cycle Up to 8K x 14 words of Flash Program Mem ory, Up to 368 x 8 bytes of Data Memory (RAM), Up to 256 x 8 bytes of EEPROM Dat a Memory Pinout compatible to other 28-pin or 40/44-pin PIC16CXXX and PIC16FXX X microcontrollers Special Microcontroller Features: 100,000 erase/write cycle Enhanced Flash program memory typical 1,000,000 er ase/write cycle Data EEPROM memory typical Data EEPROM Retention > 40 years Self-reprogrammable under software control In-Circuit Serial Programming (ICS P) via two pins Single-supply 5V In-Circuit Serial Programming Watchdog Tim er (WDT) with its own on-chip RC oscillator for reliable operation Programmabl e code protection Power saving Sleep mode Selectable oscillator options In -Circuit Debug (ICD) via two pins Peripheral Features: Timer0: 8-bit timer/counter with 8-bit prescaler Timer1: 16-bit timer/counte r with prescaler, can be incremented during Sleep via external crystal/clock T imer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler Two Capture, Compare, PWM modules - Capture is 16-bit, max. resolution is 12.5 ns - Compare is 16-bit, max. resolution is 200 ns - PWM max. resolution is 10-b it Synchronous Serial Port (SSP) with SPI (Master mode) and I2C (Master/Slav e) Universal Synchronous Asynchronous Receiver Transmitter (USART/SCI) with 9bit address detection Parallel Slave Port (PSP) 8 bits wide with external RD , WR and CS controls (40/44-pin only) Brown-out detection circuitry for Brownout Reset (BOR) CMOS Technology: Low-power, high-speed Flash/EEPROM technology Fully static design Wide ope rating voltage range (2.0V to 5.5V) Commercial and Industrial temperature rang es Low-power consumption Device MSSP Data EEPROM 10-bit CCP Timers SRAM I/O USART Comparators # Single Word (Byt es) A/D (ch) (PWM) SPI Master 8/16-bit Bytes (Bytes) Instructions I2C 7.2K 7.2K 4096 4096 8192 8192 192 192 368 368 128 128 256 256 22 33 22 33 5 8 5 8 2 2 2 2 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 2/1 2/1 2/1 2/1 2 2 2 2 Program Memory PIC16F873A PIC16F874A PIC16F876A 14.3K PIC16F877A 14.3K 2003 Microchip Technology Inc.

DS39582B-page 1

PIC16F87XA Pin Diagrams 28-Pin PDIP, SOIC, SSOP MCLR/VPP RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ RA4/T0CKI/C1OUT RA5/A N4/SS/C2OUT VSS OSC1/CLKI OSC2/CLKO RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/ SCK/SCL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RB7/PGD RB6/PGC RB5 RB4 RB3/PGM RB2 RB1 RB0/INT VDD VSS RC7/RX/DT RC6/TX/CK R C5/SDO RC4/SDI/SDA PIC16F873A/876A 28-Pin QFN RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ RA4/T0CKI/C1OUT RA5/AN4/SS/C2OUT VSS OSC1/CLKI OSC2/CLKO 1 2 3 4 5 6 7 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RA1/AN1 RA0/AN0 MCLR/VPP RB7/PGD RB6/PGC RB5 RB4 PIC16F873A PIC16F876A 44-Pin QFN 44 43 42 41 40 39 38 37 36 35 34 RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 RD1/PSP1 RD0/PSP0 RC3/SCK/SCL RC 2/CCP1 RC1/T1OSI/CCP2 RC0/T1OSO/T1CKI RB3/PGM NC RB4 RB5 RB6/PGC RB7/PGD MCLR/VPP RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ 12 13 14 15 16 17 18 19 20 21 22 RC7/RX/DT RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7 VSS VDD VDD RB0/INT RB1 RB2 1 2 3 4 5 6 7 8 9 10 11 PIC16F874A PIC16F877A 33 32 31 30 29 28 27 26 25 24 23 OSC2/CLKO OSC1/CLKI VSS VSS VDD VDD RE2/CS/AN7 RE1/WR/AN6 RE0/RD/AN5 RA5/AN4/SS/ C2OUT RA4/T0CKI/C1OUT DS39582B-page 2 RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/C K 8 9 10 11 12 13 14 RB3/PGM RB2 RB1 RB0/INT VDD VSS RC7/RX/DT 2003 Microchip Technology Inc.

PIC16F87XA Pin Diagrams (Continued) 40-Pin PDIP MCLR/VPP RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ RA4/T0CKI/C1OUT RA5/A N4/SS/C2OUT RE0/RD/AN5 RE1/WR/AN6 RE2/CS/AN7 VDD VSS OSC1/CLKI OSC2/CLKO RC0/T1O SO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RD0/PSP0 RD1/PSP1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 2 5 24 23 22 21 RB7/PGD RB6/PGC RB5 RB4 RB3/PGM RB2 RB1 RB0/INT VDD VSS RD7/PSP7 R D6/PSP6 RD5/PSP5 RD4/PSP4 RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/P SP2 PIC16F874A/877A 44-Pin PLCC RA4/T0CKI/C1OUT RA5/AN4/SS/C2OUT RE0/RD/AN5 RE1/WR/AN6 RE2/CS/AN7 VDD VSS OSC1/C LKI OSC2/CLKO RC0/T1OSO/T1CK1 NC RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 RD1/PSP1 RD0/PSP0 RC3/SCK/SCL RC2/CCP1 RC1/T1OSI/CCP2 NC 6 5 4 3 2 1 44 43 42 4 1 40 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 9 RB3/PGM RB2 R B1 RB0/INT VDD VSS RD7/PSP7 RD6/PSP6 RD5/PSP5 RD4/PSP4 RC7/RX/DT 44-Pin TQFP 44 43 42 41 40 39 38 37 36 35 34 2003 Microchip Technology Inc. NC NC RB4 RB5 RB6/PGC RB7/PGD MCLR/VPP RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF RA3/A N3/VREF+ 12 13 14 15 16 17 18 19 20 21 22 RC7/RX/DT RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7 VSS VDD RB0/INT RB1 RB2 RB3/PGM 1 2 3 4 5 6 7 8 9 10 11 PIC16F874A PIC16F877A 33 32 31 30 29 28 27 26 25 24 23 NC RC0/T1OSO/T1CKI OSC2/CLKO OSC1/CLKI VSS VDD RE2/CS/AN7 RE1/WR/AN6 RE0/RD/AN5 RA5/AN4/SS/C2OUT RA4/T0CKI/C1OUT RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RD0/PSP0 RD1/PSP1 RD2/PSP2 RD3/PSP3 RC4/SDI/ SDA RC5/SDO RC6/TX/CK NC 18 19 20 21 22 23 24 25 26 27 282 RA3/AN3/VREF+ RA2/AN2/VREF-/CVREF RA1/AN1 RA0/AN0 MCLR/VPP NC RB7/PGD RB6/PGC RB 5 RB4 NC PIC16F874A PIC16F877A DS39582B-page 3

PIC16F87XA Table of Contents 1.0 Device Overview ............................................................ ................................................................................ ............................. 5 2.0 Memory Organization......................... ................................................................................ ....................................................... 15 3.0 Data EEPROM and F lash Program Memory ............................................................ ................................................................ 33 4.0 I/O Port s............................................................................... ................................................................................ ..................... 41 5.0 Timer0 Module ..................................... ................................................................................ ..................................................... 53 6.0 Timer1 Module ..... ................................................................................ ................................................................................ ..... 57 7.0 Timer2 Module ..................................................... ................................................................................ ..................................... 61 8.0 Capture/Compare/PWM Modules ....... ................................................................................ ...................................................... 63 9.0 Master Synchronous Serial Port (MSSP) Module...................................................... ............................................................... 71 10.0 Addressa ble Universal Synchronous Asynchronous Receiver Transmitter (USART) ............ ................................................ 111 11.0 Analog-to-Digital Conv erter (A/D) Module ............................................................. ................................................................. 127 12.0 Compa rator Module ................................................................... ................................................................................ ............. 135 13.0 Comparator Voltage Reference Module ..................... ................................................................................ ............................ 141 14.0 Special Features of the CPU .............. ................................................................................ .................................................... 143 15.0 Instruction Set Su mmary........................................................................... .............................................................................. 1 59 16.0 Development Support .................................................... ................................................................................ ......................... 167 17.0 Electrical Characteristics................... ................................................................................ ...................................................... 173 18.0 DC and AC Charac teristics Graphs and Tables .................................................... ................................................................. 197 19.0 Packa ging Information ............................................................... ................................................................................ ............. 209 Appendix A: Revision History ................................. ................................................................................ ........................................... 219 Appendix B: Device Differences.. ................................................................................ ...................................................................... 219 Appen dix C: Conversion Considerations................................................ ................................................................................ ........... 220 Index .......................................................... ................................................................................ ....................................................... 221 On-Line Support..... ................................................................................ ................................................................................ ........... 229 Systems Information and Upgrade Hot Line ....................... ................................................................................ .............................. 229 Reader Response .............................

................................................................................ ................................................................ 230 PIC16F87XA Product Identification System................................................... ................................................................................ ... 231 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we wi ll continue to improve our publications to better suit your needs. Our publicati ons will be refined and enhanced as new volumes and updates are introduced. If y ou have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@mail.microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150 . We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version o f a data sheet by examining its literature number found on the bottom outside co rner of any page. The last character of the literature number is the version num ber, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet an d recommended workarounds, may exist for current devices. As device/documentatio n issues become known to us, we will publish an errata sheet. The errata will sp ecify the revision of silicon and revision of document to which it applies. To d etermine if an errata sheet exists for a particular device, please check with on e of the following: Microchips Worldwide Web site; http://www.microchip.com Your local Microchi p sales office (see last page) The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277 When contacting a sales office or the literature center, please specify which de vice, revision of silicon and data sheet (include literature number) you are usi ng. Customer Notification System Register on our Web site at www.microchip.com/cn to receive the most current inf ormation on all of our products. DS39582B-page 4 2003 Microchip Technology Inc.

PIC16F87XA 1.0 DEVICE OVERVIEW This document contains device specific information about the following devices: PIC16F873A PIC16F874A PIC16F876A PIC16F877A The available features are s ummarized in Table 1-1. Block diagrams of the PIC16F873A/876A and PIC16F874A/877 A devices are provided in Figure 1-1 and Figure 1-2, respectively. The pinouts f or these device families are listed in Table 1-2 and Table 1-3. Additional infor mation may be found in the PICmicro Mid-Range Reference Manual (DS33023), which may be obtained from your local Microchip Sales Representative or downloaded fr om the Microchip web site. The Reference Manual should be considered a complemen tary document to this data sheet and is highly recommended reading for a better understanding of the device architecture and operation of the peripheral modules . PIC16F873A/876A devices are available only in 28-pin packages, while PIC16F874A/ 877A devices are available in 40-pin and 44-pin packages. All devices in the PIC 16F87XA family share common architecture with the following differences: The P IC16F873A and PIC16F874A have one-half of the total on-chip memory of the PIC16F 876A and PIC16F877A The 28-pin devices have three I/O ports, while the 40/44-p in devices have five The 28-pin devices have fourteen interrupts, while the 40 /44-pin devices have fifteen The 28-pin devices have five A/D input channels, while the 40/44-pin devices have eight The Parallel Slave Port is implemented only on the 40/44-pin devices TABLE 1-1: PIC16F87XA DEVICE FEATURES PIC16F873A DC 20 MHz POR, BOR (PWRT, OST) 4K 192 128 14 Ports A, B, C 3 2 MSSP , USART 5 input channels 2 35 Instructions 28-pin PDIP 28-pin SOIC 28-pin SSOP 28-pin QFN PIC16F874A DC 20 MHz POR, BOR (PWRT, OST) 4K 192 128 15 Ports A, B , C, D, E 3 2 MSSP, USART PSP 8 input channels 2 35 Instructions 40-pin PDIP 44pin PLCC 44-pin TQFP 44-pin QFN PIC16F876A DC 20 MHz POR, BOR (PWRT, OST) 8K 3 68 256 14 Ports A, B, C 3 2 MSSP, USART 5 input channels 2 35 Instructions 28pin PDIP 28-pin SOIC 28-pin SSOP 28-pin QFN PIC16F877A DC 20 MHz POR, BOR (PWR T, OST) 8K 368 256 15 Ports A, B, C, D, E 3 2 MSSP, USART PSP 8 input channels 2 35 Instructions 40-pin PDIP 44-pin PLCC 44-pin TQFP 44-pin QFN Key Features Operating Frequency Resets (and Delays) Flash Program Memory (14-bi t words) Data Memory (bytes) EEPROM Data Memory (bytes) Interrupts I/O Ports Tim ers Capture/Compare/PWM modules Serial Communications Parallel Communications 10 -bit Analog-to-Digital Module Analog Comparators Instruction Set Packages 2003 Microchip Technology Inc. DS39582B-page 5

PIC16F87XA FIGURE 1-1: PIC16F873A/876A BLOCK DIAGRAM 13 Program Counter Flash Program Memory Data Bus 8 PORTA RA0/AN0 RA1/AN1 RA2/AN2 /VREF-/CVREF RA3/AN3/VREF+ RA4/T0CKI/C1OUT RA5/AN4/SS/C2OUT 8 Level Stack (13-bit) RAM File Registers RAM Addr(1) 9 Program Bus 14 Instruction reg Direct Addr 7 Addr MUX 8 Indirect Addr PORTB RB0/INT RB1 RB2 RB3/PGM RB4 RB5 RB6/PGC RB7/PGD FSR reg Status reg 8 3 Power-up Timer Instruction Decode & Control Timing Generation OSC1/CLKI OSC2/CLK O Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset In-Cir cuit Debugger Low-Voltage Programming 8 MUX ALU PORTC W reg RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT MCLR VDD, VSS Timer0 Timer1 Timer2 10-bit A/D Data EEPROM CCP1,2 Synchronous Serial Port USART Comparator Voltage Reference Device PIC16F873A PIC16F876A Program Flash 4K words 8K words Data Memory 192 Bytes 368 Bytes Data EEPROM 128 Bytes 256 Bytes Note 1: Higher order bits are from the Status register.

DS39582B-page 6 2003 Microchip Technology Inc.

PIC16F87XA FIGURE 1-2: PIC16F874A/877A BLOCK DIAGRAM 13 Program Counter Flash Program Memory Data Bus 8 PORTA RA0/AN0 RA1/AN1 RA2/AN2 /VREF-/CVREF RA3/AN3/VREF+ RA4/T0CKI/C1OUT RA5/AN4/SS/C2OUT PORTB RB0/INT RB1 RB 2 RB3/PGM RB4 RB5 RB6/PGC RB7/PGD PORTC Power-up Timer Instruction Decode & Cont rol Timing Generation OSC1/CLKI OSC2/CLKO Oscillator Start-up Timer Power-on Res et Watchdog Timer Brown-out Reset In-Circuit Debugger Low-Voltage Programming 8 W reg PORTD RD0/PSP0 RD1/PSP1 RD2/PSP2 RD3/PSP3 RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/P SP7 PORTE MCLR VDD, VSS RE0/RD/AN5 RE1/WR/AN6 RE2/CS/AN7 3 MUX RC0/T1OSO/T1CKI R C1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT 8 Level Stack (13-bit) RAM File Registers RAM Addr(1) 9 Program Bus 14 Instruction reg Direct Addr 7 Addr MUX 8 Indirect Addr FSR reg Status reg 8 ALU Timer0 Timer1 Timer2 10-bit A/D Parallel Slave Port Data EEPROM CCP1,2 Synchronous Serial Port USART Comparator Voltage Reference Device PIC16F874A PIC16F877A Program Flash 4K words 8K words Data Memory 192 Bytes 368 Bytes Data EEPROM 128 Bytes 256 Bytes Note 1: Higher order bits are from the Status register. 2003 Microchip Technology Inc. DS39582B-page 7

PIC16F87XA TABLE 1-2: Pin Name OSC1/CLKI OSC1 CLKI OSC2/CLKO OSC2 CLKO MCLR/VPP MCLR VPP RA0/AN0 RA0 A N0 RA1/AN1 RA1 AN1 RA2/AN2/VREF-/ CVREF RA2 AN2 VREFCVREF RA3/AN3/VREF+ RA3 AN3 VREF+ RA4/T0CKI/C1OUT RA4 T0CKI C1OUT RA5/AN4/SS/C2OUT RA5 AN4 SS C2OUT Legend: Note 1: 2: 3: 2 27 I/O I 3 28 I/O I 4 1 I/O I I O 5 2 I/O I I 6 3 I/O I O 7 4 I/ O I I O TTL Digital I/O. Analog input 4. SPI slave select input. Comparator 2 ou tput. ST Digital I/O Open-drain when configured as output. Timer0 external clo ck input. Comparator 1 output. TTL Digital I/O. Analog input 3. A/D reference vo ltage (High) input. TTL Digital I/O. Analog input 2. A/D reference voltage (Low) input. Comparator VREF output. TTL Digital I/O. Analog input 1. 1 26 I P TTL Di gital I/O. Analog input 0. 10 7 O O ST PIC16F873A/876A PINOUT DESCRIPTION PDIP, SOIC, SSOP Pin# 9 QFN Pin# 6 I I I/O/P Type Buffer Type Description ST/CMOS(3) Oscillator crystal or external clock input. Oscillator crystal input or external clock source input. ST buffer when configured in RC mode; otherwise CMOS. External clock source input. Always associated with pin function OSC1 (see OSC1/CLKI, OSC2/CLKO pins). Oscillator crystal or clock output. Oscillator cr ystal output. Connects to crystal or resonator in Crystal Oscillator mode. In RC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes th e instruction cycle rate. Master Clear (input) or programming voltage (output). Master Clear (Reset) input. This pin is an active low Reset to the device. Progr amming voltage input. PORTA is a bidirectional I/O port. I = input O = output I/O = input/output P = power = Not used TTL = TTL input S T = Schmitt Trigger input This buffer is a Schmitt Trigger input when configured as the external interrupt. This buffer is a Schmitt Trigger input when used in Serial Programming mode. This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise. DS39582B-page 8 2003 Microchip Technology Inc.

PIC16F87XA TABLE 1-2: Pin Name PIC16F873A/876A PINOUT DESCRIPTION (CONTINUED) PDIP, SOIC, SSOP Pin# QFN Pin# I/O/P Type Buffer Type Description PORTB is a bid irectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/INT RB0 INT RB1 RB2 RB3/PGM RB3 PGM RB4 RB5 RB6/PGC RB6 PGC RB7/PGD RB7 PGD RC0/T1OSO/T1CKI RC0 T1OSO T1CKI RC1/T1OSI/CCP2 RC1 T1OSI CCP2 RC2/CCP1 RC2 CCP1 RC3/SCK/SCL RC3 SCK SCL RC4/SDI/SDA RC4 SDI SDA RC5/SDO RC5 SDO RC6/TX/CK RC6 TX CK RC7/RX/DT RC7 RX DT VSS VDD Legend: Note 1: 2: 3: 21 18 I/O I TTL/ST(1) Digital I/O. External interrupt. TTL TTL TTL I/O I Digital I/O. Low-vo ltage (single-supply) ICSP programming enable pin. TTL TTL TTL/ST(2) I/O I Digit al I/O. In-circuit debugger and ICSP programming clock. TTL/ST(2) I/O I/O Digita l I/O. In-circuit debugger and ICSP programming data. PORTC is a bidirectional I /O port. ST I/O O I Digital I/O. Timer1 oscillator output. Timer1 external clock input. ST I/O I I/O Digital I/O. Timer1 oscillator input. Capture2 input, Compa re2 output, PWM2 output. ST I/O I/O Digital I/O. Capture1 input, Compare1 output , PWM1 output. ST I/O I/O I/O Digital I/O. Synchronous serial clock input/output for SPI mode. Synchronous serial clock input/output for I2C mode. ST I/O I I/O Digital I/O. SPI data in. I2C data I/O. ST I/O O Digital I/O. SPI data out. ST I /O O I/O Digital I/O. USART asynchronous transmit. USART1 synchronous clock. ST I/O I I/O Digital I/O. USART asynchronous receive. USART synchronous data. G round reference for logic and I/O pins. Positive supply for logic and I/O pins. Digital I/O. Digital I/O. Digital I/O. Digital I/O. 22 23 24 19 20 21 I/O I/O 25 26 27 22 23 24 I/O I/O 28 25 11 8 12 9 13 10

14 11 15 12 16 13 17 14 18 15 8, 19 20 5, 6 17 P P I = input O = output I/O = input/output P = power = Not used TTL = TTL input S T = Schmitt Trigger input This buffer is a Schmitt Trigger input when configured as the external interrupt. This buffer is a Schmitt Trigger input when used in Serial Programming mode. This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise. 2003 Microchip Technology Inc. DS39582B-page 9

PIC16F87XA TABLE 1-3: Pin Name OSC1/CLKI OSC1 PIC16F874A/877A PINOUT DESCRIPTION PDIP Pin# 13 PLCC TQFP Pin# Pin# 14 30 QFN Pin# 32 I I/O/P Type Buffer Type Desc ription CLKI I ST/CMOS(4) Oscillator crystal or external clock input. Oscillator crystal input or external clock source input. ST buffer when configured in RC mode; otherwise CMOS. External clock source input. Always associated with pin function OSC1 (see OSC1/CLKI, OSC2/CLKO pins). Oscillator crystal or clock output. Oscillator cr ystal output. Connects to crystal or resonator in Crystal Oscillator mode. In RC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes th e instruction cycle rate. Master Clear (input) or programming voltage (output). Master Clear (Reset) input. This pin is an active low Reset to the device. Progr amming voltage input. PORTA is a bidirectional I/O port. OSC2/CLKO OSC2 14 15 31 33 O CLKO O MCLR/VPP MCLR VPP RA0/AN0 RA0 AN0 RA1/AN1 RA1 AN1 RA2/AN2/VREF-/CVREF RA2 AN2 VR EFCVREF RA3/AN3/VREF+ RA3 AN3 VREF+ RA4/T0CKI/C1OUT RA4 T0CKI C1OUT RA5/AN4/SS/C 2OUT RA5 AN4 SS C2OUT Legend: Note 1: 2: 3: 1 2 18 18 I P ST 2 3 19 19 I/O I TTL Digital I/O. Analog input 0. TTL I/O I Digital I/O. Analog input 1. TTL I/O I I O Digital I/O. Analog input 2. A/D reference voltage (Low) input. Comparator

VREF output. TTL I/O I I Digital I/O. Analog input 3. A/D reference voltage (Hi gh) input. ST I/O I O Digital I/O Open-drain when configured as output. Timer0 external clock input. Comparator 1 output. TTL I/O I I O Digital I/O. Analog in put 4. SPI slave select input. Comparator 2 output. 3 4 20 20 4 5 21 21 5 6 22 22 6 7 23 23 7 8 24 24 I = input O = output I/O = input/output P = power = Not used TTL = TTL input S T = Schmitt Trigger input This buffer is a Schmitt Trigger input when configured as the external interrupt. This buffer is a Schmitt Trigger input when used in Serial Programming mode. This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise. DS39582B-page 10 2003 Microchip Technology Inc.

PIC16F87XA TABLE 1-3: Pin Name PIC16F874A/877A PINOUT DESCRIPTION (CONTINUED) PDIP Pin# PLCC TQFP Pin# Pin# QFN Pin# I/O/P Type Buffer Type Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs. RB0/INT RB0 INT RB1 RB2 RB3/PGM RB3 PGM RB4 RB5 RB6/PGC RB6 PGC RB7/PGD RB7 PGD Legend: Note 1: 2: 3: 33 36 8 9 I/O I TTL/ST(1) Digital I/O. External interrupt. TTL TTL TTL I/O I Digital I/O. Low-vo ltage ICSP programming enable pin. TTL TTL TTL/ST(2) I/O I Digital I/O. In-circu it debugger and ICSP programming clock. TTL/ST(2) I/O I/O Digital I/O. In-circui t debugger and ICSP programming data. Digital I/O. Digital I/O. Digital I/O. Dig ital I/O. 34 35 36 37 38 39 9 10 11 10 11 12 I/O I/O 37 38 39 41 42 43 14 15 16 14 15 16 I/O I/O 40 44 17 17 I = input O = output I/O = input/output P = power = Not used TTL = TTL input S T = Schmitt Trigger input This buffer is a Schmitt Trigger input when configured as the external interrupt. This buffer is a Schmitt Trigger input when used in Serial Programming mode. This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.

2003 Microchip Technology Inc. DS39582B-page 11

PIC16F87XA TABLE 1-3: Pin Name PIC16F874A/877A PINOUT DESCRIPTION (CONTINUED) PDIP Pin# PLCC TQFP Pin# Pin# QFN Pin# I/O/P Type Buffer Type Description PORTC is a bidirectional I/O port. RC0/T1OSO/T1CKI RC0 T1OSO T1CKI RC1/T1OSI/CCP2 RC1 T1OSI CCP2 RC2/CCP1 RC2 CCP1 RC3/SCK/SCL RC3 SCK SCL RC4/SDI/SDA RC4 SDI SDA RC5/SDO RC5 SDO RC6/TX/CK RC6 TX CK RC7/RX/DT RC7 RX DT Legend: Note 1: 2: 3: 15 16 32 34 I/O O I ST Digital I/O. Timer1 oscillator output. Timer1 external clock input. ST I/O I I/O Digital I/O. Timer1 oscillator input. Capture2 input, Compare2 output, PWM2 output. ST I/O I/O Digital I/O. Capture1 input, Compare1 output, PWM1 output. ST I/O I/O I/O Digital I/O. Synchronous serial clock input/output for SPI mode. Sy nchronous serial clock input/output for I2C mode. ST I/O I I/O Digital I/O. SPI data in. I2C data I/O. ST I/O O Digital I/O. SPI data out. ST I/O O I/O Digital I/O. USART asynchronous transmit. USART1 synchronous clock. ST I/O I I/O Digital I/O. USART asynchronous receive. USART synchronous data. 16 18 35 35 17 19 36 36 18 20 37 37 23 25 42 42

24 26 43 43 25 27 44 44 26 29 1 1 I = input O = output I/O = input/output P = power = Not used TTL = TTL input S T = Schmitt Trigger input This buffer is a Schmitt Trigger input when configured as the external interrupt. This buffer is a Schmitt Trigger input when used in Serial Programming mode. This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise. DS39582B-page 12 2003 Microchip Technology Inc.

PIC16F87XA TABLE 1-3: Pin Name PIC16F874A/877A PINOUT DESCRIPTION (CONTINUED) PDIP Pin# PLCC TQFP Pin# Pin# QFN Pin# I/O/P Type Buffer Type Description PORTD is a bidirectional I/O port or Parallel Slave Port when interfacing to a micropr ocessor bus. RD0/PSP0 RD0 PSP0 RD1/PSP1 RD1 PSP1 RD2/PSP2 RD2 PSP2 RD3/PSP3 RD3 PSP3 RD4/PSP4 RD4 PSP4 RD5/PSP5 RD5 PSP5 RD6/PSP6 RD6 PSP6 RD7/PSP7 RD7 PSP7 RE0/RD/AN5 RE0 R D AN5 RE1/WR/AN6 RE1 WR AN6 RE2/CS/AN7 RE2 CS AN7 VSS VDD NC Legend: Note 1: 2: 3: 19 21 38 38 I/O I/O ST/TTL(3) Digital I/O. Parallel Slave Port data. ST/TTL(3) I/O I/O Digital I/O. Parallel Slave Port data. ST/TTL(3) I/O I/O Digital I/O. Parallel Slave Port dat a. ST/TTL(3) I/O I/O Digital I/O. Parallel Slave Port data. ST/TTL(3) I/O I/O Di gital I/O. Parallel Slave Port data. ST/TTL(3) I/O I/O Digital I/O. Parallel Sla ve Port data. ST/TTL(3) I/O I/O Digital I/O. Parallel Slave Port data. ST/TTL(3) I/O I/O Digital I/O. Parallel Slave Port data. PORTE is a bidirectional I/O por t. ST/TTL(3) I/O I I Digital I/O. Read control for Parallel Slave Port. Analog i nput 5. ST/TTL(3) I/O I I Digital I/O. Write control for Parallel Slave Port. An alog input 6. ST/TTL(3) I/O I I Digital I/O. Chip select control for Parallel Sl ave Port. Analog input 7. Ground reference for logic and I/O pins. Positiv e supply for logic and I/O pins. These pins are not internally connected. These pins should be left unconnected. 20 22 39 39 21 23 40 40 22 24 41 41 27

30 2 2 28 31 3 3 29 32 4 4 30 33 5 5 8 9 25 25 9 10 26 26 10 11 27 27 12, 31 13, 34 11, 32 12, 35 6, 29 7, 28 6, 30, 31 7, 8, 28, 29 13

P P 1, 17, 12,13, 28, 40 33, 34 I = input O = output I/O = input/output P = power = Not used TTL = TTL input S T = Schmitt Trigger input This buffer is a Schmitt Trigger input when configured as the external interrupt. This buffer is a Schmitt Trigger input when used in Serial Programming mode. This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise. 2003 Microchip Technology Inc. DS39582B-page 13

PIC16F87XA NOTES: DS39582B-page 14 2003 Microchip Technology Inc.

PIC16F87XA 2.0 MEMORY ORGANIZATION 2.1 Program Memory Organization There are three memory blocks in each of the PIC16F87XA devices. The program mem ory and data memory have separate buses so that concurrent access can occur and is detailed in this section. The EEPROM data memory block is detailed in Section 3.0 Data EEPROM and Flash Program Memory. Additional information on device me mory may be found in the PICmicro Mid-Range MCU Family Reference Manual (DS3302 3). The PIC16F87XA devices have a 13-bit program counter capable of addressing a n 8K word x 14 bit program memory space. The PIC16F876A/877A devices have 8K wor ds x 14 bits of Flash program memory, while PIC16F873A/874A devices have 4K word s x 14 bits. Accessing a location above the physically implemented address will cause a wraparound. The Reset vector is at 0000h and the interrupt vector is at 0004h. FIGURE 2-1: PIC16F876A/877A PROGRAM MEMORY MAP AND STACK PC FIGURE 2-2: PIC16F873A/874A PROGRAM MEMORY MAP AND STACK PC CALL, RETURN RETFIE, RETLW 13 CALL, RETURN RETFIE, RETLW 13 Stack Level 1 Stack Level 2 Stack Level 1 Stack Level 2 Stack Level 8 Stack Level 8 Reset Vector 0000h Reset Vector 0000h Interrupt Vector 0004h 0005h Interrupt Vector 0004h 0005h Page 0 07FFh 0800h Page 1 On-Chip Program Memory Page 2 17FFh 1800h Page 3 1FFFh 0FFFh 1000h

On-Chip Program Memory Page 0 07FFh 0800h Page 1 0FFFh 1000h 1FFFh 2003 Microchip Technology Inc. DS39582B-page 15

PIC16F87XA 2.2 Data Memory Organization The data memory is partitioned into multiple banks which contain the General Pur pose Registers and the Special Function Registers. Bits RP1 (Status) and RP0 (Status) are the bank select bits. RP1:RP0 00 01 10 11 Bank 0 1 2 3 Each bank extends up to 7Fh (128 bytes). The lower locations of each bank are reserved fo r the Special Function Registers. Above the Special Function Registers are Gener al Purpose Registers, implemented as static RAM. All implemented banks contain S pecial Function Registers. Some frequently used Special Function Registers from one bank may be mirrored in another bank for code reduction and quicker access. Note: The EEPROM data memory description can be found in Section 3.0 Data EEPRO M and Flash Program Memory of this data sheet. 2.2.1 GENERAL PURPOSE REGISTER FILE The register file can be accessed either directly, or indirectly, through the Fi le Select Register (FSR). DS39582B-page 16 2003 Microchip Technology Inc.

PIC16F87XA FIGURE 2-3: PIC16F876A/877A REGISTER FILE MAP File Address Indirect addr.(*) TMR0 PCL STATUS FSR PORTA PORTB PORTC PORTD(1) PO RTE(1) PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG CCPR2L CCPR2H CCP2CON ADRESH ADCON0 00h 01h 02 h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16 h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h File Address Indirect addr.(*) OPTION_ REG PCL STATUS FSR TRISA TRISB TRISC TRISD(1) TRISE(1) PCLATH INTCON PIE1 PIE2 P CON 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h General Purpose Register 80 Bytes EFh F0h FFh Bank 1 Bank 2 General Purpose Register 80 Bytes 16Fh 170h 17Fh Bank 3 Indirect addr.(*) TMR0 PCL STATUS FSR PORTB File Address 100h 101h 1 02h 103h 104h 105h 106h 107h 108h 109h 10Ah 10Bh 10Ch 10Dh 10Eh 10Fh 110h 111h 1 12h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh 11Fh 120h File A ddress Indirect addr.(*) OPTION_REG PCL STATUS FSR TRISB 180h 181h 182h 183h 184 h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194 h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh 1A0h General Purpose Re gister 80 Bytes 1EFh 1F0h 1FFh PCLATH INTCON EEDATA EEADR EEDATH EEADRH PCLATH INTCON EECON1 EECON2 Reserved(2) Reserved(2) SSPCON2 PR2 SSPADD SSPSTAT TXSTA SPBRG General Purpose Register 16 Bytes General Purpose Register 16 Bytes CMCON CVRCON ADRESL ADCON1 General Purpose Register 96 Bytes accesses 70h-7Fh 7Fh Bank 0 accesses 70h-7Fh accesses 70h - 7Fh * Note 1: 2: Unimplemented data memory locations, read as 0. Not a physical register. These registers are not implemented on the PIC16F876A. These registers are reserved; maintain these registers clear. 2003 Microchip Technology Inc. DS39582B-page 17

PIC16F87XA FIGURE 2-4: PIC16F873A/874A REGISTER FILE MAP File Address Indirect addr.(*) TMR0 PCL STATUS FSR PORTA PORTB PORTC PORTD(1) PO RTE(1) PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG CCPR2L CCPR2H CCP2CON ADRESH ADCON0 00h 01h 02 h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16 h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h File Address Indirect addr.(*) OPTION_ REG PCL STATUS FSR TRISA TRISB TRISC TRISD(1) TRISE(1) PCLATH INTCON PIE1 PIE2 P CON 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h General Purpose Register 96 Bytes File Address Indirect addr.(*) 100h 101h TMR0 102h PCL 103h STATUS 104 h FSR 105h 106h PORTB 107h 108h 109h 10Ah PCLATH 10Bh INTCON 10Ch EEDATA EEADR 1 0Dh 10Eh EEDATH 10Fh EEADRH 110h File Address Indirect addr.(*) OPTION_REG PCL S TATUS FSR TRISB 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h PCLATH INTCON EECON1 EECON2 Reserved(2) Reserved(2) SSPCON2 PR2 SSPADD SSPSTAT TXSTA SPBRG CMCON CVRCON ADRESL ADCON1 120h 1A0h General Purpose Register 96 Bytes accesses 20h-7Fh 16Fh 170h FFh 17Fh Bank 2 accesses A0h - FFh 1EFh 1F0h 1FFh Bank 3 7Fh Bank 0 Bank 1 * Note 1: 2: Unimplemented data memory locations, read as 0. Not a physical register. These registers are not implemented on the PIC16F873A. These registers are reserved; maintain these registers clear. DS39582B-page 18 2003 Microchip Technology Inc.

PIC16F87XA 2.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers are registers used by the CPU and peripheral modu les for controlling the desired operation of the device. These registers are imp lemented as static RAM. A list of these registers is given in Table 2-1. The Spe cial Function Registers can be classified into two sets: core (CPU) and peripher al. Those registers associated with the core functions are described in detail i n this section. Those related to the operation of the peripheral features are de scribed in detail in the peripheral features section. TABLE 2-1: Address Bank 0 00h(3) 01h 02h(3) 03h(3) 04h(3) 05h 06h 07h 08h(4) 09h(4) 0Ah(1,3 ) 0Bh(3) 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh Legend: Note 1: 2: 3: 4: 5: INDF TMR0 PCL STATUS FSR PORTA PORTB PORTC PORTD PORTE PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON C CPR1L CCPR1H CCP1CON RCSTA TXREG RCREG CCPR2L CCPR2H CCP2CON ADRESH ADCON0 Name SPECIAL FUNCTION REGISTER SUMMARY Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: Details POR, BOR on pa ge: Addressing this location uses contents of FSR to address data memory (not a phys ical register) 0000 0000 31, 150 Timer0 Module Register Program Counter (PC) Lea st Significant Byte IRP RP1 RP0 TO PD Z DC C xxxx xxxx 55, 150 0000 0000 30, 150 0001 1xxx 22, 150 xxxx xxxx 31, 150 --0x 0000 43, 150 xxxx xxxx 45, 150 xxx x xxxx 47, 150 xxxx xxxx 48, 150 RE2 TMR0IF CCP1IF RE1 INTF TMR2IF RE0 RBIF ---- -xxx 49, 150 ---0 0000 30, 150 0000 000x 24, 150 Indirect Data Memory Address Pointer PORTA Data Latch when written: PORTA pins w hen read PORTB Data Latch when written: PORTB pins when read PORTC Data Latch wh en written: PORTC pins when read PORTD Data Latch when written: PORTD pins when read GIE PSPIF(3) PEIE ADIF CMIF TMR0IE RCIF INTE TXIF EEIF RBIE SSPIF BCLIF Write Buffer for the upper 5 bits of the Program Counter TMR1IF 0000 0000 26, 150 CCP2IF -0-0 0--0 28, 150 xxxx xxxx 60, 150 xxxx xxxx 60 , 150 Holding Register for the Least Significant Byte of the 16-bit TMR1 Register Hold ing Register for the Most Significant Byte of the 16-bit TMR1 Register WCOL T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR2ON SSPM2 TMR1CS TMR1ON --00 0000 57, 150 0000 0000 62, 150 T2CKPS1 T2CKPS0 -000 0000 61, 150 xxxx xxxx 79, 150 SSPM1 SSPM0 0000 0000 82, 82, 150 Timer2 Module Register TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 SSPOV SSPEN CKP SSPM3 Syn chronous Serial Port Receive Buffer/Transmit Register Capture/Compare/PWM Register 1 (LSB) Capture/Compare/PWM Register 1 (MSB) SPEN RX9 CCP1X SREN CCP1Y CREN CCP1M3 ADDEN CCP1M2 FERR OERR RX9D xxxx xxxx 63, 150 xxxx xxxx 63, 150 CCP1M1 CCP1M0 --00 0000 64, 150 0000 000x 11 2, 150 0000 0000 118, 150 0000 0000 118, 150 xxxx xxxx 63, 150 xxxx xxxx 63, 150 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 64, 150 xxxx xxxx 133, 150 USART Transmit Data Register USART Receive Data Register Capture/Compare/PWM Reg ister 2 (LSB) Capture/Compare/PWM Register 2 (MSB) CCP2X CCP2Y A/D Result Re gister High Byte ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE ADON 0000 00-0 127, 150

x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r ead as 0, r = reserved. Shaded locations are unimplemented, read as 0. The u pper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC, whose contents are transferred to the upper byte of the program counter. Bits PSPIE and PSPIF are reserved on PIC16F873A/876A device s; always maintain these bits clear. These registers can be addressed from any b ank. PORTD, PORTE, TRISD and TRISE are not implemented on PIC16F873A/876A device s, read as 0. Bit 4 of EEADRH implemented only on the PIC16F876A/877A devices. 2003 Microchip Technology Inc. DS39582B-page 19

PIC16F87XA TABLE 2-1: Address Bank 1 80h(3) 81h 82h(3) 83h(3) 84h(3) 85h 86h 87h 88h(4) 89h(4) 8Ah(1,3 ) 8Bh(3) 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh Legend: Note 1: 2: 3: 4: 5: PR2 SSPADD SSPSTAT TXSTA SPBRG CM CON CVRCON ADRESL ADCON1 INDF OPTION_REG PCL STATUS FSR TRISA TRISB TRISC TRISD TRISE PCLATH INTCON PIE1 PIE2 PCON SSPCON2 Addressing this location uses con tents of FSR to address data memory (not a physical register) 0000 0000 31, 150 RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 23, 150 0000 0000 30, 150 PD Z D C C 0001 1xxx 22, 150 xxxx xxxx 31, 150 --11 1111 43, 150 1111 1111 45, 150 1111 1111 47, 150 1111 1111 48, 151 PSPMODE INTE TXIE EEIE RBIE SSPIE BCLIE PO RTE Data Direction bits TMR0IF CCP1IE INTF TMR2IE POR RBIF 0000 -111 50, 1 51 ---0 0000 30, 150 0000 000x 24, 150 Write Buffer for the upper 5 bits of the Program Counter Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: Details POR, BOR on pa ge: Program Counter (PC) Least Significant Byte IRP RP1 RP0 TO Indirect Data Memory Address Pointer PORTA Data Direction Register PORTB Data Di rection Register PORTC Data Direction Register PORTD Data Direction Register IBF GIE PSPIE(2) OBF PEIE ADIE CMIE IBOV TMR0IE RCIE TMR1IE 0000 0000 25, 151 CCP2IE -0-0 0--0 27, 151 BOR ---- --qq 29, 151 Unimplemented Unimplemented GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN Timer2 Pe riod Register Synchronous Serial Port (I2C mode) Address Register SMP CKE D/A P S R/W UA BF 0000 0000 83, 151 1111 1111 62, 151 0000 0000 79, 151 0000 0000 79, 151 Unimplemented Unimplemented Unimplemented CSRC TX9 TXEN SYNC BRGH TRMT TX9D Ba ud Rate Generator Register Unimplemented Unimplemented C2OUT CVREN ADFM C1OUT CV ROE ADCS2 C2INV CVRR C1INV CIS CVR3 PCFG3 CM2 CVR2 PCFG2 CM1 CVR1 PCFG1 CM 0 CVR0 PCFG0 0000 -010 111, 151 0000 0000 113, 151 0000 0111 135, 151 000- 0000 141, 151 xxxx xxxx 133, 151 00-- 0000 128, 151 A/D Result Register Low Byte x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r ead as 0, r = reserved. Shaded locations are unimplemented, read as 0. The u pper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC, whose contents are transferred to the upper byte of the program counter. Bits PSPIE and PSPIF are reserved on PIC16F873A/876A device s; always maintain these bits clear. These registers can be addressed from any b ank. PORTD, PORTE, TRISD and TRISE are not implemented on PIC16F873A/876A device s, read as 0. Bit 4 of EEADRH implemented only on the PIC16F876A/877A devices. DS39582B-page 20 2003 Microchip Technology Inc.

PIC16F87XA TABLE 2-1: Address Bank 2 100h(3) 101h 102h(3) 103h(3) 104h(3) 105h 106h 107h 108h 109h 10B h(3) 10Ch 10Dh 10Eh 10Fh Bank 3 180h(3) 181h 182h(3) 183h(3) 184h(3) 185h 186h 1 87h 188h 189h 18Bh(3) 18Ch 18Dh 18Eh 18Fh Legend: Note 1: 2: 3: 4: 5: INDF OPTIO N_REG PCL STATUS FSR TRISB INTCON EECON1 EECON2 Addressing this loca tion uses contents of FSR to address data memory (not a physical register) 0000 0000 31, 150 RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 23, 150 0000 0000 3 0, 150 PD Z DC C 0001 1xxx 22, 150 xxxx xxxx 31, 150 TMR0IE Write Bu ffer for the upper 5 bits of the Program Counter INTE RBIE WRERR TMR0IF WREN I NTF WR RBIF RD 1111 1111 45, 150 INDF TMR0 PCL STATUS FSR PORTB INTCON EEDATA EEADR EEDATH EEADRH Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 31, 150 Timer0 Module Register Program Counters (PC) Least Significant Byte IRP RP1 RP0 TO PD Z DC C xxxx xxxx 55, 150 0000 0000 30, 150 0001 1xxx 22, 150 xxxx xxxx 31, 150 TMR0IE Write Buffer for the upper 5 bits of the Program Counter INTE RBIE TMR 0IF INTF RBIF xxxx xxxx 45, 150 Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: Details POR, BOR on pa ge: Indirect Data Memory Address Pointer Unimplemented PORTB Data Latch when written : PORTB pins when read Unimplemented Unimplemented Unimplemented GIE PEIE 10Ah(1,3) PCLATH ---0 0000 30, 150 0000 000x 24, 150 xxxx xxxx 39, 151 xxxx xxxx 39, 151 --xx xxx x 39, 151 ---- xxxx 39, 151 EEPROM Data Register Low Byte EEPROM Address Register Low Byte EEPROM Da ta Register High Byte (5) EEPROM Address Register High Byte Program Counter (PC) Least Significant Byte IRP RP1 RP0 TO Indirect Data Memory Address Pointer Unimplemented PORTB Data Direction Register Unimplemented Unimplemented Unimplemented GIE EEPGD PEIE 18Ah(1,3) PCLATH ---0 0000 30, 150 0000 000x 24, 150 x--- x000 34, 151 ---- ---- 39, 151 0000 000 0 0000 0000 EEPROM Control Register 2 (not a physical register) Reserved; maintain clear Res erved; maintain clear x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r ead as 0, r = reserved. Shaded locations are unimplemented, read as 0. The u pper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC, whose contents are transferred to the upper byte of the program counter. Bits PSPIE and PSPIF are reserved on PIC16F873A/876A device s; always maintain these bits clear. These registers can be addressed from any b ank. PORTD, PORTE, TRISD and TRISE are not implemented on PIC16F873A/876A device s, read as 0. Bit 4 of EEADRH implemented only on the PIC16F876A/877A devices. 2003 Microchip Technology Inc. DS39582B-page 21

PIC16F87XA 2.2.2.1 Status Register The Status register contains the arithmetic status of the ALU, the Reset status and the bank select bits for data memory. The Status register can be the destina tion for any instruction, as with any other register. If the Status register is the destination for an instruction that affects the Z, DC or C bits, then the wr ite to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable, therefore, t he result of an instruction with the Status register as destination may be diffe rent than intended. For example, CLRF STATUS, will clear the upper three bits an d set the Z bit. This leaves the Status register as 000u u1uu (where u = unchang ed). It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructi ons are used to alter the Status register because these instructions do not affe ct the Z, C or DC bits from the Status register. For other instructions not affe cting any status bits, see Section 15.0 Instruction Set Summary. Note: The C a nd DC bits operate as a borrow and digit borrow bit, respectively, in subtractio n. See the SUBLW and SUBWF instructions for examples. REGISTER 2-1: STATUS REGISTER (ADDRESS 03h, 83h, 103h, 183h) R/W-0 IRP bit 7 R/W-0 RP1 R/W-0 RP0 R-1 TO R-1 PD R/W-x Z R/W-x DC R/W-x C bit 0 bit 7 IRP: Register Bank Select bit (used for indirect addressing) 1 = Bank 2, 3 (100h -1FFh) 0 = Bank 0, 1 (00h-FFh) RP1:RP0: Register Bank Select bits (used for dire ct addressing) 11 = Bank 3 (180h-1FFh) 10 = Bank 2 (100h-17Fh) 01 = Bank 1 (80hFFh) 00 = Bank 0 (00h-7Fh) Each bank is 128 bytes. TO: Time-out bit 1 = After po wer-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction Z: Zero bit 1 = The result of an arithmetic or logic op eration is zero 0 = The result of an arithmetic or logic operation is not zero D C: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow, t he polarity is reversed) 1 = A carry-out from the 4th low order bit of the resul t occurred 0 = No carry-out from the 4th low order bit of the result C: Carry/bo rrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) 1 = A carry-out from the Most S ignificant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note: For borrow, the polarity is reversed. A subtra ction is executed by adding the twos complement of the second operand. For rota te (RRF, RLF) instructions, this bit is loaded with either the high, or low orde r bit of the source register. bit 6-5 bit 4 bit 3 bit 2 bit 1 bit 0 Legend: R = Readable bit - n = Value at POR W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown DS39582B-page 22

2003 Microchip Technology Inc.

PIC16F87XA 2.2.2.2 OPTION_REG Register Note: The OPTION_REG Register is a readable and writable register, which contain s various control bits to configure the TMR0 prescaler/WDT postscaler (single as signable register known also as the prescaler), the external INT interrupt, TMR0 and the weak pull-ups on PORTB. To achieve a 1:1 prescaler assignment for the T MR0 register, assign the prescaler to the Watchdog Timer. REGISTER 2-2: OPTION_REG REGISTER (ADDRESS 81h, 181h) R/W-1 RBPU bit 7 R/W-1 INTEDG R/W-1 T0CS R/W-1 T0SE R/W-1 PSA R/W-1 PS2 R/W-1 PS 1 R/W-1 PS0 bit 0 bit 7 RBPU: PORTB Pull-up Enable bit 1 = PORTB pull-ups are disabled 0 = PORTB pull-up s are enabled by individual port latch values INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0 /INT pin T0CS: TMR0 Clock Source Select bit 1 = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (CLKO) T0SE: TMR0 Source Edge Select bit 1 = In crement on high-to-low transition on RA4/T0CKI pin 0 = Increment on low-to-high transition on RA4/T0CKI pin PSA: Prescaler Assignment bit 1 = Prescaler is assig ned to the WDT 0 = Prescaler is assigned to the Timer0 module PS2:PS0: Prescaler Rate Select bits Bit Value 000 001 010 011 100 101 110 111 Legend: R = Readable bit - n = Value at POR Note: W = Writable bit 1 = Bit is set U = Unimplemente d bit, read as 0 0 = Bit is cleared x = Bit is unknown TMR0 Rate WDT Rate 1: 2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 bit 6 bit 5 bit 4 bit 3 bit 2-0 When using Low-Voltage ICSP Programming (LVP) and the pull-ups on PORTB are enab led, bit 3 in the TRISB register must be cleared to disable the pull-up on RB3 a nd ensure the proper operation of the device 2003 Microchip Technology Inc. DS39582B-page 23

PIC16F87XA 2.2.2.3 INTCON Register Note: The INTCON register is a readable and writable register, which contains va rious enable and flag bits for the TMR0 register overflow, RB port change and ex ternal RB0/INT pin interrupts. Interrupt flag bits are set when an interrupt con dition occurs regardless of the state of its corresponding enable bit or the glo bal enable bit, GIE (INTCON). User software should ensure the appropriate int errupt flag bits are clear prior to enabling an interrupt. REGISTER 2-3: INTCON REGISTER (ADDRESS 0Bh, 8Bh, 10Bh, 18Bh) R/W-0 GIE bit 7 R/W-0 PEIE R/W-0 TMR0IE R/W-0 INTE R/W-0 RBIE R/W-0 TMR0IF R/W-0 INTF R/W-x RBIF bit 0 bit 7 GIE: Global Interrupt Enable bit 1 = Enables all unmasked interrupts 0 = Disable s all interrupts PEIE: Peripheral Interrupt Enable bit 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts TMR0IE: TMR0 Overfl ow Interrupt Enable bit 1 = Enables the TMR0 interrupt 0 = Disables the TMR0 int errupt INTE: RB0/INT External Interrupt Enable bit 1 = Enables the RB0/INT exter nal interrupt 0 = Disables the RB0/INT external interrupt RBIE: RB Port Change I nterrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt TMR0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 registe r has overflowed (must be cleared in software) 0 = TMR0 register did not overflo w INTF: RB0/INT External Interrupt Flag bit 1 = The RB0/INT external interrupt o ccurred (must be cleared in software) 0 = The RB0/INT external interrupt did not occur RBIF: RB Port Change Interrupt Flag bit 1 = At least one of the RB7:RB4 p ins changed state; a mismatch condition will continue to set the bit. Reading PO RTB will end the mismatch condition and allow the bit to be cleared (must be cle ared in software). 0 = None of the RB7:RB4 pins have changed state Legend: R = R eadable bit - n = Value at POR W = Writable bit 1 = Bit is set U = Unimplement ed bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DS39582B-page 24 2003 Microchip Technology Inc.

PIC16F87XA 2.2.2.4 PIE1 Register Note: The PIE1 register contains the individual enable bits for the peripheral i nterrupts. Bit PEIE (INTCON) must be set to enable any peripheral interrupt. REGISTER 2-4: PIE1 REGISTER (ADDRESS 8Ch) R/W-0 PSPIE(1) bit 7 R/W-0 ADIE R/W-0 RCIE R/W-0 TXIE R/W-0 SSPIE R/W-0 CCP1IE R /W-0 TMR2IE R/W-0 TMR1IE bit 0 bit 7 PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit(1) 1 = Enables the PS P read/write interrupt 0 = Disables the PSP read/write interrupt Note 1: PSPIE i s reserved on PIC16F873A/876A devices; always maintain this bit clear. bit 6 ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D converter interrupt 0 = Disables the A/D converter interrupt RCIE: USART Receive Interrupt Enable b it 1 = Enables the USART receive interrupt 0 = Disables the USART receive interr upt TXIE: USART Transmit Interrupt Enable bit 1 = Enables the USART transmit int errupt 0 = Disables the USART transmit interrupt SSPIE: Synchronous Serial Port Interrupt Enable bit 1 = Enables the SSP interrupt 0 = Disables the SSP interrup t CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables th e TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt TMR1I E: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Legend: R = Readable bit - n = Value at POR W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown 2003 Microchip Technology Inc. DS39582B-page 25

PIC16F87XA 2.2.2.5 PIR1 Register Note: The PIR1 register contains the individual flag bits for the peripheral int errupts. Interrupt flag bits are set when an interrupt condition occurs regardle ss of the state of its corresponding enable bit or the global enable bit, GIE (I NTCON). User software should ensure the appropriate interrupt bits are clear prior to enabling an interrupt. REGISTER 2-5: PIR1 REGISTER (ADDRESS 0Ch) R/W-0 PSPIF bit 7 (1) R/W-0 ADIF R-0 RCIF R-0 TXIF R/W-0 SSPIF R/W-0 CCP1IF R/W-0 TMR2IF R/W-0 TMR1IF bit 0 bit 7 PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit(1) 1 = A read or a writ e operation has taken place (must be cleared in software) 0 = No read or write h as occurred Note 1: PSPIF is reserved on PIC16F873A/876A devices; always maintai n this bit clear. ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion c ompleted 0 = The A/D conversion is not complete RCIF: USART Receive Interrupt Fl ag bit 1 = The USART receive buffer is full 0 = The USART receive buffer is empt y TXIF: USART Transmit Interrupt Flag bit 1 = The USART transmit buffer is empty 0 = The USART transmit buffer is full SSPIF: Synchronous Serial Port (SSP) Inte rrupt Flag bit 1 = The SSP interrupt condition has occurred and must be cleared in software before returning from the Interrupt Service Routine. The conditions that will set this bit are: SPI A transmission/reception has taken place. I2C Slave A transmission/reception has taken place. I2C Master - A transmiss ion/reception has taken place. - The initiated Start condition was completed by the SSP module. - The initiated Stop condition was completed by the SSP module. - The initiated Restart condition was completed by the SSP module. - The initiat ed Acknowledge condition was completed by the SSP module. - A Start condition oc curred while the SSP module was Idle (multi-master system). - A Stop condition o ccurred while the SSP module was Idle (multi-master system). 0 = No SSP interrup t condition has occurred CCP1IF: CCP1 Interrupt Flag bit Capture mode: 1 = A TMR 1 register capture occurred (must be cleared in software) 0 = No TMR1 register c apture occurred Compare mode: 1 = A TMR1 register compare match occurred (must b e cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unu sed in this mode. TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 m atch occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred TM R1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cle ared in software) 0 = TMR1 register did not overflow Legend: R = Readable bit n = Value at POR bit 6

bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown DS39582B-page 26 2003 Microchip Technology Inc.

PIC16F87XA 2.2.2.6 PIE2 Register Note: The PIE2 register contains the individual enable bits for the CCP2 periphe ral interrupt, the SSP bus collision interrupt, EEPROM write operation interrupt and the comparator interrupt. Bit PEIE (INTCON) must be set to enable any pe ripheral interrupt. REGISTER 2-6: PIE2 REGISTER (ADDRESS 8Dh) U-0 bit 7 R/W-0 CMIE U-0 R/W-0 EEIE R/W-0 BCLIE U-0 U-0 R/W-0 CCP2IE bit 0 bit 7 bit 6 Unimplemented: Read as 0 CMIE: Comparator Interrupt Enable bit 1 = Enables the comparator interrupt 0 = Disable the comparator interrupt Unimplemented: Read a s 0 EEIE: EEPROM Write Operation Interrupt Enable bit 1 = Enable EEPROM write interrupt 0 = Disable EEPROM write interrupt BCLIE: Bus Collision Interrupt Enab le bit 1 = Enable bus collision interrupt 0 = Disable bus collision interrupt Un implemented: Read as 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enables the CCP2 interrupt 0 = Disables the CCP2 interrupt Legend: R = Readable bit - n = Value a t POR W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 5 bit 4 bit 3 bit 2-1 bit 0 2003 Microchip Technology Inc. DS39582B-page 27

PIC16F87XA 2.2.2.7 PIR2 Register Note: The PIR2 register contains the flag bits for the CCP2 interrupt, the SSP b us collision interrupt, EEPROM write operation interrupt and the comparator inte rrupt. Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INT CON). User software should ensure the appropriate interrupt flag bits are cle ar prior to enabling an interrupt. REGISTER 2-7: PIR2 REGISTER (ADDRESS 0Dh) U-0 bit 7 R/W-0 CMIF U-0 R/W-0 EEIF R/W-0 BCLIF U-0 U-0 R/W-0 CCP2IF bit 0 bit 7 bit 6 Unimplemented: Read as 0 CMIF: Comparator Interrupt Flag bit 1 = The comparato r input has changed (must be cleared in software) 0 = The comparator input has n ot changed Unimplemented: Read as 0 EEIF: EEPROM Write Operation Interrupt Fla g bit 1 = The write operation completed (must be cleared in software) 0 = The wr ite operation is not complete or has not been started BCLIF: Bus Collision Inter rupt Flag bit 1 = A bus collision has occurred in the SSP when configured for I2 C Master mode 0 = No bus collision has occurred Unimplemented: Read as 0 CCP2I F: CCP2 Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (m ust be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused. Legend: R = Readable bit - n = Value at POR W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 5 bit 4 bit 3 bit 2-1 bit 0 DS39582B-page 28 2003 Microchip Technology Inc.

PIC16F87XA 2.2.2.8 PCON Register Note: The Power Control (PCON) register contains flag bits to allow differentiat ion between a Power-on Reset (POR), a Brown-out Reset (BOR), a Watchdog Reset (W DT) and an external MCLR Reset. BOR is unknown on Power-on Reset. It must be set by the user and checked on subsequent Resets to see if BOR is clear, indicating a brown-out has occurred. The BOR status bit is a dont care and is not predi ctable if the brown-out circuit is disabled (by clearing the BODEN bit in the co nfiguration word). REGISTER 2-8: PCON REGISTER (ADDRESS 8Eh) U-0 bit 7 U-0 U-0 U-0 U-0 U-0 R/W-0 POR R/W-1 BOR bit 0 bit 7-2 bit 1 Unimplemented: Read as 0 POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset o ccurs) Legend: R = Readable bit - n = Value at POR W = Writable bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is cleared x = Bit is unknown bit 0 2003 Microchip Technology Inc. DS39582B-page 29

PIC16F87XA 2.3 PCL and PCLATH The Program Counter (PC) is 13 bits wide. The low byte comes from the PCL regist er which is a readable and writable register. The upper bits (PC) are not readable, but are indirectly writable through the PCLATH register. On any Reset, the upper bits of the PC will be cleared. Figure 2-5 shows the two situations f or the loading of the PC. The upper example in the figure shows how the PC is lo aded on a write to PCL (PCLATH PCH). The lower example in the figure show s how the PC is loaded during a CALL or GOTO instruction (PCLATH PCH). No te 1: There are no status bits to indicate stack overflow or stack underflow con ditions. 2: There are no instructions/mnemonics called PUSH or POP. These are ac tions that occur from the execution of the CALL, RETURN, RETLW and RETFIE instru ctions or the vectoring to an interrupt address. 2.4 Program Memory Paging FIGURE 2-5: LOADING OF PC IN DIFFERENT SITUATIONS PCL 8 7 0 Instruction with PCL as Destination ALU PCH 12 PC 5 PCLATH 8 PCLATH PCH 12 PC 2 PCLATH 11 Opcode PCLATH 11 10 8 7 PCL 0 GOTO,CALL All PIC16F87XA devices are capable of addressing a continuous 8K word block of p rogram memory. The CALL and GOTO instructions provide only 11 bits of address to allow branching within any 2K program memory page. When doing a CALL or GOTO in struction, the upper 2 bits of the address are provided by PCLATH. When doi ng a CALL or GOTO instruction, the user must ensure that the page select bits ar e programmed so that the desired program memory page is addressed. If a return f rom a CALL instruction (or interrupt) is executed, the entire 13-bit PC is poppe d off the stack. Therefore, manipulation of the PCLATH bits is not required for the RETURN instructions (which POPs the address from the stack). Note: The contents of the PCLATH register are unchanged after a RETURN or RETFIE instructi on is executed. The user must rewrite the contents of the PCLATH register for an y subsequent subroutine calls or GOTO instructions. 2.3.1 COMPUTED GOTO Example 2-1 shows the calling of a subroutine in page 1 of the program memory. T his example assumes that PCLATH is saved and restored by the Interrupt Service R outine (if interrupts are used). A computed GOTO is accomplished by adding an offset to the program counter (ADDW F PCL). When doing a table read using a computed GOTO method, care should be exe rcised if the table location crosses a PCL memory boundary (each 256-byte block) . Refer to the application note, AN556, Implementing a Table Read (DS00556). EXAMPLE 2-1: CALL OF A SUBROUTINE IN PAGE 1 FROM PAGE 0

ORG 0x500 BCF PCLATH,4 BSF PCLATH,3 CALL SUB1_P1 : : ORG 0x900 SUB1_P1 : : RETUR N 2.3.2 STACK ;Select page 1 ;(800h-FFFh) ;Call subroutine in ;page 1 (800h-FFFh) ;page 1 (800 h-FFFh) ;called subroutine ;page 1 (800h-FFFh) ;return to ;Call subroutine ;in p age 0 ;(000h-7FFh) The PIC16F87XA family has an 8-level deep x 13-bit wide hardware stack. The stac k space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction i s executed, or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation. The stack operates as a circular buffer. This means that after the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on). DS39582B-page 30 2003 Microchip Technology Inc.

PIC16F87XA 2.5 Indirect Addressing, INDF and FSR Registers A simple program to clear RAM locations 20h-2Fh using indirect addressing is sho wn in Example 2-2. The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing. Indirect addressing is possible by using the INDF reg ister. Any instruction using the INDF register actually accesses the register po inted to by the File Select Register, FSR. Reading the INDF register itself, ind irectly (FSR = 0) will read 00h. Writing to the INDF register indirectly results in a no operation (although status bits may be affected). An effective 9-bit ad dress is obtained by concatenating the 8-bit FSR register and the IRP bit (Statu s) as shown in Figure 2-6. EXAMPLE 2-2: MOVLW MOVWF CLRF INCF BTFSS GOTO : INDIRECT ADDRESSING 0x20 FSR INDF FSR,F FSR,4 NEXT ;initialize pointer ;to RAM ;clear INDF register ;inc pointer ;all done? ;no clear next ;yes continue NEXT CONTINUE FIGURE 2-6: DIRECT/INDIRECT ADDRESSING Indirect Addressing 0 IRP 7 FSR Register 0 Direct Addressing RP1:RP0 6 From Opcode Bank Select Location Select 00 00h 01 80h 10 100h 11 180h Bank Select Location Select Data Memory(1) 7Fh Bank 0 FFh Bank 1 17Fh Bank 2 1FFh Bank 3 Note 1: For register file map detail, see Figure 2-3. 2003 Microchip Technology Inc. DS39582B-page 31

PIC16F87XA NOTES: DS39582B-page 32 2003 Microchip Technology Inc.

PIC16F87XA 3.0 DATA EEPROM AND FLASH PROGRAM MEMORY 3.1 EEADR and EEADRH The EEADRH:EEADR register pair can address up to a maximum of 256 bytes of data EEPROM or up to a maximum of 8K words of program EEPROM. When selecting a data a ddress value, only the LSByte of the address is written to the EEADR register. W hen selecting a program address value, the MSByte of the address is written to t he EEADRH register and the LSByte is written to the EEADR register. If the devic e contains less memory than the full address reach of the address register pair, the Most Significant bits of the registers are not implemented. For example, if the device has 128 bytes of data EEPROM, the Most Significant bit of EEADR is n ot implemented on access to data EEPROM. The data EEPROM and Flash program memory is readable and writable during normal operation (over the full VDD range). This memory is not directly mapped in the r egister file space. Instead, it is indirectly addressed through the Special Func tion Registers. There are six SFRs used to read and write this memory: EECON1 EECON2 EEDATA EEDATH EEADR EEADRH When interfacing to the data memory block, EEDATA holds the 8-bit data for read/ write and EEADR holds the address of the EEPROM location being accessed. These d evices have 128 or 256 bytes of data EEPROM (depending on the device), with an a ddress range from 00h to FFh. On devices with 128 bytes, addresses from 80h to F Fh are unimplemented and will wraparound to the beginning of data EEPROM memory. When writing to unimplemented locations, the on-chip charge pump will be turned off. When interfacing the program memory block, the EEDATA and EEDATH registers form a two-byte word that holds the 14-bit data for read/write and the EEADR an d EEADRH registers form a two-byte word that holds the 13-bit address of the pro gram memory location being accessed. These devices have 4 or 8K words of program Flash, with an address range from 0000h to 0FFFh for the PIC16F873A/874A and 00 00h to 1FFFh for the PIC16F876A/877A. Addresses above the range of the respectiv e device will wraparound to the beginning of program memory. The EEPROM data mem ory allows single-byte read and write. The Flash program memory allows single-wo rd reads and four-word block writes. Program memory write operations automatical ly perform an erase-beforewrite on blocks of four words. A byte write in data EE PROM memory automatically erases the location and writes the new data (erase-bef ore-write). The write time is controlled by an on-chip timer. The write/erase vo ltages are generated by an on-chip charge pump, rated to operate over the voltag e range of the device for byte or word operations. When the device is code-prote cted, the CPU may continue to read and write the data EEPROM memory. Depending o n the settings of the write-protect bits, the device may or may not be able to w rite certain blocks of the program memory; however, reads of the program memory are allowed. When code-protected, the device programmer can no longer access dat a or program memory; this does NOT inhibit internal reads or writes. 3.2 EECON1 and EECON2 Registers EECON1 is the control register for memory accesses. Control bit, EEPGD, determin es if the access will be a program or data memory access. When clear, as it is w hen reset, any subsequent operations will operate on the data memory. When set, any subsequent operations will operate on the program memory. Control bits, RD a nd WR, initiate read and write or erase, respectively. These bits cannot be clea red, only set, in software. They are cleared in hardware at completion of the re ad or write operation. The inability to clear the WR bit in software prevents th e accidental, premature termination of a write operation. The WREN bit, when set , will allow a write or erase operation. On power-up, the WREN bit is clear. The WRERR bit is set when a write (or erase) operation is interrupted by a MCLR or a WDT Time-out Reset during normal operation. In these situations, following Res

et, the user can check the WRERR bit and rewrite the location. The data and addr ess will be unchanged in the EEDATA and EEADR registers. Interrupt flag bit, EEI F in the PIR2 register, is set when the write is complete. It must be cleared in software. EECON2 is not a physical register. Reading EECON2 will read all 0s. The EECON2 register is used exclusively in the EEPROM write sequence. Note: The self-programming mechanism for Flash program memory has been changed. On previo us PIC16F87X devices, Flash programming was done in single-word erase/ write cyc les. The newer PIC18F87XA devices use a four-word erase/write cycle. See Section 3.6 Writing to Flash Program Memory for more information. 2003 Microchip Technology Inc. DS39582B-page 33

PIC16F87XA REGISTER 3-1: EECON1 REGISTER (ADDRESS 18Ch) R/W-x EEPGD bit 7 bit 7 U-0 U-0 U-0 R/W-x WRERR R/W-0 WREN R/S-0 WR R/S-0 RD bit 0 EEPGD: Program/Data EEPROM Select bit 1 = Accesses program memory 0 = Accesses d ata memory Reads 0 after a POR; this bit cannot be changed while a write opera tion is in progress. Unimplemented: Read as 0 WRERR: EEPROM Error Flag bit 1 = A write operation is prematurely terminated (any MCLR or any WDT Reset during n ormal operation) 0 = The write operation completed WREN: EEPROM Write Enable bit 1 = Allows write cycles 0 = Inhibits write to the EEPROM WR: Write Control bit 1 = Initiates a write cycle. The bit is cleared by hardware once write is comple te. The WR bit can only be set (not cleared) in software. 0 = Write cycle to the EEPROM is complete RD: Read Control bit 1 = Initiates an EEPROM read; RD is cle ared in hardware. The RD bit can only be set (not cleared) in software. 0 = Does not initiate an EEPROM read Legend: R = Readable bit - n = Value at POR W = Wri table bit 1 = Bit is set U = Unimplemented bit, read as 0 0 = Bit is clear ed x = Bit is unknown bit 6-4 bit 3 bit 2 bit 1 bit 0 DS39582B-page 34 2003 Microchip Technology Inc.

PIC16F87XA 3.3 Reading Data EEPROM Memory The steps to write to EEPROM data memory are: 1. If step 10 is not implemented, check the WR bit to see if a write is in progress. 2. Write the address to EEADR . Make sure that the address is not larger than the memory size of the device. 3 . Write the 8-bit data value to be programmed in the EEDATA register. 4. Clear t he EEPGD bit to point to EEPROM data memory. 5. Set the WREN bit to enable progr am operations. 6. Disable interrupts (if enabled). 7. Execute the special five i nstruction sequence: Write 55h to EECON2 in two steps (first to W, then to EEC ON2) Write AAh to EECON2 in two steps (first to W, then to EECON2) Set the W R bit 8. Enable interrupts (if using interrupts). 9. Clear the WREN bit to disab le program operations. 10. At the completion of the write cycle, the WR bit is c leared and the EEIF interrupt flag bit is set. (EEIF must be cleared by firmware .) If step 1 is not implemented, then firmware should check for EEIF to be set, or WR to clear, to indicate the end of the program cycle. To read a data memory location, the user must write the address to the EEADR register, clear the EEPGD control bit (EECON1) and then set control bit RD (EECON1). The data is av ailable in the very next cycle in the EEDATA register; therefore, it can be read in the next instruction (see Example 3-1). EEDATA will hold this value until an other read or until it is written to by the user (during a write operation). The steps to reading the EEPROM data memory are: 1. Write the address to EEADR. Mak e sure that the address is not larger than the memory size of the device. Clear the EEPGD bit to point to EEPROM data memory. Set the RD bit to start the read o peration. Read the data from the EEDATA register. 2. 3. 4. EXAMPLE 3-1: BSF BCF MOVF MOVWF BSF BCF BSF BCF MOVF DATA EEPROM READ ; ; ; ; ; ; ; ; ; ; Bank 2 Data Memory Address to read Bank 3 Point to Data memo ry EE Read Bank 2 W = EEDATA STATUS,RP1 STATUS,RP0 DATA_EE_ADDR,W EEADR STATUS,RP0 EECON1,EEPGD EECON1,RD STA TUS,RP0 EEDATA,W EXAMPLE 3-2: DATA EEPROM WRITE ; ;Wait for write ;to complete ;Bank 2 ;Data Memory ;Address to write ;Data Memo ry Value ;to write ;Bank 3 ;Point to DATA ;memory ;Enable writes ;Disable INTs. ; ;Write 55h ; ;Write AAh ;Set WR bit to ;begin write ;Enable INTs. ;Disable wri tes 3.4 Writing to Data EEPROM Memory To write an EEPROM data location, the user must first write the address to the E EADR register and the data to the EEDATA register. Then the user must follow a s pecific write sequence to initiate the write for each byte. The write will not i nitiate if the write sequence is not exactly followed (write 55h to EECON2, writ e AAh to EECON2, then set WR bit) for each byte. We strongly recommend that inte rrupts be disabled during this code segment (see Example 3-2). Additionally, the WREN bit in EECON1 must be set to enable write. This mechanism prevents acciden tal writes to data EEPROM due to errant (unexpected) code execution (i.e., lost programs). The user should keep the WREN bit clear at all times, except when upd ating EEPROM. The WREN bit is not cleared by hardware After a write sequence has been initiated, clearing the WREN bit will not affect this write cycle. The WR

bit will be inhibited from being set unless the WREN bit is set. At the completi on of the write cycle, the WR bit is cleared in hardware and the EE Write Comple te Interrupt Flag bit (EEIF) is set. The user can either enable this interrupt o r poll this bit. EEIF must be cleared by software. BSF BSF BTFSC GOTO BCF MOVF MOVWF MOVF MOVWF BSF BCF BSF BCF MOVLW MOVWF MOVLW M OVWF BSF BSF BCF STATUS,RP1 STATUS,RP0 EECON1,WR $-1 STATUS, RP0 DATA_EE_ADDR,W EEADR DATA_EE_DAT A,W EEDATA STATUS,RP0 EECON1,EEPGD EECON1,WREN INTCON,GIE 55h EECON2 AAh EECON2 EECON1,WR INTCON,GIE EECON1,WREN 2003 Microchip Technology Inc. Required Sequence DS39582B-page 35

PIC16F87XA 3.5 Reading Flash Program Memory To read a program memory location, the user must write two bytes of the address to the EEADR and EEADRH registers, set the EEPGD control bit (EECON1) and the n set control bit RD (EECON1). Once the read control bit is set, the program memory Flash controller will use the next two instruction cycles to read the dat a. This causes these two instructions immediately following the BSF EECON1,RD instruction to be ignored. The data is available in the very next cycle in the E EDATA and EEDATH registers; therefore, it can be read as two bytes in the follow ing instructions. EEDATA and EEDATH registers will hold this value until another read or until it is written to by the user (during a write operation). EXAMPLE 3-3: BSF BCF MOVLW MOVWF MOVLW MOVWF BSF BSF BSF Required Sequence FLASH PROGRAM READ STATUS, RP1 STATUS, RP0 MS_PROG_EE_ADDR EEADRH LS_PROG_EE_ADDR EEADR STATUS, RP0 EECON1, EEPGD EECON1, RD ; ; ; ; ; ; ; ; ; Bank 2 MS Byte of Program Address to read LS Byte of Program Address to read Bank 3 Point to PROGRAM memory EE Read ; NOP NOP ; BCF MOVF MOVWF MOVF MOVWF STATUS, RP0 EEDATA, W DATAL EEDATH, W DATA H ; Bank 2 ; W = LS Byte of Program EEDATA ; ; W = MS Byte of Program EEDATA ; ; Any instructions here are ignored as program ; memory is read in second cycle a fter BSF EECON1,RD DS39582B-page 36 2003 Microchip Technology Inc.

PIC16F87XA 3.6 Writing to Flash Program Memory Flash program memory may only be written to if the destination address is in a s egment of memory that is not write-protected, as defined in bits WRT1:WRT0 of th e device configuration word (Register 14-1). Flash program memory must be writte n in four-word blocks. A block consists of four words with sequential addresses, with a lower boundary defined by an address, where EEADR = 00. At the same time, all block writes to program memory are done as erase and write operations . The write operation is edge-aligned and cannot occur across boundaries. To wri te program data, it must first be loaded into the buffer registers (see Figure 3 -1). This is accomplished by first writing the destination address to EEADR and EEADRH and then writing the data to EEDATA and EEDATH. After the address and dat a have been set up, then the following sequence of events must be executed: 1. 2 . 3. Set the EEPGD control bit (EECON1). Write 55h, then AAh, to EECON2 (Flas h programming sequence). Set the WR control bit (EECON1). To transfer data fr om the buffer registers to the program memory, the EEADR and EEADRH must point t o the last location in the four-word block (EEADR = 11). Then the following sequence of events must be executed: 1. 2. 3. Set the EEPGD control bit (EECON1 ). Write 55h, then AAh, to EECON2 (Flash programming sequence). Set control b it WR (EECON1) to begin the write operation. The user must follow the same specific sequence to initiate the write for each w ord in the program block, writing each program word in sequence (00,01,10,11). W hen the write is performed on the last word (EEADR = 11), the block of four words are automatically erased and the contents of the buffer registers are wri tten into the program memory. After the BSF EECON1,WR instruction, the process or requires two cycles to set up the erase/write operation. The user must place two NOP instructions after the WR bit is set. Since data is being written to buf fer registers, the writing of the first three words of the block appears to occu r immediately. The processor will halt internal operations for the typical 4 ms, only during the cycle in which the erase takes place (i.e., the last word of th e four-word block). This is not Sleep mode as the clocks and peripherals will co ntinue to run. After the write cycle, the processor will resume operation with t he third instruction after the EECON1 write instruction. If the sequence is perf ormed to any other location, the action is ignored. All four buffer register locations MUST be written to with correct data. If only one, two or three words are being written to in the block of four words, then a read from the program memory location(s) not being written to must be performed . This takes the data from the program location(s) not being written and loads i t into the EEDATA and EEDATH registers. Then the sequence of events to transfer data to the buffer registers must be executed. FIGURE 3-1: BLOCK WRITES TO FLASH PROGRAM MEMORY 7 5 EEDATH 0 7 EEDATA 0 Four words of Flash are erased, then all buffers are tra nsferred to Flash automatically after this word is written 6 First word of block to be written 8 14 EEADR = 00 Buffer Register EEADR = 01 14 EEADR = 10

14 EEADR = 11 14 Buffer Register Buffer Register Buffer Register Program Memory 2003 Microchip Technology Inc. DS39582B-page 37

PIC16F87XA An example of the complete four-word write sequence is shown in Example 3-4. The initial address is loaded into the EEADRH:EEADR register pair; the four words o f data are loaded using indirect addressing. EXAMPLE 3-4: ; ; ; ; ; ; WRITING TO FLASH PROGRAM MEMORY This write routine assumes the following: 1. A valid starting address (the least significant bits = 00)is loaded in ADDRH:ADDRL 2. The 8 bytes of data are loa ded, starting at the address in DATADDR 3. ADDRH, ADDRL and DATADDR are all loca ted in shared data memory 0x70 - 0x7f BSF BCF MOVF MOVWF MOVF MOVWF MOVF MOVWF M OVF MOVWF INCF MOVF MOVWF INCF BSF BSF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF NOP N OP BCF BSF BCF INCF MOVF ANDLW XORLW BTFSC GOTO EECON1,WREN INTCON,GIE STATUS,RP 0 EEADR,F EEADR,W 0x03 0x03 STATUS,Z LOOP STATUS,RP1 STATUS,RP0 ADDRH,W EEADRH A DDRL,W EEADR DATAADDR,W FSR INDF,W EEDATA FSR,F INDF,W EEDATH FSR,F STATUS,RP0 E ECON1,EEPGD EECON1,WREN INTCON,GIE 55h EECON2 AAh EECON2 EECON1,WR ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; Bank 2 Load initial address Load initial data address Load first data byte into lower Next byte Load second data byte into upper LOOP Bank 3 Point to program memory Enable writes Disable interrupts (if using) Start of required write sequence: Write 55h Write AAh Set WR bit to begin write Any i nstructions here are ignored as processor halts to begin write sequence processo r will stop here and wait for write complete after write processor continues wit h 3rd instruction Disable writes Enable interrupts (if using) Bank 2 Increment a ddress Check if lower two bits of address are 00 Indicates when four words hav e been programmed Exit if more than four words, Continue if less than four words Required Sequence DS39582B-page 38 2003 Microchip Technology Inc.

PIC16F87XA 3.7 Protection Against Spurious Write 3.8 Operation During Code-Protect There are conditions when the device should not write to the data EEPROM or Flas h program memory. To protect against spurious writes, various mechanisms have be en built-in. On power-up, WREN is cleared. Also, the Power-up Timer (72 ms durat ion) prevents an EEPROM write. The write initiate sequence and the WREN bit toge ther help prevent an accidental write during brown-out, power glitch or software malfunction. When the data EEPROM is code-protected, the microcontroller can re ad and write to the EEPROM normally. However, all external access to the EEPROM is disabled. External write access to the program memory is also disabled. When program memory is code-protected, the microcontroller can read and write to prog ram memory normally, as well as execute instructions. Writes by the device may b e selectively inhibited to regions of the memory depending on the setting of bit s WR1:WR0 of the configuration word (see Section 14.1 Configuration Bits for a dditional information). External access to the memory is also disabled. TABLE 3-1: REGISTERS/BITS ASSOCIATED WITH DATA EEPROM AND FLASH PROGRAM MEMORIES Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset Val ue on all other Resets Address 10Ch 10Dh 10Eh 10Fh 18Ch 18Dh 0Dh 8Dh Legend: EEDATA EEADR EEDATH EEADRH EECON1 EECON2 PIR2 PIE2 EEPROM/Flash Data Register Low Byte EEPROM/Flash Address Register Low Byte E EPGD CMIF CMIE EEPROM/Flash Data Register High Byte EEPROM/Fla sh Address Register High Byte EEIF EEIE WRERR BCLIF BCLIE WREN WR RD C CP2IF CCP2IE xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx ---0 q000 xxxx xxxx ---- ---x-- x000 ---0 q000 ---- ---- ---- ----0-0 0--0 -0-0 0--0 -0-0 0--0 -0-0 0--0 EEPROM Control Register 2 (not a physical register) x = unknown, u = unchanged, - = unimplemented, read as 0, q = value depends up on condition. Shaded cells are not used by data EEPROM or Flash program memory. 2003 Microchip Technology Inc. DS39582B-page 39

PIC16F87XA NOTES: DS39582B-page 40 2003 Microchip Technology Inc.

PIC16F87XA 4.0 I/O PORTS EXAMPLE 4-1: BCF BCF CLRF INITIALIZING PORTA ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; Bank0 Initialize PORTA by clearing output data lat ches Select Bank 1 Configure all pins as digital inputs Value used to initialize data direction Set RA as inputs RA as outputs TRISAare always re ad as 0 . Some pins for these I/O ports are multiplexed with an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, th at pin may not be used as a general purpose I/O pin. Additional information on I /O ports may be found in the PICmicro Mid-Range Reference Manual (DS33023). STATUS, RP0 STATUS, RP1 PORTA 4.1 PORTA and the TRISA Register BSF MOVLW MOVWF MOVLW STATUS, RP0 0x06 ADCON1 0xCF PORTA is a 6-bit wide, bidirectional port. The corresponding data direction regi ster is TRISA. Setting a TRISA bit (= 1) will make the corresponding PORTA pin a n input (i.e., put the corresponding output driver in a High-Impedance mode). Cl earing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., put the contents of the output latch on the selected pin). Reading the PORTA reg ister reads the status of the pins, whereas writing to it will write to the port latch. All write operations are read-modify-write operations. Therefore, a writ e to a port implies that the port pins are read, the value is modified and then written to the port data latch. Pin RA4 is multiplexed with the Timer0 module cl ock input to become the RA4/T0CKI pin. The RA4/T0CKI pin is a Schmitt Trigger in put and an open-drain output. All other PORTA pins have TTL input levels and ful l CMOS output drivers. Other PORTA pins are multiplexed with analog inputs and t he analog VREF input for both the A/D converters and the comparators. The operat ion of each pin is selected by clearing/setting the appropriate control bits in the ADCON1 and/or CMCON registers. Note: On a Power-on Reset, these pins are con figured as analog inputs and read as 0. The comparators are in the off (digita l) state. MOVWF TRISA FIGURE 4-1: Data Bus Data Latch D Q BLOCK DIAGRAM OF RA3:RA0 PINS WR PORTA VDD CK Q P I/O pin(1) TRIS Latch D WR TRISA Q N CK

Q VSS Analog Input Mode RD TRISA TTL Input Buffer Q D The TRISA register controls the direction of the port pins even when they are be ing used as analog