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NOT FOR NEW DESIGN

November 2000This is information on a product still in production but not recommended for new designs.

M27128A

NMOS 128 Kbit (16Kb x 8) UV EPROM

FAST ACCESS TIME: 200ns EXTENDED TEMPERATURE RANGE SINGLE 5 V SUPPLY VOLTAGE LOW STANDBY CURRENT: 40mA max TTL COMPATIBLE DURING READ and

PROGRAM FAST PROGRAMMING ALGORITHM ELECTRONIC SIGNATURE PROGRAMMING VOLTAGE: 12V

DESCRIPTIONThe M27128A is a 131,072 bit UV erasable andelectrically programmable memory EPROM. It isorganized as 16,384 words by 8 bits.The M27128A is housed in a 28 Pin Window Ce-ramic Frit-Seal Dual-in-Line package. The trans-parent lid allows the user to expose the chip toultraviolet light to erase the bit pattern. A new pat-tern can then be written to the device by followingthe programming procedure.

Figure 1. Logic Diagram

AI00769B

14

A0-A13

P

Q0-Q7

VPPVCC

M27128A

G

E

VSS

8

1

28

FDIP28W (F)

Q2VSS

A3

A0Q0Q1

A2A1

G

Q5

A10E

Q3

A11

Q7Q6

Q4

A13PA12

A4

VPP VCC

A7

AI00770

M27128A8

1234567

91011121314

201918171615

A6A5 A9

A8

2827262524232221

Figure 2. DIP Pin Connections

Symbol Parameter Value UnitTA Ambient Operating Temperature grade 1

grade 60 to 70

40 to 85 C

TBIAS Temperature Under Bias grade 1grade 6

10 to 80 50 to 95 C

TSTG Storage Temperature 65 to 125 CVIO Input or Output Voltages 0.6 to 6.25 VVCC Supply Voltage 0.6 to 6.25 VVA9 A9 Voltage 0.6 to 13.5 VVPP Program Supply 0.6 to 14 V

Note: Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may causepermanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above thoseindicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periodsmay affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.

Table 2. Absolute Maximum Ratings

DEVICE OPERATIONThe seven modes of operation of the M27128A arelisted in the Operating Modes table. A single 5Vpower supply is required in the read mode. Allinputs are TTL levels except for VPP and 12V on A9for Electronic Signature.

Read ModeThe M27128A has two control functions, both ofwhich must be logically satisfied in order to obtaindata at the outputs. Chip Enable (E) is the powercontrol and should be used for device selection.Output Enable (G) is the output control and shouldbe used to gate data to the output pins, inde-pendent of device selection.Assuming that the addresses are stable, addressaccess time (tAVQV) is equal to the delay from E tooutput (tELQV). Data is available at the outputs afterthe falling edge of G, assuming that E has been lowand the addresses have been stable for at leasttAVQV-tGLQV.Standby ModeThe M27128A has a standby mode which reducesthe maximum active power current from 85mA to40mA. The M27128A is placed in the standby modeby applying a TTL high signal to the E input. Whenin the standby mode, the outputs are in a highimpedance state, independent of the G input.Two Line Output ControlBecause EPROMs are usually used in larger mem-ory arrays, this product features a 2 line controlfunction which accommodates the use of multiplememory connection. The two line control functionallows:a. the lowest possible memory power dissipation,b. complete assurance that output bus contention

will not occur.

M27128A

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For the most efficient use of these two control lines,E should be decoded and used as the primarydevice selecting function, while G should be madea common connection to all devices in the arrayand connected to the READ line from the systemcontrol bus.This ensures that all deselected memory devicesare in their low power standby mode and that theoutput pins are only active when data is requiredfrom a particular memory device.System ConsiderationsThe power switching characteristics of fastEPROMs require careful decoupling of the devices.The supply current, ICC, has three segments thatare of interest to the system designer: the standbycurrent level, the active current level, and transientcurrent peaks that are produced by the falling andrising edges of E. The magnitude of this transientcurrent peaks is dependent on the capacitive andinductive loading of the device at the output. Theassociated transient voltage peaks can be sup-pressed by complying with the two line outputcontrol and by properly selected decoupling ca-pacitors. It is recommended that a 1F ceramiccapacitor be used on every device between VCCand VSS. This should be a high frequency capacitor

of low inherent inductance and should be placedas close to the device as possible. In addition, a4.7F bulk electrolytic capacitor should be usedbetween VCC and GND for every eight devices. Thebulk capacitor should be located near the powersupply connection point. The purpose of the bulkcapacitor is to overcome the voltage drop causedby the inductive effects of PCB traces.ProgrammingWhen delivered (and after each erasure for UVEPPROM), all bits of the M27128A are in the 1"state. Data is introduced by selectively program-ming 0s" into the desired bit locations. Althoughonly 0s will be programmed, both 1s and 0scan be present in the data word. The only way tochange a 0" to a 1" is by ultraviolet light erasure.The M27128A is in the programming mode whenVPP input is at 12.5V and E and P are at TTL low.The data to be programmed is applied 8 bits inparallel, to the data output pins. The levels requiredfor the address and data inputs are TTL.Fast Programming AlgorithmFast Programming Algorithm rapidly programsM27128A EPROMs using an efficient and reliablemethod suited to the production programming en-vironment. Programming reliability is also ensuredas the incremental program margin of each byte is

Mode E G P A9 VPP Q0 - Q7

Read VIL VIL VIH X VCC Data Out

Output Disable VIL VIH VIH X VCC Hi-Z

Program VIL VIH VIL Pulse X VPP Data In

Verify VIL VIL VIH X VPP Data Out

Program Inhibit VIH X X X VPP Hi-Z

Standby VIH X X X VCC Hi-Z

Electronic Signature VIL VIL VIH VID VCC Codes OutNote: X = VIH or VIL, VID = 12V 0.5%.

Table 3. Operating Modes

Identifier A0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Hex DataManufacturers Code VIL 0 0 1 0 0 0 0 0 20h

Device Code VIH 1 0 0 0 1 0 0 1 89h

Table 4. Electronic Signature

DEVICE OPERATION (contd)

M27128A

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AI00827

2.4V

0.45V

2.0V

0.8V

Figure 3. AC Testing Input Output Waveforms

Input Rise and Fall Times 20nsInput Pulse Voltages 0.45V to 2.4VInput and Output Timing Ref. Voltages 0.8V to 2.0V

AC MEASUREMENT CONDITIONS

AI00828

1.3V

OUT

CL = 100pF

CL includes JIG capacitance

3.3k

1N914

DEVICEUNDERTEST

Figure 4. AC Testing Load Circuit

Note that Output Hi-Z is defined as the point where datais no longer driven.

Symbol Parameter Test Condition Min Max UnitCIN Input Capacitance VIN = 0V = 6 pF

COUT Output Capacitance VOUT = 0V = 12 pFNote: 1. Sampled only, not 100% tested.

Table 5. Capacitance (1) (TA = 25 C, f = 1 MHz )

AI00771

tAXQX

tEHQZ

DATA OUT

A0-A13

E

G

Q0-Q7

tAVQV

tGHQZ

tGLQV

tELQV

VALID

Hi-Z

Figure 5. Read Mode AC Waveforms

M27128A

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Symbol Alt Parameter TestCondition

M27128AUnit

-2, -20 blank, -25 -3, -30 -4Min Max Min Max Min Max Min Max

tAVQV tACC Address Valid toOutput ValidE = VIL, G = VIL 200 250 300 450 ns

tELQV tCE Chip Enable Low toOutput Valid G = VIL 200 250 300 450 ns

tGLQV tOE Output Enable Lowto Output Valid E = VIL 75 100 120 150 ns

tEHQZ (2) tDF Chip Enable High toOutput Hi-Z G = VIL 0 55 0 60 0 105 0 130 ns

tGHQZ (2) tDF Output Enable Highto Output Hi-Z E = VIL 0 55 0 60 0 105 0 130 ns

tAXQX tOH Address Transition toOutput TransitionE = VIL, G = VIL 0 0 0 0 ns

Notes: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. 2. Sampled only, not 100% tested.

Table 7. Read Mode AC Characteristics (1)(TA = 0 to 70 C or 40 to 85 C; VCC = 5V 5% or 5V 10%; VPP = VCC)

Symbol Parameter Test Condition Min Max UnitILI Input Leakage Current 0 VIN VCC 10 AILO Output Leakage Current VOUT = VCC 10 AICC Supply Current E = VIL, G = VIL 75 mAICC1 Supply Current (Standby) E = VIH 35 mAIPP Program Current VPP = VCC 5 mAVIL Input Low Voltage 0.1 0.8 VVIH Input High Voltage 2 VCC + 1 VVOL Output Low Voltage IOL = 2.1mA = 0.45 VVOH Output High Voltage IOH = 400A 2.4 V

Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.

Table 6. Read Mode DC Characteristics (1)(TA = 0 to 70 C or 40 to 85 C; VCC = 5V 5% or 5V 10%; VPP = VCC)

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Symbol Parameter Test Condition Min Max Unit

ILI Input Leakage Current VIL VIN VIH 10 A

ICC Supply Current 100 mA

IPP Program Current E = VIL 50 mA

VIL Input Low Voltage 0.1 0.8 V

VIH Input High Voltage 2 VCC + 1 V

VOL Output Low Voltage IOL = 2.1mA 0.45 V

VOH Output High Voltage IOH = 400A 2.4 V

VID A9 Voltage 11.5 12.5 VNote: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.

Table 8. Programming Mode DC Characteristics (1)(TA = 25 C; VCC = 6V 0.25V; VPP = 12.5V 0.3V)

Symbol Alt Parameter Test Condition Min Max Unit

tAVPL tAS Address Valid to Program Low 2 s

tQVPL tDS Input Valid to Program Low 2 s

tVPHPL tVPS VPP High to Program Low 2 s

tVCHPL tVCS VCC High to Program Low 2 s

tELPL tCES Chip Enable Low to ProgramLow 2 s

tPLPH tPW Program Pulse Width (Initial) Note 2 0.95 1.05 ms

tPLPH tOPW Program Pulse Width(Overprogram) Note 3 2.85 78.75 ms

tPHQX tDH Program High to InputTransition 2 s

tQXGL tOES Input Transition to OutputEnable Low 2 s

tGLQV tOE Output Enable Low to Output Valid 150 ns

tGHQZ (4) tDFP Output Enable High to Output Hi-Z 0 130 ns

tGHAX tAH Output Enable High to Address Transition 0 n s

Notes: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. 2. The Initial Program Pulse width tolerance is 1 ms 5%. 3. The length of the Over-program Pulse varies from 2.85 ms to 78.95 ms, depending on the multiplication value of the iteration counter. 4. Sampled only, not 100% tested.

Table 9. Programming Mode AC Characteristics (1)(TA = 25 C; VCC = 6V 0.25V; VPP = 12.5V 0.3V)

M27128A

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tAVPL

VALID

AI00772

A0-A13

Q0-Q7

VPP

VCC

P

G

DATA IN DATA OUT

E

tQVPL

tVPHPL

tVCHPL

tPHQX

tPLPH

tGLQV

tQXGL

tELPL

tGHQZ

tGHAX

PROGRAM VERIFY

Figure 6. Programming and Verify Modes AC Waveforms

AI00775B

n = 1

LastAddr

VERIFY

P = 1ms Pulse

++n> 25 ++ Addr

VCC = 6V, VPP = 12.5V

FAIL

CHECK ALL BYTESVCC = 5V, VPP 5V

YES

NO

YES

NO

YES

NO

P = 3ms Pulse by n

Figure 7. Programming Flowchartcontinually monitored to determine when it hasbeen successfully programmed. A flowchart of theM27128A Fast Programming Algorithm is shownon the last page. The Fast Programming Algorithmutilizes two different pulse types: initial and over-program.The duration of the initial P pulse(s) is 1ms, whichwill then be followed by a longer overprogram pulseof length 3ms by n (n is equal to the number of theinitial one millisecond pulses applied to a particularM27128A location), before a correct verify occurs.Up to 25 one-millisecond pulses per byte are pro-vided for before the over program pulse is applied.The entire sequence of program pulses and byteverifications is performed at VCC = 6V and VPP =12.5V. When the Fast Programming cycle has beencompleted, all bytes should be compared to theoriginal data with VCC = 5 and VPP = 5V.Program InhibitProgramming of multiple M27128As in parallel withdifferent data is also easily accomplished. Exceptfor E, all like inputs (including G) of the parallelM27128A may be common. A TTL low pulse ap-plied to a M27128As E input, with VPP = 12.5V, willprogram that M27128A. A high level E input inhibitsthe other M27128As from being programmed.

DEVICE OPERATION (contd)

M27128A

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Program VerifyA verify should be performed on the programmedbits to determine that they were correctly pro-grammed. The verify is accomplished with G = VIL,E = VIL, P = VIH and VPP at 12.5V.Electronic SignatureThe Electronic Signature mode allows the readingout of a binary code from an EPROM that willidentify its manufacturer and type. This mode isintended for use by programming equipment toautomatically match the device to be programmedwith its corresponding programming algorithm.This mode is functional in the25C 5C ambienttemperature range that is required when program-ming the M27128A.To activate this mode, the programming equipmentmust force 11.5V to 12.5V on address line A9 of theM27128A. Two identifier bytes may then be se-quenced from the device outputs by toggling ad-dress line A0 from VIL to VIH. All other address linesmust be held at VIL during Electronic Signaturemode. Byte 0 (A0 = VIL) represents the manufac-turer code and byte 1 (A0 = VIH) the device identifiercode. For the STMicroelectronics M27128A, these two identifier bytes are given below.

ERASURE OPERATION (applies to UV EPROM)The erasure characteristic of the M27128A is suchthat erasure begins when the cells are exposed tolight with wavelengths shorter than approximately4000 . It should be noted that sunlight and sometype of fluorescent lamps have wavelengths in the3000-4000 range. Research shows that constantexposure to room level fluorescent lighting coulderase a typical M27128A in about 3 years, while itwould take approximately 1 week to cause erasurewhen exposed to direct sunlight. If the M27128A isto be exposed to these types of lighting conditionsfor extended periods of time, it is suggested thatopaque labels be put over the M27128A window toprevent unintentional erasure. The recommendederasure procedure for the M27128A is exposure toshort wave ultraviolet light which has wavelength2537 . The integrated dose (i.e. UV intensity xexposure time) for erasure should be a minimumof 15 W-sec/cm2. The erasure time with this dosageis approximately 15 to 20 minutes using an ultra-violet lamp with 12000 W/cm2 power rating. TheM27128A should be placed within 2.5cm (1 inch)of the lamp tubes during the erasure. Some lampshave a filter on their tubes which should be re-moved before erasure.

Speed and VCC Tolerance-2 200 ns, 5V 5%

blank 250 ns, 5V 5% -3 300 ns, 5V 5% -4 450 ns, 5V 5% -20 200 ns, 5V 10%-25 250 ns, 5V 10%-30 300 ns, 5V 10%

PackageF FDIP28W

Temperature Range1 0 to 70 C 6 40 to 85 C

Example: M27128A -2 F 1

ORDERING INFORMATION SCHEME

For a list of available options (Speed, VCC Tolerance, Package, etc...) refer to the current Memory Shortformcatalogue.For further information on any aspect of this device, please contact STMicroelectronics Sales Office nearestto you.

M27128A

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FDIPW-a

A2

A1

A

L

B1 B e1

DS

E1 E

N

1

CeA

e3

Symb mm inchesTyp Min Max Typ Min Max

A 5.71 0.225A1 0.50 1.78 0.020 0.070A2 3.90 5.08 0.154 0.200B 0.40 0.55 0.016 0.022B1 1.17 1.42 0.046 0.056C 0.22 0.31 0.009 0.012D 38.10 1.500E 15.40 15.80 0.606 0.622E1 13.05 13.36 0.514 0.526e1 2.54 0.100 e3 33.02 1.300 eA 16.17 18.32 0.637 0.721L 3.18 4.10 0.125 0.161S 1.52 2.49 0.060 0.098 7.11 0.280 4 15 4 15

N 2 8 28

Drawing is not to scale

FDIP28W - 28 pin Ceramic Frit-seal DIP, with window

M27128A

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M27128A

10/10

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequencesof use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is grantedby implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subjectto change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are notauthorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is registered trademark of STMicroelectronicsAll other names are the property of their respective owners

2000 STMicroelectronics - All Rights Reserved

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