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www.sigmatrainers.com

SIGMA TRAINERS

AHMEDABAD (INDIA)

PULSE CODE MODULATION

TRANSMITTER & DEMODULATION

RECEIVER TRAINER

MODEL-COM203-COM204

More

than2000

Trainers

Since

23

Years

TRAINERS

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INTRODUCTION

This trainer has been designed with a view to provide practical and experimental knowledge of Pulse Code

Modulation technique as practically implemented in Digital Communication systems on a SINGLE P.C.B.

SPECIFICATIONS

1. Power supply requirement : 230V AC, 50 Hz.

2. Built in IC based power supply.

3. On Board Sampling Pulse signal generator.

Frequency Range - Fast Mode : 1.2 to 1.4 MHzFrequency Range - Slow Mode : 0.8 Hz to 1.2 HZ

4. Built in variable DC power supply (0 to+ 5V) to see the effect of DC on the output waveform.

5. On Board Input Audio amplifier with Volume control for modulating external signal from Mike or Tape

recorder.

6. On Board Output Audio amplifier with speaker & Volume Control.

7. LED indicators for PCM output bits.

8. Modulator Sections : Ramp Generator, Comparator,

Parallel to serial converter.

9. Demodulator Sections : Serial to parallel converter, Latch,D/A converter and Low Pass Filter.

10. Standard Accessories : 1. A Training Manual.

2. Connecting Patch cords.

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CHAPTER-1

THEORY OF PULSE CODE MODULATION

In continuous wave (CW) modulation, some parameter of a sinusoidal carrier wave is varied continuously inaccordance with the message. In contrast with this, in pulse modulation, some parameter of a regular pulse train

is varied in accordance with the message. One may distinguish two basic types of pulse modulation, namely,

pulse-analogue modulation and pulse-code modulation. In the former, a periodic pulse train is used as the carrierwave, and some characteristic feature of each pulse (e.g.emplitude duration or position) is varied in a continuous

manner in accordance with the pertinent sample value of the message signal. On the other hand, in pulse code

modulation (PCM), a discrete-time, discrete amplitude representation is used for the signal and, as such, it has noCW counterpart. In a PCM system, the message signal is sampled and the amplitude of each sample is rounded

off to the nearest one of a finite set of allowable values and the rounded values are coded.

(i) PCM

The essential operations on the transmitter of a PCM system are sampling, quantising and encoding, as

shown in Fig. 1. The quantising and encoding operations are usually performed in the same circuit. The encoded

output is the PCM signal. The PCM pulses get distorted & corrupted with noise in the transmission. The receiverregenerates these impaired signal pulses, decodes and filters to reproduce the message signal.

(i i) Sampling

The incoming message wave is sampled with a train of narrow rectangular pulses so as to closely approxi-mate the instantaneous sampling process. In order to ensure perfect reconstruction of the message at the receiver,

the sampling rate must be greater than twice the highest frequency component wm of the message wave. In

practice, a low-pass filter is used at the front end of the sampler in order to exclude frequencies greater than w mbefore sampling.

(i i i) Quantizing

A continuous signal, such as voice, has within its finite amplitude range, an infinite number of amplitudelevels. However, in PCM one retains only a finite number of discrete levels by using quantisation. This introduce

some error in the signal. This is called quantisation error or quantisation noise. This means that the original

continuous signal may be approximated by a signal constructed of discrete amplitudes selected on a minimum

error basis from an available set. Clearly if one assigns the discrete amplitude levels with sufficiently close

spacing, one can make the approximated signal practically indistinguishable from the original continuous signal.

Graphically, the quantising process means that a straight line representing the relation between input and

output of a linear continuous system is replaced by a staircase characteristic as in Fig.2.

The quantising error consists of the difference between the input and output signals of the quantizer. It is

apparent that the maximum instantaneous value of this error is half of the separation between two adjacent

permissible amplitude levels.

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(iv) Encoding

The quantised sample values are coded. Any plan for representing each of this discrete set of values as a

particular arrangement of discrete event in a code is called a code One of the discrete events in a code is called a

code element or symbol. In a binary code, each symbol may be either of two distinct values or kinds, such as the presence or absence of a pulse. The two symbols of a binary code results in the maximum advantage over the

effects of noise in a transmission medium. It is also easy to regenerate.With an n bit (binary digit) binary code, one can represent a total of 2 n distinct numbers. There are several ways

by which binary symbols 1 and 0 can be represented by electrical signals. These constitute the PCM signal.

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CHAPTER-2

THEORY OF PULSE CODE DEMODULATION

(i) Decoding

At the receiver, the received PCM pulses may be reshaped. The reshaped clean pulses are regrouped into

code words in the receiver and decoded into a quantised PCM signal. The decoding process involves generating a pulse the amplitude of which is the linear sum of all the pulses in the code word, each pulse weighted by its

place-value (20, 21,22,2 3,....for a binary code) in the code.

(i i) Filtering

The final operation in the receiving is to recover the signal wave by passing the decoder output through a

low-pass reconstruction filter whose cut off frequency is equal to the message bandwidth wm. Assuming that thetransmission path is error free, the recovered signal includes no noise with the exception of the initial distortion

introduced by the quantisation process.

(i i i) Quantising Noise

As mentioned earlier, quantising noise is produced in the transmitter end of a PCM system by rounding off

the sampled values of a continuous base band signal to the nearest permitted quantising levels. For a Quantising

process, let the step size be unifor m and equal to S volts. It is cl ear from Fig. 2 that if qe denotes the value of the

error produced by the quantising process, with a random input signal, the quantising error is a random variable

which is bounded by -S/2 = q e = S/2. It can also be shown that the mean squared value of the quantising noise q eis S2/12. When the message signal has uniform probability distribution over each setup size.

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CHAPTER-3

CIRCUIT DESCRIPTION OF PULSE CODE MODULATION

The PCM Modulation and Demodulation System consist of following sections.

1. Modulating Audio Signal Generator

2. Sampling Pulse Generator

3. PCM Modulator (Encoder) section4. Power supply.

(1) Modulating Audio Signal Generator section :-

IC 8038 - waveform generator - is used generate sine wave signal. 10K Pot is used to vary its frequency. The

frequency range is 300 Hz to 3.4Khz. Two 100K presets are adjusted for proper peaks of sine wave signal. 1K

preset is used to adjust duty cycle. The sine wave output signal available at pin 2 of IC 8038 is given to IC 356

through Amplitude pot for amplification. The amplified sinewave signal from pin 6 of IC 356 is then available atSINE O/P terminal. 22k Pot is used to vary the amplitude of Sine wave signal. The output amplitude varies

from 0 to 15Vpp.

(2). Sampling Pulse Generator:-

The function of this stage to generate sampling pulses. The basic clock is generated by NOT gates made from

NAND gates (IC 4011). The clock frequency depends on R-C network selected by Switch and it can be varied by

frequency pot. On FAST position the clock frequency available is 1.1 MHz to 1.4 MHz while selecting SLOW position 1 to 2 Hz clock is available. This sampling clock (1.28MHz) is then given to counter IC (4040) in

modulator section.

(3) Study of PCM Modulator (Encoder) section

The 1.28 MHz sampling clock from sampling pulse generator is applied to binary counter IC - 4040. Assuming3 bit/4 bit - bit select switch in the 4 bit position, then the output signals of 4040 counter viz. Q2, Q3, Q4, Q5 (at

pins 2,3,5 and 6) are current weighted by resistors 10K, 22K, 39K & 82K and are summed in resistor 1K5 to

produce Ramp waveform of 16 steps. (This ramp waveform can be observed at RAMP o/p socket.) The ramp issymmetrical about 0 volt. The modulating analog signal is connected at input connector from Audi sine wave

generator section. This modulating signal is buffered by buffer IC 741 & applied to one input of comparator

IC529 at pin 3 through 15K resistor. The ramp waveform is connected to other input of comparator 529 at pin 4.

The comparator output is +6 V so long as the input voltage exceeds the ramp voltage, but when this situation isreversed the output changes to 0V. These two levels are converted to those acceptable by the remainder of the

circuit, which operates with thresholds of + 2.4 V, by Zener (2.7V Zener).

The output of comparator is strobed by AND gate (IC 4081 pin 8,9,10), which derives its other, input

from AND gate (IC 4081 pin 13,12,11). This occurs once for every step of the ramp. So long as the comparatoroutput is high the st robe cause o/p at pin 10 (4081) to go high so th at the data presented at inpu ts D0, D1, D2, D3

of latch (IC 4042 pin 4, 7, 13, 14) is latched to the outputs Q0', Q1', Q2', Q3' (IC 4042 pin 2,1 0, 11, 1). However,

when the ramp voltage exceeds the input and the comparator goes low, the latch ceases to be clocked and the previous digital number is stored. When the counter is full, all inputs to NAND gate (IC 4068) are high & the

output goes low (pin 13 of 4068), consequently the Enable input of Shift register (IC 4021 pin 9) goes high and

the parallel data present on inputs P0-P7 (IC 4021 pin 5,10,13,14) are loaded. This data is PCM 4 bit data and are

given to NOT gates (IC 4049) for display on LED as well as these data are clocked at pin 3 in serial form, the

clock signal being taken from the Q1 output of Counter (IC 4040 pin 7). This serial data forms the PCM output

and is available at PCM o/p socket. A synchronization output is provided to assist in viewing the PCM outputwith CRO Operation of bit select switch selects 3-bit operation by providing a permanently low fourth bit. Here

logic 1 is +6 Volt and logic 0 is -6 Volt. The PCM data streams consist of two guard bits (Low), four data

bits (High or low as per input signal), two guard bits (Low) and eight-bit long Sync pulse (High).

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(4) Power supply section:-

The regulated power supply is used for different supply voltages.

Following output D.C. Voltages are required to operate PCM Modulation demodulation system.

+15V, 250mA-15V, 250mA

+ 6V, 500mA

- 6V, 500mA,

Three terminal regulators are used for different output voltages i.e.

IC 7815 for +15V,

IC 7915 for -15V,IC 7806 for +6V,

IC 7906 for -6V,

These ICs are supplied different dc input voltages by two Bridge rectifiers consisting of D1-D4 and D5-D8 &

two 1000/25 EC and 1000/10 EC. The capacitors at each input & each output are for filtering purpose.

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CHAPTER-4

CIRCUIT DESCRIPTION OF PULSE CODE DEMODULATION

The PCM Demodulation System consist of following sections.

1. Pulse Code Demodulator (Decoder) section

2. Low pass filter

3. Power supply.

(1) Study of PCM Demodulator (Decoder) section

The decoder also incorporates a sampling clock made of NAND gates ( IC 4011). This clock is gated by the

sync detector consisting of IC 3140 (used as comparator) and transistor Q1 (2N2907A). When the PCM input is

high Q1 is turned OFF and capacitor C1- 560pf charges through resistor R1 - 33K, when the PCM input is low,Q1 conducts discharging C1-560pf. The time constant C1 & R1 is selected so that the voltage on the comparator

(IC 3140) reaches the threshold set by two 33K resistors at pin 2 of 3140 after six consecutive high pulses. When

the threshold is reached (during the sync pulse only), the comparator output goes low and inhibits the clock. At

the end of the sync pulse C1 is discharged, the comparator output returns to the high state, the clock starts andthe counter 4040 is reset. The clock output is divided by two by the D flip flop 4013. (Divided o/p is available at

pin 1 of IC 4013.) This divided clock is regated by AND gate (IC 4081 pin 1,2,3) to form relatively narrow clock

pulses with their leading edge delayed (delay time is decided by 4K7 and 33pf ) from the PCM data transition by

half a pulse width. This pulse is further gated by AND gate (IC 4081 pin 4,5,6) and is used to clock the shiftresister (IC 4015). The counter 4040 and inverter (IC 4011 pin 8, 9,10) allow eight clock pulses to occur before

AND gate (IC 4081 pin 4,5,6) is inhibited. Thus the two sets of guard bits and four data bits are loaded into shift

register (4015). The data bits Q0, Q1, Q2, Q3 (at pin 3,10,12,13 of IC 4015) are loaded into latch (IC 4040) by

NAND gate (IC 4011 pin 12,13,11) on the ninth clock pulse. The output of the latch is connected to weightedresistors identical to those in the decoder, which sum a current into resistor R9-1K5. The voltage developed

across R9-1K5 is amplified to restore the original level.

(2). Low pass fi lter:

This section passes only low frequencies up to 3.4 KHz and reduces all other frequencies. This filter is requiredto remove high frequency quantisation error noise from demodulated signal. This section is based on IC 741 and

R-C circuits.

(3) Power supply section:

The regulated power supply is used for different supply voltages.

Following output D.C. Voltages are required to operate PCM Modulation demodulation system.

+ 6V, 500mA- 6V, 500mA,

Three terminal regulators are used for different output voltages i.e.

IC 7806 for +6V,IC 7906 for -6V,

These ICs are supplied different dc input voltages by two Bridge rectifiers consisting of D1-D4 & two 1000/16uF and 100/16 uF. The capacitors at each input & each output are for filtering purpose.

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BLOCK DIAGRAM OF PULSE CODE MODULATION

Modulating Sampled

Audio Signal Comparator Data Shift Register

+ Strobe PCM Signal

T1- T3

Ramp T6Signal

T2

BLOCK DIAGRAM PCM DEMODULATOR

Sync Sampling Pulse

Detector Generator

Sync Sync ClkPCM

Signal

Shift Register Strobe Raw Recovered

t Data Data

T4 T5

Low Pass Filter

Latch Adder

Parallel to

Ser ial

Converter

Counter

Sync

Gen.

SP G

AF

Counter

Serial toParallel

Converter

D/ A

Converter LP F

SP GSync

Det.

Latch

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EXPERIMENT PROCEDURE

EXP. (1). TO GENERATE PCM SIGNAL BY MODULATING WITH AUDIO SIGNAL GENERATOR:

1. Connect MOD I/P terminal of PCM modulator to Sine O/P terminal of Audio Oscillator.Connect CRO channel-1 at Sine O/P terminal (T1) of Audio Oscillator.

Connect ground of probe to ground terminal of Audio oscillator.

Adjust amplitude of sine wave to 2 Vpp and audio frequency to 1 KHz. _______Waveform (T1)

2. Connect CRO channe l-2 at Samp Clockterminal (T2) of Sampling pulse generator.

Connect ground of probe to ground terminal of PCM demodulator.Keep Freq. Selection switch at Fast Position. _______Waveform (T2)

3. Then connect CRO channel-2 at PCM O/P terminal of modulator. Keep Bit select switch at 4-bit position.

The PCM modulated waveform will be seen. ______ Waveform (T3)

EXP. (2). TO OBSERVE THE EFFECT OF DC SIGNAL INPUT ON PCM OUTPUT

4. Now connect variable DC signal at MOD I/P terminal of PCM modulator. I.e. connect link between VARD.C.

an d MOD I/P terminals. Keep Freq. Selection switch at Fast Position.

5. Vary the DC volts control POT in DC Source section and see counting effect on LEDS output.

EXP. (3). TO Demodulate PCM SIGNAL: -

6. Connect link between PCM O/P terminal and PCM I/P terminal.

Connect CRO channel-2 at RAW DATA terminal of demodulator.

Observe quantised recovered raw data signal. ______ Waveform (T4)

7. Change bit select switch to 3-bit position and observe steps in output. The steps will be reduced to 8 from 16.

8. Then connect CRO channel-2 at FIL O/P terminal of Low pass filtered and observe filtered recovered output

signal. ______ Waveform (T5)

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TEST POINT WAVEFORMS

T1. Modulating Sinewave signal: (at Sine O/P terminal of Audio Oscillator) : 1 KHz, 2Vpp-

+ 1V

-1V1 ms

T2. Sampling Clock signal: - (1.28 MHz, TTL).

+6 V

-6 V0.8us

T3 Ramp Signal (25KHz): -

+1V 40 us

-1V

H = 0.5 ms

V = 1.0 V

Trig = CRO-1

H = 0.2 us

V = 5.0 V

Trig= CRO-2

H = 20 us

V = 1.0 V

Trig= CRO-2

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T4 PCM O/P signal

8 bit high Level Sync.

+6V 40us

10 us

2 bit2 bit

H = 10 us

V = 5.0 V

Trig= CRO-2

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